Revision e7493b25
| b/hw/eepro100.c | ||
|---|---|---|
| 154 | 154 |
uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ |
| 155 | 155 |
uint8_t tx_threshold; /* transmit threshold */ |
| 156 | 156 |
uint8_t tbd_count; /* TBD number */ |
| 157 |
//~ /* This constitutes two "TBD" entries: hdr and data */ |
|
| 158 |
//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ |
|
| 159 |
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */ |
|
| 160 |
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ |
|
| 161 |
//~ int32_t tx_buf_size1; /* Length of Tx data. */ |
|
| 157 |
#if 0 |
|
| 158 |
/* This constitutes two "TBD" entries: hdr and data */ |
|
| 159 |
uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ |
|
| 160 |
int32_t tx_buf_size0; /* Length of Tx hdr. */ |
|
| 161 |
uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ |
|
| 162 |
int32_t tx_buf_size1; /* Length of Tx data. */ |
|
| 163 |
#endif |
|
| 162 | 164 |
} eepro100_tx_t; |
| 163 | 165 |
|
| 164 | 166 |
/* Receive frame descriptor. */ |
| ... | ... | |
| 398 | 400 |
s->mem[SCBAck] |= status; |
| 399 | 401 |
status = s->scb_stat = s->mem[SCBAck]; |
| 400 | 402 |
status &= (mask | 0x0f); |
| 401 |
//~ status &= (~s->mem[SCBIntmask] | 0x0xf); |
|
| 403 |
#if 0 |
|
| 404 |
status &= (~s->mem[SCBIntmask] | 0x0xf); |
|
| 405 |
#endif |
|
| 402 | 406 |
if (status && (mask & 0x01)) {
|
| 403 | 407 |
/* SCB mask and SCB Bit M do not disable interrupt. */ |
| 404 | 408 |
enable_interrupt(s); |
| ... | ... | |
| 477 | 481 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
| 478 | 482 |
/* PCI Cache Line Size */ |
| 479 | 483 |
/* check cache line size!!! */ |
| 480 |
//~ PCI_CONFIG_8(0x0c, 0x00); |
|
| 484 |
#if 0 |
|
| 485 |
PCI_CONFIG_8(0x0c, 0x00); |
|
| 486 |
#endif |
|
| 481 | 487 |
/* PCI Latency Timer */ |
| 482 |
PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
|
|
| 488 |
PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
|
|
| 483 | 489 |
/* PCI Header Type */ |
| 484 | 490 |
/* BIST (built-in self test) */ |
| 485 | 491 |
/* Expansion ROM Base Address (depends on boot disable!!!) */ |
| ... | ... | |
| 492 | 498 |
/* Interrupt Line */ |
| 493 | 499 |
/* Interrupt Pin */ |
| 494 | 500 |
/* TODO: RST# value should be 0 */ |
| 495 |
PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
|
|
| 501 |
PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); /* interrupt pin 0 */
|
|
| 496 | 502 |
/* Minimum Grant */ |
| 497 | 503 |
PCI_CONFIG_8(PCI_MIN_GNT, 0x08); |
| 498 | 504 |
/* Maximum Latency */ |
| ... | ... | |
| 500 | 506 |
|
| 501 | 507 |
switch (device) {
|
| 502 | 508 |
case i82550: |
| 503 |
// TODO: check device id.
|
|
| 509 |
/* TODO: check device id. */
|
|
| 504 | 510 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 505 | 511 |
/* Revision ID: 0x0c, 0x0d, 0x0e. */ |
| 506 | 512 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); |
| 507 |
// TODO: check size of statistical counters.
|
|
| 513 |
/* TODO: check size of statistical counters. */
|
|
| 508 | 514 |
s->stats_size = 80; |
| 509 |
// TODO: check extended tcb support.
|
|
| 515 |
/* TODO: check extended tcb support. */
|
|
| 510 | 516 |
s->has_extended_tcb_support = 1; |
| 511 | 517 |
break; |
| 512 | 518 |
case i82551: |
| 513 | 519 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 514 | 520 |
/* Revision ID: 0x0f, 0x10. */ |
| 515 | 521 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0f); |
| 516 |
// TODO: check size of statistical counters.
|
|
| 522 |
/* TODO: check size of statistical counters. */
|
|
| 517 | 523 |
s->stats_size = 80; |
| 518 | 524 |
s->has_extended_tcb_support = 1; |
| 519 | 525 |
break; |
| ... | ... | |
| 572 | 578 |
PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
| 573 | 579 |
PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST); |
| 574 | 580 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08); |
| 575 |
// TODO: Windows wants revision id 0x0c.
|
|
| 581 |
/* TODO: Windows wants revision id 0x0c. */
|
|
| 576 | 582 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0c); |
| 577 | 583 |
#if EEPROM_SIZE > 0 |
| 578 | 584 |
PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086); |
| ... | ... | |
| 590 | 596 |
s->has_extended_tcb_support = 1; |
| 591 | 597 |
break; |
| 592 | 598 |
case i82562: |
| 593 |
// TODO: check device id.
|
|
| 599 |
/* TODO: check device id. */
|
|
| 594 | 600 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 595 | 601 |
/* TODO: wrong revision id. */ |
| 596 | 602 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0e); |
| ... | ... | |
| 637 | 643 |
|
| 638 | 644 |
#if EEPROM_SIZE > 0 |
| 639 | 645 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
| 640 |
// TODO: get vendor id from EEPROM for i82557C or later. |
|
| 641 |
// TODO: get device id from EEPROM for i82557C or later. |
|
| 642 |
// TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. |
|
| 643 |
// TODO: header type is determined by EEPROM for i82559. |
|
| 644 |
// TODO: get subsystem id from EEPROM for i82557C or later. |
|
| 645 |
// TODO: get subsystem vendor id from EEPROM for i82557C or later. |
|
| 646 |
// TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. |
|
| 647 |
// TODO: capability pointer depends on EEPROM for i82558. |
|
| 646 |
/* |
|
| 647 |
TODO: get vendor id from EEPROM for i82557C or later. |
|
| 648 |
TODO: get device id from EEPROM for i82557C or later. |
|
| 649 |
TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. |
|
| 650 |
TODO: header type is determined by EEPROM for i82559. |
|
| 651 |
TODO: get subsystem id from EEPROM for i82557C or later. |
|
| 652 |
TODO: get subsystem vendor id from EEPROM for i82557C or later. |
|
| 653 |
TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. |
|
| 654 |
TODO: capability pointer depends on EEPROM for i82558. |
|
| 655 |
*/ |
|
| 648 | 656 |
logout("Get device id and revision from EEPROM!!!\n");
|
| 649 | 657 |
} |
| 650 | 658 |
#endif /* EEPROM_SIZE > 0 */ |
| ... | ... | |
| 654 | 662 |
{
|
| 655 | 663 |
size_t i; |
| 656 | 664 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
| 657 |
//~ eeprom93xx_reset(s->eeprom); |
|
| 665 |
#if 0 |
|
| 666 |
eeprom93xx_reset(s->eeprom); |
|
| 667 |
#endif |
|
| 658 | 668 |
memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
| 659 | 669 |
eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
| 660 | 670 |
if (s->device == i82557B || s->device == i82557C) |
| ... | ... | |
| 738 | 748 |
static uint16_t eepro100_read_command(EEPRO100State * s) |
| 739 | 749 |
{
|
| 740 | 750 |
uint16_t val = 0xffff; |
| 741 |
//~ TRACE(OTHER, logout("val=0x%04x\n", val));
|
|
| 751 |
TRACE(OTHER, logout("val=0x%04x\n", val));
|
|
| 742 | 752 |
return val; |
| 743 | 753 |
} |
| 744 | 754 |
#endif |
| ... | ... | |
| 793 | 803 |
stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames); |
| 794 | 804 |
stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors); |
| 795 | 805 |
stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors); |
| 796 |
//~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); |
|
| 797 |
//~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); |
|
| 798 |
//~ missing("CU dump statistical counters");
|
|
| 806 |
#if 0 |
|
| 807 |
stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames); |
|
| 808 |
stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames); |
|
| 809 |
missing("CU dump statistical counters");
|
|
| 810 |
#endif |
|
| 799 | 811 |
} |
| 800 | 812 |
|
| 801 | 813 |
static void read_cb(EEPRO100State *s) |
| ... | ... | |
| 832 | 844 |
while (size < tcb_bytes) {
|
| 833 | 845 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
| 834 | 846 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4); |
| 835 |
//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); |
|
| 847 |
#if 0 |
|
| 848 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6); |
|
| 849 |
#endif |
|
| 836 | 850 |
tbd_address += 8; |
| 837 | 851 |
TRACE(RXTX, logout |
| 838 | 852 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
| ... | ... | |
| 889 | 903 |
s->statistics.tx_good_frames++; |
| 890 | 904 |
/* Transmit with bad status would raise an CX/TNO interrupt. |
| 891 | 905 |
* (82557 only). Emulation never has bad status. */ |
| 892 |
//~ eepro100_cx_interrupt(s); |
|
| 906 |
#if 0 |
|
| 907 |
eepro100_cx_interrupt(s); |
|
| 908 |
#endif |
|
| 893 | 909 |
} |
| 894 | 910 |
|
| 895 | 911 |
static void set_multicast_list(EEPRO100State *s) |
| ... | ... | |
| 1016 | 1032 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
| 1017 | 1033 |
/* Workaround for bad Linux eepro100 driver which resumes |
| 1018 | 1034 |
* from idle state. */ |
| 1019 |
//~ missing("cu resume");
|
|
| 1035 |
#if 0 |
|
| 1036 |
missing("cu resume");
|
|
| 1037 |
#endif |
|
| 1020 | 1038 |
set_cu_state(s, cu_suspended); |
| 1021 | 1039 |
} |
| 1022 | 1040 |
if (get_cu_state(s) == cu_suspended) {
|
| ... | ... | |
| 1067 | 1085 |
/* RU start. */ |
| 1068 | 1086 |
if (get_ru_state(s) != ru_idle) {
|
| 1069 | 1087 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
| 1070 |
//~ assert(!"wrong RU state"); |
|
| 1088 |
#if 0 |
|
| 1089 |
assert(!"wrong RU state"); |
|
| 1090 |
#endif |
|
| 1071 | 1091 |
} |
| 1072 | 1092 |
set_ru_state(s, ru_ready); |
| 1073 | 1093 |
s->ru_offset = s->pointer; |
| ... | ... | |
| 1078 | 1098 |
if (get_ru_state(s) != ru_suspended) {
|
| 1079 | 1099 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
| 1080 | 1100 |
ru_suspended); |
| 1081 |
//~ assert(!"wrong RU state"); |
|
| 1101 |
#if 0 |
|
| 1102 |
assert(!"wrong RU state"); |
|
| 1103 |
#endif |
|
| 1082 | 1104 |
} |
| 1083 | 1105 |
set_ru_state(s, ru_ready); |
| 1084 | 1106 |
break; |
| ... | ... | |
| 1140 | 1162 |
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
| 1141 | 1163 |
|
| 1142 | 1164 |
/* mask unwriteable bits */ |
| 1143 |
//~ val = SET_MASKED(val, 0x31, eeprom->value); |
|
| 1165 |
#if 0 |
|
| 1166 |
val = SET_MASKED(val, 0x31, eeprom->value); |
|
| 1167 |
#endif |
|
| 1144 | 1168 |
|
| 1145 | 1169 |
int eecs = ((val & EEPROM_CS) != 0); |
| 1146 | 1170 |
int eesk = ((val & EEPROM_SK) != 0); |
| ... | ... | |
| 1222 | 1246 |
val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); |
| 1223 | 1247 |
if (phy != 1) {
|
| 1224 | 1248 |
/* Unsupported PHY address. */ |
| 1225 |
//~ logout("phy must be 1 but is %u\n", phy);
|
|
| 1249 |
#if 0 |
|
| 1250 |
logout("phy must be 1 but is %u\n", phy);
|
|
| 1251 |
#endif |
|
| 1226 | 1252 |
data = 0; |
| 1227 | 1253 |
} else if (opcode != 1 && opcode != 2) {
|
| 1228 | 1254 |
/* Unsupported opcode. */ |
| ... | ... | |
| 1368 | 1394 |
|
| 1369 | 1395 |
switch (addr) {
|
| 1370 | 1396 |
case SCBStatus: |
| 1371 |
//~ val = eepro100_read_status(s); |
|
| 1397 |
#if 0 |
|
| 1398 |
val = eepro100_read_status(s); |
|
| 1399 |
#endif |
|
| 1372 | 1400 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1373 | 1401 |
break; |
| 1374 | 1402 |
case SCBAck: |
| 1375 |
//~ val = eepro100_read_status(s); |
|
| 1403 |
#if 0 |
|
| 1404 |
val = eepro100_read_status(s); |
|
| 1405 |
#endif |
|
| 1376 | 1406 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1377 | 1407 |
break; |
| 1378 | 1408 |
case SCBCmd: |
| 1379 | 1409 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| 1380 |
//~ val = eepro100_read_command(s); |
|
| 1410 |
#if 0 |
|
| 1411 |
val = eepro100_read_command(s); |
|
| 1412 |
#endif |
|
| 1381 | 1413 |
break; |
| 1382 | 1414 |
case SCBIntmask: |
| 1383 | 1415 |
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
| ... | ... | |
| 1413 | 1445 |
|
| 1414 | 1446 |
switch (addr) {
|
| 1415 | 1447 |
case SCBStatus: |
| 1416 |
//~ val = eepro100_read_status(s); |
|
| 1448 |
#if 0 |
|
| 1449 |
val = eepro100_read_status(s); |
|
| 1450 |
#endif |
|
| 1417 | 1451 |
case SCBCmd: |
| 1418 | 1452 |
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
| 1419 | 1453 |
break; |
| ... | ... | |
| 1437 | 1471 |
|
| 1438 | 1472 |
switch (addr) {
|
| 1439 | 1473 |
case SCBStatus: |
| 1440 |
//~ val = eepro100_read_status(s); |
|
| 1474 |
#if 0 |
|
| 1475 |
val = eepro100_read_status(s); |
|
| 1476 |
#endif |
|
| 1441 | 1477 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1442 | 1478 |
break; |
| 1443 | 1479 |
case SCBPointer: |
| 1444 |
//~ val = eepro100_read_pointer(s); |
|
| 1480 |
#if 0 |
|
| 1481 |
val = eepro100_read_pointer(s); |
|
| 1482 |
#endif |
|
| 1445 | 1483 |
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
| 1446 | 1484 |
break; |
| 1447 | 1485 |
case SCBPort: |
| ... | ... | |
| 1468 | 1506 |
|
| 1469 | 1507 |
switch (addr) {
|
| 1470 | 1508 |
case SCBStatus: |
| 1471 |
//~ eepro100_write_status(s, val); |
|
| 1509 |
#if 0 |
|
| 1510 |
eepro100_write_status(s, val); |
|
| 1511 |
#endif |
|
| 1472 | 1512 |
break; |
| 1473 | 1513 |
case SCBAck: |
| 1474 | 1514 |
eepro100_acknowledge(s); |
| ... | ... | |
| 1508 | 1548 |
|
| 1509 | 1549 |
switch (addr) {
|
| 1510 | 1550 |
case SCBStatus: |
| 1511 |
//~ eepro100_write_status(s, val); |
|
| 1551 |
#if 0 |
|
| 1552 |
eepro100_write_status(s, val); |
|
| 1553 |
#endif |
|
| 1512 | 1554 |
eepro100_acknowledge(s); |
| 1513 | 1555 |
break; |
| 1514 | 1556 |
case SCBCmd: |
| ... | ... | |
| 1556 | 1598 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
| 1557 | 1599 |
{
|
| 1558 | 1600 |
EEPRO100State *s = opaque; |
| 1559 |
//~ logout("addr=%s\n", regname(addr));
|
|
| 1601 |
#if 0 |
|
| 1602 |
logout("addr=%s\n", regname(addr));
|
|
| 1603 |
#endif |
|
| 1560 | 1604 |
return eepro100_read1(s, addr - s->region[1]); |
| 1561 | 1605 |
} |
| 1562 | 1606 |
|
| ... | ... | |
| 1575 | 1619 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
| 1576 | 1620 |
{
|
| 1577 | 1621 |
EEPRO100State *s = opaque; |
| 1578 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1622 |
#if 0 |
|
| 1623 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1624 |
#endif |
|
| 1579 | 1625 |
eepro100_write1(s, addr - s->region[1], val); |
| 1580 | 1626 |
} |
| 1581 | 1627 |
|
| ... | ... | |
| 1623 | 1669 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1624 | 1670 |
{
|
| 1625 | 1671 |
EEPRO100State *s = opaque; |
| 1626 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1672 |
#if 0 |
|
| 1673 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1674 |
#endif |
|
| 1627 | 1675 |
eepro100_write1(s, addr, val); |
| 1628 | 1676 |
} |
| 1629 | 1677 |
|
| 1630 | 1678 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1631 | 1679 |
{
|
| 1632 | 1680 |
EEPRO100State *s = opaque; |
| 1633 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1681 |
#if 0 |
|
| 1682 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1683 |
#endif |
|
| 1634 | 1684 |
eepro100_write2(s, addr, val); |
| 1635 | 1685 |
} |
| 1636 | 1686 |
|
| 1637 | 1687 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1638 | 1688 |
{
|
| 1639 | 1689 |
EEPRO100State *s = opaque; |
| 1640 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1690 |
#if 0 |
|
| 1691 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
| 1692 |
#endif |
|
| 1641 | 1693 |
eepro100_write4(s, addr, val); |
| 1642 | 1694 |
} |
| 1643 | 1695 |
|
| 1644 | 1696 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1645 | 1697 |
{
|
| 1646 | 1698 |
EEPRO100State *s = opaque; |
| 1647 |
//~ logout("addr=%s\n", regname(addr));
|
|
| 1699 |
#if 0 |
|
| 1700 |
logout("addr=%s\n", regname(addr));
|
|
| 1701 |
#endif |
|
| 1648 | 1702 |
return eepro100_read1(s, addr); |
| 1649 | 1703 |
} |
| 1650 | 1704 |
|
| 1651 | 1705 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1652 | 1706 |
{
|
| 1653 | 1707 |
EEPRO100State *s = opaque; |
| 1654 |
//~ logout("addr=%s\n", regname(addr));
|
|
| 1708 |
#if 0 |
|
| 1709 |
logout("addr=%s\n", regname(addr));
|
|
| 1710 |
#endif |
|
| 1655 | 1711 |
return eepro100_read2(s, addr); |
| 1656 | 1712 |
} |
| 1657 | 1713 |
|
| 1658 | 1714 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1659 | 1715 |
{
|
| 1660 | 1716 |
EEPRO100State *s = opaque; |
| 1661 |
//~ logout("addr=%s\n", regname(addr));
|
|
| 1717 |
#if 0 |
|
| 1718 |
logout("addr=%s\n", regname(addr));
|
|
| 1719 |
#endif |
|
| 1662 | 1720 |
return eepro100_read4(s, addr); |
| 1663 | 1721 |
} |
| 1664 | 1722 |
|
| ... | ... | |
| 1695 | 1753 |
EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 1696 | 1754 |
TRACE(RXTX, logout("%p\n", s));
|
| 1697 | 1755 |
return get_ru_state(s) == ru_ready; |
| 1698 |
//~ return !eepro100_buffer_full(s); |
|
| 1756 |
#if 0 |
|
| 1757 |
return !eepro100_buffer_full(s); |
|
| 1758 |
#endif |
|
| 1699 | 1759 |
} |
| 1700 | 1760 |
|
| 1701 | 1761 |
static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
| ... | ... | |
| 1724 | 1784 |
* Short frame is discarded */ |
| 1725 | 1785 |
logout("%p received short frame (%zu byte)\n", s, size);
|
| 1726 | 1786 |
s->statistics.rx_short_frame_errors++; |
| 1727 |
//~ return -1; |
|
| 1787 |
#if 0 |
|
| 1788 |
return -1; |
|
| 1789 |
#endif |
|
| 1728 | 1790 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
|
| 1729 | 1791 |
/* Long frame and configuration byte 18/3 (long receive ok) not set: |
| 1730 | 1792 |
* Long frames are discarded. */ |
| 1731 | 1793 |
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
| 1732 | 1794 |
return -1; |
| 1733 |
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
|
|
| 1795 |
} else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
|
|
| 1734 | 1796 |
/* Frame matches individual address. */ |
| 1735 | 1797 |
/* TODO: check configuration byte 15/4 (ignore U/L). */ |
| 1736 | 1798 |
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
| ... | ... | |
| 1774 | 1836 |
/* TODO: RNR interrupt only at first failed frame? */ |
| 1775 | 1837 |
eepro100_rnr_interrupt(s); |
| 1776 | 1838 |
s->statistics.rx_resource_errors++; |
| 1777 |
//~ assert(!"no resources"); |
|
| 1839 |
#if 0 |
|
| 1840 |
assert(!"no resources"); |
|
| 1841 |
#endif |
|
| 1778 | 1842 |
return -1; |
| 1779 | 1843 |
} |
| 1780 |
//~ !!! |
|
| 1781 |
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
|
| 1844 |
/* !!! */ |
|
| 1782 | 1845 |
eepro100_rx_t rx; |
| 1783 | 1846 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
| 1784 | 1847 |
offsetof(eepro100_rx_t, packet)); |
| ... | ... | |
| 1799 | 1862 |
rfd_status); |
| 1800 | 1863 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
| 1801 | 1864 |
/* Early receive interrupt not supported. */ |
| 1802 |
//~ eepro100_er_interrupt(s); |
|
| 1865 |
#if 0 |
|
| 1866 |
eepro100_er_interrupt(s); |
|
| 1867 |
#endif |
|
| 1803 | 1868 |
/* Receive CRC Transfer not supported. */ |
| 1804 | 1869 |
if (s->configuration[18] & BIT(2)) {
|
| 1805 | 1870 |
missing("Receive CRC Transfer");
|
| 1806 | 1871 |
return -1; |
| 1807 | 1872 |
} |
| 1808 | 1873 |
/* TODO: check stripping enable bit. */ |
| 1809 |
//~ assert(!(s->configuration[17] & BIT(0))); |
|
| 1874 |
#if 0 |
|
| 1875 |
assert(!(s->configuration[17] & BIT(0))); |
|
| 1876 |
#endif |
|
| 1810 | 1877 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
| 1811 | 1878 |
offsetof(eepro100_rx_t, packet), buf, size); |
| 1812 | 1879 |
s->statistics.rx_good_frames++; |
Also available in: Unified diff