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/*
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 * Copyright (C) 2010 Red Hat, Inc.
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 *
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 * written by Gerd Hoffmann <kraxel@redhat.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw.h"
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#include "pci.h"
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#include "msi.h"
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#include "qemu-timer.h"
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#include "audiodev.h"
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#include "intel-hda.h"
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#include "intel-hda-defs.h"
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/* --------------------------------------------------------------------- */
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/* hda bus                                                               */
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static struct BusInfo hda_codec_bus_info = {
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    .name      = "HDA",
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    .size      = sizeof(HDACodecBus),
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    .props     = (Property[]) {
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        DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
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        DEFINE_PROP_END_OF_LIST()
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    }
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};
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void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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                        hda_codec_response_func response,
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                        hda_codec_xfer_func xfer)
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{
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    qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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    bus->response = response;
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    bus->xfer = xfer;
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}
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base)
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{
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    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
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    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
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    HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base);
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    dev->info = info;
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    if (dev->cad == -1) {
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        dev->cad = bus->next_cad;
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    }
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    if (dev->cad >= 15) {
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        return -1;
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    }
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    bus->next_cad = dev->cad + 1;
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    return info->init(dev);
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}
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static int hda_codec_dev_exit(DeviceState *qdev)
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{
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    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
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    if (dev->info->exit) {
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        dev->info->exit(dev);
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    }
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    return 0;
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}
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void hda_codec_register(HDACodecDeviceInfo *info)
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{
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    info->qdev.init = hda_codec_dev_init;
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    info->qdev.exit = hda_codec_dev_exit;
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    info->qdev.bus_info = &hda_codec_bus_info;
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    qdev_register(&info->qdev);
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}
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HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
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{
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    DeviceState *qdev;
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    HDACodecDevice *cdev;
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    QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
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        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
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        if (cdev->cad == cad) {
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            return cdev;
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        }
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    }
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    return NULL;
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}
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void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
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{
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    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
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    bus->response(dev, solicited, response);
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}
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bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
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                    uint8_t *buf, uint32_t len)
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{
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    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
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    return bus->xfer(dev, stnr, output, buf, len);
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}
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/* --------------------------------------------------------------------- */
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/* intel hda emulation                                                   */
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typedef struct IntelHDAStream IntelHDAStream;
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typedef struct IntelHDAState IntelHDAState;
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typedef struct IntelHDAReg IntelHDAReg;
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typedef struct bpl {
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    uint64_t addr;
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    uint32_t len;
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    uint32_t flags;
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} bpl;
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struct IntelHDAStream {
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    /* registers */
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    uint32_t ctl;
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    uint32_t lpib;
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    uint32_t cbl;
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    uint32_t lvi;
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    uint32_t fmt;
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    uint32_t bdlp_lbase;
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    uint32_t bdlp_ubase;
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    /* state */
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    bpl      *bpl;
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    uint32_t bentries;
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    uint32_t bsize, be, bp;
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};
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struct IntelHDAState {
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    PCIDevice pci;
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    const char *name;
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    HDACodecBus codecs;
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    /* registers */
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    uint32_t g_ctl;
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    uint32_t wake_en;
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    uint32_t state_sts;
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    uint32_t int_ctl;
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    uint32_t int_sts;
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    uint32_t wall_clk;
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    uint32_t corb_lbase;
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    uint32_t corb_ubase;
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    uint32_t corb_rp;
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    uint32_t corb_wp;
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    uint32_t corb_ctl;
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    uint32_t corb_sts;
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    uint32_t corb_size;
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    uint32_t rirb_lbase;
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    uint32_t rirb_ubase;
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    uint32_t rirb_wp;
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    uint32_t rirb_cnt;
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    uint32_t rirb_ctl;
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    uint32_t rirb_sts;
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    uint32_t rirb_size;
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    uint32_t dp_lbase;
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    uint32_t dp_ubase;
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    uint32_t icw;
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    uint32_t irr;
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    uint32_t ics;
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    /* streams */
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    IntelHDAStream st[8];
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    /* state */
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    int mmio_addr;
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    uint32_t rirb_count;
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    int64_t wall_base_ns;
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    /* debug logging */
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    const IntelHDAReg *last_reg;
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    uint32_t last_val;
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    uint32_t last_write;
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    uint32_t last_sec;
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    uint32_t repeat_count;
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    /* properties */
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    uint32_t debug;
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    uint32_t msi;
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};
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struct IntelHDAReg {
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    const char *name;      /* register name */
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    uint32_t   size;       /* size in bytes */
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    uint32_t   reset;      /* reset value */
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    uint32_t   wmask;      /* write mask */
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    uint32_t   wclear;     /* write 1 to clear bits */
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    uint32_t   offset;     /* location in IntelHDAState */
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    uint32_t   shift;      /* byte access entries for dwords */
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    uint32_t   stream;
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    void       (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
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    void       (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
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};
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static void intel_hda_reset(DeviceState *dev);
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/* --------------------------------------------------------------------- */
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static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
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{
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    target_phys_addr_t addr;
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#if TARGET_PHYS_ADDR_BITS == 32
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    addr = lbase;
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#else
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    addr = ubase;
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    addr <<= 32;
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    addr |= lbase;
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#endif
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    return addr;
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}
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static void stl_phys_le(target_phys_addr_t addr, uint32_t value)
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{
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    uint32_t value_le = cpu_to_le32(value);
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    cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
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}
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static uint32_t ldl_phys_le(target_phys_addr_t addr)
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{
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    uint32_t value_le;
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    cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
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    return le32_to_cpu(value_le);
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}
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static void intel_hda_update_int_sts(IntelHDAState *d)
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{
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    uint32_t sts = 0;
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    uint32_t i;
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    /* update controller status */
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    if (d->rirb_sts & ICH6_RBSTS_IRQ) {
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        sts |= (1 << 30);
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    }
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    if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
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        sts |= (1 << 30);
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    }
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    if (d->state_sts & d->wake_en) {
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        sts |= (1 << 30);
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    }
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    /* update stream status */
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    for (i = 0; i < 8; i++) {
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        /* buffer completion interrupt */
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        if (d->st[i].ctl & (1 << 26)) {
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            sts |= (1 << i);
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        }
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    }
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    /* update global status */
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    if (sts & d->int_ctl) {
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        sts |= (1 << 31);
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    }
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    d->int_sts = sts;
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}
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static void intel_hda_update_irq(IntelHDAState *d)
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{
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    int msi = d->msi && msi_enabled(&d->pci);
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    int level;
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    intel_hda_update_int_sts(d);
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    if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
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        level = 1;
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    } else {
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        level = 0;
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    }
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    dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
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           level, msi ? "msi" : "intx");
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    if (msi) {
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        if (level) {
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            msi_notify(&d->pci, 0);
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        }
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    } else {
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        qemu_set_irq(d->pci.irq[0], level);
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    }
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}
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static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
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{
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    uint32_t cad, nid, data;
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    HDACodecDevice *codec;
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    cad = (verb >> 28) & 0x0f;
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    if (verb & (1 << 27)) {
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        /* indirect node addressing, not specified in HDA 1.0 */
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        dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
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        return -1;
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    }
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    nid = (verb >> 20) & 0x7f;
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    data = verb & 0xfffff;
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    codec = hda_codec_find(&d->codecs, cad);
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    if (codec == NULL) {
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        dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
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        return -1;
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    }
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    codec->info->command(codec, nid, data);
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    return 0;
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}
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static void intel_hda_corb_run(IntelHDAState *d)
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{
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    target_phys_addr_t addr;
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    uint32_t rp, verb;
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    if (d->ics & ICH6_IRS_BUSY) {
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        dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
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        intel_hda_send_command(d, d->icw);
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        return;
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    }
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    for (;;) {
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        if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
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            dprint(d, 2, "%s: !run\n", __FUNCTION__);
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            return;
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        }
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        if ((d->corb_rp & 0xff) == d->corb_wp) {
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            dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
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            return;
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        }
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        if (d->rirb_count == d->rirb_cnt) {
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            dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
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            return;
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        }
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        rp = (d->corb_rp + 1) & 0xff;
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        addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
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        verb = ldl_phys_le(addr + 4*rp);
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        d->corb_rp = rp;
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        dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
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        intel_hda_send_command(d, verb);
349 d61a4ce8 Gerd Hoffmann
    }
350 d61a4ce8 Gerd Hoffmann
}
351 d61a4ce8 Gerd Hoffmann
352 d61a4ce8 Gerd Hoffmann
static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
353 d61a4ce8 Gerd Hoffmann
{
354 d61a4ce8 Gerd Hoffmann
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
355 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
356 d61a4ce8 Gerd Hoffmann
    target_phys_addr_t addr;
357 d61a4ce8 Gerd Hoffmann
    uint32_t wp, ex;
358 d61a4ce8 Gerd Hoffmann
359 d61a4ce8 Gerd Hoffmann
    if (d->ics & ICH6_IRS_BUSY) {
360 d61a4ce8 Gerd Hoffmann
        dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
361 d61a4ce8 Gerd Hoffmann
               __FUNCTION__, response, dev->cad);
362 d61a4ce8 Gerd Hoffmann
        d->irr = response;
363 d61a4ce8 Gerd Hoffmann
        d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
364 d61a4ce8 Gerd Hoffmann
        d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
365 d61a4ce8 Gerd Hoffmann
        return;
366 d61a4ce8 Gerd Hoffmann
    }
367 d61a4ce8 Gerd Hoffmann
368 d61a4ce8 Gerd Hoffmann
    if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
369 d61a4ce8 Gerd Hoffmann
        dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
370 d61a4ce8 Gerd Hoffmann
        return;
371 d61a4ce8 Gerd Hoffmann
    }
372 d61a4ce8 Gerd Hoffmann
373 d61a4ce8 Gerd Hoffmann
    ex = (solicited ? 0 : (1 << 4)) | dev->cad;
374 d61a4ce8 Gerd Hoffmann
    wp = (d->rirb_wp + 1) & 0xff;
375 d61a4ce8 Gerd Hoffmann
    addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
376 d61a4ce8 Gerd Hoffmann
    stl_phys_le(addr + 8*wp, response);
377 d61a4ce8 Gerd Hoffmann
    stl_phys_le(addr + 8*wp + 4, ex);
378 d61a4ce8 Gerd Hoffmann
    d->rirb_wp = wp;
379 d61a4ce8 Gerd Hoffmann
380 d61a4ce8 Gerd Hoffmann
    dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
381 d61a4ce8 Gerd Hoffmann
           __FUNCTION__, wp, response, ex);
382 d61a4ce8 Gerd Hoffmann
383 d61a4ce8 Gerd Hoffmann
    d->rirb_count++;
384 d61a4ce8 Gerd Hoffmann
    if (d->rirb_count == d->rirb_cnt) {
385 d61a4ce8 Gerd Hoffmann
        dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
386 d61a4ce8 Gerd Hoffmann
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
387 d61a4ce8 Gerd Hoffmann
            d->rirb_sts |= ICH6_RBSTS_IRQ;
388 d61a4ce8 Gerd Hoffmann
            intel_hda_update_irq(d);
389 d61a4ce8 Gerd Hoffmann
        }
390 d61a4ce8 Gerd Hoffmann
    } else if ((d->corb_rp & 0xff) == d->corb_wp) {
391 d61a4ce8 Gerd Hoffmann
        dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
392 d61a4ce8 Gerd Hoffmann
               d->rirb_count, d->rirb_cnt);
393 d61a4ce8 Gerd Hoffmann
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
394 d61a4ce8 Gerd Hoffmann
            d->rirb_sts |= ICH6_RBSTS_IRQ;
395 d61a4ce8 Gerd Hoffmann
            intel_hda_update_irq(d);
396 d61a4ce8 Gerd Hoffmann
        }
397 d61a4ce8 Gerd Hoffmann
    }
398 d61a4ce8 Gerd Hoffmann
}
399 d61a4ce8 Gerd Hoffmann
400 d61a4ce8 Gerd Hoffmann
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
401 d61a4ce8 Gerd Hoffmann
                           uint8_t *buf, uint32_t len)
402 d61a4ce8 Gerd Hoffmann
{
403 d61a4ce8 Gerd Hoffmann
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
404 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
405 d61a4ce8 Gerd Hoffmann
    IntelHDAStream *st = NULL;
406 d61a4ce8 Gerd Hoffmann
    target_phys_addr_t addr;
407 d61a4ce8 Gerd Hoffmann
    uint32_t s, copy, left;
408 d61a4ce8 Gerd Hoffmann
    bool irq = false;
409 d61a4ce8 Gerd Hoffmann
410 d61a4ce8 Gerd Hoffmann
    for (s = 0; s < ARRAY_SIZE(d->st); s++) {
411 d61a4ce8 Gerd Hoffmann
        if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) {
412 d61a4ce8 Gerd Hoffmann
            st = d->st + s;
413 d61a4ce8 Gerd Hoffmann
            break;
414 d61a4ce8 Gerd Hoffmann
        }
415 d61a4ce8 Gerd Hoffmann
    }
416 d61a4ce8 Gerd Hoffmann
    if (st == NULL) {
417 d61a4ce8 Gerd Hoffmann
        return false;
418 d61a4ce8 Gerd Hoffmann
    }
419 d61a4ce8 Gerd Hoffmann
    if (st->bpl == NULL) {
420 d61a4ce8 Gerd Hoffmann
        return false;
421 d61a4ce8 Gerd Hoffmann
    }
422 d61a4ce8 Gerd Hoffmann
    if (st->ctl & (1 << 26)) {
423 d61a4ce8 Gerd Hoffmann
        /*
424 d61a4ce8 Gerd Hoffmann
         * Wait with the next DMA xfer until the guest
425 d61a4ce8 Gerd Hoffmann
         * has acked the buffer completion interrupt
426 d61a4ce8 Gerd Hoffmann
         */
427 d61a4ce8 Gerd Hoffmann
        return false;
428 d61a4ce8 Gerd Hoffmann
    }
429 d61a4ce8 Gerd Hoffmann
430 d61a4ce8 Gerd Hoffmann
    left = len;
431 d61a4ce8 Gerd Hoffmann
    while (left > 0) {
432 d61a4ce8 Gerd Hoffmann
        copy = left;
433 d61a4ce8 Gerd Hoffmann
        if (copy > st->bsize - st->lpib)
434 d61a4ce8 Gerd Hoffmann
            copy = st->bsize - st->lpib;
435 d61a4ce8 Gerd Hoffmann
        if (copy > st->bpl[st->be].len - st->bp)
436 d61a4ce8 Gerd Hoffmann
            copy = st->bpl[st->be].len - st->bp;
437 d61a4ce8 Gerd Hoffmann
438 d61a4ce8 Gerd Hoffmann
        dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
439 d61a4ce8 Gerd Hoffmann
               st->be, st->bp, st->bpl[st->be].len, copy);
440 d61a4ce8 Gerd Hoffmann
441 d61a4ce8 Gerd Hoffmann
        cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp,
442 d61a4ce8 Gerd Hoffmann
                               buf, copy, !output);
443 d61a4ce8 Gerd Hoffmann
        st->lpib += copy;
444 d61a4ce8 Gerd Hoffmann
        st->bp += copy;
445 d61a4ce8 Gerd Hoffmann
        buf += copy;
446 d61a4ce8 Gerd Hoffmann
        left -= copy;
447 d61a4ce8 Gerd Hoffmann
448 d61a4ce8 Gerd Hoffmann
        if (st->bpl[st->be].len == st->bp) {
449 d61a4ce8 Gerd Hoffmann
            /* bpl entry filled */
450 d61a4ce8 Gerd Hoffmann
            if (st->bpl[st->be].flags & 0x01) {
451 d61a4ce8 Gerd Hoffmann
                irq = true;
452 d61a4ce8 Gerd Hoffmann
            }
453 d61a4ce8 Gerd Hoffmann
            st->bp = 0;
454 d61a4ce8 Gerd Hoffmann
            st->be++;
455 d61a4ce8 Gerd Hoffmann
            if (st->be == st->bentries) {
456 d61a4ce8 Gerd Hoffmann
                /* bpl wrap around */
457 d61a4ce8 Gerd Hoffmann
                st->be = 0;
458 d61a4ce8 Gerd Hoffmann
                st->lpib = 0;
459 d61a4ce8 Gerd Hoffmann
            }
460 d61a4ce8 Gerd Hoffmann
        }
461 d61a4ce8 Gerd Hoffmann
    }
462 d61a4ce8 Gerd Hoffmann
    if (d->dp_lbase & 0x01) {
463 d61a4ce8 Gerd Hoffmann
        addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
464 d61a4ce8 Gerd Hoffmann
        stl_phys_le(addr + 8*s, st->lpib);
465 d61a4ce8 Gerd Hoffmann
    }
466 d61a4ce8 Gerd Hoffmann
    dprint(d, 3, "dma: --\n");
467 d61a4ce8 Gerd Hoffmann
468 d61a4ce8 Gerd Hoffmann
    if (irq) {
469 d61a4ce8 Gerd Hoffmann
        st->ctl |= (1 << 26); /* buffer completion interrupt */
470 d61a4ce8 Gerd Hoffmann
        intel_hda_update_irq(d);
471 d61a4ce8 Gerd Hoffmann
    }
472 d61a4ce8 Gerd Hoffmann
    return true;
473 d61a4ce8 Gerd Hoffmann
}
474 d61a4ce8 Gerd Hoffmann
475 d61a4ce8 Gerd Hoffmann
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
476 d61a4ce8 Gerd Hoffmann
{
477 d61a4ce8 Gerd Hoffmann
    target_phys_addr_t addr;
478 d61a4ce8 Gerd Hoffmann
    uint8_t buf[16];
479 d61a4ce8 Gerd Hoffmann
    uint32_t i;
480 d61a4ce8 Gerd Hoffmann
481 d61a4ce8 Gerd Hoffmann
    addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
482 d61a4ce8 Gerd Hoffmann
    st->bentries = st->lvi +1;
483 d61a4ce8 Gerd Hoffmann
    qemu_free(st->bpl);
484 d61a4ce8 Gerd Hoffmann
    st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
485 d61a4ce8 Gerd Hoffmann
    for (i = 0; i < st->bentries; i++, addr += 16) {
486 d61a4ce8 Gerd Hoffmann
        cpu_physical_memory_read(addr, buf, 16);
487 d61a4ce8 Gerd Hoffmann
        st->bpl[i].addr  = le64_to_cpu(*(uint64_t *)buf);
488 d61a4ce8 Gerd Hoffmann
        st->bpl[i].len   = le32_to_cpu(*(uint32_t *)(buf + 8));
489 d61a4ce8 Gerd Hoffmann
        st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
490 d61a4ce8 Gerd Hoffmann
        dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
491 d61a4ce8 Gerd Hoffmann
               i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
492 d61a4ce8 Gerd Hoffmann
    }
493 d61a4ce8 Gerd Hoffmann
494 d61a4ce8 Gerd Hoffmann
    st->bsize = st->cbl;
495 d61a4ce8 Gerd Hoffmann
    st->lpib  = 0;
496 d61a4ce8 Gerd Hoffmann
    st->be    = 0;
497 d61a4ce8 Gerd Hoffmann
    st->bp    = 0;
498 d61a4ce8 Gerd Hoffmann
}
499 d61a4ce8 Gerd Hoffmann
500 d61a4ce8 Gerd Hoffmann
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running)
501 d61a4ce8 Gerd Hoffmann
{
502 d61a4ce8 Gerd Hoffmann
    DeviceState *qdev;
503 d61a4ce8 Gerd Hoffmann
    HDACodecDevice *cdev;
504 d61a4ce8 Gerd Hoffmann
505 d61a4ce8 Gerd Hoffmann
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
506 d61a4ce8 Gerd Hoffmann
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
507 d61a4ce8 Gerd Hoffmann
        if (cdev->info->stream) {
508 d61a4ce8 Gerd Hoffmann
            cdev->info->stream(cdev, stream, running);
509 d61a4ce8 Gerd Hoffmann
        }
510 d61a4ce8 Gerd Hoffmann
    }
511 d61a4ce8 Gerd Hoffmann
}
512 d61a4ce8 Gerd Hoffmann
513 d61a4ce8 Gerd Hoffmann
/* --------------------------------------------------------------------- */
514 d61a4ce8 Gerd Hoffmann
515 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516 d61a4ce8 Gerd Hoffmann
{
517 d61a4ce8 Gerd Hoffmann
    if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
518 d61a4ce8 Gerd Hoffmann
        intel_hda_reset(&d->pci.qdev);
519 d61a4ce8 Gerd Hoffmann
    }
520 d61a4ce8 Gerd Hoffmann
}
521 d61a4ce8 Gerd Hoffmann
522 6a0d02f5 Gerd Hoffmann
static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
523 6a0d02f5 Gerd Hoffmann
{
524 6a0d02f5 Gerd Hoffmann
    intel_hda_update_irq(d);
525 6a0d02f5 Gerd Hoffmann
}
526 6a0d02f5 Gerd Hoffmann
527 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
528 d61a4ce8 Gerd Hoffmann
{
529 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
530 d61a4ce8 Gerd Hoffmann
}
531 d61a4ce8 Gerd Hoffmann
532 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
533 d61a4ce8 Gerd Hoffmann
{
534 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
535 d61a4ce8 Gerd Hoffmann
}
536 d61a4ce8 Gerd Hoffmann
537 d61a4ce8 Gerd Hoffmann
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
538 d61a4ce8 Gerd Hoffmann
{
539 d61a4ce8 Gerd Hoffmann
    int64_t ns;
540 d61a4ce8 Gerd Hoffmann
541 d61a4ce8 Gerd Hoffmann
    ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
542 d61a4ce8 Gerd Hoffmann
    d->wall_clk = (uint32_t)(ns * 24 / 1000);  /* 24 MHz */
543 d61a4ce8 Gerd Hoffmann
}
544 d61a4ce8 Gerd Hoffmann
545 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
546 d61a4ce8 Gerd Hoffmann
{
547 d61a4ce8 Gerd Hoffmann
    intel_hda_corb_run(d);
548 d61a4ce8 Gerd Hoffmann
}
549 d61a4ce8 Gerd Hoffmann
550 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
551 d61a4ce8 Gerd Hoffmann
{
552 d61a4ce8 Gerd Hoffmann
    intel_hda_corb_run(d);
553 d61a4ce8 Gerd Hoffmann
}
554 d61a4ce8 Gerd Hoffmann
555 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
556 d61a4ce8 Gerd Hoffmann
{
557 d61a4ce8 Gerd Hoffmann
    if (d->rirb_wp & ICH6_RIRBWP_RST) {
558 d61a4ce8 Gerd Hoffmann
        d->rirb_wp = 0;
559 d61a4ce8 Gerd Hoffmann
    }
560 d61a4ce8 Gerd Hoffmann
}
561 d61a4ce8 Gerd Hoffmann
562 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
563 d61a4ce8 Gerd Hoffmann
{
564 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
565 d61a4ce8 Gerd Hoffmann
566 d61a4ce8 Gerd Hoffmann
    if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
567 d61a4ce8 Gerd Hoffmann
        /* cleared ICH6_RBSTS_IRQ */
568 d61a4ce8 Gerd Hoffmann
        d->rirb_count = 0;
569 d61a4ce8 Gerd Hoffmann
        intel_hda_corb_run(d);
570 d61a4ce8 Gerd Hoffmann
    }
571 d61a4ce8 Gerd Hoffmann
}
572 d61a4ce8 Gerd Hoffmann
573 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
574 d61a4ce8 Gerd Hoffmann
{
575 d61a4ce8 Gerd Hoffmann
    if (d->ics & ICH6_IRS_BUSY) {
576 d61a4ce8 Gerd Hoffmann
        intel_hda_corb_run(d);
577 d61a4ce8 Gerd Hoffmann
    }
578 d61a4ce8 Gerd Hoffmann
}
579 d61a4ce8 Gerd Hoffmann
580 d61a4ce8 Gerd Hoffmann
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
581 d61a4ce8 Gerd Hoffmann
{
582 d61a4ce8 Gerd Hoffmann
    IntelHDAStream *st = d->st + reg->stream;
583 d61a4ce8 Gerd Hoffmann
584 d61a4ce8 Gerd Hoffmann
    if (st->ctl & 0x01) {
585 d61a4ce8 Gerd Hoffmann
        /* reset */
586 d61a4ce8 Gerd Hoffmann
        dprint(d, 1, "st #%d: reset\n", reg->stream);
587 d61a4ce8 Gerd Hoffmann
        st->ctl = 0;
588 d61a4ce8 Gerd Hoffmann
    }
589 d61a4ce8 Gerd Hoffmann
    if ((st->ctl & 0x02) != (old & 0x02)) {
590 d61a4ce8 Gerd Hoffmann
        uint32_t stnr = (st->ctl >> 20) & 0x0f;
591 d61a4ce8 Gerd Hoffmann
        /* run bit flipped */
592 d61a4ce8 Gerd Hoffmann
        if (st->ctl & 0x02) {
593 d61a4ce8 Gerd Hoffmann
            /* start */
594 d61a4ce8 Gerd Hoffmann
            dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
595 d61a4ce8 Gerd Hoffmann
                   reg->stream, stnr, st->cbl);
596 d61a4ce8 Gerd Hoffmann
            intel_hda_parse_bdl(d, st);
597 d61a4ce8 Gerd Hoffmann
            intel_hda_notify_codecs(d, stnr, true);
598 d61a4ce8 Gerd Hoffmann
        } else {
599 d61a4ce8 Gerd Hoffmann
            /* stop */
600 d61a4ce8 Gerd Hoffmann
            dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
601 d61a4ce8 Gerd Hoffmann
            intel_hda_notify_codecs(d, stnr, false);
602 d61a4ce8 Gerd Hoffmann
        }
603 d61a4ce8 Gerd Hoffmann
    }
604 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
605 d61a4ce8 Gerd Hoffmann
}
606 d61a4ce8 Gerd Hoffmann
607 d61a4ce8 Gerd Hoffmann
/* --------------------------------------------------------------------- */
608 d61a4ce8 Gerd Hoffmann
609 d61a4ce8 Gerd Hoffmann
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
610 d61a4ce8 Gerd Hoffmann
611 d61a4ce8 Gerd Hoffmann
static const struct IntelHDAReg regtab[] = {
612 d61a4ce8 Gerd Hoffmann
    /* global */
613 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_GCAP ] = {
614 d61a4ce8 Gerd Hoffmann
        .name     = "GCAP",
615 d61a4ce8 Gerd Hoffmann
        .size     = 2,
616 d61a4ce8 Gerd Hoffmann
        .reset    = 0x4401,
617 d61a4ce8 Gerd Hoffmann
    },
618 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_VMIN ] = {
619 d61a4ce8 Gerd Hoffmann
        .name     = "VMIN",
620 d61a4ce8 Gerd Hoffmann
        .size     = 1,
621 d61a4ce8 Gerd Hoffmann
    },
622 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_VMAJ ] = {
623 d61a4ce8 Gerd Hoffmann
        .name     = "VMAJ",
624 d61a4ce8 Gerd Hoffmann
        .size     = 1,
625 d61a4ce8 Gerd Hoffmann
        .reset    = 1,
626 d61a4ce8 Gerd Hoffmann
    },
627 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_OUTPAY ] = {
628 d61a4ce8 Gerd Hoffmann
        .name     = "OUTPAY",
629 d61a4ce8 Gerd Hoffmann
        .size     = 2,
630 d61a4ce8 Gerd Hoffmann
        .reset    = 0x3c,
631 d61a4ce8 Gerd Hoffmann
    },
632 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_INPAY ] = {
633 d61a4ce8 Gerd Hoffmann
        .name     = "INPAY",
634 d61a4ce8 Gerd Hoffmann
        .size     = 2,
635 d61a4ce8 Gerd Hoffmann
        .reset    = 0x1d,
636 d61a4ce8 Gerd Hoffmann
    },
637 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_GCTL ] = {
638 d61a4ce8 Gerd Hoffmann
        .name     = "GCTL",
639 d61a4ce8 Gerd Hoffmann
        .size     = 4,
640 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x0103,
641 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, g_ctl),
642 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_g_ctl,
643 d61a4ce8 Gerd Hoffmann
    },
644 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_WAKEEN ] = {
645 d61a4ce8 Gerd Hoffmann
        .name     = "WAKEEN",
646 d61a4ce8 Gerd Hoffmann
        .size     = 2,
647 df0db221 Gerd Hoffmann
        .wmask    = 0x7fff,
648 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, wake_en),
649 6a0d02f5 Gerd Hoffmann
        .whandler = intel_hda_set_wake_en,
650 d61a4ce8 Gerd Hoffmann
    },
651 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_STATESTS ] = {
652 d61a4ce8 Gerd Hoffmann
        .name     = "STATESTS",
653 d61a4ce8 Gerd Hoffmann
        .size     = 2,
654 df0db221 Gerd Hoffmann
        .wmask    = 0x7fff,
655 df0db221 Gerd Hoffmann
        .wclear   = 0x7fff,
656 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, state_sts),
657 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_state_sts,
658 d61a4ce8 Gerd Hoffmann
    },
659 d61a4ce8 Gerd Hoffmann
660 d61a4ce8 Gerd Hoffmann
    /* interrupts */
661 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_INTCTL ] = {
662 d61a4ce8 Gerd Hoffmann
        .name     = "INTCTL",
663 d61a4ce8 Gerd Hoffmann
        .size     = 4,
664 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xc00000ff,
665 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, int_ctl),
666 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_int_ctl,
667 d61a4ce8 Gerd Hoffmann
    },
668 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_INTSTS ] = {
669 d61a4ce8 Gerd Hoffmann
        .name     = "INTSTS",
670 d61a4ce8 Gerd Hoffmann
        .size     = 4,
671 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xc00000ff,
672 d61a4ce8 Gerd Hoffmann
        .wclear   = 0xc00000ff,
673 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, int_sts),
674 d61a4ce8 Gerd Hoffmann
    },
675 d61a4ce8 Gerd Hoffmann
676 d61a4ce8 Gerd Hoffmann
    /* misc */
677 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_WALLCLK ] = {
678 d61a4ce8 Gerd Hoffmann
        .name     = "WALLCLK",
679 d61a4ce8 Gerd Hoffmann
        .size     = 4,
680 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, wall_clk),
681 d61a4ce8 Gerd Hoffmann
        .rhandler = intel_hda_get_wall_clk,
682 d61a4ce8 Gerd Hoffmann
    },
683 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_WALLCLK + 0x2000 ] = {
684 d61a4ce8 Gerd Hoffmann
        .name     = "WALLCLK(alias)",
685 d61a4ce8 Gerd Hoffmann
        .size     = 4,
686 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, wall_clk),
687 d61a4ce8 Gerd Hoffmann
        .rhandler = intel_hda_get_wall_clk,
688 d61a4ce8 Gerd Hoffmann
    },
689 d61a4ce8 Gerd Hoffmann
690 d61a4ce8 Gerd Hoffmann
    /* dma engine */
691 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBLBASE ] = {
692 d61a4ce8 Gerd Hoffmann
        .name     = "CORBLBASE",
693 d61a4ce8 Gerd Hoffmann
        .size     = 4,
694 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffff80,
695 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_lbase),
696 d61a4ce8 Gerd Hoffmann
    },
697 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBUBASE ] = {
698 d61a4ce8 Gerd Hoffmann
        .name     = "CORBUBASE",
699 d61a4ce8 Gerd Hoffmann
        .size     = 4,
700 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,
701 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_ubase),
702 d61a4ce8 Gerd Hoffmann
    },
703 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBWP ] = {
704 d61a4ce8 Gerd Hoffmann
        .name     = "CORBWP",
705 d61a4ce8 Gerd Hoffmann
        .size     = 2,
706 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xff,
707 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_wp),
708 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_corb_wp,
709 d61a4ce8 Gerd Hoffmann
    },
710 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBRP ] = {
711 d61a4ce8 Gerd Hoffmann
        .name     = "CORBRP",
712 d61a4ce8 Gerd Hoffmann
        .size     = 2,
713 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x80ff,
714 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_rp),
715 d61a4ce8 Gerd Hoffmann
    },
716 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBCTL ] = {
717 d61a4ce8 Gerd Hoffmann
        .name     = "CORBCTL",
718 d61a4ce8 Gerd Hoffmann
        .size     = 1,
719 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x03,
720 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_ctl),
721 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_corb_ctl,
722 d61a4ce8 Gerd Hoffmann
    },
723 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBSTS ] = {
724 d61a4ce8 Gerd Hoffmann
        .name     = "CORBSTS",
725 d61a4ce8 Gerd Hoffmann
        .size     = 1,
726 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x01,
727 d61a4ce8 Gerd Hoffmann
        .wclear   = 0x01,
728 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_sts),
729 d61a4ce8 Gerd Hoffmann
    },
730 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_CORBSIZE ] = {
731 d61a4ce8 Gerd Hoffmann
        .name     = "CORBSIZE",
732 d61a4ce8 Gerd Hoffmann
        .size     = 1,
733 d61a4ce8 Gerd Hoffmann
        .reset    = 0x42,
734 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, corb_size),
735 d61a4ce8 Gerd Hoffmann
    },
736 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBLBASE ] = {
737 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBLBASE",
738 d61a4ce8 Gerd Hoffmann
        .size     = 4,
739 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffff80,
740 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_lbase),
741 d61a4ce8 Gerd Hoffmann
    },
742 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBUBASE ] = {
743 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBUBASE",
744 d61a4ce8 Gerd Hoffmann
        .size     = 4,
745 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,
746 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_ubase),
747 d61a4ce8 Gerd Hoffmann
    },
748 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBWP ] = {
749 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBWP",
750 d61a4ce8 Gerd Hoffmann
        .size     = 2,
751 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x8000,
752 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_wp),
753 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_rirb_wp,
754 d61a4ce8 Gerd Hoffmann
    },
755 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RINTCNT ] = {
756 d61a4ce8 Gerd Hoffmann
        .name     = "RINTCNT",
757 d61a4ce8 Gerd Hoffmann
        .size     = 2,
758 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xff,
759 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_cnt),
760 d61a4ce8 Gerd Hoffmann
    },
761 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBCTL ] = {
762 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBCTL",
763 d61a4ce8 Gerd Hoffmann
        .size     = 1,
764 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x07,
765 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_ctl),
766 d61a4ce8 Gerd Hoffmann
    },
767 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBSTS ] = {
768 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBSTS",
769 d61a4ce8 Gerd Hoffmann
        .size     = 1,
770 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x05,
771 d61a4ce8 Gerd Hoffmann
        .wclear   = 0x05,
772 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_sts),
773 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_rirb_sts,
774 d61a4ce8 Gerd Hoffmann
    },
775 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_RIRBSIZE ] = {
776 d61a4ce8 Gerd Hoffmann
        .name     = "RIRBSIZE",
777 d61a4ce8 Gerd Hoffmann
        .size     = 1,
778 d61a4ce8 Gerd Hoffmann
        .reset    = 0x42,
779 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, rirb_size),
780 d61a4ce8 Gerd Hoffmann
    },
781 d61a4ce8 Gerd Hoffmann
782 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_DPLBASE ] = {
783 d61a4ce8 Gerd Hoffmann
        .name     = "DPLBASE",
784 d61a4ce8 Gerd Hoffmann
        .size     = 4,
785 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffff81,
786 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, dp_lbase),
787 d61a4ce8 Gerd Hoffmann
    },
788 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_DPUBASE ] = {
789 d61a4ce8 Gerd Hoffmann
        .name     = "DPUBASE",
790 d61a4ce8 Gerd Hoffmann
        .size     = 4,
791 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,
792 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, dp_ubase),
793 d61a4ce8 Gerd Hoffmann
    },
794 d61a4ce8 Gerd Hoffmann
795 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_IC ] = {
796 d61a4ce8 Gerd Hoffmann
        .name     = "ICW",
797 d61a4ce8 Gerd Hoffmann
        .size     = 4,
798 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,
799 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, icw),
800 d61a4ce8 Gerd Hoffmann
    },
801 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_IR ] = {
802 d61a4ce8 Gerd Hoffmann
        .name     = "IRR",
803 d61a4ce8 Gerd Hoffmann
        .size     = 4,
804 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, irr),
805 d61a4ce8 Gerd Hoffmann
    },
806 d61a4ce8 Gerd Hoffmann
    [ ICH6_REG_IRS ] = {
807 d61a4ce8 Gerd Hoffmann
        .name     = "ICS",
808 d61a4ce8 Gerd Hoffmann
        .size     = 2,
809 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x0003,
810 d61a4ce8 Gerd Hoffmann
        .wclear   = 0x0002,
811 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, ics),
812 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_ics,
813 d61a4ce8 Gerd Hoffmann
    },
814 d61a4ce8 Gerd Hoffmann
815 d61a4ce8 Gerd Hoffmann
#define HDA_STREAM(_t, _i)                                            \
816 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_CTL) ] = {                               \
817 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
818 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " CTL",                          \
819 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
820 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x1cff001f,                                       \
821 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
822 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_st_ctl,                             \
823 d61a4ce8 Gerd Hoffmann
    },                                                                \
824 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = {                            \
825 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
826 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " CTL(stnr)",                    \
827 d61a4ce8 Gerd Hoffmann
        .size     = 1,                                                \
828 d61a4ce8 Gerd Hoffmann
        .shift    = 16,                                               \
829 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x00ff0000,                                       \
830 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
831 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_st_ctl,                             \
832 d61a4ce8 Gerd Hoffmann
    },                                                                \
833 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_STS)] = {                                \
834 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
835 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " CTL(sts)",                     \
836 d61a4ce8 Gerd Hoffmann
        .size     = 1,                                                \
837 d61a4ce8 Gerd Hoffmann
        .shift    = 24,                                               \
838 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x1c000000,                                       \
839 d61a4ce8 Gerd Hoffmann
        .wclear   = 0x1c000000,                                       \
840 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
841 d61a4ce8 Gerd Hoffmann
        .whandler = intel_hda_set_st_ctl,                             \
842 d61a4ce8 Gerd Hoffmann
    },                                                                \
843 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = {                              \
844 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
845 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " LPIB",                         \
846 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
847 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
848 d61a4ce8 Gerd Hoffmann
    },                                                                \
849 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = {                     \
850 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
851 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " LPIB(alias)",                  \
852 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
853 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
854 d61a4ce8 Gerd Hoffmann
    },                                                                \
855 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_CBL) ] = {                               \
856 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
857 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " CBL",                          \
858 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
859 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,                                       \
860 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].cbl),              \
861 d61a4ce8 Gerd Hoffmann
    },                                                                \
862 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_LVI) ] = {                               \
863 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
864 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " LVI",                          \
865 d61a4ce8 Gerd Hoffmann
        .size     = 2,                                                \
866 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x00ff,                                           \
867 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].lvi),              \
868 d61a4ce8 Gerd Hoffmann
    },                                                                \
869 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = {                          \
870 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
871 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " FIFOS",                        \
872 d61a4ce8 Gerd Hoffmann
        .size     = 2,                                                \
873 d61a4ce8 Gerd Hoffmann
        .reset    = HDA_BUFFER_SIZE,                                  \
874 d61a4ce8 Gerd Hoffmann
    },                                                                \
875 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = {                            \
876 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
877 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " FMT",                          \
878 d61a4ce8 Gerd Hoffmann
        .size     = 2,                                                \
879 d61a4ce8 Gerd Hoffmann
        .wmask    = 0x7f7f,                                           \
880 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].fmt),              \
881 d61a4ce8 Gerd Hoffmann
    },                                                                \
882 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = {                             \
883 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
884 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " BDLPL",                        \
885 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
886 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffff80,                                       \
887 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_lbase),       \
888 d61a4ce8 Gerd Hoffmann
    },                                                                \
889 d61a4ce8 Gerd Hoffmann
    [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = {                             \
890 d61a4ce8 Gerd Hoffmann
        .stream   = _i,                                               \
891 d61a4ce8 Gerd Hoffmann
        .name     = _t stringify(_i) " BDLPU",                        \
892 d61a4ce8 Gerd Hoffmann
        .size     = 4,                                                \
893 d61a4ce8 Gerd Hoffmann
        .wmask    = 0xffffffff,                                       \
894 d61a4ce8 Gerd Hoffmann
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_ubase),       \
895 d61a4ce8 Gerd Hoffmann
    },                                                                \
896 d61a4ce8 Gerd Hoffmann
897 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("IN", 0)
898 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("IN", 1)
899 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("IN", 2)
900 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("IN", 3)
901 d61a4ce8 Gerd Hoffmann
902 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("OUT", 4)
903 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("OUT", 5)
904 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("OUT", 6)
905 d61a4ce8 Gerd Hoffmann
    HDA_STREAM("OUT", 7)
906 d61a4ce8 Gerd Hoffmann
907 d61a4ce8 Gerd Hoffmann
};
908 d61a4ce8 Gerd Hoffmann
909 d61a4ce8 Gerd Hoffmann
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
910 d61a4ce8 Gerd Hoffmann
{
911 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg;
912 d61a4ce8 Gerd Hoffmann
913 d61a4ce8 Gerd Hoffmann
    if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
914 d61a4ce8 Gerd Hoffmann
        goto noreg;
915 d61a4ce8 Gerd Hoffmann
    }
916 d61a4ce8 Gerd Hoffmann
    reg = regtab+addr;
917 d61a4ce8 Gerd Hoffmann
    if (reg->name == NULL) {
918 d61a4ce8 Gerd Hoffmann
        goto noreg;
919 d61a4ce8 Gerd Hoffmann
    }
920 d61a4ce8 Gerd Hoffmann
    return reg;
921 d61a4ce8 Gerd Hoffmann
922 d61a4ce8 Gerd Hoffmann
noreg:
923 d61a4ce8 Gerd Hoffmann
    dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
924 d61a4ce8 Gerd Hoffmann
    return NULL;
925 d61a4ce8 Gerd Hoffmann
}
926 d61a4ce8 Gerd Hoffmann
927 d61a4ce8 Gerd Hoffmann
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
928 d61a4ce8 Gerd Hoffmann
{
929 d61a4ce8 Gerd Hoffmann
    uint8_t *addr = (void*)d;
930 d61a4ce8 Gerd Hoffmann
931 d61a4ce8 Gerd Hoffmann
    addr += reg->offset;
932 d61a4ce8 Gerd Hoffmann
    return (uint32_t*)addr;
933 d61a4ce8 Gerd Hoffmann
}
934 d61a4ce8 Gerd Hoffmann
935 d61a4ce8 Gerd Hoffmann
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
936 d61a4ce8 Gerd Hoffmann
                                uint32_t wmask)
937 d61a4ce8 Gerd Hoffmann
{
938 d61a4ce8 Gerd Hoffmann
    uint32_t *addr;
939 d61a4ce8 Gerd Hoffmann
    uint32_t old;
940 d61a4ce8 Gerd Hoffmann
941 d61a4ce8 Gerd Hoffmann
    if (!reg) {
942 d61a4ce8 Gerd Hoffmann
        return;
943 d61a4ce8 Gerd Hoffmann
    }
944 d61a4ce8 Gerd Hoffmann
945 d61a4ce8 Gerd Hoffmann
    if (d->debug) {
946 d61a4ce8 Gerd Hoffmann
        time_t now = time(NULL);
947 d61a4ce8 Gerd Hoffmann
        if (d->last_write && d->last_reg == reg && d->last_val == val) {
948 d61a4ce8 Gerd Hoffmann
            d->repeat_count++;
949 d61a4ce8 Gerd Hoffmann
            if (d->last_sec != now) {
950 d61a4ce8 Gerd Hoffmann
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
951 d61a4ce8 Gerd Hoffmann
                d->last_sec = now;
952 d61a4ce8 Gerd Hoffmann
                d->repeat_count = 0;
953 d61a4ce8 Gerd Hoffmann
            }
954 d61a4ce8 Gerd Hoffmann
        } else {
955 d61a4ce8 Gerd Hoffmann
            if (d->repeat_count) {
956 d61a4ce8 Gerd Hoffmann
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
957 d61a4ce8 Gerd Hoffmann
            }
958 d61a4ce8 Gerd Hoffmann
            dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
959 d61a4ce8 Gerd Hoffmann
            d->last_write = 1;
960 d61a4ce8 Gerd Hoffmann
            d->last_reg   = reg;
961 d61a4ce8 Gerd Hoffmann
            d->last_val   = val;
962 d61a4ce8 Gerd Hoffmann
            d->last_sec   = now;
963 d61a4ce8 Gerd Hoffmann
            d->repeat_count = 0;
964 d61a4ce8 Gerd Hoffmann
        }
965 d61a4ce8 Gerd Hoffmann
    }
966 d61a4ce8 Gerd Hoffmann
    assert(reg->offset != 0);
967 d61a4ce8 Gerd Hoffmann
968 d61a4ce8 Gerd Hoffmann
    addr = intel_hda_reg_addr(d, reg);
969 d61a4ce8 Gerd Hoffmann
    old = *addr;
970 d61a4ce8 Gerd Hoffmann
971 d61a4ce8 Gerd Hoffmann
    if (reg->shift) {
972 d61a4ce8 Gerd Hoffmann
        val <<= reg->shift;
973 d61a4ce8 Gerd Hoffmann
        wmask <<= reg->shift;
974 d61a4ce8 Gerd Hoffmann
    }
975 d61a4ce8 Gerd Hoffmann
    wmask &= reg->wmask;
976 d61a4ce8 Gerd Hoffmann
    *addr &= ~wmask;
977 d61a4ce8 Gerd Hoffmann
    *addr |= wmask & val;
978 d61a4ce8 Gerd Hoffmann
    *addr &= ~(val & reg->wclear);
979 d61a4ce8 Gerd Hoffmann
980 d61a4ce8 Gerd Hoffmann
    if (reg->whandler) {
981 d61a4ce8 Gerd Hoffmann
        reg->whandler(d, reg, old);
982 d61a4ce8 Gerd Hoffmann
    }
983 d61a4ce8 Gerd Hoffmann
}
984 d61a4ce8 Gerd Hoffmann
985 d61a4ce8 Gerd Hoffmann
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
986 d61a4ce8 Gerd Hoffmann
                                   uint32_t rmask)
987 d61a4ce8 Gerd Hoffmann
{
988 d61a4ce8 Gerd Hoffmann
    uint32_t *addr, ret;
989 d61a4ce8 Gerd Hoffmann
990 d61a4ce8 Gerd Hoffmann
    if (!reg) {
991 d61a4ce8 Gerd Hoffmann
        return 0;
992 d61a4ce8 Gerd Hoffmann
    }
993 d61a4ce8 Gerd Hoffmann
994 d61a4ce8 Gerd Hoffmann
    if (reg->rhandler) {
995 d61a4ce8 Gerd Hoffmann
        reg->rhandler(d, reg);
996 d61a4ce8 Gerd Hoffmann
    }
997 d61a4ce8 Gerd Hoffmann
998 d61a4ce8 Gerd Hoffmann
    if (reg->offset == 0) {
999 d61a4ce8 Gerd Hoffmann
        /* constant read-only register */
1000 d61a4ce8 Gerd Hoffmann
        ret = reg->reset;
1001 d61a4ce8 Gerd Hoffmann
    } else {
1002 d61a4ce8 Gerd Hoffmann
        addr = intel_hda_reg_addr(d, reg);
1003 d61a4ce8 Gerd Hoffmann
        ret = *addr;
1004 d61a4ce8 Gerd Hoffmann
        if (reg->shift) {
1005 d61a4ce8 Gerd Hoffmann
            ret >>= reg->shift;
1006 d61a4ce8 Gerd Hoffmann
        }
1007 d61a4ce8 Gerd Hoffmann
        ret &= rmask;
1008 d61a4ce8 Gerd Hoffmann
    }
1009 d61a4ce8 Gerd Hoffmann
    if (d->debug) {
1010 d61a4ce8 Gerd Hoffmann
        time_t now = time(NULL);
1011 d61a4ce8 Gerd Hoffmann
        if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1012 d61a4ce8 Gerd Hoffmann
            d->repeat_count++;
1013 d61a4ce8 Gerd Hoffmann
            if (d->last_sec != now) {
1014 d61a4ce8 Gerd Hoffmann
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1015 d61a4ce8 Gerd Hoffmann
                d->last_sec = now;
1016 d61a4ce8 Gerd Hoffmann
                d->repeat_count = 0;
1017 d61a4ce8 Gerd Hoffmann
            }
1018 d61a4ce8 Gerd Hoffmann
        } else {
1019 d61a4ce8 Gerd Hoffmann
            if (d->repeat_count) {
1020 d61a4ce8 Gerd Hoffmann
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1021 d61a4ce8 Gerd Hoffmann
            }
1022 d61a4ce8 Gerd Hoffmann
            dprint(d, 2, "read  %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1023 d61a4ce8 Gerd Hoffmann
            d->last_write = 0;
1024 d61a4ce8 Gerd Hoffmann
            d->last_reg   = reg;
1025 d61a4ce8 Gerd Hoffmann
            d->last_val   = ret;
1026 d61a4ce8 Gerd Hoffmann
            d->last_sec   = now;
1027 d61a4ce8 Gerd Hoffmann
            d->repeat_count = 0;
1028 d61a4ce8 Gerd Hoffmann
        }
1029 d61a4ce8 Gerd Hoffmann
    }
1030 d61a4ce8 Gerd Hoffmann
    return ret;
1031 d61a4ce8 Gerd Hoffmann
}
1032 d61a4ce8 Gerd Hoffmann
1033 d61a4ce8 Gerd Hoffmann
static void intel_hda_regs_reset(IntelHDAState *d)
1034 d61a4ce8 Gerd Hoffmann
{
1035 d61a4ce8 Gerd Hoffmann
    uint32_t *addr;
1036 d61a4ce8 Gerd Hoffmann
    int i;
1037 d61a4ce8 Gerd Hoffmann
1038 d61a4ce8 Gerd Hoffmann
    for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1039 d61a4ce8 Gerd Hoffmann
        if (regtab[i].name == NULL) {
1040 d61a4ce8 Gerd Hoffmann
            continue;
1041 d61a4ce8 Gerd Hoffmann
        }
1042 d61a4ce8 Gerd Hoffmann
        if (regtab[i].offset == 0) {
1043 d61a4ce8 Gerd Hoffmann
            continue;
1044 d61a4ce8 Gerd Hoffmann
        }
1045 d61a4ce8 Gerd Hoffmann
        addr = intel_hda_reg_addr(d, regtab + i);
1046 d61a4ce8 Gerd Hoffmann
        *addr = regtab[i].reset;
1047 d61a4ce8 Gerd Hoffmann
    }
1048 d61a4ce8 Gerd Hoffmann
}
1049 d61a4ce8 Gerd Hoffmann
1050 d61a4ce8 Gerd Hoffmann
/* --------------------------------------------------------------------- */
1051 d61a4ce8 Gerd Hoffmann
1052 d61a4ce8 Gerd Hoffmann
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1053 d61a4ce8 Gerd Hoffmann
{
1054 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1055 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1056 d61a4ce8 Gerd Hoffmann
1057 d61a4ce8 Gerd Hoffmann
    intel_hda_reg_write(d, reg, val, 0xff);
1058 d61a4ce8 Gerd Hoffmann
}
1059 d61a4ce8 Gerd Hoffmann
1060 d61a4ce8 Gerd Hoffmann
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1061 d61a4ce8 Gerd Hoffmann
{
1062 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1063 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1064 d61a4ce8 Gerd Hoffmann
1065 d61a4ce8 Gerd Hoffmann
    intel_hda_reg_write(d, reg, val, 0xffff);
1066 d61a4ce8 Gerd Hoffmann
}
1067 d61a4ce8 Gerd Hoffmann
1068 d61a4ce8 Gerd Hoffmann
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1069 d61a4ce8 Gerd Hoffmann
{
1070 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1071 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1072 d61a4ce8 Gerd Hoffmann
1073 d61a4ce8 Gerd Hoffmann
    intel_hda_reg_write(d, reg, val, 0xffffffff);
1074 d61a4ce8 Gerd Hoffmann
}
1075 d61a4ce8 Gerd Hoffmann
1076 d61a4ce8 Gerd Hoffmann
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1077 d61a4ce8 Gerd Hoffmann
{
1078 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1079 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1080 d61a4ce8 Gerd Hoffmann
1081 d61a4ce8 Gerd Hoffmann
    return intel_hda_reg_read(d, reg, 0xff);
1082 d61a4ce8 Gerd Hoffmann
}
1083 d61a4ce8 Gerd Hoffmann
1084 d61a4ce8 Gerd Hoffmann
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1085 d61a4ce8 Gerd Hoffmann
{
1086 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1087 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1088 d61a4ce8 Gerd Hoffmann
1089 d61a4ce8 Gerd Hoffmann
    return intel_hda_reg_read(d, reg, 0xffff);
1090 d61a4ce8 Gerd Hoffmann
}
1091 d61a4ce8 Gerd Hoffmann
1092 d61a4ce8 Gerd Hoffmann
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1093 d61a4ce8 Gerd Hoffmann
{
1094 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = opaque;
1095 d61a4ce8 Gerd Hoffmann
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1096 d61a4ce8 Gerd Hoffmann
1097 d61a4ce8 Gerd Hoffmann
    return intel_hda_reg_read(d, reg, 0xffffffff);
1098 d61a4ce8 Gerd Hoffmann
}
1099 d61a4ce8 Gerd Hoffmann
1100 d61a4ce8 Gerd Hoffmann
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = {
1101 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_readb,
1102 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_readw,
1103 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_readl,
1104 d61a4ce8 Gerd Hoffmann
};
1105 d61a4ce8 Gerd Hoffmann
1106 d61a4ce8 Gerd Hoffmann
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = {
1107 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_writeb,
1108 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_writew,
1109 d61a4ce8 Gerd Hoffmann
    intel_hda_mmio_writel,
1110 d61a4ce8 Gerd Hoffmann
};
1111 d61a4ce8 Gerd Hoffmann
1112 d61a4ce8 Gerd Hoffmann
static void intel_hda_map(PCIDevice *pci, int region_num,
1113 d61a4ce8 Gerd Hoffmann
                          pcibus_t addr, pcibus_t size, int type)
1114 d61a4ce8 Gerd Hoffmann
{
1115 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1116 d61a4ce8 Gerd Hoffmann
1117 d61a4ce8 Gerd Hoffmann
    cpu_register_physical_memory(addr, 0x4000, d->mmio_addr);
1118 d61a4ce8 Gerd Hoffmann
}
1119 d61a4ce8 Gerd Hoffmann
1120 d61a4ce8 Gerd Hoffmann
/* --------------------------------------------------------------------- */
1121 d61a4ce8 Gerd Hoffmann
1122 d61a4ce8 Gerd Hoffmann
static void intel_hda_reset(DeviceState *dev)
1123 d61a4ce8 Gerd Hoffmann
{
1124 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1125 d61a4ce8 Gerd Hoffmann
    DeviceState *qdev;
1126 d61a4ce8 Gerd Hoffmann
    HDACodecDevice *cdev;
1127 d61a4ce8 Gerd Hoffmann
1128 d61a4ce8 Gerd Hoffmann
    intel_hda_regs_reset(d);
1129 d61a4ce8 Gerd Hoffmann
    d->wall_base_ns = qemu_get_clock(vm_clock);
1130 d61a4ce8 Gerd Hoffmann
1131 d61a4ce8 Gerd Hoffmann
    /* reset codecs */
1132 d61a4ce8 Gerd Hoffmann
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
1133 d61a4ce8 Gerd Hoffmann
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1134 d61a4ce8 Gerd Hoffmann
        if (qdev->info->reset) {
1135 d61a4ce8 Gerd Hoffmann
            qdev->info->reset(qdev);
1136 d61a4ce8 Gerd Hoffmann
        }
1137 d61a4ce8 Gerd Hoffmann
        d->state_sts |= (1 << cdev->cad);
1138 d61a4ce8 Gerd Hoffmann
    }
1139 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
1140 d61a4ce8 Gerd Hoffmann
}
1141 d61a4ce8 Gerd Hoffmann
1142 d61a4ce8 Gerd Hoffmann
static int intel_hda_init(PCIDevice *pci)
1143 d61a4ce8 Gerd Hoffmann
{
1144 d61a4ce8 Gerd Hoffmann
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1145 d61a4ce8 Gerd Hoffmann
    uint8_t *conf = d->pci.config;
1146 d61a4ce8 Gerd Hoffmann
1147 d61a4ce8 Gerd Hoffmann
    d->name = d->pci.qdev.info->name;
1148 d61a4ce8 Gerd Hoffmann
1149 d61a4ce8 Gerd Hoffmann
    pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL);
1150 d61a4ce8 Gerd Hoffmann
    pci_config_set_device_id(conf, 0x2668);
1151 d61a4ce8 Gerd Hoffmann
    pci_config_set_revision(conf, 1);
1152 d61a4ce8 Gerd Hoffmann
    pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO);
1153 d61a4ce8 Gerd Hoffmann
    pci_config_set_interrupt_pin(conf, 1);
1154 d61a4ce8 Gerd Hoffmann
1155 d61a4ce8 Gerd Hoffmann
    /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1156 d61a4ce8 Gerd Hoffmann
    conf[0x40] = 0x01;
1157 d61a4ce8 Gerd Hoffmann
1158 d61a4ce8 Gerd Hoffmann
    d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
1159 d61a4ce8 Gerd Hoffmann
                                          intel_hda_mmio_write, d);
1160 d61a4ce8 Gerd Hoffmann
    pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY,
1161 d61a4ce8 Gerd Hoffmann
                     intel_hda_map);
1162 17786d52 Gerd Hoffmann
    if (d->msi) {
1163 17786d52 Gerd Hoffmann
        msi_init(&d->pci, 0x50, 1, true, false);
1164 17786d52 Gerd Hoffmann
    }
1165 d61a4ce8 Gerd Hoffmann
1166 d61a4ce8 Gerd Hoffmann
    hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1167 d61a4ce8 Gerd Hoffmann
                       intel_hda_response, intel_hda_xfer);
1168 d61a4ce8 Gerd Hoffmann
1169 d61a4ce8 Gerd Hoffmann
    return 0;
1170 d61a4ce8 Gerd Hoffmann
}
1171 d61a4ce8 Gerd Hoffmann
1172 dc4b9240 Gerd Hoffmann
static int intel_hda_exit(PCIDevice *pci)
1173 dc4b9240 Gerd Hoffmann
{
1174 dc4b9240 Gerd Hoffmann
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1175 dc4b9240 Gerd Hoffmann
1176 17786d52 Gerd Hoffmann
    if (d->msi) {
1177 17786d52 Gerd Hoffmann
        msi_uninit(&d->pci);
1178 17786d52 Gerd Hoffmann
    }
1179 dc4b9240 Gerd Hoffmann
    cpu_unregister_io_memory(d->mmio_addr);
1180 dc4b9240 Gerd Hoffmann
    return 0;
1181 dc4b9240 Gerd Hoffmann
}
1182 dc4b9240 Gerd Hoffmann
1183 17786d52 Gerd Hoffmann
static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,
1184 17786d52 Gerd Hoffmann
                                   uint32_t val, int len)
1185 17786d52 Gerd Hoffmann
{
1186 17786d52 Gerd Hoffmann
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1187 17786d52 Gerd Hoffmann
1188 17786d52 Gerd Hoffmann
    pci_default_write_config(pci, addr, val, len);
1189 17786d52 Gerd Hoffmann
    if (d->msi) {
1190 17786d52 Gerd Hoffmann
        msi_write_config(pci, addr, val, len);
1191 17786d52 Gerd Hoffmann
    }
1192 17786d52 Gerd Hoffmann
}
1193 17786d52 Gerd Hoffmann
1194 d61a4ce8 Gerd Hoffmann
static int intel_hda_post_load(void *opaque, int version)
1195 d61a4ce8 Gerd Hoffmann
{
1196 d61a4ce8 Gerd Hoffmann
    IntelHDAState* d = opaque;
1197 d61a4ce8 Gerd Hoffmann
    int i;
1198 d61a4ce8 Gerd Hoffmann
1199 d61a4ce8 Gerd Hoffmann
    dprint(d, 1, "%s\n", __FUNCTION__);
1200 d61a4ce8 Gerd Hoffmann
    for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1201 d61a4ce8 Gerd Hoffmann
        if (d->st[i].ctl & 0x02) {
1202 d61a4ce8 Gerd Hoffmann
            intel_hda_parse_bdl(d, &d->st[i]);
1203 d61a4ce8 Gerd Hoffmann
        }
1204 d61a4ce8 Gerd Hoffmann
    }
1205 d61a4ce8 Gerd Hoffmann
    intel_hda_update_irq(d);
1206 d61a4ce8 Gerd Hoffmann
    return 0;
1207 d61a4ce8 Gerd Hoffmann
}
1208 d61a4ce8 Gerd Hoffmann
1209 d61a4ce8 Gerd Hoffmann
static const VMStateDescription vmstate_intel_hda_stream = {
1210 d61a4ce8 Gerd Hoffmann
    .name = "intel-hda-stream",
1211 d61a4ce8 Gerd Hoffmann
    .version_id = 1,
1212 d61a4ce8 Gerd Hoffmann
    .fields = (VMStateField []) {
1213 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(ctl, IntelHDAStream),
1214 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(lpib, IntelHDAStream),
1215 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(cbl, IntelHDAStream),
1216 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(lvi, IntelHDAStream),
1217 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(fmt, IntelHDAStream),
1218 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1219 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1220 d61a4ce8 Gerd Hoffmann
        VMSTATE_END_OF_LIST()
1221 d61a4ce8 Gerd Hoffmann
    }
1222 d61a4ce8 Gerd Hoffmann
};
1223 d61a4ce8 Gerd Hoffmann
1224 d61a4ce8 Gerd Hoffmann
static const VMStateDescription vmstate_intel_hda = {
1225 d61a4ce8 Gerd Hoffmann
    .name = "intel-hda",
1226 d61a4ce8 Gerd Hoffmann
    .version_id = 1,
1227 d61a4ce8 Gerd Hoffmann
    .post_load = intel_hda_post_load,
1228 d61a4ce8 Gerd Hoffmann
    .fields = (VMStateField []) {
1229 d61a4ce8 Gerd Hoffmann
        VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1230 d61a4ce8 Gerd Hoffmann
1231 d61a4ce8 Gerd Hoffmann
        /* registers */
1232 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(g_ctl, IntelHDAState),
1233 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(wake_en, IntelHDAState),
1234 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(state_sts, IntelHDAState),
1235 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(int_ctl, IntelHDAState),
1236 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(int_sts, IntelHDAState),
1237 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(wall_clk, IntelHDAState),
1238 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_lbase, IntelHDAState),
1239 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_ubase, IntelHDAState),
1240 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_rp, IntelHDAState),
1241 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_wp, IntelHDAState),
1242 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_ctl, IntelHDAState),
1243 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_sts, IntelHDAState),
1244 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(corb_size, IntelHDAState),
1245 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1246 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1247 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_wp, IntelHDAState),
1248 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1249 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1250 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_sts, IntelHDAState),
1251 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_size, IntelHDAState),
1252 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(dp_lbase, IntelHDAState),
1253 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(dp_ubase, IntelHDAState),
1254 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(icw, IntelHDAState),
1255 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(irr, IntelHDAState),
1256 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(ics, IntelHDAState),
1257 d61a4ce8 Gerd Hoffmann
        VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1258 d61a4ce8 Gerd Hoffmann
                             vmstate_intel_hda_stream,
1259 d61a4ce8 Gerd Hoffmann
                             IntelHDAStream),
1260 d61a4ce8 Gerd Hoffmann
1261 d61a4ce8 Gerd Hoffmann
        /* additional state info */
1262 d61a4ce8 Gerd Hoffmann
        VMSTATE_UINT32(rirb_count, IntelHDAState),
1263 d61a4ce8 Gerd Hoffmann
        VMSTATE_INT64(wall_base_ns, IntelHDAState),
1264 d61a4ce8 Gerd Hoffmann
1265 d61a4ce8 Gerd Hoffmann
        VMSTATE_END_OF_LIST()
1266 d61a4ce8 Gerd Hoffmann
    }
1267 d61a4ce8 Gerd Hoffmann
};
1268 d61a4ce8 Gerd Hoffmann
1269 d61a4ce8 Gerd Hoffmann
static PCIDeviceInfo intel_hda_info = {
1270 d61a4ce8 Gerd Hoffmann
    .qdev.name    = "intel-hda",
1271 d61a4ce8 Gerd Hoffmann
    .qdev.desc    = "Intel HD Audio Controller",
1272 d61a4ce8 Gerd Hoffmann
    .qdev.size    = sizeof(IntelHDAState),
1273 d61a4ce8 Gerd Hoffmann
    .qdev.vmsd    = &vmstate_intel_hda,
1274 d61a4ce8 Gerd Hoffmann
    .qdev.reset   = intel_hda_reset,
1275 d61a4ce8 Gerd Hoffmann
    .init         = intel_hda_init,
1276 dc4b9240 Gerd Hoffmann
    .exit         = intel_hda_exit,
1277 17786d52 Gerd Hoffmann
    .config_write = intel_hda_write_config,
1278 d61a4ce8 Gerd Hoffmann
    .qdev.props   = (Property[]) {
1279 d61a4ce8 Gerd Hoffmann
        DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1280 17786d52 Gerd Hoffmann
        DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1281 d61a4ce8 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
1282 d61a4ce8 Gerd Hoffmann
    }
1283 d61a4ce8 Gerd Hoffmann
};
1284 d61a4ce8 Gerd Hoffmann
1285 d61a4ce8 Gerd Hoffmann
static void intel_hda_register(void)
1286 d61a4ce8 Gerd Hoffmann
{
1287 d61a4ce8 Gerd Hoffmann
    pci_qdev_register(&intel_hda_info);
1288 d61a4ce8 Gerd Hoffmann
}
1289 d61a4ce8 Gerd Hoffmann
device_init(intel_hda_register);
1290 d61a4ce8 Gerd Hoffmann
1291 d61a4ce8 Gerd Hoffmann
/*
1292 d61a4ce8 Gerd Hoffmann
 * create intel hda controller with codec attached to it,
1293 d61a4ce8 Gerd Hoffmann
 * so '-soundhw hda' works.
1294 d61a4ce8 Gerd Hoffmann
 */
1295 d61a4ce8 Gerd Hoffmann
int intel_hda_and_codec_init(PCIBus *bus)
1296 d61a4ce8 Gerd Hoffmann
{
1297 d61a4ce8 Gerd Hoffmann
    PCIDevice *controller;
1298 d61a4ce8 Gerd Hoffmann
    BusState *hdabus;
1299 d61a4ce8 Gerd Hoffmann
    DeviceState *codec;
1300 d61a4ce8 Gerd Hoffmann
1301 d61a4ce8 Gerd Hoffmann
    controller = pci_create_simple(bus, -1, "intel-hda");
1302 d61a4ce8 Gerd Hoffmann
    hdabus = QLIST_FIRST(&controller->qdev.child_bus);
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    codec = qdev_create(hdabus, "hda-duplex");
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    qdev_init_nofail(codec);
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    return 0;
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}