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/*
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 * OMAP clocks.
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 *
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 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
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 *
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 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw.h"
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#include "omap.h"
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struct clk {
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    const char *name;
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    const char *alias;
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    struct clk *parent;
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    struct clk *child1;
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    struct clk *sibling;
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#define ALWAYS_ENABLED                (1 << 0)
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#define CLOCK_IN_OMAP310        (1 << 10)
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#define CLOCK_IN_OMAP730        (1 << 11)
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#define CLOCK_IN_OMAP1510        (1 << 12)
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#define CLOCK_IN_OMAP16XX        (1 << 13)
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#define CLOCK_IN_OMAP242X        (1 << 14)
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#define CLOCK_IN_OMAP243X        (1 << 15)
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#define CLOCK_IN_OMAP343X        (1 << 16)
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    uint32_t flags;
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    int id;
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    int running;                /* Is currently ticking */
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    int enabled;                /* Is enabled, regardless of its input clk */
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    unsigned long rate;                /* Current rate (if .running) */
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    unsigned int divisor;        /* Rate relative to input (if .enabled) */
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    unsigned int multiplier;        /* Rate relative to input (if .enabled) */
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    qemu_irq users[16];                /* Who to notify on change */
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    int usecount;                /* Automatically idle when unused */
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};
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static struct clk xtal_osc12m = {
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    .name        = "xtal_osc_12m",
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk xtal_osc32k = {
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    .name        = "xtal_osc_32k",
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    .rate        = 32768,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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};
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static struct clk ck_ref = {
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    .name        = "ck_ref",
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    .alias        = "clkin",
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    .parent        = &xtal_osc12m,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
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static struct clk dpll1 = {
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    .name        = "dpll1",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk dpll2 = {
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    .name        = "dpll2",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
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static struct clk dpll3 = {
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    .name        = "dpll3",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
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static struct clk dpll4 = {
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    .name        = "dpll4",
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    .parent        = &ck_ref,
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    .multiplier        = 4,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk apll = {
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    .name        = "apll",
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    .parent        = &ck_ref,
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    .multiplier        = 48,
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    .divisor        = 12,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk ck_48m = {
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    .name        = "ck_48m",
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    .parent        = &dpll4,        /* either dpll4 or apll */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk ck_dpll1out = {
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    .name        = "ck_dpll1out",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk sossi_ck = {
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    .name        = "ck_sossi",
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    .parent        = &ck_dpll1out,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk clkm1 = {
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    .name        = "clkm1",
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    .alias        = "ck_gen1",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk clkm2 = {
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    .name        = "clkm2",
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    .alias        = "ck_gen2",
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    .parent        = &dpll1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk clkm3 = {
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    .name        = "clkm3",
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    .alias        = "ck_gen3",
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    .parent        = &dpll1,        /* either dpll1 or ck_ref */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk arm_ck = {
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    .name        = "arm_ck",
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    .alias        = "mpu_ck",
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    .parent        = &clkm1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk armper_ck = {
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    .name        = "armper_ck",
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    .alias        = "mpuper_ck",
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    .parent        = &clkm1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk arm_gpio_ck = {
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    .name        = "arm_gpio_ck",
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    .alias        = "mpu_gpio_ck",
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    .parent        = &clkm1,
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    .divisor        = 1,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk armxor_ck = {
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    .name        = "armxor_ck",
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    .alias        = "mpuxor_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk armtim_ck = {
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    .name        = "armtim_ck",
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    .alias        = "mputim_ck",
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    .parent        = &ck_ref,        /* either CLKIN or DPLL1 */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk armwdt_ck = {
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    .name        = "armwdt_ck",
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    .alias        = "mpuwd_ck",
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    .parent        = &clkm1,
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    .divisor        = 14,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk arminth_ck16xx = {
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    .name        = "arminth_ck",
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    .parent        = &arm_ck,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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    /* Note: On 16xx the frequency can be divided by 2 by programming
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     * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
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     *
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     * 1510 version is in TC clocks.
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     */
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};
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static struct clk dsp_ck = {
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    .name        = "dsp_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk dspmmu_ck = {
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    .name        = "dspmmu_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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            ALWAYS_ENABLED,
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};
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static struct clk dspper_ck = {
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    .name        = "dspper_ck",
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    .parent        = &clkm2,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk dspxor_ck = {
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    .name        = "dspxor_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk dsptim_ck = {
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    .name        = "dsptim_ck",
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    .parent        = &ck_ref,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk tc_ck = {
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    .name        = "tc_ck",
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    .parent        = &clkm3,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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            CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk arminth_ck15xx = {
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    .name        = "arminth_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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    /* Note: On 1510 the frequency follows TC_CK
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     *
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     * 16xx version is in MPU clocks.
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     */
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};
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static struct clk tipb_ck = {
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    /* No-idle controlled by "tc_ck" */
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    .name        = "tipb_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
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static struct clk l3_ocpi_ck = {
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    /* No-idle controlled by "tc_ck" */
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    .name        = "l3_ocpi_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk tc1_ck = {
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    .name        = "tc1_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk tc2_ck = {
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    .name        = "tc2_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk dma_ck = {
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    /* No-idle controlled by "tc_ck" */
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    .name        = "dma_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk dma_lcdfree_ck = {
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    .name        = "dma_lcdfree_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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};
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static struct clk api_ck = {
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    .name        = "api_ck",
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    .alias        = "mpui_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk lb_ck = {
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    .name        = "lb_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk lbfree_ck = {
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    .name        = "lbfree_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk hsab_ck = {
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    .name        = "hsab_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk rhea1_ck = {
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    .name        = "rhea1_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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};
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static struct clk rhea2_ck = {
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    .name        = "rhea2_ck",
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    .parent        = &tc_ck,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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};
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static struct clk lcd_ck_16xx = {
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    .name        = "lcd_ck",
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    .parent        = &clkm3,
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    .flags        = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
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};
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static struct clk lcd_ck_1510 = {
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    .name        = "lcd_ck",
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    .parent        = &clkm3,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk uart1_1510 = {
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    .name        = "uart1_ck",
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    /* Direct from ULPD, no real parent */
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    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
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static struct clk uart1_16xx = {
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    .name        = "uart1_ck",
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    /* Direct from ULPD, no real parent */
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    .parent        = &armper_ck,
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    .rate        = 48000000,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk uart2_ck = {
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    .name        = "uart2_ck",
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    /* Direct from ULPD, no real parent */
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    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
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            ALWAYS_ENABLED,
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};
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static struct clk uart3_1510 = {
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    .name        = "uart3_ck",
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    /* Direct from ULPD, no real parent */
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    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
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};
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static struct clk uart3_16xx = {
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    .name        = "uart3_ck",
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    /* Direct from ULPD, no real parent */
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    .parent        = &armper_ck,
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    .rate        = 48000000,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk usb_clk0 = {        /* 6 MHz output on W4_USB_CLK0 */
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    .name        = "usb_clk0",
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    .alias        = "usb.clko",
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    /* Direct from ULPD, no parent */
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    .rate        = 6000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk usb_hhc_ck1510 = {
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    .name        = "usb_hhc_ck",
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    /* Direct from ULPD, no parent */
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    .rate        = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
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};
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static struct clk usb_hhc_ck16xx = {
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    .name        = "usb_hhc_ck",
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    /* Direct from ULPD, no parent */
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    .rate        = 48000000,
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    /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk usb_w2fc_mclk = {
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    .name        = "usb_w2fc_mclk",
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    .alias        = "usb_w2fc_ck",
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    .parent        = &ck_48m,
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    .rate        = 48000000,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk mclk_1510 = {
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    .name        = "mclk",
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    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510,
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};
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static struct clk bclk_310 = {
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    .name        = "bt_mclk_out",        /* Alias midi_mclk_out? */
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    .parent        = &armper_ck,
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    .flags        = CLOCK_IN_OMAP310,
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};
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static struct clk mclk_310 = {
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    .name        = "com_mclk_out",
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    .parent        = &armper_ck,
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    .flags        = CLOCK_IN_OMAP310,
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};
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static struct clk mclk_16xx = {
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    .name        = "mclk",
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    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk bclk_1510 = {
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    .name        = "bclk",
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    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
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    .rate        = 12000000,
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    .flags        = CLOCK_IN_OMAP1510,
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};
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static struct clk bclk_16xx = {
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    .name        = "bclk",
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    /* Direct from ULPD, no parent. May be enabled by ext hardware. */
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk mmc1_ck = {
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    .name        = "mmc_ck",
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    .id                = 1,
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    /* Functional clock is direct from ULPD, interface clock is ARMPER */
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    .parent        = &armper_ck,        /* either armper_ck or dpll4 */
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    .rate        = 48000000,
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    .flags        = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
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};
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static struct clk mmc2_ck = {
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    .name        = "mmc_ck",
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    .id                = 2,
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    /* Functional clock is direct from ULPD, interface clock is ARMPER */
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    .parent        = &armper_ck,
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    .rate        = 48000000,
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    .flags        = CLOCK_IN_OMAP16XX,
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};
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static struct clk cam_mclk = {
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    .name        = "cam.mclk",
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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    .rate        = 12000000,
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};
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static struct clk cam_exclk = {
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    .name        = "cam.exclk",
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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    /* Either 12M from cam.mclk or 48M from dpll4 */
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    .parent        = &cam_mclk,
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};
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static struct clk cam_lclk = {
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    .name        = "cam.lclk",
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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};
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static struct clk i2c_fck = {
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    .name        = "i2c_fck",
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    .id                = 1,
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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            ALWAYS_ENABLED,
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    .parent        = &armxor_ck,
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};
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static struct clk i2c_ick = {
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    .name        = "i2c_ick",
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    .id                = 1,
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    .flags        = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
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    .parent        = &armper_ck,
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};
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static struct clk clk32k = {
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    .name        = "clk32-kHz",
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    .flags        = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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            CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .parent        = &xtal_osc32k,
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};
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static struct clk ref_clk = {
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    .name        = "ref_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 12000000,        /* 12 MHz or 13 MHz or 19.2 MHz */
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    /*.parent        = sys.xtalin */
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};
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static struct clk apll_96m = {
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    .name        = "apll_96m",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 96000000,
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    /*.parent        = ref_clk */
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};
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static struct clk apll_54m = {
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    .name        = "apll_54m",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 54000000,
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    /*.parent        = ref_clk */
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};
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static struct clk sys_clk = {
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    .name        = "sys_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 32768,
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    /*.parent        = sys.xtalin */
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};
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static struct clk sleep_clk = {
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    .name        = "sleep_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 32768,
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    /*.parent        = sys.xtalin */
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};
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static struct clk dpll_ck = {
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    .name        = "dpll",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .parent        = &ref_clk,
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};
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static struct clk dpll_x2_ck = {
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    .name        = "dpll_x2",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .parent        = &ref_clk,
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};
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static struct clk wdt1_sys_clk = {
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    .name        = "wdt1_sys_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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    .rate        = 32768,
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    /*.parent        = sys.xtalin */
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};
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static struct clk func_96m_clk = {
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    .name        = "func_96m_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .divisor        = 1,
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    .parent        = &apll_96m,
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};
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static struct clk func_48m_clk = {
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    .name        = "func_48m_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .divisor        = 2,
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    .parent        = &apll_96m,
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};
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static struct clk func_12m_clk = {
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    .name        = "func_12m_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .divisor        = 8,
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    .parent        = &apll_96m,
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};
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static struct clk func_54m_clk = {
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    .name        = "func_54m_clk",
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    .flags        = CLOCK_IN_OMAP242X,
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    .divisor        = 1,
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    .parent        = &apll_54m,
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};
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static struct clk sys_clkout = {
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    .name        = "clkout",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk sys_clkout2 = {
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    .name        = "clkout2",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_clk = {
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    .name        = "core_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &dpll_x2_ck,        /* Switchable between dpll_ck and clk32k */
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};
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static struct clk l3_clk = {
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    .name        = "l3_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk core_l4_iclk = {
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    .name        = "core_l4_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &l3_clk,
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};
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static struct clk wu_l4_iclk = {
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    .name        = "wu_l4_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &l3_clk,
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};
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static struct clk core_l3_iclk = {
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    .name        = "core_l3_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk core_l4_usb_clk = {
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    .name        = "core_l4_usb_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &l3_clk,
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};
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static struct clk wu_gpt1_clk = {
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    .name        = "wu_gpt1_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk wu_32k_clk = {
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    .name        = "wu_32k_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk uart1_fclk = {
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    .name        = "uart1_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_48m_clk,
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};
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static struct clk uart1_iclk = {
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    .name        = "uart1_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk uart2_fclk = {
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    .name        = "uart2_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_48m_clk,
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};
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static struct clk uart2_iclk = {
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    .name        = "uart2_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk uart3_fclk = {
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    .name        = "uart3_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_48m_clk,
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};
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static struct clk uart3_iclk = {
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    .name        = "uart3_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk mpu_fclk = {
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    .name        = "mpu_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk mpu_iclk = {
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    .name        = "mpu_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk int_m_fclk = {
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    .name        = "int_m_fclk",
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    .alias        = "mpu_intc_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk int_m_iclk = {
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    .name        = "int_m_iclk",
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    .alias        = "mpu_intc_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_clk,
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};
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static struct clk core_gpt2_clk = {
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    .name        = "core_gpt2_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt3_clk = {
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    .name        = "core_gpt3_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt4_clk = {
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    .name        = "core_gpt4_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt5_clk = {
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    .name        = "core_gpt5_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt6_clk = {
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    .name        = "core_gpt6_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt7_clk = {
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    .name        = "core_gpt7_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt8_clk = {
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    .name        = "core_gpt8_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt9_clk = {
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    .name        = "core_gpt9_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt10_clk = {
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    .name        = "core_gpt10_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt11_clk = {
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    .name        = "core_gpt11_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk core_gpt12_clk = {
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    .name        = "core_gpt12_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &sys_clk,
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};
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static struct clk mcbsp1_clk = {
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    .name        = "mcbsp1_cg",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .divisor        = 2,
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    .parent        = &func_96m_clk,
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};
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static struct clk mcbsp2_clk = {
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    .name        = "mcbsp2_cg",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .divisor        = 2,
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    .parent        = &func_96m_clk,
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};
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static struct clk emul_clk = {
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    .name        = "emul_ck",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_54m_clk,
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};
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static struct clk sdma_fclk = {
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    .name        = "sdma_fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &l3_clk,
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};
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static struct clk sdma_iclk = {
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    .name        = "sdma_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l3_iclk, /* core_l4_iclk for the configuration port */
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};
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static struct clk i2c1_fclk = {
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    .name        = "i2c1.fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_12m_clk,
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    .divisor        = 1,
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};
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static struct clk i2c1_iclk = {
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    .name        = "i2c1.iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk i2c2_fclk = {
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    .name        = "i2c2.fclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_12m_clk,
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    .divisor        = 1,
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};
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static struct clk i2c2_iclk = {
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    .name        = "i2c2.iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk gpio_dbclk[4] = {
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    {
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        .name        = "gpio1_dbclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &wu_32k_clk,
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    }, {
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        .name        = "gpio2_dbclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &wu_32k_clk,
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    }, {
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        .name        = "gpio3_dbclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &wu_32k_clk,
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    }, {
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        .name        = "gpio4_dbclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &wu_32k_clk,
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    },
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};
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static struct clk gpio_iclk = {
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    .name        = "gpio_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &wu_l4_iclk,
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};
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static struct clk mmc_fck = {
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    .name        = "mmc_fclk",
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    .flags        = CLOCK_IN_OMAP242X,
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    .parent        = &func_96m_clk,
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};
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static struct clk mmc_ick = {
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    .name        = "mmc_iclk",
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    .flags        = CLOCK_IN_OMAP242X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk spi_fclk[3] = {
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    {
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        .name        = "spi1_fclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &func_48m_clk,
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    }, {
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        .name        = "spi2_fclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &func_48m_clk,
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    }, {
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        .name        = "spi3_fclk",
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        .flags        = CLOCK_IN_OMAP243X,
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        .parent        = &func_48m_clk,
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    },
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};
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static struct clk dss_clk[2] = {
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    {
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        .name        = "dss_clk1",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &core_clk,
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    }, {
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        .name        = "dss_clk2",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &sys_clk,
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    },
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};
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static struct clk dss_54m_clk = {
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    .name        = "dss_54m_clk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &func_54m_clk,
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};
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static struct clk dss_l3_iclk = {
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    .name        = "dss_l3_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l3_iclk,
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};
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static struct clk dss_l4_iclk = {
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    .name        = "dss_l4_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    .parent        = &core_l4_iclk,
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};
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static struct clk spi_iclk[3] = {
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    {
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        .name        = "spi1_iclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &core_l4_iclk,
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    }, {
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        .name        = "spi2_iclk",
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        .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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        .parent        = &core_l4_iclk,
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    }, {
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        .name        = "spi3_iclk",
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        .flags        = CLOCK_IN_OMAP243X,
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        .parent        = &core_l4_iclk,
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    },
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};
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static struct clk omapctrl_clk = {
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    .name        = "omapctrl_iclk",
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    .flags        = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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    /* XXX Should be in WKUP domain */
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    .parent        = &core_l4_iclk,
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};
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static struct clk *onchip_clks[] = {
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    /* OMAP 1 */
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    /* non-ULPD clocks */
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    &xtal_osc12m,
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    &xtal_osc32k,
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    &ck_ref,
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    &dpll1,
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    &dpll2,
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    &dpll3,
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    &dpll4,
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    &apll,
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    &ck_48m,
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    /* CK_GEN1 clocks */
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    &clkm1,
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    &ck_dpll1out,
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    &sossi_ck,
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    &arm_ck,
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    &armper_ck,
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    &arm_gpio_ck,
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    &armxor_ck,
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    &armtim_ck,
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    &armwdt_ck,
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    &arminth_ck15xx,  &arminth_ck16xx,
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    /* CK_GEN2 clocks */
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    &clkm2,
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    &dsp_ck,
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    &dspmmu_ck,
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    &dspper_ck,
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    &dspxor_ck,
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    &dsptim_ck,
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    /* CK_GEN3 clocks */
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    &clkm3,
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    &tc_ck,
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    &tipb_ck,
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    &l3_ocpi_ck,
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    &tc1_ck,
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    &tc2_ck,
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    &dma_ck,
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    &dma_lcdfree_ck,
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    &api_ck,
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    &lb_ck,
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    &lbfree_ck,
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    &hsab_ck,
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    &rhea1_ck,
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    &rhea2_ck,
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    &lcd_ck_16xx,
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    &lcd_ck_1510,
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    /* ULPD clocks */
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    &uart1_1510,
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    &uart1_16xx,
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    &uart2_ck,
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    &uart3_1510,
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    &uart3_16xx,
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    &usb_clk0,
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    &usb_hhc_ck1510, &usb_hhc_ck16xx,
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    &mclk_1510,  &mclk_16xx, &mclk_310,
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    &bclk_1510,  &bclk_16xx, &bclk_310,
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    &mmc1_ck,
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    &mmc2_ck,
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    &cam_mclk,
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    &cam_exclk,
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    &cam_lclk,
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    &clk32k,
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    &usb_w2fc_mclk,
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    /* Virtual clocks */
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    &i2c_fck,
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    &i2c_ick,
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    /* OMAP 2 */
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    &ref_clk,
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    &apll_96m,
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    &apll_54m,
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    &sys_clk,
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    &sleep_clk,
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    &dpll_ck,
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    &dpll_x2_ck,
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    &wdt1_sys_clk,
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    &func_96m_clk,
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    &func_48m_clk,
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    &func_12m_clk,
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    &func_54m_clk,
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    &sys_clkout,
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    &sys_clkout2,
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    &core_clk,
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    &l3_clk,
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    &core_l4_iclk,
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    &wu_l4_iclk,
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    &core_l3_iclk,
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    &core_l4_usb_clk,
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    &wu_gpt1_clk,
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    &wu_32k_clk,
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    &uart1_fclk,
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    &uart1_iclk,
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    &uart2_fclk,
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    &uart2_iclk,
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    &uart3_fclk,
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    &uart3_iclk,
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    &mpu_fclk,
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    &mpu_iclk,
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    &int_m_fclk,
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    &int_m_iclk,
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    &core_gpt2_clk,
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    &core_gpt3_clk,
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    &core_gpt4_clk,
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    &core_gpt5_clk,
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    &core_gpt6_clk,
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    &core_gpt7_clk,
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    &core_gpt8_clk,
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    &core_gpt9_clk,
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    &core_gpt10_clk,
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    &core_gpt11_clk,
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    &core_gpt12_clk,
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    &mcbsp1_clk,
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    &mcbsp2_clk,
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    &emul_clk,
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    &sdma_fclk,
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    &sdma_iclk,
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    &i2c1_fclk,
1066 827df9f3 balrog
    &i2c1_iclk,
1067 827df9f3 balrog
    &i2c2_fclk,
1068 827df9f3 balrog
    &i2c2_iclk,
1069 827df9f3 balrog
    &gpio_dbclk[0],
1070 827df9f3 balrog
    &gpio_dbclk[1],
1071 827df9f3 balrog
    &gpio_dbclk[2],
1072 827df9f3 balrog
    &gpio_dbclk[3],
1073 827df9f3 balrog
    &gpio_iclk,
1074 827df9f3 balrog
    &mmc_fck,
1075 827df9f3 balrog
    &mmc_ick,
1076 827df9f3 balrog
    &spi_fclk[0],
1077 827df9f3 balrog
    &spi_iclk[0],
1078 827df9f3 balrog
    &spi_fclk[1],
1079 827df9f3 balrog
    &spi_iclk[1],
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    &spi_fclk[2],
1081 827df9f3 balrog
    &spi_iclk[2],
1082 827df9f3 balrog
    &dss_clk[0],
1083 827df9f3 balrog
    &dss_clk[1],
1084 827df9f3 balrog
    &dss_54m_clk,
1085 827df9f3 balrog
    &dss_l3_iclk,
1086 827df9f3 balrog
    &dss_l4_iclk,
1087 827df9f3 balrog
    &omapctrl_clk,
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1089 b9d38e95 Blue Swirl
    NULL
1090 c3d2689d balrog
};
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void omap_clk_adduser(struct clk *clk, qemu_irq user)
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{
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    qemu_irq *i;
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1096 c3d2689d balrog
    for (i = clk->users; *i; i ++);
1097 c3d2689d balrog
    *i = user;
1098 c3d2689d balrog
}
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struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1101 c3d2689d balrog
{
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    struct clk *i;
1103 c3d2689d balrog
1104 c3d2689d balrog
    for (i = mpu->clks; i->name; i ++)
1105 c3d2689d balrog
        if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1106 c3d2689d balrog
            return i;
1107 2ac71179 Paul Brook
    hw_error("%s: %s not found\n", __FUNCTION__, name);
1108 c3d2689d balrog
}
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1110 c3d2689d balrog
void omap_clk_get(struct clk *clk)
1111 c3d2689d balrog
{
1112 c3d2689d balrog
    clk->usecount ++;
1113 c3d2689d balrog
}
1114 c3d2689d balrog
1115 c3d2689d balrog
void omap_clk_put(struct clk *clk)
1116 c3d2689d balrog
{
1117 c3d2689d balrog
    if (!(clk->usecount --))
1118 2ac71179 Paul Brook
        hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
1119 c3d2689d balrog
}
1120 c3d2689d balrog
1121 c3d2689d balrog
static void omap_clk_update(struct clk *clk)
1122 c3d2689d balrog
{
1123 c3d2689d balrog
    int parent, running;
1124 c3d2689d balrog
    qemu_irq *user;
1125 c3d2689d balrog
    struct clk *i;
1126 c3d2689d balrog
1127 c3d2689d balrog
    if (clk->parent)
1128 c3d2689d balrog
        parent = clk->parent->running;
1129 c3d2689d balrog
    else
1130 c3d2689d balrog
        parent = 1;
1131 c3d2689d balrog
1132 c3d2689d balrog
    running = parent && (clk->enabled ||
1133 c3d2689d balrog
                    ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
1134 c3d2689d balrog
    if (clk->running != running) {
1135 c3d2689d balrog
        clk->running = running;
1136 c3d2689d balrog
        for (user = clk->users; *user; user ++)
1137 c3d2689d balrog
            qemu_set_irq(*user, running);
1138 c3d2689d balrog
        for (i = clk->child1; i; i = i->sibling)
1139 c3d2689d balrog
            omap_clk_update(i);
1140 c3d2689d balrog
    }
1141 c3d2689d balrog
}
1142 c3d2689d balrog
1143 c3d2689d balrog
static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
1144 c3d2689d balrog
                unsigned long int div, unsigned long int mult)
1145 c3d2689d balrog
{
1146 c3d2689d balrog
    struct clk *i;
1147 c3d2689d balrog
    qemu_irq *user;
1148 c3d2689d balrog
1149 c3d2689d balrog
    clk->rate = muldiv64(rate, mult, div);
1150 c3d2689d balrog
    if (clk->running)
1151 c3d2689d balrog
        for (user = clk->users; *user; user ++)
1152 c3d2689d balrog
            qemu_irq_raise(*user);
1153 c3d2689d balrog
    for (i = clk->child1; i; i = i->sibling)
1154 c3d2689d balrog
        omap_clk_rate_update_full(i, rate,
1155 c3d2689d balrog
                        div * i->divisor, mult * i->multiplier);
1156 c3d2689d balrog
}
1157 c3d2689d balrog
1158 c3d2689d balrog
static void omap_clk_rate_update(struct clk *clk)
1159 c3d2689d balrog
{
1160 c3d2689d balrog
    struct clk *i;
1161 c3d2689d balrog
    unsigned long int div, mult = div = 1;
1162 c3d2689d balrog
1163 c3d2689d balrog
    for (i = clk; i->parent; i = i->parent) {
1164 c3d2689d balrog
        div *= i->divisor;
1165 c3d2689d balrog
        mult *= i->multiplier;
1166 c3d2689d balrog
    }
1167 c3d2689d balrog
1168 c3d2689d balrog
    omap_clk_rate_update_full(clk, i->rate, div, mult);
1169 c3d2689d balrog
}
1170 c3d2689d balrog
1171 c3d2689d balrog
void omap_clk_reparent(struct clk *clk, struct clk *parent)
1172 c3d2689d balrog
{
1173 c3d2689d balrog
    struct clk **p;
1174 c3d2689d balrog
1175 c3d2689d balrog
    if (clk->parent) {
1176 c3d2689d balrog
        for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
1177 c3d2689d balrog
        *p = clk->sibling;
1178 c3d2689d balrog
    }
1179 c3d2689d balrog
1180 c3d2689d balrog
    clk->parent = parent;
1181 c3d2689d balrog
    if (parent) {
1182 c3d2689d balrog
        clk->sibling = parent->child1;
1183 c3d2689d balrog
        parent->child1 = clk;
1184 c3d2689d balrog
        omap_clk_update(clk);
1185 c3d2689d balrog
        omap_clk_rate_update(clk);
1186 c3d2689d balrog
    } else
1187 b9d38e95 Blue Swirl
        clk->sibling = NULL;
1188 c3d2689d balrog
}
1189 c3d2689d balrog
1190 c3d2689d balrog
void omap_clk_onoff(struct clk *clk, int on)
1191 c3d2689d balrog
{
1192 c3d2689d balrog
    clk->enabled = on;
1193 c3d2689d balrog
    omap_clk_update(clk);
1194 c3d2689d balrog
}
1195 c3d2689d balrog
1196 c3d2689d balrog
void omap_clk_canidle(struct clk *clk, int can)
1197 c3d2689d balrog
{
1198 c3d2689d balrog
    if (can)
1199 c3d2689d balrog
        omap_clk_put(clk);
1200 c3d2689d balrog
    else
1201 c3d2689d balrog
        omap_clk_get(clk);
1202 c3d2689d balrog
}
1203 c3d2689d balrog
1204 c3d2689d balrog
void omap_clk_setrate(struct clk *clk, int divide, int multiply)
1205 c3d2689d balrog
{
1206 c3d2689d balrog
    clk->divisor = divide;
1207 c3d2689d balrog
    clk->multiplier = multiply;
1208 c3d2689d balrog
    omap_clk_rate_update(clk);
1209 c3d2689d balrog
}
1210 c3d2689d balrog
1211 c3d2689d balrog
int64_t omap_clk_getrate(omap_clk clk)
1212 c3d2689d balrog
{
1213 c3d2689d balrog
    return clk->rate;
1214 c3d2689d balrog
}
1215 c3d2689d balrog
1216 c3d2689d balrog
void omap_clk_init(struct omap_mpu_state_s *mpu)
1217 c3d2689d balrog
{
1218 c3d2689d balrog
    struct clk **i, *j, *k;
1219 c3d2689d balrog
    int count;
1220 c3d2689d balrog
    int flag;
1221 c3d2689d balrog
1222 c3d2689d balrog
    if (cpu_is_omap310(mpu))
1223 c3d2689d balrog
        flag = CLOCK_IN_OMAP310;
1224 c3d2689d balrog
    else if (cpu_is_omap1510(mpu))
1225 c3d2689d balrog
        flag = CLOCK_IN_OMAP1510;
1226 827df9f3 balrog
    else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
1227 827df9f3 balrog
        flag = CLOCK_IN_OMAP242X;
1228 827df9f3 balrog
    else if (cpu_is_omap2430(mpu))
1229 827df9f3 balrog
        flag = CLOCK_IN_OMAP243X;
1230 827df9f3 balrog
    else if (cpu_is_omap3430(mpu))
1231 827df9f3 balrog
        flag = CLOCK_IN_OMAP243X;
1232 c3d2689d balrog
    else
1233 c3d2689d balrog
        return;
1234 c3d2689d balrog
1235 c3d2689d balrog
    for (i = onchip_clks, count = 0; *i; i ++)
1236 c3d2689d balrog
        if ((*i)->flags & flag)
1237 c3d2689d balrog
            count ++;
1238 c3d2689d balrog
    mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
1239 c3d2689d balrog
    for (i = onchip_clks, j = mpu->clks; *i; i ++)
1240 c3d2689d balrog
        if ((*i)->flags & flag) {
1241 c3d2689d balrog
            memcpy(j, *i, sizeof(struct clk));
1242 c3d2689d balrog
            for (k = mpu->clks; k < j; k ++)
1243 c3d2689d balrog
                if (j->parent && !strcmp(j->parent->name, k->name)) {
1244 c3d2689d balrog
                    j->parent = k;
1245 c3d2689d balrog
                    j->sibling = k->child1;
1246 c3d2689d balrog
                    k->child1 = j;
1247 c3d2689d balrog
                } else if (k->parent && !strcmp(k->parent->name, j->name)) {
1248 c3d2689d balrog
                    k->parent = j;
1249 c3d2689d balrog
                    k->sibling = j->child1;
1250 c3d2689d balrog
                    j->child1 = k;
1251 c3d2689d balrog
                }
1252 c3d2689d balrog
            j->divisor = j->divisor ?: 1;
1253 c3d2689d balrog
            j->multiplier = j->multiplier ?: 1;
1254 c3d2689d balrog
            j ++;
1255 c3d2689d balrog
        }
1256 b854bc19 balrog
    for (j = mpu->clks; count --; j ++) {
1257 b854bc19 balrog
        omap_clk_update(j);
1258 b854bc19 balrog
        omap_clk_rate_update(j);
1259 b854bc19 balrog
    }
1260 c3d2689d balrog
}