Revision e80cfcfc gdbstub.c
b/gdbstub.c | ||
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298 | 298 |
} |
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/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
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registers[64] = tswapl(env->y); |
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tmp = (0<<28) | (4<<24) | env->psr \ |
|
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| (env->psrs? PSR_S : 0) \ |
|
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| (env->psrs? PSR_PS : 0) \ |
|
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| (env->psret? PSR_ET : 0) \ |
|
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| env->cwp; |
|
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tmp = GET_PSR(env); |
|
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registers[65] = tswapl(tmp); |
307 | 303 |
registers[66] = tswapl(env->wim); |
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registers[67] = tswapl(env->tbr); |
... | ... | |
317 | 313 |
|
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static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
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{ |
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uint32_t *registers = (uint32_t *)mem_buf, tmp;
|
|
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uint32_t *registers = (uint32_t *)mem_buf; |
|
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int i; |
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|
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/* fill in g0..g7 */ |
... | ... | |
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} |
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/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
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env->y = tswapl(registers[64]); |
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tmp = tswapl(registers[65]); |
|
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env->psr = tmp & ~PSR_ICC; |
|
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env->psrs = (tmp & PSR_S)? 1 : 0; |
|
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env->psrps = (tmp & PSR_PS)? 1 : 0; |
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env->psret = (tmp & PSR_ET)? 1 : 0; |
|
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env->cwp = (tmp & PSR_CWP); |
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PUT_PSR(env, tswapl(registers[65])); |
|
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env->wim = tswapl(registers[66]); |
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env->tbr = tswapl(registers[67]); |
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env->pc = tswapl(registers[68]); |
... | ... | |
495 | 486 |
/* disable single step if it was enable */ |
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cpu_single_step(cpu_single_env, 0); |
497 | 488 |
|
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if (reason == EXCP_DEBUG) |
|
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if (reason == EXCP_DEBUG) { |
|
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tb_flush(cpu_single_env); |
|
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ret = SIGTRAP; |
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} |
|
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else |
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ret = 0; |
502 | 495 |
snprintf(buf, sizeof(buf), "S%02x", ret); |
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