Revision e80cfcfc hw/sun4m.c
| b/hw/sun4m.c | ||
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| 25 | 25 |
#include "m48t08.h" |
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define MMU_CONTEXT_TBL 0x00003000 |
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#define MMU_L1PTP (MMU_CONTEXT_TBL + 0x0400) |
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#define MMU_L2PTP (MMU_CONTEXT_TBL + 0x0800) |
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#define PROM_ADDR 0xffd04000 |
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#define PROM_ADDR 0xffd00000 |
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#define PROM_FILENAMEB "proll.bin" |
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#define PROM_FILENAMEE "proll.elf" |
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#define PROLL_MAGIC_ADDR 0x20000000 |
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#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */ |
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#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
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#define PHYS_JJ_IDPROM_OFF 0x1FD8 |
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#define PHYS_JJ_EEPROM_SIZE 0x2000 |
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */ |
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// IRQs are not PIL ones, but master interrupt controller register |
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// bits |
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#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
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#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
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#define PHYS_JJ_TCX_0E 0x5E000000 /* Top address, one byte used. */ |
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */ |
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#define PHYS_JJ_LEDMA 0x78400010 /* ledma, off by 10 from unused SCSI */ |
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#define PHYS_JJ_LE 0x78C00000 /* LANCE, typical sun4m */ |
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#define PHYS_JJ_LE_IRQ 6 |
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#define PHYS_JJ_CLOCK 0x71D00000 |
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#define PHYS_JJ_CLOCK_IRQ 10 |
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#define PHYS_JJ_CLOCK1 0x71D10000 |
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#define PHYS_JJ_CLOCK1_IRQ 14 |
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#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */ |
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#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
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#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
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#define PHYS_JJ_LE_IRQ 16 |
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#define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
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#define PHYS_JJ_CLOCK_IRQ 7 |
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#define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
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#define PHYS_JJ_CLOCK1_IRQ 19 |
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#define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
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#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
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#define PHYS_JJ_MS_KBD_IRQ 14 |
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#define PHYS_JJ_SER 0x71100000 /* Serial */ |
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#define PHYS_JJ_SER_IRQ 15 |
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#define PHYS_JJ_SCSI_IRQ 18 |
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#define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
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#define PHYS_JJ_FLOPPY_IRQ 22 |
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/* TSC handling */ |
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| ... | ... | |
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} |
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void DMA_run() {}
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void SB16_run() {}
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int serial_can_receive(SerialState *s) { return 0; }
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void serial_receive_byte(SerialState *s, int ch) {}
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void serial_receive_break(SerialState *s) {}
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static m48t08_t *nvram; |
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static void nvram_init(m48t08_t *nvram, uint8_t *macaddr) |
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{
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unsigned char tmp = 0; |
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int i, j; |
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i = 0x1fd8; |
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m48t08_write(nvram, i++, 0x01); |
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m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
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j = 0; |
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m48t08_write(nvram, i++, macaddr[j++]); |
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m48t08_write(nvram, i++, macaddr[j++]); |
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m48t08_write(nvram, i++, macaddr[j++]); |
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m48t08_write(nvram, i++, macaddr[j++]); |
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m48t08_write(nvram, i++, macaddr[j++]); |
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m48t08_write(nvram, i, macaddr[j]); |
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/* Calculate checksum */ |
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for (i = 0x1fd8; i < 0x1fe7; i++) {
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tmp ^= m48t08_read(nvram, i); |
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} |
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m48t08_write(nvram, 0x1fe7, tmp); |
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} |
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static void *slavio_intctl; |
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void pic_info() |
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{
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slavio_pic_info(slavio_intctl); |
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} |
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void irq_info() |
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{
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slavio_irq_info(slavio_intctl); |
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} |
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void pic_set_irq(int irq, int level) |
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{
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slavio_pic_set_irq(slavio_intctl, irq, level); |
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} |
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static void *tcx; |
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void vga_update_display() |
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{
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tcx_update_display(tcx); |
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} |
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void vga_invalidate_display() |
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{
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tcx_invalidate_display(tcx); |
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} |
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void vga_screen_dump(const char *filename) |
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{
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tcx_screen_dump(tcx, filename); |
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} |
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static void *iommu; |
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uint32_t iommu_translate(uint32_t addr) |
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{
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return iommu_translate_local(iommu, addr); |
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} |
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/* Sun4m hardware initialisation */ |
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void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
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DisplayState *ds, const char **fd_filename, int snapshot, |
| ... | ... | |
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{
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char buf[1024]; |
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int ret, linux_boot; |
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unsigned long bios_offset;
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unsigned long vram_size = 0x100000, prom_offset;
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linux_boot = (kernel_filename != NULL); |
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/* allocate RAM */ |
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cpu_register_physical_memory(0, ram_size, 0); |
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bios_offset = ram_size; |
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iommu_init(PHYS_JJ_IOMMU); |
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sched_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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tcx_init(ds, PHYS_JJ_TCX_FB);
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iommu = iommu_init(PHYS_JJ_IOMMU);
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slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size);
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lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA); |
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE, &nd_table[0].macaddr); |
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timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ); |
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timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
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magic_init(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR, PROLL_MAGIC_ADDR); |
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr); |
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slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
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slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
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slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
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fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
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/* We load Proll as the kernel and start it. It will issue a magic |
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IO to load the real kernel */ |
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if (linux_boot) {
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prom_offset = ram_size + vram_size; |
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); |
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ret = load_elf(buf, phys_ram_base + prom_offset); |
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if (ret < 0) {
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
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ret = load_kernel(buf, |
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phys_ram_base + KERNEL_LOAD_ADDR); |
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ret = load_image(buf, phys_ram_base + prom_offset); |
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} |
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load prom '%s'\n", |
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buf); |
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exit(1); |
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} |
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cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
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prom_offset | IO_MEM_ROM); |
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if (linux_boot) {
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ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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if (ret < 0) |
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ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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if (ret < 0) |
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ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n", |
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buf);
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exit(1);
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kernel_filename);
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exit(1);
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} |
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} |
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/* Setup a MMU entry for entire address space */ |
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stl_raw(phys_ram_base + MMU_CONTEXT_TBL, (MMU_L1PTP >> 4) | 1); |
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stl_raw(phys_ram_base + MMU_L1PTP, (MMU_L2PTP >> 4) | 1); |
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stl_raw(phys_ram_base + MMU_L1PTP + (0x01 << 2), (MMU_L2PTP >> 4) | 1); // 01.. == 00.. |
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stl_raw(phys_ram_base + MMU_L1PTP + (0xff << 2), (MMU_L2PTP >> 4) | 1); // ff.. == 00.. |
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stl_raw(phys_ram_base + MMU_L1PTP + (0xf0 << 2), (MMU_L2PTP >> 4) | 1); // f0.. == 00.. |
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/* 3 = U:RWX S:RWX */ |
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stl_raw(phys_ram_base + MMU_L2PTP, (3 << PTE_ACCESS_SHIFT) | 2); |
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stl_raw(phys_ram_base + MMU_L2PTP, ((0x01 << PTE_PPN_SHIFT) >> 4 ) | (3 << PTE_ACCESS_SHIFT) | 2); |
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| 113 | 184 |
} |
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