root / target-sparc / op_helper.c @ e909ec2f
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#include "exec.h" |
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MMU(fmt, args...)
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#endif
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF_MXCC(fmt, args...)
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#endif
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void raise_exception(int tt) |
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{ |
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env->exception_index = tt; |
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cpu_loop_exit(); |
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} |
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|
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void check_ieee_exceptions()
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{ |
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T0 = get_float_exception_flags(&env->fp_status); |
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if (T0)
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{ |
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/* Copy IEEE 754 flags into FSR */
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if (T0 & float_flag_invalid)
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env->fsr |= FSR_NVC; |
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if (T0 & float_flag_overflow)
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env->fsr |= FSR_OFC; |
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if (T0 & float_flag_underflow)
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env->fsr |= FSR_UFC; |
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if (T0 & float_flag_divbyzero)
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env->fsr |= FSR_DZC; |
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if (T0 & float_flag_inexact)
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env->fsr |= FSR_NXC; |
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) |
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{ |
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/* Unmasked exception, generate a trap */
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env->fsr |= FSR_FTT_IEEE_EXCP; |
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raise_exception(TT_FP_EXCP); |
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} |
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else
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{ |
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/* Accumulate exceptions */
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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} |
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} |
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} |
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
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FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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|
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void do_fitod(void) |
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{ |
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DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
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} |
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#endif
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void do_fabss(void) |
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{ |
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FT0 = float32_abs(FT1); |
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} |
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#ifdef TARGET_SPARC64
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void do_fabsd(void) |
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{ |
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DT0 = float64_abs(DT1); |
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} |
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#endif
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void do_fsqrts(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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void do_fsqrtd(void) |
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{ |
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set_float_exception_flags(0, &env->fp_status);
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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check_ieee_exceptions(); |
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} |
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#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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void glue(do_, name) (void) \ |
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{ \ |
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
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if ((env->fsr & FSR_NVM) || TRAP) { \
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env->fsr |= T0; \ |
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env->fsr |= FSR_NVC; \ |
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env->fsr |= FSR_FTT_IEEE_EXCP; \ |
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raise_exception(TT_FP_EXCP); \ |
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} else { \
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env->fsr |= FSR_NVA; \ |
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} \ |
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break; \
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case float_relation_less: \
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T0 = FSR_FCC0 << FS; \ |
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break; \
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case float_relation_greater: \
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T0 = FSR_FCC1 << FS; \ |
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break; \
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default: \
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T0 = 0; \
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break; \
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} \ |
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env->fsr |= T0; \ |
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} |
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GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
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|
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GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
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#ifdef TARGET_SPARC64
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
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|
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GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
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GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
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GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
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#endif
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
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#ifdef DEBUG_MXCC
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static void dump_mxcc(CPUState *env) |
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{ |
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printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
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printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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" %016llx %016llx %016llx %016llx\n",
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env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
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env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
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} |
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#endif
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void helper_ld_asi(int asi, int size, int sign) |
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{ |
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uint32_t ret = 0;
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uint64_t tmp; |
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#ifdef DEBUG_MXCC
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uint32_t last_T0 = T0; |
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#endif
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switch (asi) {
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case 2: /* SuperSparc MXCC registers */ |
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switch (T0) {
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case 0x01c00a00: /* MXCC control register */ |
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if (size == 8) { |
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ret = env->mxccregs[3];
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T0 = env->mxccregs[3] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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case 0x01c00a04: /* MXCC control register */ |
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if (size == 4) |
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ret = env->mxccregs[3];
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else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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case 0x01c00f00: /* MBus port address register */ |
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if (size == 8) { |
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ret = env->mxccregs[7];
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T0 = env->mxccregs[7] >> 32; |
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} else
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DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
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break;
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default:
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DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
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break;
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} |
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DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
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"T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
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#ifdef DEBUG_MXCC
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dump_mxcc(env); |
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#endif
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break;
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case 3: /* MMU probe */ |
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{ |
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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if (mmulev > 4) |
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ret = 0;
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else {
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ret = mmu_probe(env, T0, mmulev); |
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//bswap32s(&ret);
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} |
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DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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} |
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break;
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case 4: /* read MMU regs */ |
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{ |
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int reg = (T0 >> 8) & 0xf; |
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ret = env->mmuregs[reg]; |
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if (reg == 3) /* Fault status cleared on read */ |
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env->mmuregs[reg] = 0;
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DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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} |
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break;
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case 9: /* Supervisor code access */ |
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switch(size) {
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case 1: |
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ret = ldub_code(T0); |
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break;
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case 2: |
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ret = lduw_code(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_code(T0 & ~3);
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break;
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case 8: |
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tmp = ldq_code(T0 & ~7);
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ret = tmp >> 32;
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T0 = tmp & 0xffffffff;
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break;
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} |
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break;
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case 0xa: /* User data access */ |
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switch(size) {
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case 1: |
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ret = ldub_user(T0); |
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break;
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case 2: |
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ret = lduw_user(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_user(T0 & ~3);
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break;
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case 8: |
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tmp = ldq_user(T0 & ~7);
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ret = tmp >> 32;
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T0 = tmp & 0xffffffff;
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break;
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} |
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break;
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case 0xb: /* Supervisor data access */ |
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switch(size) {
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case 1: |
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ret = ldub_kernel(T0); |
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break;
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case 2: |
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ret = lduw_kernel(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_kernel(T0 & ~3);
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break;
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case 8: |
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tmp = ldq_kernel(T0 & ~7);
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ret = tmp >> 32;
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T0 = tmp & 0xffffffff;
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break;
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} |
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break;
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case 0xc: /* I-cache tag */ |
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case 0xd: /* I-cache data */ |
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case 0xe: /* D-cache tag */ |
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case 0xf: /* D-cache data */ |
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break;
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case 0x20: /* MMU passthrough */ |
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switch(size) {
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case 1: |
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ret = ldub_phys(T0); |
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break;
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case 2: |
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ret = lduw_phys(T0 & ~1);
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break;
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default:
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case 4: |
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ret = ldl_phys(T0 & ~3);
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break;
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case 8: |
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tmp = ldq_phys(T0 & ~7);
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ret = tmp >> 32;
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T0 = tmp & 0xffffffff;
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break;
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} |
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break;
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case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
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case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
318 |
switch(size) {
|
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case 1: |
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ret = ldub_phys((target_phys_addr_t)T0 |
321 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
322 |
break;
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case 2: |
324 |
ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
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| ((target_phys_addr_t)(asi & 0xf) << 32)); |
326 |
break;
|
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default:
|
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case 4: |
329 |
ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
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| ((target_phys_addr_t)(asi & 0xf) << 32)); |
331 |
break;
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332 |
case 8: |
333 |
tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
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| ((target_phys_addr_t)(asi & 0xf) << 32)); |
335 |
ret = tmp >> 32;
|
336 |
T0 = tmp & 0xffffffff;
|
337 |
break;
|
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} |
339 |
break;
|
340 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
341 |
default:
|
342 |
do_unassigned_access(T0, 0, 0, 1); |
343 |
ret = 0;
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break;
|
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} |
346 |
if (sign) {
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347 |
switch(size) {
|
348 |
case 1: |
349 |
T1 = (int8_t) ret; |
350 |
break;
|
351 |
case 2: |
352 |
T1 = (int16_t) ret; |
353 |
break;
|
354 |
default:
|
355 |
T1 = ret; |
356 |
break;
|
357 |
} |
358 |
} |
359 |
else
|
360 |
T1 = ret; |
361 |
} |
362 |
|
363 |
void helper_st_asi(int asi, int size) |
364 |
{ |
365 |
switch(asi) {
|
366 |
case 2: /* SuperSparc MXCC registers */ |
367 |
switch (T0) {
|
368 |
case 0x01c00000: /* MXCC stream data register 0 */ |
369 |
if (size == 8) |
370 |
env->mxccdata[0] = ((uint64_t)T1 << 32) | T2; |
371 |
else
|
372 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
373 |
break;
|
374 |
case 0x01c00008: /* MXCC stream data register 1 */ |
375 |
if (size == 8) |
376 |
env->mxccdata[1] = ((uint64_t)T1 << 32) | T2; |
377 |
else
|
378 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
379 |
break;
|
380 |
case 0x01c00010: /* MXCC stream data register 2 */ |
381 |
if (size == 8) |
382 |
env->mxccdata[2] = ((uint64_t)T1 << 32) | T2; |
383 |
else
|
384 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
385 |
break;
|
386 |
case 0x01c00018: /* MXCC stream data register 3 */ |
387 |
if (size == 8) |
388 |
env->mxccdata[3] = ((uint64_t)T1 << 32) | T2; |
389 |
else
|
390 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
391 |
break;
|
392 |
case 0x01c00100: /* MXCC stream source */ |
393 |
if (size == 8) |
394 |
env->mxccregs[0] = ((uint64_t)T1 << 32) | T2; |
395 |
else
|
396 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
397 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
398 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
399 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
400 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
401 |
break;
|
402 |
case 0x01c00200: /* MXCC stream destination */ |
403 |
if (size == 8) |
404 |
env->mxccregs[1] = ((uint64_t)T1 << 32) | T2; |
405 |
else
|
406 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
407 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
408 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
409 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
410 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
411 |
break;
|
412 |
case 0x01c00a00: /* MXCC control register */ |
413 |
if (size == 8) |
414 |
env->mxccregs[3] = ((uint64_t)T1 << 32) | T2; |
415 |
else
|
416 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
417 |
break;
|
418 |
case 0x01c00a04: /* MXCC control register */ |
419 |
if (size == 4) |
420 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1; |
421 |
else
|
422 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
423 |
break;
|
424 |
case 0x01c00e00: /* MXCC error register */ |
425 |
if (size == 8) |
426 |
env->mxccregs[6] = ((uint64_t)T1 << 32) | T2; |
427 |
else
|
428 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
429 |
if (env->mxccregs[6] == 0xffffffffffffffffULL) { |
430 |
// this is probably a reset
|
431 |
} |
432 |
break;
|
433 |
case 0x01c00f00: /* MBus port address register */ |
434 |
if (size == 8) |
435 |
env->mxccregs[7] = ((uint64_t)T1 << 32) | T2; |
436 |
else
|
437 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
|
438 |
break;
|
439 |
default:
|
440 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
|
441 |
break;
|
442 |
} |
443 |
DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
|
444 |
#ifdef DEBUG_MXCC
|
445 |
dump_mxcc(env); |
446 |
#endif
|
447 |
break;
|
448 |
case 3: /* MMU flush */ |
449 |
{ |
450 |
int mmulev;
|
451 |
|
452 |
mmulev = (T0 >> 8) & 15; |
453 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
454 |
switch (mmulev) {
|
455 |
case 0: // flush page |
456 |
tlb_flush_page(env, T0 & 0xfffff000);
|
457 |
break;
|
458 |
case 1: // flush segment (256k) |
459 |
case 2: // flush region (16M) |
460 |
case 3: // flush context (4G) |
461 |
case 4: // flush entire |
462 |
tlb_flush(env, 1);
|
463 |
break;
|
464 |
default:
|
465 |
break;
|
466 |
} |
467 |
#ifdef DEBUG_MMU
|
468 |
dump_mmu(env); |
469 |
#endif
|
470 |
return;
|
471 |
} |
472 |
case 4: /* write MMU regs */ |
473 |
{ |
474 |
int reg = (T0 >> 8) & 0xf; |
475 |
uint32_t oldreg; |
476 |
|
477 |
oldreg = env->mmuregs[reg]; |
478 |
switch(reg) {
|
479 |
case 0: |
480 |
env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); |
481 |
env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); |
482 |
// Mappings generated during no-fault mode or MMU
|
483 |
// disabled mode are invalid in normal mode
|
484 |
if (oldreg != env->mmuregs[reg])
|
485 |
tlb_flush(env, 1);
|
486 |
break;
|
487 |
case 2: |
488 |
env->mmuregs[reg] = T1; |
489 |
if (oldreg != env->mmuregs[reg]) {
|
490 |
/* we flush when the MMU context changes because
|
491 |
QEMU has no MMU context support */
|
492 |
tlb_flush(env, 1);
|
493 |
} |
494 |
break;
|
495 |
case 3: |
496 |
case 4: |
497 |
break;
|
498 |
default:
|
499 |
env->mmuregs[reg] = T1; |
500 |
break;
|
501 |
} |
502 |
if (oldreg != env->mmuregs[reg]) {
|
503 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
504 |
} |
505 |
#ifdef DEBUG_MMU
|
506 |
dump_mmu(env); |
507 |
#endif
|
508 |
return;
|
509 |
} |
510 |
case 0xa: /* User data access */ |
511 |
switch(size) {
|
512 |
case 1: |
513 |
stb_user(T0, T1); |
514 |
break;
|
515 |
case 2: |
516 |
stw_user(T0 & ~1, T1);
|
517 |
break;
|
518 |
default:
|
519 |
case 4: |
520 |
stl_user(T0 & ~3, T1);
|
521 |
break;
|
522 |
case 8: |
523 |
stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
524 |
break;
|
525 |
} |
526 |
break;
|
527 |
case 0xb: /* Supervisor data access */ |
528 |
switch(size) {
|
529 |
case 1: |
530 |
stb_kernel(T0, T1); |
531 |
break;
|
532 |
case 2: |
533 |
stw_kernel(T0 & ~1, T1);
|
534 |
break;
|
535 |
default:
|
536 |
case 4: |
537 |
stl_kernel(T0 & ~3, T1);
|
538 |
break;
|
539 |
case 8: |
540 |
stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
541 |
break;
|
542 |
} |
543 |
break;
|
544 |
case 0xc: /* I-cache tag */ |
545 |
case 0xd: /* I-cache data */ |
546 |
case 0xe: /* D-cache tag */ |
547 |
case 0xf: /* D-cache data */ |
548 |
case 0x10: /* I/D-cache flush page */ |
549 |
case 0x11: /* I/D-cache flush segment */ |
550 |
case 0x12: /* I/D-cache flush region */ |
551 |
case 0x13: /* I/D-cache flush context */ |
552 |
case 0x14: /* I/D-cache flush user */ |
553 |
break;
|
554 |
case 0x17: /* Block copy, sta access */ |
555 |
{ |
556 |
// value (T1) = src
|
557 |
// address (T0) = dst
|
558 |
// copy 32 bytes
|
559 |
unsigned int i; |
560 |
uint32_t src = T1 & ~3, dst = T0 & ~3, temp; |
561 |
|
562 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
563 |
temp = ldl_kernel(src); |
564 |
stl_kernel(dst, temp); |
565 |
} |
566 |
} |
567 |
return;
|
568 |
case 0x1f: /* Block fill, stda access */ |
569 |
{ |
570 |
// value (T1, T2)
|
571 |
// address (T0) = dst
|
572 |
// fill 32 bytes
|
573 |
unsigned int i; |
574 |
uint32_t dst = T0 & 7;
|
575 |
uint64_t val; |
576 |
|
577 |
val = (((uint64_t)T1) << 32) | T2;
|
578 |
|
579 |
for (i = 0; i < 32; i += 8, dst += 8) |
580 |
stq_kernel(dst, val); |
581 |
} |
582 |
return;
|
583 |
case 0x20: /* MMU passthrough */ |
584 |
{ |
585 |
switch(size) {
|
586 |
case 1: |
587 |
stb_phys(T0, T1); |
588 |
break;
|
589 |
case 2: |
590 |
stw_phys(T0 & ~1, T1);
|
591 |
break;
|
592 |
case 4: |
593 |
default:
|
594 |
stl_phys(T0 & ~3, T1);
|
595 |
break;
|
596 |
case 8: |
597 |
stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2); |
598 |
break;
|
599 |
} |
600 |
} |
601 |
return;
|
602 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
603 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
604 |
{ |
605 |
switch(size) {
|
606 |
case 1: |
607 |
stb_phys((target_phys_addr_t)T0 |
608 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
609 |
break;
|
610 |
case 2: |
611 |
stw_phys((target_phys_addr_t)(T0 & ~1)
|
612 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
613 |
break;
|
614 |
case 4: |
615 |
default:
|
616 |
stl_phys((target_phys_addr_t)(T0 & ~3)
|
617 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
618 |
break;
|
619 |
case 8: |
620 |
stq_phys((target_phys_addr_t)(T0 & ~7)
|
621 |
| ((target_phys_addr_t)(asi & 0xf) << 32), |
622 |
((uint64_t)T1 << 32) | T2);
|
623 |
break;
|
624 |
} |
625 |
} |
626 |
return;
|
627 |
case 0x31: /* Ross RT620 I-cache flush */ |
628 |
case 0x36: /* I-cache flash clear */ |
629 |
case 0x37: /* D-cache flash clear */ |
630 |
break;
|
631 |
case 9: /* Supervisor code access, XXX */ |
632 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
633 |
default:
|
634 |
do_unassigned_access(T0, 1, 0, 1); |
635 |
return;
|
636 |
} |
637 |
} |
638 |
|
639 |
#endif /* CONFIG_USER_ONLY */ |
640 |
#else /* TARGET_SPARC64 */ |
641 |
|
642 |
#ifdef CONFIG_USER_ONLY
|
643 |
void helper_ld_asi(int asi, int size, int sign) |
644 |
{ |
645 |
uint64_t ret = 0;
|
646 |
|
647 |
if (asi < 0x80) |
648 |
raise_exception(TT_PRIV_ACT); |
649 |
|
650 |
switch (asi) {
|
651 |
case 0x80: // Primary |
652 |
case 0x82: // Primary no-fault |
653 |
case 0x88: // Primary LE |
654 |
case 0x8a: // Primary no-fault LE |
655 |
{ |
656 |
switch(size) {
|
657 |
case 1: |
658 |
ret = ldub_raw(T0); |
659 |
break;
|
660 |
case 2: |
661 |
ret = lduw_raw(T0 & ~1);
|
662 |
break;
|
663 |
case 4: |
664 |
ret = ldl_raw(T0 & ~3);
|
665 |
break;
|
666 |
default:
|
667 |
case 8: |
668 |
ret = ldq_raw(T0 & ~7);
|
669 |
break;
|
670 |
} |
671 |
} |
672 |
break;
|
673 |
case 0x81: // Secondary |
674 |
case 0x83: // Secondary no-fault |
675 |
case 0x89: // Secondary LE |
676 |
case 0x8b: // Secondary no-fault LE |
677 |
// XXX
|
678 |
break;
|
679 |
default:
|
680 |
break;
|
681 |
} |
682 |
|
683 |
/* Convert from little endian */
|
684 |
switch (asi) {
|
685 |
case 0x88: // Primary LE |
686 |
case 0x89: // Secondary LE |
687 |
case 0x8a: // Primary no-fault LE |
688 |
case 0x8b: // Secondary no-fault LE |
689 |
switch(size) {
|
690 |
case 2: |
691 |
ret = bswap16(ret); |
692 |
break;
|
693 |
case 4: |
694 |
ret = bswap32(ret); |
695 |
break;
|
696 |
case 8: |
697 |
ret = bswap64(ret); |
698 |
break;
|
699 |
default:
|
700 |
break;
|
701 |
} |
702 |
default:
|
703 |
break;
|
704 |
} |
705 |
|
706 |
/* Convert to signed number */
|
707 |
if (sign) {
|
708 |
switch(size) {
|
709 |
case 1: |
710 |
ret = (int8_t) ret; |
711 |
break;
|
712 |
case 2: |
713 |
ret = (int16_t) ret; |
714 |
break;
|
715 |
case 4: |
716 |
ret = (int32_t) ret; |
717 |
break;
|
718 |
default:
|
719 |
break;
|
720 |
} |
721 |
} |
722 |
T1 = ret; |
723 |
} |
724 |
|
725 |
void helper_st_asi(int asi, int size) |
726 |
{ |
727 |
if (asi < 0x80) |
728 |
raise_exception(TT_PRIV_ACT); |
729 |
|
730 |
/* Convert to little endian */
|
731 |
switch (asi) {
|
732 |
case 0x88: // Primary LE |
733 |
case 0x89: // Secondary LE |
734 |
switch(size) {
|
735 |
case 2: |
736 |
T0 = bswap16(T0); |
737 |
break;
|
738 |
case 4: |
739 |
T0 = bswap32(T0); |
740 |
break;
|
741 |
case 8: |
742 |
T0 = bswap64(T0); |
743 |
break;
|
744 |
default:
|
745 |
break;
|
746 |
} |
747 |
default:
|
748 |
break;
|
749 |
} |
750 |
|
751 |
switch(asi) {
|
752 |
case 0x80: // Primary |
753 |
case 0x88: // Primary LE |
754 |
{ |
755 |
switch(size) {
|
756 |
case 1: |
757 |
stb_raw(T0, T1); |
758 |
break;
|
759 |
case 2: |
760 |
stw_raw(T0 & ~1, T1);
|
761 |
break;
|
762 |
case 4: |
763 |
stl_raw(T0 & ~3, T1);
|
764 |
break;
|
765 |
case 8: |
766 |
default:
|
767 |
stq_raw(T0 & ~7, T1);
|
768 |
break;
|
769 |
} |
770 |
} |
771 |
break;
|
772 |
case 0x81: // Secondary |
773 |
case 0x89: // Secondary LE |
774 |
// XXX
|
775 |
return;
|
776 |
|
777 |
case 0x82: // Primary no-fault, RO |
778 |
case 0x83: // Secondary no-fault, RO |
779 |
case 0x8a: // Primary no-fault LE, RO |
780 |
case 0x8b: // Secondary no-fault LE, RO |
781 |
default:
|
782 |
do_unassigned_access(T0, 1, 0, 1); |
783 |
return;
|
784 |
} |
785 |
} |
786 |
|
787 |
#else /* CONFIG_USER_ONLY */ |
788 |
|
789 |
void helper_ld_asi(int asi, int size, int sign) |
790 |
{ |
791 |
uint64_t ret = 0;
|
792 |
|
793 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
794 |
|| (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) |
795 |
raise_exception(TT_PRIV_ACT); |
796 |
|
797 |
switch (asi) {
|
798 |
case 0x10: // As if user primary |
799 |
case 0x18: // As if user primary LE |
800 |
case 0x80: // Primary |
801 |
case 0x82: // Primary no-fault |
802 |
case 0x88: // Primary LE |
803 |
case 0x8a: // Primary no-fault LE |
804 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
805 |
if (env->hpstate & HS_PRIV) {
|
806 |
switch(size) {
|
807 |
case 1: |
808 |
ret = ldub_hypv(T0); |
809 |
break;
|
810 |
case 2: |
811 |
ret = lduw_hypv(T0 & ~1);
|
812 |
break;
|
813 |
case 4: |
814 |
ret = ldl_hypv(T0 & ~3);
|
815 |
break;
|
816 |
default:
|
817 |
case 8: |
818 |
ret = ldq_hypv(T0 & ~7);
|
819 |
break;
|
820 |
} |
821 |
} else {
|
822 |
switch(size) {
|
823 |
case 1: |
824 |
ret = ldub_kernel(T0); |
825 |
break;
|
826 |
case 2: |
827 |
ret = lduw_kernel(T0 & ~1);
|
828 |
break;
|
829 |
case 4: |
830 |
ret = ldl_kernel(T0 & ~3);
|
831 |
break;
|
832 |
default:
|
833 |
case 8: |
834 |
ret = ldq_kernel(T0 & ~7);
|
835 |
break;
|
836 |
} |
837 |
} |
838 |
} else {
|
839 |
switch(size) {
|
840 |
case 1: |
841 |
ret = ldub_user(T0); |
842 |
break;
|
843 |
case 2: |
844 |
ret = lduw_user(T0 & ~1);
|
845 |
break;
|
846 |
case 4: |
847 |
ret = ldl_user(T0 & ~3);
|
848 |
break;
|
849 |
default:
|
850 |
case 8: |
851 |
ret = ldq_user(T0 & ~7);
|
852 |
break;
|
853 |
} |
854 |
} |
855 |
break;
|
856 |
case 0x14: // Bypass |
857 |
case 0x15: // Bypass, non-cacheable |
858 |
case 0x1c: // Bypass LE |
859 |
case 0x1d: // Bypass, non-cacheable LE |
860 |
{ |
861 |
switch(size) {
|
862 |
case 1: |
863 |
ret = ldub_phys(T0); |
864 |
break;
|
865 |
case 2: |
866 |
ret = lduw_phys(T0 & ~1);
|
867 |
break;
|
868 |
case 4: |
869 |
ret = ldl_phys(T0 & ~3);
|
870 |
break;
|
871 |
default:
|
872 |
case 8: |
873 |
ret = ldq_phys(T0 & ~7);
|
874 |
break;
|
875 |
} |
876 |
break;
|
877 |
} |
878 |
case 0x04: // Nucleus |
879 |
case 0x0c: // Nucleus Little Endian (LE) |
880 |
case 0x11: // As if user secondary |
881 |
case 0x19: // As if user secondary LE |
882 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
883 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
884 |
case 0x4a: // UPA config |
885 |
case 0x81: // Secondary |
886 |
case 0x83: // Secondary no-fault |
887 |
case 0x89: // Secondary LE |
888 |
case 0x8b: // Secondary no-fault LE |
889 |
// XXX
|
890 |
break;
|
891 |
case 0x45: // LSU |
892 |
ret = env->lsu; |
893 |
break;
|
894 |
case 0x50: // I-MMU regs |
895 |
{ |
896 |
int reg = (T0 >> 3) & 0xf; |
897 |
|
898 |
ret = env->immuregs[reg]; |
899 |
break;
|
900 |
} |
901 |
case 0x51: // I-MMU 8k TSB pointer |
902 |
case 0x52: // I-MMU 64k TSB pointer |
903 |
case 0x55: // I-MMU data access |
904 |
// XXX
|
905 |
break;
|
906 |
case 0x56: // I-MMU tag read |
907 |
{ |
908 |
unsigned int i; |
909 |
|
910 |
for (i = 0; i < 64; i++) { |
911 |
// Valid, ctx match, vaddr match
|
912 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
913 |
env->itlb_tag[i] == T0) { |
914 |
ret = env->itlb_tag[i]; |
915 |
break;
|
916 |
} |
917 |
} |
918 |
break;
|
919 |
} |
920 |
case 0x58: // D-MMU regs |
921 |
{ |
922 |
int reg = (T0 >> 3) & 0xf; |
923 |
|
924 |
ret = env->dmmuregs[reg]; |
925 |
break;
|
926 |
} |
927 |
case 0x5e: // D-MMU tag read |
928 |
{ |
929 |
unsigned int i; |
930 |
|
931 |
for (i = 0; i < 64; i++) { |
932 |
// Valid, ctx match, vaddr match
|
933 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
934 |
env->dtlb_tag[i] == T0) { |
935 |
ret = env->dtlb_tag[i]; |
936 |
break;
|
937 |
} |
938 |
} |
939 |
break;
|
940 |
} |
941 |
case 0x59: // D-MMU 8k TSB pointer |
942 |
case 0x5a: // D-MMU 64k TSB pointer |
943 |
case 0x5b: // D-MMU data pointer |
944 |
case 0x5d: // D-MMU data access |
945 |
case 0x48: // Interrupt dispatch, RO |
946 |
case 0x49: // Interrupt data receive |
947 |
case 0x7f: // Incoming interrupt vector, RO |
948 |
// XXX
|
949 |
break;
|
950 |
case 0x54: // I-MMU data in, WO |
951 |
case 0x57: // I-MMU demap, WO |
952 |
case 0x5c: // D-MMU data in, WO |
953 |
case 0x5f: // D-MMU demap, WO |
954 |
case 0x77: // Interrupt vector, WO |
955 |
default:
|
956 |
do_unassigned_access(T0, 0, 0, 1); |
957 |
ret = 0;
|
958 |
break;
|
959 |
} |
960 |
|
961 |
/* Convert from little endian */
|
962 |
switch (asi) {
|
963 |
case 0x0c: // Nucleus Little Endian (LE) |
964 |
case 0x18: // As if user primary LE |
965 |
case 0x19: // As if user secondary LE |
966 |
case 0x1c: // Bypass LE |
967 |
case 0x1d: // Bypass, non-cacheable LE |
968 |
case 0x88: // Primary LE |
969 |
case 0x89: // Secondary LE |
970 |
case 0x8a: // Primary no-fault LE |
971 |
case 0x8b: // Secondary no-fault LE |
972 |
switch(size) {
|
973 |
case 2: |
974 |
ret = bswap16(ret); |
975 |
break;
|
976 |
case 4: |
977 |
ret = bswap32(ret); |
978 |
break;
|
979 |
case 8: |
980 |
ret = bswap64(ret); |
981 |
break;
|
982 |
default:
|
983 |
break;
|
984 |
} |
985 |
default:
|
986 |
break;
|
987 |
} |
988 |
|
989 |
/* Convert to signed number */
|
990 |
if (sign) {
|
991 |
switch(size) {
|
992 |
case 1: |
993 |
ret = (int8_t) ret; |
994 |
break;
|
995 |
case 2: |
996 |
ret = (int16_t) ret; |
997 |
break;
|
998 |
case 4: |
999 |
ret = (int32_t) ret; |
1000 |
break;
|
1001 |
default:
|
1002 |
break;
|
1003 |
} |
1004 |
} |
1005 |
T1 = ret; |
1006 |
} |
1007 |
|
1008 |
void helper_st_asi(int asi, int size) |
1009 |
{ |
1010 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1011 |
|| (asi >= 0x30 && asi < 0x80) && !(env->hpstate & HS_PRIV)) |
1012 |
raise_exception(TT_PRIV_ACT); |
1013 |
|
1014 |
/* Convert to little endian */
|
1015 |
switch (asi) {
|
1016 |
case 0x0c: // Nucleus Little Endian (LE) |
1017 |
case 0x18: // As if user primary LE |
1018 |
case 0x19: // As if user secondary LE |
1019 |
case 0x1c: // Bypass LE |
1020 |
case 0x1d: // Bypass, non-cacheable LE |
1021 |
case 0x88: // Primary LE |
1022 |
case 0x89: // Secondary LE |
1023 |
switch(size) {
|
1024 |
case 2: |
1025 |
T0 = bswap16(T0); |
1026 |
break;
|
1027 |
case 4: |
1028 |
T0 = bswap32(T0); |
1029 |
break;
|
1030 |
case 8: |
1031 |
T0 = bswap64(T0); |
1032 |
break;
|
1033 |
default:
|
1034 |
break;
|
1035 |
} |
1036 |
default:
|
1037 |
break;
|
1038 |
} |
1039 |
|
1040 |
switch(asi) {
|
1041 |
case 0x10: // As if user primary |
1042 |
case 0x18: // As if user primary LE |
1043 |
case 0x80: // Primary |
1044 |
case 0x88: // Primary LE |
1045 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1046 |
if (env->hpstate & HS_PRIV) {
|
1047 |
switch(size) {
|
1048 |
case 1: |
1049 |
stb_hypv(T0, T1); |
1050 |
break;
|
1051 |
case 2: |
1052 |
stw_hypv(T0 & ~1, T1);
|
1053 |
break;
|
1054 |
case 4: |
1055 |
stl_hypv(T0 & ~3, T1);
|
1056 |
break;
|
1057 |
case 8: |
1058 |
default:
|
1059 |
stq_hypv(T0 & ~7, T1);
|
1060 |
break;
|
1061 |
} |
1062 |
} else {
|
1063 |
switch(size) {
|
1064 |
case 1: |
1065 |
stb_kernel(T0, T1); |
1066 |
break;
|
1067 |
case 2: |
1068 |
stw_kernel(T0 & ~1, T1);
|
1069 |
break;
|
1070 |
case 4: |
1071 |
stl_kernel(T0 & ~3, T1);
|
1072 |
break;
|
1073 |
case 8: |
1074 |
default:
|
1075 |
stq_kernel(T0 & ~7, T1);
|
1076 |
break;
|
1077 |
} |
1078 |
} |
1079 |
} else {
|
1080 |
switch(size) {
|
1081 |
case 1: |
1082 |
stb_user(T0, T1); |
1083 |
break;
|
1084 |
case 2: |
1085 |
stw_user(T0 & ~1, T1);
|
1086 |
break;
|
1087 |
case 4: |
1088 |
stl_user(T0 & ~3, T1);
|
1089 |
break;
|
1090 |
case 8: |
1091 |
default:
|
1092 |
stq_user(T0 & ~7, T1);
|
1093 |
break;
|
1094 |
} |
1095 |
} |
1096 |
break;
|
1097 |
case 0x14: // Bypass |
1098 |
case 0x15: // Bypass, non-cacheable |
1099 |
case 0x1c: // Bypass LE |
1100 |
case 0x1d: // Bypass, non-cacheable LE |
1101 |
{ |
1102 |
switch(size) {
|
1103 |
case 1: |
1104 |
stb_phys(T0, T1); |
1105 |
break;
|
1106 |
case 2: |
1107 |
stw_phys(T0 & ~1, T1);
|
1108 |
break;
|
1109 |
case 4: |
1110 |
stl_phys(T0 & ~3, T1);
|
1111 |
break;
|
1112 |
case 8: |
1113 |
default:
|
1114 |
stq_phys(T0 & ~7, T1);
|
1115 |
break;
|
1116 |
} |
1117 |
} |
1118 |
return;
|
1119 |
case 0x04: // Nucleus |
1120 |
case 0x0c: // Nucleus Little Endian (LE) |
1121 |
case 0x11: // As if user secondary |
1122 |
case 0x19: // As if user secondary LE |
1123 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
1124 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
1125 |
case 0x4a: // UPA config |
1126 |
case 0x81: // Secondary |
1127 |
case 0x89: // Secondary LE |
1128 |
// XXX
|
1129 |
return;
|
1130 |
case 0x45: // LSU |
1131 |
{ |
1132 |
uint64_t oldreg; |
1133 |
|
1134 |
oldreg = env->lsu; |
1135 |
env->lsu = T1 & (DMMU_E | IMMU_E); |
1136 |
// Mappings generated during D/I MMU disabled mode are
|
1137 |
// invalid in normal mode
|
1138 |
if (oldreg != env->lsu) {
|
1139 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
1140 |
#ifdef DEBUG_MMU
|
1141 |
dump_mmu(env); |
1142 |
#endif
|
1143 |
tlb_flush(env, 1);
|
1144 |
} |
1145 |
return;
|
1146 |
} |
1147 |
case 0x50: // I-MMU regs |
1148 |
{ |
1149 |
int reg = (T0 >> 3) & 0xf; |
1150 |
uint64_t oldreg; |
1151 |
|
1152 |
oldreg = env->immuregs[reg]; |
1153 |
switch(reg) {
|
1154 |
case 0: // RO |
1155 |
case 4: |
1156 |
return;
|
1157 |
case 1: // Not in I-MMU |
1158 |
case 2: |
1159 |
case 7: |
1160 |
case 8: |
1161 |
return;
|
1162 |
case 3: // SFSR |
1163 |
if ((T1 & 1) == 0) |
1164 |
T1 = 0; // Clear SFSR |
1165 |
break;
|
1166 |
case 5: // TSB access |
1167 |
case 6: // Tag access |
1168 |
default:
|
1169 |
break;
|
1170 |
} |
1171 |
env->immuregs[reg] = T1; |
1172 |
if (oldreg != env->immuregs[reg]) {
|
1173 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
1174 |
} |
1175 |
#ifdef DEBUG_MMU
|
1176 |
dump_mmu(env); |
1177 |
#endif
|
1178 |
return;
|
1179 |
} |
1180 |
case 0x54: // I-MMU data in |
1181 |
{ |
1182 |
unsigned int i; |
1183 |
|
1184 |
// Try finding an invalid entry
|
1185 |
for (i = 0; i < 64; i++) { |
1186 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1187 |
env->itlb_tag[i] = env->immuregs[6];
|
1188 |
env->itlb_tte[i] = T1; |
1189 |
return;
|
1190 |
} |
1191 |
} |
1192 |
// Try finding an unlocked entry
|
1193 |
for (i = 0; i < 64; i++) { |
1194 |
if ((env->itlb_tte[i] & 0x40) == 0) { |
1195 |
env->itlb_tag[i] = env->immuregs[6];
|
1196 |
env->itlb_tte[i] = T1; |
1197 |
return;
|
1198 |
} |
1199 |
} |
1200 |
// error state?
|
1201 |
return;
|
1202 |
} |
1203 |
case 0x55: // I-MMU data access |
1204 |
{ |
1205 |
unsigned int i = (T0 >> 3) & 0x3f; |
1206 |
|
1207 |
env->itlb_tag[i] = env->immuregs[6];
|
1208 |
env->itlb_tte[i] = T1; |
1209 |
return;
|
1210 |
} |
1211 |
case 0x57: // I-MMU demap |
1212 |
// XXX
|
1213 |
return;
|
1214 |
case 0x58: // D-MMU regs |
1215 |
{ |
1216 |
int reg = (T0 >> 3) & 0xf; |
1217 |
uint64_t oldreg; |
1218 |
|
1219 |
oldreg = env->dmmuregs[reg]; |
1220 |
switch(reg) {
|
1221 |
case 0: // RO |
1222 |
case 4: |
1223 |
return;
|
1224 |
case 3: // SFSR |
1225 |
if ((T1 & 1) == 0) { |
1226 |
T1 = 0; // Clear SFSR, Fault address |
1227 |
env->dmmuregs[4] = 0; |
1228 |
} |
1229 |
env->dmmuregs[reg] = T1; |
1230 |
break;
|
1231 |
case 1: // Primary context |
1232 |
case 2: // Secondary context |
1233 |
case 5: // TSB access |
1234 |
case 6: // Tag access |
1235 |
case 7: // Virtual Watchpoint |
1236 |
case 8: // Physical Watchpoint |
1237 |
default:
|
1238 |
break;
|
1239 |
} |
1240 |
env->dmmuregs[reg] = T1; |
1241 |
if (oldreg != env->dmmuregs[reg]) {
|
1242 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
1243 |
} |
1244 |
#ifdef DEBUG_MMU
|
1245 |
dump_mmu(env); |
1246 |
#endif
|
1247 |
return;
|
1248 |
} |
1249 |
case 0x5c: // D-MMU data in |
1250 |
{ |
1251 |
unsigned int i; |
1252 |
|
1253 |
// Try finding an invalid entry
|
1254 |
for (i = 0; i < 64; i++) { |
1255 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1256 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1257 |
env->dtlb_tte[i] = T1; |
1258 |
return;
|
1259 |
} |
1260 |
} |
1261 |
// Try finding an unlocked entry
|
1262 |
for (i = 0; i < 64; i++) { |
1263 |
if ((env->dtlb_tte[i] & 0x40) == 0) { |
1264 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1265 |
env->dtlb_tte[i] = T1; |
1266 |
return;
|
1267 |
} |
1268 |
} |
1269 |
// error state?
|
1270 |
return;
|
1271 |
} |
1272 |
case 0x5d: // D-MMU data access |
1273 |
{ |
1274 |
unsigned int i = (T0 >> 3) & 0x3f; |
1275 |
|
1276 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1277 |
env->dtlb_tte[i] = T1; |
1278 |
return;
|
1279 |
} |
1280 |
case 0x5f: // D-MMU demap |
1281 |
case 0x49: // Interrupt data receive |
1282 |
// XXX
|
1283 |
return;
|
1284 |
case 0x51: // I-MMU 8k TSB pointer, RO |
1285 |
case 0x52: // I-MMU 64k TSB pointer, RO |
1286 |
case 0x56: // I-MMU tag read, RO |
1287 |
case 0x59: // D-MMU 8k TSB pointer, RO |
1288 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
1289 |
case 0x5b: // D-MMU data pointer, RO |
1290 |
case 0x5e: // D-MMU tag read, RO |
1291 |
case 0x48: // Interrupt dispatch, RO |
1292 |
case 0x7f: // Incoming interrupt vector, RO |
1293 |
case 0x82: // Primary no-fault, RO |
1294 |
case 0x83: // Secondary no-fault, RO |
1295 |
case 0x8a: // Primary no-fault LE, RO |
1296 |
case 0x8b: // Secondary no-fault LE, RO |
1297 |
default:
|
1298 |
do_unassigned_access(T0, 1, 0, 1); |
1299 |
return;
|
1300 |
} |
1301 |
} |
1302 |
#endif /* CONFIG_USER_ONLY */ |
1303 |
|
1304 |
void helper_ldf_asi(int asi, int size, int rd) |
1305 |
{ |
1306 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
1307 |
unsigned int i; |
1308 |
|
1309 |
switch (asi) {
|
1310 |
case 0xf0: // Block load primary |
1311 |
case 0xf1: // Block load secondary |
1312 |
case 0xf8: // Block load primary LE |
1313 |
case 0xf9: // Block load secondary LE |
1314 |
if (rd & 7) { |
1315 |
raise_exception(TT_ILL_INSN); |
1316 |
return;
|
1317 |
} |
1318 |
if (T0 & 0x3f) { |
1319 |
raise_exception(TT_UNALIGNED); |
1320 |
return;
|
1321 |
} |
1322 |
for (i = 0; i < 16; i++) { |
1323 |
helper_ld_asi(asi & 0x8f, 4, 0); |
1324 |
*(uint32_t *)&env->fpr[rd++] = T1; |
1325 |
T0 += 4;
|
1326 |
} |
1327 |
T0 = tmp_T0; |
1328 |
T1 = tmp_T1; |
1329 |
|
1330 |
return;
|
1331 |
default:
|
1332 |
break;
|
1333 |
} |
1334 |
|
1335 |
helper_ld_asi(asi, size, 0);
|
1336 |
switch(size) {
|
1337 |
default:
|
1338 |
case 4: |
1339 |
*((uint32_t *)&FT0) = T1; |
1340 |
break;
|
1341 |
case 8: |
1342 |
*((int64_t *)&DT0) = T1; |
1343 |
break;
|
1344 |
} |
1345 |
T1 = tmp_T1; |
1346 |
} |
1347 |
|
1348 |
void helper_stf_asi(int asi, int size, int rd) |
1349 |
{ |
1350 |
target_ulong tmp_T0 = T0, tmp_T1 = T1; |
1351 |
unsigned int i; |
1352 |
|
1353 |
switch (asi) {
|
1354 |
case 0xf0: // Block store primary |
1355 |
case 0xf1: // Block store secondary |
1356 |
case 0xf8: // Block store primary LE |
1357 |
case 0xf9: // Block store secondary LE |
1358 |
if (rd & 7) { |
1359 |
raise_exception(TT_ILL_INSN); |
1360 |
return;
|
1361 |
} |
1362 |
if (T0 & 0x3f) { |
1363 |
raise_exception(TT_UNALIGNED); |
1364 |
return;
|
1365 |
} |
1366 |
for (i = 0; i < 16; i++) { |
1367 |
T1 = *(uint32_t *)&env->fpr[rd++]; |
1368 |
helper_st_asi(asi & 0x8f, 4); |
1369 |
T0 += 4;
|
1370 |
} |
1371 |
T0 = tmp_T0; |
1372 |
T1 = tmp_T1; |
1373 |
|
1374 |
return;
|
1375 |
default:
|
1376 |
break;
|
1377 |
} |
1378 |
|
1379 |
switch(size) {
|
1380 |
default:
|
1381 |
case 4: |
1382 |
T1 = *((uint32_t *)&FT0); |
1383 |
break;
|
1384 |
case 8: |
1385 |
T1 = *((int64_t *)&DT0); |
1386 |
break;
|
1387 |
} |
1388 |
helper_st_asi(asi, size); |
1389 |
T1 = tmp_T1; |
1390 |
} |
1391 |
|
1392 |
#endif /* TARGET_SPARC64 */ |
1393 |
|
1394 |
#ifndef TARGET_SPARC64
|
1395 |
void helper_rett()
|
1396 |
{ |
1397 |
unsigned int cwp; |
1398 |
|
1399 |
if (env->psret == 1) |
1400 |
raise_exception(TT_ILL_INSN); |
1401 |
|
1402 |
env->psret = 1;
|
1403 |
cwp = (env->cwp + 1) & (NWINDOWS - 1); |
1404 |
if (env->wim & (1 << cwp)) { |
1405 |
raise_exception(TT_WIN_UNF); |
1406 |
} |
1407 |
set_cwp(cwp); |
1408 |
env->psrs = env->psrps; |
1409 |
} |
1410 |
#endif
|
1411 |
|
1412 |
void helper_ldfsr(void) |
1413 |
{ |
1414 |
int rnd_mode;
|
1415 |
switch (env->fsr & FSR_RD_MASK) {
|
1416 |
case FSR_RD_NEAREST:
|
1417 |
rnd_mode = float_round_nearest_even; |
1418 |
break;
|
1419 |
default:
|
1420 |
case FSR_RD_ZERO:
|
1421 |
rnd_mode = float_round_to_zero; |
1422 |
break;
|
1423 |
case FSR_RD_POS:
|
1424 |
rnd_mode = float_round_up; |
1425 |
break;
|
1426 |
case FSR_RD_NEG:
|
1427 |
rnd_mode = float_round_down; |
1428 |
break;
|
1429 |
} |
1430 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
1431 |
} |
1432 |
|
1433 |
void helper_debug()
|
1434 |
{ |
1435 |
env->exception_index = EXCP_DEBUG; |
1436 |
cpu_loop_exit(); |
1437 |
} |
1438 |
|
1439 |
#ifndef TARGET_SPARC64
|
1440 |
void do_wrpsr()
|
1441 |
{ |
1442 |
if ((T0 & PSR_CWP) >= NWINDOWS)
|
1443 |
raise_exception(TT_ILL_INSN); |
1444 |
else
|
1445 |
PUT_PSR(env, T0); |
1446 |
} |
1447 |
|
1448 |
void do_rdpsr()
|
1449 |
{ |
1450 |
T0 = GET_PSR(env); |
1451 |
} |
1452 |
|
1453 |
#else
|
1454 |
|
1455 |
void do_popc()
|
1456 |
{ |
1457 |
T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); |
1458 |
T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); |
1459 |
T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); |
1460 |
T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); |
1461 |
T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); |
1462 |
T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); |
1463 |
} |
1464 |
|
1465 |
static inline uint64_t *get_gregset(uint64_t pstate) |
1466 |
{ |
1467 |
switch (pstate) {
|
1468 |
default:
|
1469 |
case 0: |
1470 |
return env->bgregs;
|
1471 |
case PS_AG:
|
1472 |
return env->agregs;
|
1473 |
case PS_MG:
|
1474 |
return env->mgregs;
|
1475 |
case PS_IG:
|
1476 |
return env->igregs;
|
1477 |
} |
1478 |
} |
1479 |
|
1480 |
static inline void change_pstate(uint64_t new_pstate) |
1481 |
{ |
1482 |
uint64_t pstate_regs, new_pstate_regs; |
1483 |
uint64_t *src, *dst; |
1484 |
|
1485 |
pstate_regs = env->pstate & 0xc01;
|
1486 |
new_pstate_regs = new_pstate & 0xc01;
|
1487 |
if (new_pstate_regs != pstate_regs) {
|
1488 |
// Switch global register bank
|
1489 |
src = get_gregset(new_pstate_regs); |
1490 |
dst = get_gregset(pstate_regs); |
1491 |
memcpy32(dst, env->gregs); |
1492 |
memcpy32(env->gregs, src); |
1493 |
} |
1494 |
env->pstate = new_pstate; |
1495 |
} |
1496 |
|
1497 |
void do_wrpstate(void) |
1498 |
{ |
1499 |
change_pstate(T0 & 0xf3f);
|
1500 |
} |
1501 |
|
1502 |
void do_done(void) |
1503 |
{ |
1504 |
env->tl--; |
1505 |
env->pc = env->tnpc[env->tl]; |
1506 |
env->npc = env->tnpc[env->tl] + 4;
|
1507 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
1508 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
1509 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
1510 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
1511 |
} |
1512 |
|
1513 |
void do_retry(void) |
1514 |
{ |
1515 |
env->tl--; |
1516 |
env->pc = env->tpc[env->tl]; |
1517 |
env->npc = env->tnpc[env->tl]; |
1518 |
PUT_CCR(env, env->tstate[env->tl] >> 32);
|
1519 |
env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
1520 |
change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
1521 |
PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
1522 |
} |
1523 |
#endif
|
1524 |
|
1525 |
void set_cwp(int new_cwp) |
1526 |
{ |
1527 |
/* put the modified wrap registers at their proper location */
|
1528 |
if (env->cwp == (NWINDOWS - 1)) |
1529 |
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
1530 |
env->cwp = new_cwp; |
1531 |
/* put the wrap registers at their temporary location */
|
1532 |
if (new_cwp == (NWINDOWS - 1)) |
1533 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
1534 |
env->regwptr = env->regbase + (new_cwp * 16);
|
1535 |
REGWPTR = env->regwptr; |
1536 |
} |
1537 |
|
1538 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
1539 |
{ |
1540 |
CPUState *saved_env; |
1541 |
#ifdef reg_REGWPTR
|
1542 |
target_ulong *saved_regwptr; |
1543 |
#endif
|
1544 |
|
1545 |
saved_env = env; |
1546 |
#ifdef reg_REGWPTR
|
1547 |
saved_regwptr = REGWPTR; |
1548 |
#endif
|
1549 |
env = env1; |
1550 |
set_cwp(new_cwp); |
1551 |
env = saved_env; |
1552 |
#ifdef reg_REGWPTR
|
1553 |
REGWPTR = saved_regwptr; |
1554 |
#endif
|
1555 |
} |
1556 |
|
1557 |
#ifdef TARGET_SPARC64
|
1558 |
void do_interrupt(int intno) |
1559 |
{ |
1560 |
#ifdef DEBUG_PCALL
|
1561 |
if (loglevel & CPU_LOG_INT) {
|
1562 |
static int count; |
1563 |
fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n", |
1564 |
count, intno, |
1565 |
env->pc, |
1566 |
env->npc, env->regwptr[6]);
|
1567 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1568 |
#if 0
|
1569 |
{
|
1570 |
int i;
|
1571 |
uint8_t *ptr;
|
1572 |
|
1573 |
fprintf(logfile, " code=");
|
1574 |
ptr = (uint8_t *)env->pc;
|
1575 |
for(i = 0; i < 16; i++) {
|
1576 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1577 |
}
|
1578 |
fprintf(logfile, "\n");
|
1579 |
}
|
1580 |
#endif
|
1581 |
count++; |
1582 |
} |
1583 |
#endif
|
1584 |
#if !defined(CONFIG_USER_ONLY)
|
1585 |
if (env->tl == MAXTL) {
|
1586 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
1587 |
return;
|
1588 |
} |
1589 |
#endif
|
1590 |
env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
1591 |
((env->pstate & 0xf3f) << 8) | GET_CWP64(env); |
1592 |
env->tpc[env->tl] = env->pc; |
1593 |
env->tnpc[env->tl] = env->npc; |
1594 |
env->tt[env->tl] = intno; |
1595 |
change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1596 |
|
1597 |
if (intno == TT_CLRWIN)
|
1598 |
set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
1599 |
else if ((intno & 0x1c0) == TT_SPILL) |
1600 |
set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
1601 |
else if ((intno & 0x1c0) == TT_FILL) |
1602 |
set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
1603 |
env->tbr &= ~0x7fffULL;
|
1604 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
1605 |
if (env->tl < MAXTL - 1) { |
1606 |
env->tl++; |
1607 |
} else {
|
1608 |
env->pstate |= PS_RED; |
1609 |
if (env->tl != MAXTL)
|
1610 |
env->tl++; |
1611 |
} |
1612 |
env->pc = env->tbr; |
1613 |
env->npc = env->pc + 4;
|
1614 |
env->exception_index = 0;
|
1615 |
} |
1616 |
#else
|
1617 |
void do_interrupt(int intno) |
1618 |
{ |
1619 |
int cwp;
|
1620 |
|
1621 |
#ifdef DEBUG_PCALL
|
1622 |
if (loglevel & CPU_LOG_INT) {
|
1623 |
static int count; |
1624 |
fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
1625 |
count, intno, |
1626 |
env->pc, |
1627 |
env->npc, env->regwptr[6]);
|
1628 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1629 |
#if 0
|
1630 |
{
|
1631 |
int i;
|
1632 |
uint8_t *ptr;
|
1633 |
|
1634 |
fprintf(logfile, " code=");
|
1635 |
ptr = (uint8_t *)env->pc;
|
1636 |
for(i = 0; i < 16; i++) {
|
1637 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1638 |
}
|
1639 |
fprintf(logfile, "\n");
|
1640 |
}
|
1641 |
#endif
|
1642 |
count++; |
1643 |
} |
1644 |
#endif
|
1645 |
#if !defined(CONFIG_USER_ONLY)
|
1646 |
if (env->psret == 0) { |
1647 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
1648 |
return;
|
1649 |
} |
1650 |
#endif
|
1651 |
env->psret = 0;
|
1652 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
1653 |
set_cwp(cwp); |
1654 |
env->regwptr[9] = env->pc;
|
1655 |
env->regwptr[10] = env->npc;
|
1656 |
env->psrps = env->psrs; |
1657 |
env->psrs = 1;
|
1658 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
1659 |
env->pc = env->tbr; |
1660 |
env->npc = env->pc + 4;
|
1661 |
env->exception_index = 0;
|
1662 |
} |
1663 |
#endif
|
1664 |
|
1665 |
#if !defined(CONFIG_USER_ONLY)
|
1666 |
|
1667 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1668 |
void *retaddr);
|
1669 |
|
1670 |
#define MMUSUFFIX _mmu
|
1671 |
#define ALIGNED_ONLY
|
1672 |
#define GETPC() (__builtin_return_address(0)) |
1673 |
|
1674 |
#define SHIFT 0 |
1675 |
#include "softmmu_template.h" |
1676 |
|
1677 |
#define SHIFT 1 |
1678 |
#include "softmmu_template.h" |
1679 |
|
1680 |
#define SHIFT 2 |
1681 |
#include "softmmu_template.h" |
1682 |
|
1683 |
#define SHIFT 3 |
1684 |
#include "softmmu_template.h" |
1685 |
|
1686 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
1687 |
void *retaddr)
|
1688 |
{ |
1689 |
#ifdef DEBUG_UNALIGNED
|
1690 |
printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
|
1691 |
#endif
|
1692 |
raise_exception(TT_UNALIGNED); |
1693 |
} |
1694 |
|
1695 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
1696 |
NULL, it means that the function was called in C code (i.e. not
|
1697 |
from generated code or from helper.c) */
|
1698 |
/* XXX: fix it to restore all registers */
|
1699 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
1700 |
{ |
1701 |
TranslationBlock *tb; |
1702 |
int ret;
|
1703 |
unsigned long pc; |
1704 |
CPUState *saved_env; |
1705 |
|
1706 |
/* XXX: hack to restore env in all cases, even if not called from
|
1707 |
generated code */
|
1708 |
saved_env = env; |
1709 |
env = cpu_single_env; |
1710 |
|
1711 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
1712 |
if (ret) {
|
1713 |
if (retaddr) {
|
1714 |
/* now we have a real cpu fault */
|
1715 |
pc = (unsigned long)retaddr; |
1716 |
tb = tb_find_pc(pc); |
1717 |
if (tb) {
|
1718 |
/* the PC is inside the translated code. It means that we have
|
1719 |
a virtual CPU fault */
|
1720 |
cpu_restore_state(tb, env, pc, (void *)T2);
|
1721 |
} |
1722 |
} |
1723 |
cpu_loop_exit(); |
1724 |
} |
1725 |
env = saved_env; |
1726 |
} |
1727 |
|
1728 |
#endif
|
1729 |
|
1730 |
#ifndef TARGET_SPARC64
|
1731 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
1732 |
int is_asi)
|
1733 |
{ |
1734 |
CPUState *saved_env; |
1735 |
|
1736 |
/* XXX: hack to restore env in all cases, even if not called from
|
1737 |
generated code */
|
1738 |
saved_env = env; |
1739 |
env = cpu_single_env; |
1740 |
if (env->mmuregs[3]) /* Fault status register */ |
1741 |
env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
1742 |
if (is_asi)
|
1743 |
env->mmuregs[3] |= 1 << 16; |
1744 |
if (env->psrs)
|
1745 |
env->mmuregs[3] |= 1 << 5; |
1746 |
if (is_exec)
|
1747 |
env->mmuregs[3] |= 1 << 6; |
1748 |
if (is_write)
|
1749 |
env->mmuregs[3] |= 1 << 7; |
1750 |
env->mmuregs[3] |= (5 << 2) | 2; |
1751 |
env->mmuregs[4] = addr; /* Fault address register */ |
1752 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
1753 |
#ifdef DEBUG_UNASSIGNED
|
1754 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
1755 |
"\n", addr, env->pc);
|
1756 |
#endif
|
1757 |
if (is_exec)
|
1758 |
raise_exception(TT_CODE_ACCESS); |
1759 |
else
|
1760 |
raise_exception(TT_DATA_ACCESS); |
1761 |
} |
1762 |
env = saved_env; |
1763 |
} |
1764 |
#else
|
1765 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
1766 |
int is_asi)
|
1767 |
{ |
1768 |
#ifdef DEBUG_UNASSIGNED
|
1769 |
CPUState *saved_env; |
1770 |
|
1771 |
/* XXX: hack to restore env in all cases, even if not called from
|
1772 |
generated code */
|
1773 |
saved_env = env; |
1774 |
env = cpu_single_env; |
1775 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
1776 |
addr, env->pc); |
1777 |
env = saved_env; |
1778 |
#endif
|
1779 |
if (is_exec)
|
1780 |
raise_exception(TT_CODE_ACCESS); |
1781 |
else
|
1782 |
raise_exception(TT_DATA_ACCESS); |
1783 |
} |
1784 |
#endif
|
1785 |
|
1786 |
#ifdef TARGET_SPARC64
|
1787 |
void do_tick_set_count(void *opaque, uint64_t count) |
1788 |
{ |
1789 |
#if !defined(CONFIG_USER_ONLY)
|
1790 |
ptimer_set_count(opaque, -count); |
1791 |
#endif
|
1792 |
} |
1793 |
|
1794 |
uint64_t do_tick_get_count(void *opaque)
|
1795 |
{ |
1796 |
#if !defined(CONFIG_USER_ONLY)
|
1797 |
return -ptimer_get_count(opaque);
|
1798 |
#else
|
1799 |
return 0; |
1800 |
#endif
|
1801 |
} |
1802 |
|
1803 |
void do_tick_set_limit(void *opaque, uint64_t limit) |
1804 |
{ |
1805 |
#if !defined(CONFIG_USER_ONLY)
|
1806 |
ptimer_set_limit(opaque, -limit, 0);
|
1807 |
#endif
|
1808 |
} |
1809 |
#endif
|