Revision e91c8a77 hw/ne2000.c
b/hw/ne2000.c | ||
---|---|---|
325 | 325 |
s->cmd = val; |
326 | 326 |
if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
327 | 327 |
s->isr &= ~ENISR_RESET; |
328 |
/* test specific case: zero length transfert */
|
|
328 |
/* test specific case: zero length transfer */ |
|
329 | 329 |
if ((val & (E8390_RREAD | E8390_RWRITE)) && |
330 | 330 |
s->rcnt == 0) { |
331 | 331 |
s->isr |= ENISR_RDC; |
... | ... | |
340 | 340 |
if (index + s->tcnt <= NE2000_PMEM_END) { |
341 | 341 |
qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
342 | 342 |
} |
343 |
/* signal end of transfert */
|
|
343 |
/* signal end of transfer */ |
|
344 | 344 |
s->tsr = ENTSR_PTX; |
345 | 345 |
s->isr |= ENISR_TX; |
346 | 346 |
s->cmd &= ~E8390_TRANS; |
... | ... | |
550 | 550 |
|
551 | 551 |
if (s->rcnt <= len) { |
552 | 552 |
s->rcnt = 0; |
553 |
/* signal end of transfert */
|
|
553 |
/* signal end of transfer */ |
|
554 | 554 |
s->isr |= ENISR_RDC; |
555 | 555 |
ne2000_update_irq(s); |
556 | 556 |
} else { |
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