Statistics
| Branch: | Revision:

root / hw / omap2.c @ e927bb00

History | View | Annotate | Download (119.7 kB)

1
/*
2
 * TI OMAP processors emulation.
3
 *
4
 * Copyright (C) 2007-2008 Nokia Corporation
5
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6
 *
7
 * This program is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU General Public License as
9
 * published by the Free Software Foundation; either version 2 or
10
 * (at your option) version 3 of the License.
11
 *
12
 * This program is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
 * GNU General Public License for more details.
16
 *
17
 * You should have received a copy of the GNU General Public License
18
 * along with this program; if not, write to the Free Software
19
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20
 * MA 02111-1307 USA
21
 */
22
#include "hw.h"
23
#include "arm-misc.h"
24
#include "omap.h"
25
#include "sysemu.h"
26
#include "qemu-timer.h"
27
#include "qemu-char.h"
28
#include "flash.h"
29

    
30
/* GP timers */
31
struct omap_gp_timer_s {
32
    qemu_irq irq;
33
    qemu_irq wkup;
34
    qemu_irq in;
35
    qemu_irq out;
36
    omap_clk clk;
37
    target_phys_addr_t base;
38
    QEMUTimer *timer;
39
    QEMUTimer *match;
40
    struct omap_target_agent_s *ta;
41

    
42
    int in_val;
43
    int out_val;
44
    int64_t time;
45
    int64_t rate;
46
    int64_t ticks_per_sec;
47

    
48
    int16_t config;
49
    int status;
50
    int it_ena;
51
    int wu_ena;
52
    int enable;
53
    int inout;
54
    int capt2;
55
    int pt;
56
    enum {
57
        gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
58
    } trigger;
59
    enum {
60
        gpt_capture_none, gpt_capture_rising,
61
        gpt_capture_falling, gpt_capture_both
62
    } capture;
63
    int scpwm;
64
    int ce;
65
    int pre;
66
    int ptv;
67
    int ar;
68
    int st;
69
    int posted;
70
    uint32_t val;
71
    uint32_t load_val;
72
    uint32_t capture_val[2];
73
    uint32_t match_val;
74
    int capt_num;
75

    
76
    uint16_t writeh;        /* LSB */
77
    uint16_t readh;        /* MSB */
78
};
79

    
80
#define GPT_TCAR_IT        (1 << 2)
81
#define GPT_OVF_IT        (1 << 1)
82
#define GPT_MAT_IT        (1 << 0)
83

    
84
static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
85
{
86
    if (timer->it_ena & it) {
87
        if (!timer->status)
88
            qemu_irq_raise(timer->irq);
89

    
90
        timer->status |= it;
91
        /* Or are the status bits set even when masked?
92
         * i.e. is masking applied before or after the status register?  */
93
    }
94

    
95
    if (timer->wu_ena & it)
96
        qemu_irq_pulse(timer->wkup);
97
}
98

    
99
static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
100
{
101
    if (!timer->inout && timer->out_val != level) {
102
        timer->out_val = level;
103
        qemu_set_irq(timer->out, level);
104
    }
105
}
106

    
107
static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
108
{
109
    uint64_t distance;
110

    
111
    if (timer->st && timer->rate) {
112
        distance = qemu_get_clock(vm_clock) - timer->time;
113
        distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
114

    
115
        if (distance >= 0xffffffff - timer->val)
116
            return 0xffffffff;
117
        else
118
            return timer->val + distance;
119
    } else
120
        return timer->val;
121
}
122

    
123
static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
124
{
125
    if (timer->st) {
126
        timer->val = omap_gp_timer_read(timer);
127
        timer->time = qemu_get_clock(vm_clock);
128
    }
129
}
130

    
131
static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
132
{
133
    int64_t expires, matches;
134

    
135
    if (timer->st && timer->rate) {
136
        expires = muldiv64(0x100000000ll - timer->val,
137
                        timer->ticks_per_sec, timer->rate);
138
        qemu_mod_timer(timer->timer, timer->time + expires);
139

    
140
        if (timer->ce && timer->match_val >= timer->val) {
141
            matches = muldiv64(timer->match_val - timer->val,
142
                            timer->ticks_per_sec, timer->rate);
143
            qemu_mod_timer(timer->match, timer->time + matches);
144
        } else
145
            qemu_del_timer(timer->match);
146
    } else {
147
        qemu_del_timer(timer->timer);
148
        qemu_del_timer(timer->match);
149
        omap_gp_timer_out(timer, timer->scpwm);
150
    }
151
}
152

    
153
static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
154
{
155
    if (timer->pt)
156
        /* TODO in overflow-and-match mode if the first event to
157
         * occurs is the match, don't toggle.  */
158
        omap_gp_timer_out(timer, !timer->out_val);
159
    else
160
        /* TODO inverted pulse on timer->out_val == 1?  */
161
        qemu_irq_pulse(timer->out);
162
}
163

    
164
static void omap_gp_timer_tick(void *opaque)
165
{
166
    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
167

    
168
    if (!timer->ar) {
169
        timer->st = 0;
170
        timer->val = 0;
171
    } else {
172
        timer->val = timer->load_val;
173
        timer->time = qemu_get_clock(vm_clock);
174
    }
175

    
176
    if (timer->trigger == gpt_trigger_overflow ||
177
                    timer->trigger == gpt_trigger_both)
178
        omap_gp_timer_trigger(timer);
179

    
180
    omap_gp_timer_intr(timer, GPT_OVF_IT);
181
    omap_gp_timer_update(timer);
182
}
183

    
184
static void omap_gp_timer_match(void *opaque)
185
{
186
    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
187

    
188
    if (timer->trigger == gpt_trigger_both)
189
        omap_gp_timer_trigger(timer);
190

    
191
    omap_gp_timer_intr(timer, GPT_MAT_IT);
192
}
193

    
194
static void omap_gp_timer_input(void *opaque, int line, int on)
195
{
196
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
197
    int trigger;
198

    
199
    switch (s->capture) {
200
    default:
201
    case gpt_capture_none:
202
        trigger = 0;
203
        break;
204
    case gpt_capture_rising:
205
        trigger = !s->in_val && on;
206
        break;
207
    case gpt_capture_falling:
208
        trigger = s->in_val && !on;
209
        break;
210
    case gpt_capture_both:
211
        trigger = (s->in_val == !on);
212
        break;
213
    }
214
    s->in_val = on;
215

    
216
    if (s->inout && trigger && s->capt_num < 2) {
217
        s->capture_val[s->capt_num] = omap_gp_timer_read(s);
218

    
219
        if (s->capt2 == s->capt_num ++)
220
            omap_gp_timer_intr(s, GPT_TCAR_IT);
221
    }
222
}
223

    
224
static void omap_gp_timer_clk_update(void *opaque, int line, int on)
225
{
226
    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
227

    
228
    omap_gp_timer_sync(timer);
229
    timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
230
    omap_gp_timer_update(timer);
231
}
232

    
233
static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
234
{
235
    omap_clk_adduser(timer->clk,
236
                    qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
237
    timer->rate = omap_clk_getrate(timer->clk);
238
}
239

    
240
static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
241
{
242
    s->config = 0x000;
243
    s->status = 0;
244
    s->it_ena = 0;
245
    s->wu_ena = 0;
246
    s->inout = 0;
247
    s->capt2 = 0;
248
    s->capt_num = 0;
249
    s->pt = 0;
250
    s->trigger = gpt_trigger_none;
251
    s->capture = gpt_capture_none;
252
    s->scpwm = 0;
253
    s->ce = 0;
254
    s->pre = 0;
255
    s->ptv = 0;
256
    s->ar = 0;
257
    s->st = 0;
258
    s->posted = 1;
259
    s->val = 0x00000000;
260
    s->load_val = 0x00000000;
261
    s->capture_val[0] = 0x00000000;
262
    s->capture_val[1] = 0x00000000;
263
    s->match_val = 0x00000000;
264
    omap_gp_timer_update(s);
265
}
266

    
267
static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
268
{
269
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
270
    int offset = addr - s->base;
271

    
272
    switch (offset) {
273
    case 0x00:        /* TIDR */
274
        return 0x21;
275

    
276
    case 0x10:        /* TIOCP_CFG */
277
        return s->config;
278

    
279
    case 0x14:        /* TISTAT */
280
        /* ??? When's this bit reset? */
281
        return 1;                                                /* RESETDONE */
282

    
283
    case 0x18:        /* TISR */
284
        return s->status;
285

    
286
    case 0x1c:        /* TIER */
287
        return s->it_ena;
288

    
289
    case 0x20:        /* TWER */
290
        return s->wu_ena;
291

    
292
    case 0x24:        /* TCLR */
293
        return (s->inout << 14) |
294
                (s->capt2 << 13) |
295
                (s->pt << 12) |
296
                (s->trigger << 10) |
297
                (s->capture << 8) |
298
                (s->scpwm << 7) |
299
                (s->ce << 6) |
300
                (s->pre << 5) |
301
                (s->ptv << 2) |
302
                (s->ar << 1) |
303
                (s->st << 0);
304

    
305
    case 0x28:        /* TCRR */
306
        return omap_gp_timer_read(s);
307

    
308
    case 0x2c:        /* TLDR */
309
        return s->load_val;
310

    
311
    case 0x30:        /* TTGR */
312
        return 0xffffffff;
313

    
314
    case 0x34:        /* TWPS */
315
        return 0x00000000;        /* No posted writes pending.  */
316

    
317
    case 0x38:        /* TMAR */
318
        return s->match_val;
319

    
320
    case 0x3c:        /* TCAR1 */
321
        return s->capture_val[0];
322

    
323
    case 0x40:        /* TSICR */
324
        return s->posted << 2;
325

    
326
    case 0x44:        /* TCAR2 */
327
        return s->capture_val[1];
328
    }
329

    
330
    OMAP_BAD_REG(addr);
331
    return 0;
332
}
333

    
334
static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
335
{
336
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
337
    uint32_t ret;
338

    
339
    if (addr & 2)
340
        return s->readh;
341
    else {
342
        ret = omap_gp_timer_readw(opaque, addr);
343
        s->readh = ret >> 16;
344
        return ret & 0xffff;
345
    }
346
}
347

    
348
static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
349
    omap_badwidth_read32,
350
    omap_gp_timer_readh,
351
    omap_gp_timer_readw,
352
};
353

    
354
static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
355
                uint32_t value)
356
{
357
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
358
    int offset = addr - s->base;
359

    
360
    switch (offset) {
361
    case 0x00:        /* TIDR */
362
    case 0x14:        /* TISTAT */
363
    case 0x34:        /* TWPS */
364
    case 0x3c:        /* TCAR1 */
365
    case 0x44:        /* TCAR2 */
366
        OMAP_RO_REG(addr);
367
        break;
368

    
369
    case 0x10:        /* TIOCP_CFG */
370
        s->config = value & 0x33d;
371
        if (((value >> 3) & 3) == 3)                                /* IDLEMODE */
372
            fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
373
                            __FUNCTION__);
374
        if (value & 2)                                                /* SOFTRESET */
375
            omap_gp_timer_reset(s);
376
        break;
377

    
378
    case 0x18:        /* TISR */
379
        if (value & GPT_TCAR_IT)
380
            s->capt_num = 0;
381
        if (s->status && !(s->status &= ~value))
382
            qemu_irq_lower(s->irq);
383
        break;
384

    
385
    case 0x1c:        /* TIER */
386
        s->it_ena = value & 7;
387
        break;
388

    
389
    case 0x20:        /* TWER */
390
        s->wu_ena = value & 7;
391
        break;
392

    
393
    case 0x24:        /* TCLR */
394
        omap_gp_timer_sync(s);
395
        s->inout = (value >> 14) & 1;
396
        s->capt2 = (value >> 13) & 1;
397
        s->pt = (value >> 12) & 1;
398
        s->trigger = (value >> 10) & 3;
399
        if (s->capture == gpt_capture_none &&
400
                        ((value >> 8) & 3) != gpt_capture_none)
401
            s->capt_num = 0;
402
        s->capture = (value >> 8) & 3;
403
        s->scpwm = (value >> 7) & 1;
404
        s->ce = (value >> 6) & 1;
405
        s->pre = (value >> 5) & 1;
406
        s->ptv = (value >> 2) & 7;
407
        s->ar = (value >> 1) & 1;
408
        s->st = (value >> 0) & 1;
409
        if (s->inout && s->trigger != gpt_trigger_none)
410
            fprintf(stderr, "%s: GP timer pin must be an output "
411
                            "for this trigger mode\n", __FUNCTION__);
412
        if (!s->inout && s->capture != gpt_capture_none)
413
            fprintf(stderr, "%s: GP timer pin must be an input "
414
                            "for this capture mode\n", __FUNCTION__);
415
        if (s->trigger == gpt_trigger_none)
416
            omap_gp_timer_out(s, s->scpwm);
417
        /* TODO: make sure this doesn't overflow 32-bits */
418
        s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);
419
        omap_gp_timer_update(s);
420
        break;
421

    
422
    case 0x28:        /* TCRR */
423
        s->time = qemu_get_clock(vm_clock);
424
        s->val = value;
425
        omap_gp_timer_update(s);
426
        break;
427

    
428
    case 0x2c:        /* TLDR */
429
        s->load_val = value;
430
        break;
431

    
432
    case 0x30:        /* TTGR */
433
        s->time = qemu_get_clock(vm_clock);
434
        s->val = s->load_val;
435
        omap_gp_timer_update(s);
436
        break;
437

    
438
    case 0x38:        /* TMAR */
439
        omap_gp_timer_sync(s);
440
        s->match_val = value;
441
        omap_gp_timer_update(s);
442
        break;
443

    
444
    case 0x40:        /* TSICR */
445
        s->posted = (value >> 2) & 1;
446
        if (value & 2)        /* How much exactly are we supposed to reset? */
447
            omap_gp_timer_reset(s);
448
        break;
449

    
450
    default:
451
        OMAP_BAD_REG(addr);
452
    }
453
}
454

    
455
static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
456
                uint32_t value)
457
{
458
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
459

    
460
    if (addr & 2)
461
        return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
462
    else
463
        s->writeh = (uint16_t) value;
464
}
465

    
466
static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
467
    omap_badwidth_write32,
468
    omap_gp_timer_writeh,
469
    omap_gp_timer_write,
470
};
471

    
472
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
473
                qemu_irq irq, omap_clk fclk, omap_clk iclk)
474
{
475
    int iomemtype;
476
    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
477
            qemu_mallocz(sizeof(struct omap_gp_timer_s));
478

    
479
    s->ta = ta;
480
    s->irq = irq;
481
    s->clk = fclk;
482
    s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
483
    s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
484
    s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
485
    omap_gp_timer_reset(s);
486
    omap_gp_timer_clk_setup(s);
487

    
488
    iomemtype = cpu_register_io_memory(0, omap_gp_timer_readfn,
489
                    omap_gp_timer_writefn, s);
490
    s->base = omap_l4_attach(ta, 0, iomemtype);
491

    
492
    return s;
493
}
494

    
495
/* 32-kHz Sync Timer of the OMAP2 */
496
static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
497
    return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);
498
}
499

    
500
static void omap_synctimer_reset(struct omap_synctimer_s *s)
501
{
502
    s->val = omap_synctimer_read(s);
503
}
504

    
505
static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
506
{
507
    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
508
    int offset = addr - s->base;
509

    
510
    switch (offset) {
511
    case 0x00:        /* 32KSYNCNT_REV */
512
        return 0x21;
513

    
514
    case 0x10:        /* CR */
515
        return omap_synctimer_read(s) - s->val;
516
    }
517

    
518
    OMAP_BAD_REG(addr);
519
    return 0;
520
}
521

    
522
static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
523
{
524
    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
525
    uint32_t ret;
526

    
527
    if (addr & 2)
528
        return s->readh;
529
    else {
530
        ret = omap_synctimer_readw(opaque, addr);
531
        s->readh = ret >> 16;
532
        return ret & 0xffff;
533
    }
534
}
535

    
536
static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
537
    omap_badwidth_read32,
538
    omap_synctimer_readh,
539
    omap_synctimer_readw,
540
};
541

    
542
static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
543
                uint32_t value)
544
{
545
    OMAP_BAD_REG(addr);
546
}
547

    
548
static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
549
    omap_badwidth_write32,
550
    omap_synctimer_write,
551
    omap_synctimer_write,
552
};
553

    
554
void omap_synctimer_init(struct omap_target_agent_s *ta,
555
                struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
556
{
557
    struct omap_synctimer_s *s = &mpu->synctimer;
558

    
559
    omap_synctimer_reset(s);
560
    s->base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
561
                            omap_synctimer_readfn, omap_synctimer_writefn, s));
562
}
563

    
564
/* General-Purpose Interface of OMAP2 */
565
struct omap2_gpio_s {
566
    target_phys_addr_t base;
567
    qemu_irq irq[2];
568
    qemu_irq wkup;
569
    qemu_irq *in;
570
    qemu_irq handler[32];
571

    
572
    uint8_t config[2];
573
    uint32_t inputs;
574
    uint32_t outputs;
575
    uint32_t dir;
576
    uint32_t level[2];
577
    uint32_t edge[2];
578
    uint32_t mask[2];
579
    uint32_t wumask;
580
    uint32_t ints[2];
581
    uint32_t debounce;
582
    uint8_t delay;
583
};
584

    
585
static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
586
                int line)
587
{
588
    qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
589
}
590

    
591
static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
592
{
593
    if (!(s->config[0] & (1 << 2)))                        /* ENAWAKEUP */
594
        return;
595
    if (!(s->config[0] & (3 << 3)))                        /* Force Idle */
596
        return;
597
    if (!(s->wumask & (1 << line)))
598
        return;
599

    
600
    qemu_irq_raise(s->wkup);
601
}
602

    
603
static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
604
                uint32_t diff)
605
{
606
    int ln;
607

    
608
    s->outputs ^= diff;
609
    diff &= ~s->dir;
610
    while ((ln = ffs(diff))) {
611
        ln --;
612
        qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
613
        diff &= ~(1 << ln);
614
    }
615
}
616

    
617
static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
618
{
619
    s->ints[line] |= s->dir &
620
            ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
621
    omap_gpio_module_int_update(s, line);
622
}
623

    
624
static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
625
{
626
    s->ints[0] |= 1 << line;
627
    omap_gpio_module_int_update(s, 0);
628
    s->ints[1] |= 1 << line;
629
    omap_gpio_module_int_update(s, 1);
630
    omap_gpio_module_wake(s, line);
631
}
632

    
633
static void omap_gpio_module_set(void *opaque, int line, int level)
634
{
635
    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
636

    
637
    if (level) {
638
        if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
639
            omap_gpio_module_int(s, line);
640
        s->inputs |= 1 << line;
641
    } else {
642
        if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
643
            omap_gpio_module_int(s, line);
644
        s->inputs &= ~(1 << line);
645
    }
646
}
647

    
648
static void omap_gpio_module_reset(struct omap2_gpio_s *s)
649
{
650
    s->config[0] = 0;
651
    s->config[1] = 2;
652
    s->ints[0] = 0;
653
    s->ints[1] = 0;
654
    s->mask[0] = 0;
655
    s->mask[1] = 0;
656
    s->wumask = 0;
657
    s->dir = ~0;
658
    s->level[0] = 0;
659
    s->level[1] = 0;
660
    s->edge[0] = 0;
661
    s->edge[1] = 0;
662
    s->debounce = 0;
663
    s->delay = 0;
664
}
665

    
666
static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
667
{
668
    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
669
    int offset = addr - s->base;
670

    
671
    switch (offset) {
672
    case 0x00:        /* GPIO_REVISION */
673
        return 0x18;
674

    
675
    case 0x10:        /* GPIO_SYSCONFIG */
676
        return s->config[0];
677

    
678
    case 0x14:        /* GPIO_SYSSTATUS */
679
        return 0x01;
680

    
681
    case 0x18:        /* GPIO_IRQSTATUS1 */
682
        return s->ints[0];
683

    
684
    case 0x1c:        /* GPIO_IRQENABLE1 */
685
    case 0x60:        /* GPIO_CLEARIRQENABLE1 */
686
    case 0x64:        /* GPIO_SETIRQENABLE1 */
687
        return s->mask[0];
688

    
689
    case 0x20:        /* GPIO_WAKEUPENABLE */
690
    case 0x80:        /* GPIO_CLEARWKUENA */
691
    case 0x84:        /* GPIO_SETWKUENA */
692
        return s->wumask;
693

    
694
    case 0x28:        /* GPIO_IRQSTATUS2 */
695
        return s->ints[1];
696

    
697
    case 0x2c:        /* GPIO_IRQENABLE2 */
698
    case 0x70:        /* GPIO_CLEARIRQENABLE2 */
699
    case 0x74:        /* GPIO_SETIREQNEABLE2 */
700
        return s->mask[1];
701

    
702
    case 0x30:        /* GPIO_CTRL */
703
        return s->config[1];
704

    
705
    case 0x34:        /* GPIO_OE */
706
        return s->dir;
707

    
708
    case 0x38:        /* GPIO_DATAIN */
709
        return s->inputs;
710

    
711
    case 0x3c:        /* GPIO_DATAOUT */
712
    case 0x90:        /* GPIO_CLEARDATAOUT */
713
    case 0x94:        /* GPIO_SETDATAOUT */
714
        return s->outputs;
715

    
716
    case 0x40:        /* GPIO_LEVELDETECT0 */
717
        return s->level[0];
718

    
719
    case 0x44:        /* GPIO_LEVELDETECT1 */
720
        return s->level[1];
721

    
722
    case 0x48:        /* GPIO_RISINGDETECT */
723
        return s->edge[0];
724

    
725
    case 0x4c:        /* GPIO_FALLINGDETECT */
726
        return s->edge[1];
727

    
728
    case 0x50:        /* GPIO_DEBOUNCENABLE */
729
        return s->debounce;
730

    
731
    case 0x54:        /* GPIO_DEBOUNCINGTIME */
732
        return s->delay;
733
    }
734

    
735
    OMAP_BAD_REG(addr);
736
    return 0;
737
}
738

    
739
static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
740
                uint32_t value)
741
{
742
    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
743
    int offset = addr - s->base;
744
    uint32_t diff;
745
    int ln;
746

    
747
    switch (offset) {
748
    case 0x00:        /* GPIO_REVISION */
749
    case 0x14:        /* GPIO_SYSSTATUS */
750
    case 0x38:        /* GPIO_DATAIN */
751
        OMAP_RO_REG(addr);
752
        break;
753

    
754
    case 0x10:        /* GPIO_SYSCONFIG */
755
        if (((value >> 3) & 3) == 3)
756
            fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
757
        if (value & 2)
758
            omap_gpio_module_reset(s);
759
        s->config[0] = value & 0x1d;
760
        break;
761

    
762
    case 0x18:        /* GPIO_IRQSTATUS1 */
763
        if (s->ints[0] & value) {
764
            s->ints[0] &= ~value;
765
            omap_gpio_module_level_update(s, 0);
766
        }
767
        break;
768

    
769
    case 0x1c:        /* GPIO_IRQENABLE1 */
770
        s->mask[0] = value;
771
        omap_gpio_module_int_update(s, 0);
772
        break;
773

    
774
    case 0x20:        /* GPIO_WAKEUPENABLE */
775
        s->wumask = value;
776
        break;
777

    
778
    case 0x28:        /* GPIO_IRQSTATUS2 */
779
        if (s->ints[1] & value) {
780
            s->ints[1] &= ~value;
781
            omap_gpio_module_level_update(s, 1);
782
        }
783
        break;
784

    
785
    case 0x2c:        /* GPIO_IRQENABLE2 */
786
        s->mask[1] = value;
787
        omap_gpio_module_int_update(s, 1);
788
        break;
789

    
790
    case 0x30:        /* GPIO_CTRL */
791
        s->config[1] = value & 7;
792
        break;
793

    
794
    case 0x34:        /* GPIO_OE */
795
        diff = s->outputs & (s->dir ^ value);
796
        s->dir = value;
797

    
798
        value = s->outputs & ~s->dir;
799
        while ((ln = ffs(diff))) {
800
            diff &= ~(1 <<-- ln);
801
            qemu_set_irq(s->handler[ln], (value >> ln) & 1);
802
        }
803

    
804
        omap_gpio_module_level_update(s, 0);
805
        omap_gpio_module_level_update(s, 1);
806
        break;
807

    
808
    case 0x3c:        /* GPIO_DATAOUT */
809
        omap_gpio_module_out_update(s, s->outputs ^ value);
810
        break;
811

    
812
    case 0x40:        /* GPIO_LEVELDETECT0 */
813
        s->level[0] = value;
814
        omap_gpio_module_level_update(s, 0);
815
        omap_gpio_module_level_update(s, 1);
816
        break;
817

    
818
    case 0x44:        /* GPIO_LEVELDETECT1 */
819
        s->level[1] = value;
820
        omap_gpio_module_level_update(s, 0);
821
        omap_gpio_module_level_update(s, 1);
822
        break;
823

    
824
    case 0x48:        /* GPIO_RISINGDETECT */
825
        s->edge[0] = value;
826
        break;
827

    
828
    case 0x4c:        /* GPIO_FALLINGDETECT */
829
        s->edge[1] = value;
830
        break;
831

    
832
    case 0x50:        /* GPIO_DEBOUNCENABLE */
833
        s->debounce = value;
834
        break;
835

    
836
    case 0x54:        /* GPIO_DEBOUNCINGTIME */
837
        s->delay = value;
838
        break;
839

    
840
    case 0x60:        /* GPIO_CLEARIRQENABLE1 */
841
        s->mask[0] &= ~value;
842
        omap_gpio_module_int_update(s, 0);
843
        break;
844

    
845
    case 0x64:        /* GPIO_SETIRQENABLE1 */
846
        s->mask[0] |= value;
847
        omap_gpio_module_int_update(s, 0);
848
        break;
849

    
850
    case 0x70:        /* GPIO_CLEARIRQENABLE2 */
851
        s->mask[1] &= ~value;
852
        omap_gpio_module_int_update(s, 1);
853
        break;
854

    
855
    case 0x74:        /* GPIO_SETIREQNEABLE2 */
856
        s->mask[1] |= value;
857
        omap_gpio_module_int_update(s, 1);
858
        break;
859

    
860
    case 0x80:        /* GPIO_CLEARWKUENA */
861
        s->wumask &= ~value;
862
        break;
863

    
864
    case 0x84:        /* GPIO_SETWKUENA */
865
        s->wumask |= value;
866
        break;
867

    
868
    case 0x90:        /* GPIO_CLEARDATAOUT */
869
        omap_gpio_module_out_update(s, s->outputs & value);
870
        break;
871

    
872
    case 0x94:        /* GPIO_SETDATAOUT */
873
        omap_gpio_module_out_update(s, ~s->outputs & value);
874
        break;
875

    
876
    default:
877
        OMAP_BAD_REG(addr);
878
        return;
879
    }
880
}
881

    
882
static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
883
{
884
    return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
885
}
886

    
887
static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
888
                uint32_t value)
889
{
890
    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
891
    int offset = addr - s->base;
892
    uint32_t cur = 0;
893
    uint32_t mask = 0xffff;
894

    
895
    switch (offset & ~3) {
896
    case 0x00:        /* GPIO_REVISION */
897
    case 0x14:        /* GPIO_SYSSTATUS */
898
    case 0x38:        /* GPIO_DATAIN */
899
        OMAP_RO_REG(addr);
900
        break;
901

    
902
    case 0x10:        /* GPIO_SYSCONFIG */
903
    case 0x1c:        /* GPIO_IRQENABLE1 */
904
    case 0x20:        /* GPIO_WAKEUPENABLE */
905
    case 0x2c:        /* GPIO_IRQENABLE2 */
906
    case 0x30:        /* GPIO_CTRL */
907
    case 0x34:        /* GPIO_OE */
908
    case 0x3c:        /* GPIO_DATAOUT */
909
    case 0x40:        /* GPIO_LEVELDETECT0 */
910
    case 0x44:        /* GPIO_LEVELDETECT1 */
911
    case 0x48:        /* GPIO_RISINGDETECT */
912
    case 0x4c:        /* GPIO_FALLINGDETECT */
913
    case 0x50:        /* GPIO_DEBOUNCENABLE */
914
    case 0x54:        /* GPIO_DEBOUNCINGTIME */
915
        cur = omap_gpio_module_read(opaque, addr & ~3) &
916
                ~(mask << ((addr & 3) << 3));
917

    
918
        /* Fall through.  */
919
    case 0x18:        /* GPIO_IRQSTATUS1 */
920
    case 0x28:        /* GPIO_IRQSTATUS2 */
921
    case 0x60:        /* GPIO_CLEARIRQENABLE1 */
922
    case 0x64:        /* GPIO_SETIRQENABLE1 */
923
    case 0x70:        /* GPIO_CLEARIRQENABLE2 */
924
    case 0x74:        /* GPIO_SETIREQNEABLE2 */
925
    case 0x80:        /* GPIO_CLEARWKUENA */
926
    case 0x84:        /* GPIO_SETWKUENA */
927
    case 0x90:        /* GPIO_CLEARDATAOUT */
928
    case 0x94:        /* GPIO_SETDATAOUT */
929
        value <<= (addr & 3) << 3;
930
        omap_gpio_module_write(opaque, addr, cur | value);
931
        break;
932

    
933
    default:
934
        OMAP_BAD_REG(addr);
935
        return;
936
    }
937
}
938

    
939
static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
940
    omap_gpio_module_readp,
941
    omap_gpio_module_readp,
942
    omap_gpio_module_read,
943
};
944

    
945
static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
946
    omap_gpio_module_writep,
947
    omap_gpio_module_writep,
948
    omap_gpio_module_write,
949
};
950

    
951
static void omap_gpio_module_init(struct omap2_gpio_s *s,
952
                struct omap_target_agent_s *ta, int region,
953
                qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
954
                omap_clk fclk, omap_clk iclk)
955
{
956
    int iomemtype;
957

    
958
    s->irq[0] = mpu;
959
    s->irq[1] = dsp;
960
    s->wkup = wkup;
961
    s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
962

    
963
    iomemtype = cpu_register_io_memory(0, omap_gpio_module_readfn,
964
                    omap_gpio_module_writefn, s);
965
    s->base = omap_l4_attach(ta, region, iomemtype);
966
}
967

    
968
struct omap_gpif_s {
969
    struct omap2_gpio_s module[5];
970
    int modules;
971

    
972
    target_phys_addr_t topbase;
973
    int autoidle;
974
    int gpo;
975
};
976

    
977
static void omap_gpif_reset(struct omap_gpif_s *s)
978
{
979
    int i;
980

    
981
    for (i = 0; i < s->modules; i ++)
982
        omap_gpio_module_reset(s->module + i);
983

    
984
    s->autoidle = 0;
985
    s->gpo = 0;
986
}
987

    
988
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
989
{
990
    struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
991
    int offset = addr - s->topbase;
992

    
993
    switch (offset) {
994
    case 0x00:        /* IPGENERICOCPSPL_REVISION */
995
        return 0x18;
996

    
997
    case 0x10:        /* IPGENERICOCPSPL_SYSCONFIG */
998
        return s->autoidle;
999

    
1000
    case 0x14:        /* IPGENERICOCPSPL_SYSSTATUS */
1001
        return 0x01;
1002

    
1003
    case 0x18:        /* IPGENERICOCPSPL_IRQSTATUS */
1004
        return 0x00;
1005

    
1006
    case 0x40:        /* IPGENERICOCPSPL_GPO */
1007
        return s->gpo;
1008

    
1009
    case 0x50:        /* IPGENERICOCPSPL_GPI */
1010
        return 0x00;
1011
    }
1012

    
1013
    OMAP_BAD_REG(addr);
1014
    return 0;
1015
}
1016

    
1017
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1018
                uint32_t value)
1019
{
1020
    struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1021
    int offset = addr - s->topbase;
1022

    
1023
    switch (offset) {
1024
    case 0x00:        /* IPGENERICOCPSPL_REVISION */
1025
    case 0x14:        /* IPGENERICOCPSPL_SYSSTATUS */
1026
    case 0x18:        /* IPGENERICOCPSPL_IRQSTATUS */
1027
    case 0x50:        /* IPGENERICOCPSPL_GPI */
1028
        OMAP_RO_REG(addr);
1029
        break;
1030

    
1031
    case 0x10:        /* IPGENERICOCPSPL_SYSCONFIG */
1032
        if (value & (1 << 1))                                        /* SOFTRESET */
1033
            omap_gpif_reset(s);
1034
        s->autoidle = value & 1;
1035
        break;
1036

    
1037
    case 0x40:        /* IPGENERICOCPSPL_GPO */
1038
        s->gpo = value & 1;
1039
        break;
1040

    
1041
    default:
1042
        OMAP_BAD_REG(addr);
1043
        return;
1044
    }
1045
}
1046

    
1047
static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
1048
    omap_gpif_top_read,
1049
    omap_gpif_top_read,
1050
    omap_gpif_top_read,
1051
};
1052

    
1053
static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
1054
    omap_gpif_top_write,
1055
    omap_gpif_top_write,
1056
    omap_gpif_top_write,
1057
};
1058

    
1059
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1060
                qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1061
{
1062
    int iomemtype, i;
1063
    struct omap_gpif_s *s = (struct omap_gpif_s *)
1064
            qemu_mallocz(sizeof(struct omap_gpif_s));
1065
    int region[4] = { 0, 2, 4, 5 };
1066

    
1067
    s->modules = modules;
1068
    for (i = 0; i < modules; i ++)
1069
        omap_gpio_module_init(s->module + i, ta, region[i],
1070
                        irq[i], 0, 0, fclk[i], iclk);
1071

    
1072
    omap_gpif_reset(s);
1073

    
1074
    iomemtype = cpu_register_io_memory(0, omap_gpif_top_readfn,
1075
                    omap_gpif_top_writefn, s);
1076
    s->topbase = omap_l4_attach(ta, 1, iomemtype);
1077

    
1078
    return s;
1079
}
1080

    
1081
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1082
{
1083
    if (start >= s->modules * 32 || start < 0)
1084
        cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
1085
                        __FUNCTION__, start);
1086
    return s->module[start >> 5].in + (start & 31);
1087
}
1088

    
1089
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1090
{
1091
    if (line >= s->modules * 32 || line < 0)
1092
        cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
1093
    s->module[line >> 5].handler[line & 31] = handler;
1094
}
1095

    
1096
/* Multichannel SPI */
1097
struct omap_mcspi_s {
1098
    target_phys_addr_t base;
1099
    qemu_irq irq;
1100
    int chnum;
1101

    
1102
    uint32_t sysconfig;
1103
    uint32_t systest;
1104
    uint32_t irqst;
1105
    uint32_t irqen;
1106
    uint32_t wken;
1107
    uint32_t control;
1108

    
1109
    struct omap_mcspi_ch_s {
1110
        qemu_irq txdrq;
1111
        qemu_irq rxdrq;
1112
        uint32_t (*txrx)(void *opaque, uint32_t, int);
1113
        void *opaque;
1114

    
1115
        uint32_t tx;
1116
        uint32_t rx;
1117

    
1118
        uint32_t config;
1119
        uint32_t status;
1120
        uint32_t control;
1121
    } ch[4];
1122
};
1123

    
1124
static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1125
{
1126
    qemu_set_irq(s->irq, s->irqst & s->irqen);
1127
}
1128

    
1129
static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1130
{
1131
    qemu_set_irq(ch->txdrq,
1132
                    (ch->control & 1) &&                /* EN */
1133
                    (ch->config & (1 << 14)) &&                /* DMAW */
1134
                    (ch->status & (1 << 1)) &&                /* TXS */
1135
                    ((ch->config >> 12) & 3) != 1);        /* TRM */
1136
    qemu_set_irq(ch->rxdrq,
1137
                    (ch->control & 1) &&                /* EN */
1138
                    (ch->config & (1 << 15)) &&                /* DMAW */
1139
                    (ch->status & (1 << 0)) &&                /* RXS */
1140
                    ((ch->config >> 12) & 3) != 2);        /* TRM */
1141
}
1142

    
1143
static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1144
{
1145
    struct omap_mcspi_ch_s *ch = s->ch + chnum;
1146

    
1147
    if (!(ch->control & 1))                                /* EN */
1148
        return;
1149
    if ((ch->status & (1 << 0)) &&                        /* RXS */
1150
                    ((ch->config >> 12) & 3) != 2 &&        /* TRM */
1151
                    !(ch->config & (1 << 19)))                /* TURBO */
1152
        goto intr_update;
1153
    if ((ch->status & (1 << 1)) &&                        /* TXS */
1154
                    ((ch->config >> 12) & 3) != 1)        /* TRM */
1155
        goto intr_update;
1156

    
1157
    if (!(s->control & 1) ||                                /* SINGLE */
1158
                    (ch->config & (1 << 20))) {                /* FORCE */
1159
        if (ch->txrx)
1160
            ch->rx = ch->txrx(ch->opaque, ch->tx,        /* WL */
1161
                            1 + (0x1f & (ch->config >> 7)));
1162
    }
1163

    
1164
    ch->tx = 0;
1165
    ch->status |= 1 << 2;                                /* EOT */
1166
    ch->status |= 1 << 1;                                /* TXS */
1167
    if (((ch->config >> 12) & 3) != 2)                        /* TRM */
1168
        ch->status |= 1 << 0;                                /* RXS */
1169

    
1170
intr_update:
1171
    if ((ch->status & (1 << 0)) &&                        /* RXS */
1172
                    ((ch->config >> 12) & 3) != 2 &&        /* TRM */
1173
                    !(ch->config & (1 << 19)))                /* TURBO */
1174
        s->irqst |= 1 << (2 + 4 * chnum);                /* RX_FULL */
1175
    if ((ch->status & (1 << 1)) &&                        /* TXS */
1176
                    ((ch->config >> 12) & 3) != 1)        /* TRM */
1177
        s->irqst |= 1 << (0 + 4 * chnum);                /* TX_EMPTY */
1178
    omap_mcspi_interrupt_update(s);
1179
    omap_mcspi_dmarequest_update(ch);
1180
}
1181

    
1182
static void omap_mcspi_reset(struct omap_mcspi_s *s)
1183
{
1184
    int ch;
1185

    
1186
    s->sysconfig = 0;
1187
    s->systest = 0;
1188
    s->irqst = 0;
1189
    s->irqen = 0;
1190
    s->wken = 0;
1191
    s->control = 4;
1192

    
1193
    for (ch = 0; ch < 4; ch ++) {
1194
        s->ch[ch].config = 0x060000;
1195
        s->ch[ch].status = 2;                                /* TXS */
1196
        s->ch[ch].control = 0;
1197

    
1198
        omap_mcspi_dmarequest_update(s->ch + ch);
1199
    }
1200

    
1201
    omap_mcspi_interrupt_update(s);
1202
}
1203

    
1204
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1205
{
1206
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1207
    int offset = addr - s->base;
1208
    int ch = 0;
1209
    uint32_t ret;
1210

    
1211
    switch (offset) {
1212
    case 0x00:        /* MCSPI_REVISION */
1213
        return 0x91;
1214

    
1215
    case 0x10:        /* MCSPI_SYSCONFIG */
1216
        return s->sysconfig;
1217

    
1218
    case 0x14:        /* MCSPI_SYSSTATUS */
1219
        return 1;                                        /* RESETDONE */
1220

    
1221
    case 0x18:        /* MCSPI_IRQSTATUS */
1222
        return s->irqst;
1223

    
1224
    case 0x1c:        /* MCSPI_IRQENABLE */
1225
        return s->irqen;
1226

    
1227
    case 0x20:        /* MCSPI_WAKEUPENABLE */
1228
        return s->wken;
1229

    
1230
    case 0x24:        /* MCSPI_SYST */
1231
        return s->systest;
1232

    
1233
    case 0x28:        /* MCSPI_MODULCTRL */
1234
        return s->control;
1235

    
1236
    case 0x68: ch ++;
1237
    case 0x54: ch ++;
1238
    case 0x40: ch ++;
1239
    case 0x2c:        /* MCSPI_CHCONF */
1240
        return s->ch[ch].config;
1241

    
1242
    case 0x6c: ch ++;
1243
    case 0x58: ch ++;
1244
    case 0x44: ch ++;
1245
    case 0x30:        /* MCSPI_CHSTAT */
1246
        return s->ch[ch].status;
1247

    
1248
    case 0x70: ch ++;
1249
    case 0x5c: ch ++;
1250
    case 0x48: ch ++;
1251
    case 0x34:        /* MCSPI_CHCTRL */
1252
        return s->ch[ch].control;
1253

    
1254
    case 0x74: ch ++;
1255
    case 0x60: ch ++;
1256
    case 0x4c: ch ++;
1257
    case 0x38:        /* MCSPI_TX */
1258
        return s->ch[ch].tx;
1259

    
1260
    case 0x78: ch ++;
1261
    case 0x64: ch ++;
1262
    case 0x50: ch ++;
1263
    case 0x3c:        /* MCSPI_RX */
1264
        s->ch[ch].status &= ~(1 << 0);                        /* RXS */
1265
        ret = s->ch[ch].rx;
1266
        omap_mcspi_transfer_run(s, ch);
1267
        return ret;
1268
    }
1269

    
1270
    OMAP_BAD_REG(addr);
1271
    return 0;
1272
}
1273

    
1274
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1275
                uint32_t value)
1276
{
1277
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1278
    int offset = addr - s->base;
1279
    int ch = 0;
1280

    
1281
    switch (offset) {
1282
    case 0x00:        /* MCSPI_REVISION */
1283
    case 0x14:        /* MCSPI_SYSSTATUS */
1284
    case 0x30:        /* MCSPI_CHSTAT0 */
1285
    case 0x3c:        /* MCSPI_RX0 */
1286
    case 0x44:        /* MCSPI_CHSTAT1 */
1287
    case 0x50:        /* MCSPI_RX1 */
1288
    case 0x58:        /* MCSPI_CHSTAT2 */
1289
    case 0x64:        /* MCSPI_RX2 */
1290
    case 0x6c:        /* MCSPI_CHSTAT3 */
1291
    case 0x78:        /* MCSPI_RX3 */
1292
        OMAP_RO_REG(addr);
1293
        return;
1294

    
1295
    case 0x10:        /* MCSPI_SYSCONFIG */
1296
        if (value & (1 << 1))                                /* SOFTRESET */
1297
            omap_mcspi_reset(s);
1298
        s->sysconfig = value & 0x31d;
1299
        break;
1300

    
1301
    case 0x18:        /* MCSPI_IRQSTATUS */
1302
        if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1303
            s->irqst &= ~value;
1304
            omap_mcspi_interrupt_update(s);
1305
        }
1306
        break;
1307

    
1308
    case 0x1c:        /* MCSPI_IRQENABLE */
1309
        s->irqen = value & 0x1777f;
1310
        omap_mcspi_interrupt_update(s);
1311
        break;
1312

    
1313
    case 0x20:        /* MCSPI_WAKEUPENABLE */
1314
        s->wken = value & 1;
1315
        break;
1316

    
1317
    case 0x24:        /* MCSPI_SYST */
1318
        if (s->control & (1 << 3))                        /* SYSTEM_TEST */
1319
            if (value & (1 << 11)) {                        /* SSB */
1320
                s->irqst |= 0x1777f;
1321
                omap_mcspi_interrupt_update(s);
1322
            }
1323
        s->systest = value & 0xfff;
1324
        break;
1325

    
1326
    case 0x28:        /* MCSPI_MODULCTRL */
1327
        if (value & (1 << 3))                                /* SYSTEM_TEST */
1328
            if (s->systest & (1 << 11)) {                /* SSB */
1329
                s->irqst |= 0x1777f;
1330
                omap_mcspi_interrupt_update(s);
1331
            }
1332
        s->control = value & 0xf;
1333
        break;
1334

    
1335
    case 0x68: ch ++;
1336
    case 0x54: ch ++;
1337
    case 0x40: ch ++;
1338
    case 0x2c:        /* MCSPI_CHCONF */
1339
        if ((value ^ s->ch[ch].config) & (3 << 14))        /* DMAR | DMAW */
1340
            omap_mcspi_dmarequest_update(s->ch + ch);
1341
        if (((value >> 12) & 3) == 3)                        /* TRM */
1342
            fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1343
        if (((value >> 7) & 0x1f) < 3)                        /* WL */
1344
            fprintf(stderr, "%s: invalid WL value (%i)\n",
1345
                            __FUNCTION__, (value >> 7) & 0x1f);
1346
        s->ch[ch].config = value & 0x7fffff;
1347
        break;
1348

    
1349
    case 0x70: ch ++;
1350
    case 0x5c: ch ++;
1351
    case 0x48: ch ++;
1352
    case 0x34:        /* MCSPI_CHCTRL */
1353
        if (value & ~s->ch[ch].control & 1) {                /* EN */
1354
            s->ch[ch].control |= 1;
1355
            omap_mcspi_transfer_run(s, ch);
1356
        } else
1357
            s->ch[ch].control = value & 1;
1358
        break;
1359

    
1360
    case 0x74: ch ++;
1361
    case 0x60: ch ++;
1362
    case 0x4c: ch ++;
1363
    case 0x38:        /* MCSPI_TX */
1364
        s->ch[ch].tx = value;
1365
        s->ch[ch].status &= ~(1 << 1);                        /* TXS */
1366
        omap_mcspi_transfer_run(s, ch);
1367
        break;
1368

    
1369
    default:
1370
        OMAP_BAD_REG(addr);
1371
        return;
1372
    }
1373
}
1374

    
1375
static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
1376
    omap_badwidth_read32,
1377
    omap_badwidth_read32,
1378
    omap_mcspi_read,
1379
};
1380

    
1381
static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
1382
    omap_badwidth_write32,
1383
    omap_badwidth_write32,
1384
    omap_mcspi_write,
1385
};
1386

    
1387
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1388
                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1389
{
1390
    int iomemtype;
1391
    struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1392
            qemu_mallocz(sizeof(struct omap_mcspi_s));
1393
    struct omap_mcspi_ch_s *ch = s->ch;
1394

    
1395
    s->irq = irq;
1396
    s->chnum = chnum;
1397
    while (chnum --) {
1398
        ch->txdrq = *drq ++;
1399
        ch->rxdrq = *drq ++;
1400
        ch ++;
1401
    }
1402
    omap_mcspi_reset(s);
1403

    
1404
    iomemtype = cpu_register_io_memory(0, omap_mcspi_readfn,
1405
                    omap_mcspi_writefn, s);
1406
    s->base = omap_l4_attach(ta, 0, iomemtype);
1407

    
1408
    return s;
1409
}
1410

    
1411
void omap_mcspi_attach(struct omap_mcspi_s *s,
1412
                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
1413
                int chipselect)
1414
{
1415
    if (chipselect < 0 || chipselect >= s->chnum)
1416
        cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
1417
                        __FUNCTION__, chipselect);
1418

    
1419
    s->ch[chipselect].txrx = txrx;
1420
    s->ch[chipselect].opaque = opaque;
1421
}
1422

    
1423
/* STI/XTI (emulation interface) console - reverse engineered only */
1424
struct omap_sti_s {
1425
    target_phys_addr_t base;
1426
    target_phys_addr_t channel_base;
1427
    qemu_irq irq;
1428
    CharDriverState *chr;
1429

    
1430
    uint32_t sysconfig;
1431
    uint32_t systest;
1432
    uint32_t irqst;
1433
    uint32_t irqen;
1434
    uint32_t clkcontrol;
1435
    uint32_t serial_config;
1436
};
1437

    
1438
#define STI_TRACE_CONSOLE_CHANNEL        239
1439
#define STI_TRACE_CONTROL_CHANNEL        253
1440

    
1441
static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
1442
{
1443
    qemu_set_irq(s->irq, s->irqst & s->irqen);
1444
}
1445

    
1446
static void omap_sti_reset(struct omap_sti_s *s)
1447
{
1448
    s->sysconfig = 0;
1449
    s->irqst = 0;
1450
    s->irqen = 0;
1451
    s->clkcontrol = 0;
1452
    s->serial_config = 0;
1453

    
1454
    omap_sti_interrupt_update(s);
1455
}
1456

    
1457
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
1458
{
1459
    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1460
    int offset = addr - s->base;
1461

    
1462
    switch (offset) {
1463
    case 0x00:        /* STI_REVISION */
1464
        return 0x10;
1465

    
1466
    case 0x10:        /* STI_SYSCONFIG */
1467
        return s->sysconfig;
1468

    
1469
    case 0x14:        /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1470
        return 0x00;
1471

    
1472
    case 0x18:        /* STI_IRQSTATUS */
1473
        return s->irqst;
1474

    
1475
    case 0x1c:        /* STI_IRQSETEN / STI_IRQCLREN */
1476
        return s->irqen;
1477

    
1478
    case 0x24:        /* STI_ER / STI_DR / XTI_TRACESELECT */
1479
    case 0x28:        /* STI_RX_DR / XTI_RXDATA */
1480
        /* TODO */
1481
        return 0;
1482

    
1483
    case 0x2c:        /* STI_CLK_CTRL / XTI_SCLKCRTL */
1484
        return s->clkcontrol;
1485

    
1486
    case 0x30:        /* STI_SERIAL_CFG / XTI_SCONFIG */
1487
        return s->serial_config;
1488
    }
1489

    
1490
    OMAP_BAD_REG(addr);
1491
    return 0;
1492
}
1493

    
1494
static void omap_sti_write(void *opaque, target_phys_addr_t addr,
1495
                uint32_t value)
1496
{
1497
    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1498
    int offset = addr - s->base;
1499

    
1500
    switch (offset) {
1501
    case 0x00:        /* STI_REVISION */
1502
    case 0x14:        /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1503
        OMAP_RO_REG(addr);
1504
        return;
1505

    
1506
    case 0x10:        /* STI_SYSCONFIG */
1507
        if (value & (1 << 1))                                /* SOFTRESET */
1508
            omap_sti_reset(s);
1509
        s->sysconfig = value & 0xfe;
1510
        break;
1511

    
1512
    case 0x18:        /* STI_IRQSTATUS */
1513
        s->irqst &= ~value;
1514
        omap_sti_interrupt_update(s);
1515
        break;
1516

    
1517
    case 0x1c:        /* STI_IRQSETEN / STI_IRQCLREN */
1518
        s->irqen = value & 0xffff;
1519
        omap_sti_interrupt_update(s);
1520
        break;
1521

    
1522
    case 0x2c:        /* STI_CLK_CTRL / XTI_SCLKCRTL */
1523
        s->clkcontrol = value & 0xff;
1524
        break;
1525

    
1526
    case 0x30:        /* STI_SERIAL_CFG / XTI_SCONFIG */
1527
        s->serial_config = value & 0xff;
1528
        break;
1529

    
1530
    case 0x24:        /* STI_ER / STI_DR / XTI_TRACESELECT */
1531
    case 0x28:        /* STI_RX_DR / XTI_RXDATA */
1532
        /* TODO */
1533
        return;
1534

    
1535
    default:
1536
        OMAP_BAD_REG(addr);
1537
        return;
1538
    }
1539
}
1540

    
1541
static CPUReadMemoryFunc *omap_sti_readfn[] = {
1542
    omap_badwidth_read32,
1543
    omap_badwidth_read32,
1544
    omap_sti_read,
1545
};
1546

    
1547
static CPUWriteMemoryFunc *omap_sti_writefn[] = {
1548
    omap_badwidth_write32,
1549
    omap_badwidth_write32,
1550
    omap_sti_write,
1551
};
1552

    
1553
static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
1554
{
1555
    OMAP_BAD_REG(addr);
1556
    return 0;
1557
}
1558

    
1559
static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
1560
                uint32_t value)
1561
{
1562
    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1563
    int offset = addr - s->channel_base;
1564
    int ch = offset >> 6;
1565
    uint8_t byte = value;
1566

    
1567
    if (ch == STI_TRACE_CONTROL_CHANNEL) {
1568
        /* Flush channel <i>value</i>.  */
1569
        qemu_chr_write(s->chr, "\r", 1);
1570
    } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
1571
        if (value == 0xc0 || value == 0xc3) {
1572
            /* Open channel <i>ch</i>.  */
1573
        } else if (value == 0x00)
1574
            qemu_chr_write(s->chr, "\n", 1);
1575
        else
1576
            qemu_chr_write(s->chr, &byte, 1);
1577
    }
1578
}
1579

    
1580
static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
1581
    omap_sti_fifo_read,
1582
    omap_badwidth_read8,
1583
    omap_badwidth_read8,
1584
};
1585

    
1586
static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
1587
    omap_sti_fifo_write,
1588
    omap_badwidth_write8,
1589
    omap_badwidth_write8,
1590
};
1591

    
1592
struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
1593
                target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
1594
                CharDriverState *chr)
1595
{
1596
    int iomemtype;
1597
    struct omap_sti_s *s = (struct omap_sti_s *)
1598
            qemu_mallocz(sizeof(struct omap_sti_s));
1599

    
1600
    s->irq = irq;
1601
    omap_sti_reset(s);
1602

    
1603
    s->chr = chr ?: qemu_chr_open("null");
1604

    
1605
    iomemtype = cpu_register_io_memory(0, omap_sti_readfn,
1606
                    omap_sti_writefn, s);
1607
    s->base = omap_l4_attach(ta, 0, iomemtype);
1608

    
1609
    iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
1610
                    omap_sti_fifo_writefn, s);
1611
    s->channel_base = channel_base;
1612
    cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
1613

    
1614
    return s;
1615
}
1616

    
1617
/* L4 Interconnect */
1618
struct omap_target_agent_s {
1619
    struct omap_l4_s *bus;
1620
    int regions;
1621
    struct omap_l4_region_s *start;
1622
    target_phys_addr_t base;
1623
    uint32_t component;
1624
    uint32_t control;
1625
    uint32_t status;
1626
};
1627

    
1628
struct omap_l4_s {
1629
    target_phys_addr_t base;
1630
    int ta_num;
1631
    struct omap_target_agent_s ta[0];
1632
};
1633

    
1634
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
1635
{
1636
    struct omap_l4_s *bus = qemu_mallocz(
1637
                    sizeof(*bus) + ta_num * sizeof(*bus->ta));
1638

    
1639
    bus->ta_num = ta_num;
1640
    bus->base = base;
1641

    
1642
    return bus;
1643
}
1644

    
1645
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
1646
{
1647
    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1648
    target_phys_addr_t reg = addr - s->base;
1649

    
1650
    switch (reg) {
1651
    case 0x00:        /* COMPONENT */
1652
        return s->component;
1653

    
1654
    case 0x20:        /* AGENT_CONTROL */
1655
        return s->control;
1656

    
1657
    case 0x28:        /* AGENT_STATUS */
1658
        return s->status;
1659
    }
1660

    
1661
    OMAP_BAD_REG(addr);
1662
    return 0;
1663
}
1664

    
1665
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
1666
                uint32_t value)
1667
{
1668
    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1669
    target_phys_addr_t reg = addr - s->base;
1670

    
1671
    switch (reg) {
1672
    case 0x00:        /* COMPONENT */
1673
    case 0x28:        /* AGENT_STATUS */
1674
        OMAP_RO_REG(addr);
1675
        break;
1676

    
1677
    case 0x20:        /* AGENT_CONTROL */
1678
        s->control = value & 0x01000700;
1679
        if (value & 1)                                        /* OCP_RESET */
1680
            s->status &= ~1;                                /* REQ_TIMEOUT */
1681
        break;
1682

    
1683
    default:
1684
        OMAP_BAD_REG(addr);
1685
    }
1686
}
1687

    
1688
static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
1689
    omap_badwidth_read16,
1690
    omap_l4ta_read,
1691
    omap_badwidth_read16,
1692
};
1693

    
1694
static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
1695
    omap_badwidth_write32,
1696
    omap_badwidth_write32,
1697
    omap_l4ta_write,
1698
};
1699

    
1700
#define L4TA(n)                (n)
1701
#define L4TAO(n)        ((n) + 39)
1702

    
1703
static struct omap_l4_region_s {
1704
    target_phys_addr_t offset;
1705
    size_t size;
1706
    int access;
1707
} omap_l4_region[125] = {
1708
    [  1] = { 0x40800,  0x800, 32          }, /* Initiator agent */
1709
    [  2] = { 0x41000, 0x1000, 32          }, /* Link agent */
1710
    [  0] = { 0x40000,  0x800, 32          }, /* Address and protection */
1711
    [  3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
1712
    [  4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
1713
    [  5] = { 0x04000, 0x1000, 32 | 16     }, /* 32K Timer */
1714
    [  6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
1715
    [  7] = { 0x08000,  0x800, 32          }, /* PRCM Region A */
1716
    [  8] = { 0x08800,  0x800, 32          }, /* PRCM Region B */
1717
    [  9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
1718
    [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
1719
    [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
1720
    [ 12] = { 0x14000, 0x1000, 32          }, /* Test/emulation (TAP) */
1721
    [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
1722
    [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
1723
    [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
1724
    [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
1725
    [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
1726
    [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
1727
    [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
1728
    [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
1729
    [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
1730
    [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
1731
    [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
1732
    [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
1733
    [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
1734
    [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
1735
    [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
1736
    [ 28] = { 0x50000,  0x400, 32 | 16 | 8 }, /* Display top */
1737
    [ 29] = { 0x50400,  0x400, 32 | 16 | 8 }, /* Display control */
1738
    [ 30] = { 0x50800,  0x400, 32 | 16 | 8 }, /* Display RFBI */
1739
    [ 31] = { 0x50c00,  0x400, 32 | 16 | 8 }, /* Display encoder */
1740
    [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
1741
    [ 33] = { 0x52000,  0x400, 32 | 16 | 8 }, /* Camera top */
1742
    [ 34] = { 0x52400,  0x400, 32 | 16 | 8 }, /* Camera core */
1743
    [ 35] = { 0x52800,  0x400, 32 | 16 | 8 }, /* Camera DMA */
1744
    [ 36] = { 0x52c00,  0x400, 32 | 16 | 8 }, /* Camera MMU */
1745
    [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
1746
    [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
1747
    [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
1748
    [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
1749
    [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
1750
    [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
1751
    [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
1752
    [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
1753
    [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
1754
    [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
1755
    [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
1756
    [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
1757
    [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
1758
    [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
1759
    [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
1760
    [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
1761
    [ 53] = { 0x66000,  0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
1762
    [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
1763
    [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
1764
    [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
1765
    [ 57] = { 0x6a000, 0x1000,      16 | 8 }, /* UART1 */
1766
    [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
1767
    [ 59] = { 0x6c000, 0x1000,      16 | 8 }, /* UART2 */
1768
    [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
1769
    [ 61] = { 0x6e000, 0x1000,      16 | 8 }, /* UART3 */
1770
    [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
1771
    [ 63] = { 0x70000, 0x1000,      16     }, /* I2C1 */
1772
    [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
1773
    [ 65] = { 0x72000, 0x1000,      16     }, /* I2C2 */
1774
    [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
1775
    [ 67] = { 0x74000, 0x1000,      16     }, /* McBSP1 */
1776
    [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
1777
    [ 69] = { 0x76000, 0x1000,      16     }, /* McBSP2 */
1778
    [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
1779
    [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
1780
    [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
1781
    [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
1782
    [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
1783
    [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
1784
    [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
1785
    [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
1786
    [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
1787
    [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
1788
    [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
1789
    [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
1790
    [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
1791
    [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
1792
    [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
1793
    [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
1794
    [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
1795
    [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
1796
    [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
1797
    [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
1798
    [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
1799
    [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
1800
    [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
1801
    [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
1802
    [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
1803
    [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
1804
    [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
1805
    [ 97] = { 0x90000, 0x1000,      16     }, /* EAC */
1806
    [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
1807
    [ 99] = { 0x92000, 0x1000,      16     }, /* FAC */
1808
    [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
1809
    [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
1810
    [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
1811
    [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
1812
    [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
1813
    [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
1814
    [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
1815
    [107] = { 0x9c000, 0x1000,      16 | 8 }, /* MMC SDIO */
1816
    [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
1817
    [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
1818
    [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
1819
    [111] = { 0xa0000, 0x1000, 32          }, /* RNG */
1820
    [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
1821
    [113] = { 0xa2000, 0x1000, 32          }, /* DES3DES */
1822
    [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
1823
    [115] = { 0xa4000, 0x1000, 32          }, /* SHA1MD5 */
1824
    [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
1825
    [117] = { 0xa6000, 0x1000, 32          }, /* AES */
1826
    [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
1827
    [119] = { 0xa8000, 0x2000, 32          }, /* PKA */
1828
    [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
1829
    [121] = { 0xb0000, 0x1000, 32          }, /* MG */
1830
    [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
1831
    [123] = { 0xb2000, 0x1000, 32          }, /* HDQ/1-Wire */
1832
    [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
1833
};
1834

    
1835
static struct omap_l4_agent_info_s {
1836
    int ta;
1837
    int region;
1838
    int regions;
1839
    int ta_region;
1840
} omap_l4_agent_info[54] = {
1841
    { 0,           0, 3, 2 }, /* L4IA initiatior agent */
1842
    { L4TAO(1),    3, 2, 1 }, /* Control and pinout module */
1843
    { L4TAO(2),    5, 2, 1 }, /* 32K timer */
1844
    { L4TAO(3),    7, 3, 2 }, /* PRCM */
1845
    { L4TA(1),    10, 2, 1 }, /* BCM */
1846
    { L4TA(2),    12, 2, 1 }, /* Test JTAG */
1847
    { L4TA(3),    14, 6, 3 }, /* Quad GPIO */
1848
    { L4TA(4),    20, 4, 3 }, /* WD timer 1/2 */
1849
    { L4TA(7),    24, 2, 1 }, /* GP timer 1 */
1850
    { L4TA(9),    26, 2, 1 }, /* ATM11 ETB */
1851
    { L4TA(10),   28, 5, 4 }, /* Display subsystem */
1852
    { L4TA(11),   33, 5, 4 }, /* Camera subsystem */
1853
    { L4TA(12),   38, 2, 1 }, /* sDMA */
1854
    { L4TA(13),   40, 5, 4 }, /* SSI */
1855
    { L4TAO(4),   45, 2, 1 }, /* USB */
1856
    { L4TA(14),   47, 2, 1 }, /* Win Tracer1 */
1857
    { L4TA(15),   49, 2, 1 }, /* Win Tracer2 */
1858
    { L4TA(16),   51, 2, 1 }, /* Win Tracer3 */
1859
    { L4TA(17),   53, 2, 1 }, /* Win Tracer4 */
1860
    { L4TA(18),   55, 2, 1 }, /* XTI */
1861
    { L4TA(19),   57, 2, 1 }, /* UART1 */
1862
    { L4TA(20),   59, 2, 1 }, /* UART2 */
1863
    { L4TA(21),   61, 2, 1 }, /* UART3 */
1864
    { L4TAO(5),   63, 2, 1 }, /* I2C1 */
1865
    { L4TAO(6),   65, 2, 1 }, /* I2C2 */
1866
    { L4TAO(7),   67, 2, 1 }, /* McBSP1 */
1867
    { L4TAO(8),   69, 2, 1 }, /* McBSP2 */
1868
    { L4TA(5),    71, 2, 1 }, /* WD Timer 3 (DSP) */
1869
    { L4TA(6),    73, 2, 1 }, /* WD Timer 4 (IVA) */
1870
    { L4TA(8),    75, 2, 1 }, /* GP Timer 2 */
1871
    { L4TA(22),   77, 2, 1 }, /* GP Timer 3 */
1872
    { L4TA(23),   79, 2, 1 }, /* GP Timer 4 */
1873
    { L4TA(24),   81, 2, 1 }, /* GP Timer 5 */
1874
    { L4TA(25),   83, 2, 1 }, /* GP Timer 6 */
1875
    { L4TA(26),   85, 2, 1 }, /* GP Timer 7 */
1876
    { L4TA(27),   87, 2, 1 }, /* GP Timer 8 */
1877
    { L4TA(28),   89, 2, 1 }, /* GP Timer 9 */
1878
    { L4TA(29),   91, 2, 1 }, /* GP Timer 10 */
1879
    { L4TA(30),   93, 2, 1 }, /* GP Timer 11 */
1880
    { L4TA(31),   95, 2, 1 }, /* GP Timer 12 */
1881
    { L4TA(32),   97, 2, 1 }, /* EAC */
1882
    { L4TA(33),   99, 2, 1 }, /* FAC */
1883
    { L4TA(34),  101, 2, 1 }, /* IPC */
1884
    { L4TA(35),  103, 2, 1 }, /* SPI1 */
1885
    { L4TA(36),  105, 2, 1 }, /* SPI2 */
1886
    { L4TAO(9),  107, 2, 1 }, /* MMC SDIO */
1887
    { L4TAO(10), 109, 2, 1 },
1888
    { L4TAO(11), 111, 2, 1 }, /* RNG */
1889
    { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1890
    { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1891
    { L4TA(37),  117, 2, 1 }, /* AES */
1892
    { L4TA(38),  119, 2, 1 }, /* PKA */
1893
    { -1,        121, 2, 1 },
1894
    { L4TA(39),  123, 2, 1 }, /* HDQ/1-Wire */
1895
};
1896

    
1897
#define omap_l4ta(bus, cs)        omap_l4ta_get(bus, L4TA(cs))
1898
#define omap_l4tao(bus, cs)        omap_l4ta_get(bus, L4TAO(cs))
1899

    
1900
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
1901
{
1902
    int i, iomemtype;
1903
    struct omap_target_agent_s *ta = 0;
1904
    struct omap_l4_agent_info_s *info = 0;
1905

    
1906
    for (i = 0; i < bus->ta_num; i ++)
1907
        if (omap_l4_agent_info[i].ta == cs) {
1908
            ta = &bus->ta[i];
1909
            info = &omap_l4_agent_info[i];
1910
            break;
1911
        }
1912
    if (!ta) {
1913
        fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
1914
        exit(-1);
1915
    }
1916

    
1917
    ta->bus = bus;
1918
    ta->start = &omap_l4_region[info->region];
1919
    ta->regions = info->regions;
1920
    ta->base = bus->base + ta->start[info->ta_region].offset;
1921

    
1922
    ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1923
    ta->status = 0x00000000;
1924
    ta->control = 0x00000200;        /* XXX 01000200 for L4TAO */
1925

    
1926
    iomemtype = cpu_register_io_memory(0, omap_l4ta_readfn,
1927
                    omap_l4ta_writefn, ta);
1928
    cpu_register_physical_memory(ta->base, 0x200, iomemtype);
1929

    
1930
    return ta;
1931
}
1932

    
1933
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
1934
                int iotype)
1935
{
1936
    target_phys_addr_t base;
1937
    size_t size;
1938

    
1939
    if (region < 0 || region >= ta->regions) {
1940
        fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
1941
        exit(-1);
1942
    }
1943

    
1944
    base = ta->bus->base + ta->start[region].offset;
1945
    size = ta->start[region].size;
1946
    if (iotype)
1947
        cpu_register_physical_memory(base, size, iotype);
1948

    
1949
    return base;
1950
}
1951

    
1952
/* TEST-Chip-level TAP */
1953
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
1954
{
1955
    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1956
    target_phys_addr_t reg = addr - s->tap_base;
1957

    
1958
    switch (reg) {
1959
    case 0x204:        /* IDCODE_reg */
1960
        switch (s->mpu_model) {
1961
        case omap2420:
1962
        case omap2422:
1963
        case omap2423:
1964
            return 0x5b5d902f;        /* ES 2.2 */
1965
        case omap2430:
1966
            return 0x5b68a02f;        /* ES 2.2 */
1967
        case omap3430:
1968
            return 0x1b7ae02f;        /* ES 2 */
1969
        default:
1970
            cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
1971
        }
1972

    
1973
    case 0x208:        /* PRODUCTION_ID_reg for OMAP2 */
1974
    case 0x210:        /* PRODUCTION_ID_reg for OMAP3 */
1975
        switch (s->mpu_model) {
1976
        case omap2420:
1977
            return 0x000254f0;        /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
1978
        case omap2422:
1979
            return 0x000400f0;
1980
        case omap2423:
1981
            return 0x000800f0;
1982
        case omap2430:
1983
            return 0x000000f0;
1984
        case omap3430:
1985
            return 0x000000f0;
1986
        default:
1987
            cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
1988
        }
1989

    
1990
    case 0x20c:
1991
        switch (s->mpu_model) {
1992
        case omap2420:
1993
        case omap2422:
1994
        case omap2423:
1995
            return 0xcafeb5d9;        /* ES 2.2 */
1996
        case omap2430:
1997
            return 0xcafeb68a;        /* ES 2.2 */
1998
        case omap3430:
1999
            return 0xcafeb7ae;        /* ES 2 */
2000
        default:
2001
            cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2002
        }
2003

    
2004
    case 0x218:        /* DIE_ID_reg */
2005
        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2006
    case 0x21c:        /* DIE_ID_reg */
2007
        return 0x54 << 24;
2008
    case 0x220:        /* DIE_ID_reg */
2009
        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2010
    case 0x224:        /* DIE_ID_reg */
2011
        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2012
    }
2013

    
2014
    OMAP_BAD_REG(addr);
2015
    return 0;
2016
}
2017

    
2018
static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2019
                uint32_t value)
2020
{
2021
    OMAP_BAD_REG(addr);
2022
}
2023

    
2024
static CPUReadMemoryFunc *omap_tap_readfn[] = {
2025
    omap_badwidth_read32,
2026
    omap_badwidth_read32,
2027
    omap_tap_read,
2028
};
2029

    
2030
static CPUWriteMemoryFunc *omap_tap_writefn[] = {
2031
    omap_badwidth_write32,
2032
    omap_badwidth_write32,
2033
    omap_tap_write,
2034
};
2035

    
2036
void omap_tap_init(struct omap_target_agent_s *ta,
2037
                struct omap_mpu_state_s *mpu)
2038
{
2039
    mpu->tap_base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
2040
                            omap_tap_readfn, omap_tap_writefn, mpu));
2041
}
2042

    
2043
/* Power, Reset, and Clock Management */
2044
struct omap_prcm_s {
2045
    target_phys_addr_t base;
2046
    qemu_irq irq[3];
2047
    struct omap_mpu_state_s *mpu;
2048

    
2049
    uint32_t irqst[3];
2050
    uint32_t irqen[3];
2051

    
2052
    uint32_t sysconfig;
2053
    uint32_t voltctrl;
2054
    uint32_t scratch[20];
2055

    
2056
    uint32_t clksrc[1];
2057
    uint32_t clkout[1];
2058
    uint32_t clkemul[1];
2059
    uint32_t clkpol[1];
2060
    uint32_t clksel[8];
2061
    uint32_t clken[12];
2062
    uint32_t clkctrl[4];
2063
    uint32_t clkidle[7];
2064
    uint32_t setuptime[2];
2065

    
2066
    uint32_t wkup[3];
2067
    uint32_t wken[3];
2068
    uint32_t wkst[3];
2069
    uint32_t rst[4];
2070
    uint32_t rstctrl[1];
2071
    uint32_t power[4];
2072
    uint32_t rsttime_wkup;
2073

    
2074
    uint32_t ev;
2075
    uint32_t evtime[2];
2076
};
2077

    
2078
static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2079
{
2080
    qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2081
    /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2082
}
2083

    
2084
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2085
{
2086
    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2087
    int offset = addr - s->base;
2088

    
2089
    switch (offset) {
2090
    case 0x000:        /* PRCM_REVISION */
2091
        return 0x10;
2092

    
2093
    case 0x010:        /* PRCM_SYSCONFIG */
2094
        return s->sysconfig;
2095

    
2096
    case 0x018:        /* PRCM_IRQSTATUS_MPU */
2097
        return s->irqst[0];
2098

    
2099
    case 0x01c:        /* PRCM_IRQENABLE_MPU */
2100
        return s->irqen[0];
2101

    
2102
    case 0x050:        /* PRCM_VOLTCTRL */
2103
        return s->voltctrl;
2104
    case 0x054:        /* PRCM_VOLTST */
2105
        return s->voltctrl & 3;
2106

    
2107
    case 0x060:        /* PRCM_CLKSRC_CTRL */
2108
        return s->clksrc[0];
2109
    case 0x070:        /* PRCM_CLKOUT_CTRL */
2110
        return s->clkout[0];
2111
    case 0x078:        /* PRCM_CLKEMUL_CTRL */
2112
        return s->clkemul[0];
2113
    case 0x080:        /* PRCM_CLKCFG_CTRL */
2114
    case 0x084:        /* PRCM_CLKCFG_STATUS */
2115
        return 0;
2116

    
2117
    case 0x090:        /* PRCM_VOLTSETUP */
2118
        return s->setuptime[0];
2119

    
2120
    case 0x094:        /* PRCM_CLKSSETUP */
2121
        return s->setuptime[1];
2122

    
2123
    case 0x098:        /* PRCM_POLCTRL */
2124
        return s->clkpol[0];
2125

    
2126
    case 0x0b0:        /* GENERAL_PURPOSE1 */
2127
    case 0x0b4:        /* GENERAL_PURPOSE2 */
2128
    case 0x0b8:        /* GENERAL_PURPOSE3 */
2129
    case 0x0bc:        /* GENERAL_PURPOSE4 */
2130
    case 0x0c0:        /* GENERAL_PURPOSE5 */
2131
    case 0x0c4:        /* GENERAL_PURPOSE6 */
2132
    case 0x0c8:        /* GENERAL_PURPOSE7 */
2133
    case 0x0cc:        /* GENERAL_PURPOSE8 */
2134
    case 0x0d0:        /* GENERAL_PURPOSE9 */
2135
    case 0x0d4:        /* GENERAL_PURPOSE10 */
2136
    case 0x0d8:        /* GENERAL_PURPOSE11 */
2137
    case 0x0dc:        /* GENERAL_PURPOSE12 */
2138
    case 0x0e0:        /* GENERAL_PURPOSE13 */
2139
    case 0x0e4:        /* GENERAL_PURPOSE14 */
2140
    case 0x0e8:        /* GENERAL_PURPOSE15 */
2141
    case 0x0ec:        /* GENERAL_PURPOSE16 */
2142
    case 0x0f0:        /* GENERAL_PURPOSE17 */
2143
    case 0x0f4:        /* GENERAL_PURPOSE18 */
2144
    case 0x0f8:        /* GENERAL_PURPOSE19 */
2145
    case 0x0fc:        /* GENERAL_PURPOSE20 */
2146
        return s->scratch[(offset - 0xb0) >> 2];
2147

    
2148
    case 0x140:        /* CM_CLKSEL_MPU */
2149
        return s->clksel[0];
2150
    case 0x148:        /* CM_CLKSTCTRL_MPU */
2151
        return s->clkctrl[0];
2152

    
2153
    case 0x158:        /* RM_RSTST_MPU */
2154
        return s->rst[0];
2155
    case 0x1c8:        /* PM_WKDEP_MPU */
2156
        return s->wkup[0];
2157
    case 0x1d4:        /* PM_EVGENCTRL_MPU */
2158
        return s->ev;
2159
    case 0x1d8:        /* PM_EVEGENONTIM_MPU */
2160
        return s->evtime[0];
2161
    case 0x1dc:        /* PM_EVEGENOFFTIM_MPU */
2162
        return s->evtime[1];
2163
    case 0x1e0:        /* PM_PWSTCTRL_MPU */
2164
        return s->power[0];
2165
    case 0x1e4:        /* PM_PWSTST_MPU */
2166
        return 0;
2167

    
2168
    case 0x200:        /* CM_FCLKEN1_CORE */
2169
        return s->clken[0];
2170
    case 0x204:        /* CM_FCLKEN2_CORE */
2171
        return s->clken[1];
2172
    case 0x210:        /* CM_ICLKEN1_CORE */
2173
        return s->clken[2];
2174
    case 0x214:        /* CM_ICLKEN2_CORE */
2175
        return s->clken[3];
2176
    case 0x21c:        /* CM_ICLKEN4_CORE */
2177
        return s->clken[4];
2178

    
2179
    case 0x220:        /* CM_IDLEST1_CORE */
2180
        /* TODO: check the actual iclk status */
2181
        return 0x7ffffff9;
2182
    case 0x224:        /* CM_IDLEST2_CORE */
2183
        /* TODO: check the actual iclk status */
2184
        return 0x00000007;
2185
    case 0x22c:        /* CM_IDLEST4_CORE */
2186
        /* TODO: check the actual iclk status */
2187
        return 0x0000001f;
2188

    
2189
    case 0x230:        /* CM_AUTOIDLE1_CORE */
2190
        return s->clkidle[0];
2191
    case 0x234:        /* CM_AUTOIDLE2_CORE */
2192
        return s->clkidle[1];
2193
    case 0x238:        /* CM_AUTOIDLE3_CORE */
2194
        return s->clkidle[2];
2195
    case 0x23c:        /* CM_AUTOIDLE4_CORE */
2196
        return s->clkidle[3];
2197

    
2198
    case 0x240:        /* CM_CLKSEL1_CORE */
2199
        return s->clksel[1];
2200
    case 0x244:        /* CM_CLKSEL2_CORE */
2201
        return s->clksel[2];
2202

    
2203
    case 0x248:        /* CM_CLKSTCTRL_CORE */
2204
        return s->clkctrl[1];
2205

    
2206
    case 0x2a0:        /* PM_WKEN1_CORE */
2207
        return s->wken[0];
2208
    case 0x2a4:        /* PM_WKEN2_CORE */
2209
        return s->wken[1];
2210

    
2211
    case 0x2b0:        /* PM_WKST1_CORE */
2212
        return s->wkst[0];
2213
    case 0x2b4:        /* PM_WKST2_CORE */
2214
        return s->wkst[1];
2215
    case 0x2c8:        /* PM_WKDEP_CORE */
2216
        return 0x1e;
2217

    
2218
    case 0x2e0:        /* PM_PWSTCTRL_CORE */
2219
        return s->power[1];
2220
    case 0x2e4:        /* PM_PWSTST_CORE */
2221
        return 0x000030 | (s->power[1] & 0xfc00);
2222

    
2223
    case 0x300:        /* CM_FCLKEN_GFX */
2224
        return s->clken[5];
2225
    case 0x310:        /* CM_ICLKEN_GFX */
2226
        return s->clken[6];
2227
    case 0x320:        /* CM_IDLEST_GFX */
2228
        /* TODO: check the actual iclk status */
2229
        return 0x00000001;
2230
    case 0x340:        /* CM_CLKSEL_GFX */
2231
        return s->clksel[3];
2232
    case 0x348:        /* CM_CLKSTCTRL_GFX */
2233
        return s->clkctrl[2];
2234
    case 0x350:        /* RM_RSTCTRL_GFX */
2235
        return s->rstctrl[0];
2236
    case 0x358:        /* RM_RSTST_GFX */
2237
        return s->rst[1];
2238
    case 0x3c8:        /* PM_WKDEP_GFX */
2239
        return s->wkup[1];
2240

    
2241
    case 0x3e0:        /* PM_PWSTCTRL_GFX */
2242
        return s->power[2];
2243
    case 0x3e4:        /* PM_PWSTST_GFX */
2244
        return s->power[2] & 3;
2245

    
2246
    case 0x400:        /* CM_FCLKEN_WKUP */
2247
        return s->clken[7];
2248
    case 0x410:        /* CM_ICLKEN_WKUP */
2249
        return s->clken[8];
2250
    case 0x420:        /* CM_IDLEST_WKUP */
2251
        /* TODO: check the actual iclk status */
2252
        return 0x0000003f;
2253
    case 0x430:        /* CM_AUTOIDLE_WKUP */
2254
        return s->clkidle[4];
2255
    case 0x440:        /* CM_CLKSEL_WKUP */
2256
        return s->clksel[4];
2257
    case 0x450:        /* RM_RSTCTRL_WKUP */
2258
        return 0;
2259
    case 0x454:        /* RM_RSTTIME_WKUP */
2260
        return s->rsttime_wkup;
2261
    case 0x458:        /* RM_RSTST_WKUP */
2262
        return s->rst[2];
2263
    case 0x4a0:        /* PM_WKEN_WKUP */
2264
        return s->wken[2];
2265
    case 0x4b0:        /* PM_WKST_WKUP */
2266
        return s->wkst[2];
2267

    
2268
    case 0x500:        /* CM_CLKEN_PLL */
2269
        return s->clken[9];
2270
    case 0x520:        /* CM_IDLEST_CKGEN */
2271
        /* Core uses 32-kHz clock */
2272
        if (!(s->clksel[6] & 3))
2273
            return 0x00000377;
2274
        /* DPLL not in lock mode, core uses ref_clk */
2275
        if ((s->clken[9] & 3) != 3)
2276
            return 0x00000375;
2277
        /* Core uses DPLL */
2278
        return 0x00000376;
2279
    case 0x530:        /* CM_AUTOIDLE_PLL */
2280
        return s->clkidle[5];
2281
    case 0x540:        /* CM_CLKSEL1_PLL */
2282
        return s->clksel[5];
2283
    case 0x544:        /* CM_CLKSEL2_PLL */
2284
        return s->clksel[6];
2285

    
2286
    case 0x800:        /* CM_FCLKEN_DSP */
2287
        return s->clken[10];
2288
    case 0x810:        /* CM_ICLKEN_DSP */
2289
        return s->clken[11];
2290
    case 0x820:        /* CM_IDLEST_DSP */
2291
        /* TODO: check the actual iclk status */
2292
        return 0x00000103;
2293
    case 0x830:        /* CM_AUTOIDLE_DSP */
2294
        return s->clkidle[6];
2295
    case 0x840:        /* CM_CLKSEL_DSP */
2296
        return s->clksel[7];
2297
    case 0x848:        /* CM_CLKSTCTRL_DSP */
2298
        return s->clkctrl[3];
2299
    case 0x850:        /* RM_RSTCTRL_DSP */
2300
        return 0;
2301
    case 0x858:        /* RM_RSTST_DSP */
2302
        return s->rst[3];
2303
    case 0x8c8:        /* PM_WKDEP_DSP */
2304
        return s->wkup[2];
2305
    case 0x8e0:        /* PM_PWSTCTRL_DSP */
2306
        return s->power[3];
2307
    case 0x8e4:        /* PM_PWSTST_DSP */
2308
        return 0x008030 | (s->power[3] & 0x3003);
2309

    
2310
    case 0x8f0:        /* PRCM_IRQSTATUS_DSP */
2311
        return s->irqst[1];
2312
    case 0x8f4:        /* PRCM_IRQENABLE_DSP */
2313
        return s->irqen[1];
2314

    
2315
    case 0x8f8:        /* PRCM_IRQSTATUS_IVA */
2316
        return s->irqst[2];
2317
    case 0x8fc:        /* PRCM_IRQENABLE_IVA */
2318
        return s->irqen[2];
2319
    }
2320

    
2321
    OMAP_BAD_REG(addr);
2322
    return 0;
2323
}
2324

    
2325
static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
2326
                uint32_t value)
2327
{
2328
    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2329
    int offset = addr - s->base;
2330

    
2331
    switch (offset) {
2332
    case 0x000:        /* PRCM_REVISION */
2333
    case 0x054:        /* PRCM_VOLTST */
2334
    case 0x084:        /* PRCM_CLKCFG_STATUS */
2335
    case 0x1e4:        /* PM_PWSTST_MPU */
2336
    case 0x220:        /* CM_IDLEST1_CORE */
2337
    case 0x224:        /* CM_IDLEST2_CORE */
2338
    case 0x22c:        /* CM_IDLEST4_CORE */
2339
    case 0x2c8:        /* PM_WKDEP_CORE */
2340
    case 0x2e4:        /* PM_PWSTST_CORE */
2341
    case 0x320:        /* CM_IDLEST_GFX */
2342
    case 0x3e4:        /* PM_PWSTST_GFX */
2343
    case 0x420:        /* CM_IDLEST_WKUP */
2344
    case 0x520:        /* CM_IDLEST_CKGEN */
2345
    case 0x820:        /* CM_IDLEST_DSP */
2346
    case 0x8e4:        /* PM_PWSTST_DSP */
2347
        OMAP_RO_REG(addr);
2348
        return;
2349

    
2350
    case 0x010:        /* PRCM_SYSCONFIG */
2351
        s->sysconfig = value & 1;
2352
        break;
2353

    
2354
    case 0x018:        /* PRCM_IRQSTATUS_MPU */
2355
        s->irqst[0] &= ~value;
2356
        omap_prcm_int_update(s, 0);
2357
        break;
2358
    case 0x01c:        /* PRCM_IRQENABLE_MPU */
2359
        s->irqen[0] = value & 0x3f;
2360
        omap_prcm_int_update(s, 0);
2361
        break;
2362

    
2363
    case 0x050:        /* PRCM_VOLTCTRL */
2364
        s->voltctrl = value & 0xf1c3;
2365
        break;
2366

    
2367
    case 0x060:        /* PRCM_CLKSRC_CTRL */
2368
        s->clksrc[0] = value & 0xdb;
2369
        /* TODO update clocks */
2370
        break;
2371

    
2372
    case 0x070:        /* PRCM_CLKOUT_CTRL */
2373
        s->clkout[0] = value & 0xbbbb;
2374
        /* TODO update clocks */
2375
        break;
2376

    
2377
    case 0x078:        /* PRCM_CLKEMUL_CTRL */
2378
        s->clkemul[0] = value & 1;
2379
        /* TODO update clocks */
2380
        break;
2381

    
2382
    case 0x080:        /* PRCM_CLKCFG_CTRL */
2383
        break;
2384

    
2385
    case 0x090:        /* PRCM_VOLTSETUP */
2386
        s->setuptime[0] = value & 0xffff;
2387
        break;
2388
    case 0x094:        /* PRCM_CLKSSETUP */
2389
        s->setuptime[1] = value & 0xffff;
2390
        break;
2391

    
2392
    case 0x098:        /* PRCM_POLCTRL */
2393
        s->clkpol[0] = value & 0x701;
2394
        break;
2395

    
2396
    case 0x0b0:        /* GENERAL_PURPOSE1 */
2397
    case 0x0b4:        /* GENERAL_PURPOSE2 */
2398
    case 0x0b8:        /* GENERAL_PURPOSE3 */
2399
    case 0x0bc:        /* GENERAL_PURPOSE4 */
2400
    case 0x0c0:        /* GENERAL_PURPOSE5 */
2401
    case 0x0c4:        /* GENERAL_PURPOSE6 */
2402
    case 0x0c8:        /* GENERAL_PURPOSE7 */
2403
    case 0x0cc:        /* GENERAL_PURPOSE8 */
2404
    case 0x0d0:        /* GENERAL_PURPOSE9 */
2405
    case 0x0d4:        /* GENERAL_PURPOSE10 */
2406
    case 0x0d8:        /* GENERAL_PURPOSE11 */
2407
    case 0x0dc:        /* GENERAL_PURPOSE12 */
2408
    case 0x0e0:        /* GENERAL_PURPOSE13 */
2409
    case 0x0e4:        /* GENERAL_PURPOSE14 */
2410
    case 0x0e8:        /* GENERAL_PURPOSE15 */
2411
    case 0x0ec:        /* GENERAL_PURPOSE16 */
2412
    case 0x0f0:        /* GENERAL_PURPOSE17 */
2413
    case 0x0f4:        /* GENERAL_PURPOSE18 */
2414
    case 0x0f8:        /* GENERAL_PURPOSE19 */
2415
    case 0x0fc:        /* GENERAL_PURPOSE20 */
2416
        s->scratch[(offset - 0xb0) >> 2] = value;
2417
        break;
2418

    
2419
    case 0x140:        /* CM_CLKSEL_MPU */
2420
        s->clksel[0] = value & 0x1f;
2421
        /* TODO update clocks */
2422
        break;
2423
    case 0x148:        /* CM_CLKSTCTRL_MPU */
2424
        s->clkctrl[0] = value & 0x1f;
2425
        break;
2426

    
2427
    case 0x158:        /* RM_RSTST_MPU */
2428
        s->rst[0] &= ~value;
2429
        break;
2430
    case 0x1c8:        /* PM_WKDEP_MPU */
2431
        s->wkup[0] = value & 0x15;
2432
        break;
2433

    
2434
    case 0x1d4:        /* PM_EVGENCTRL_MPU */
2435
        s->ev = value & 0x1f;
2436
        break;
2437
    case 0x1d8:        /* PM_EVEGENONTIM_MPU */
2438
        s->evtime[0] = value;
2439
        break;
2440
    case 0x1dc:        /* PM_EVEGENOFFTIM_MPU */
2441
        s->evtime[1] = value;
2442
        break;
2443

    
2444
    case 0x1e0:        /* PM_PWSTCTRL_MPU */
2445
        s->power[0] = value & 0xc0f;
2446
        break;
2447

    
2448
    case 0x200:        /* CM_FCLKEN1_CORE */
2449
        s->clken[0] = value & 0xbfffffff;
2450
        /* TODO update clocks */
2451
        break;
2452
    case 0x204:        /* CM_FCLKEN2_CORE */
2453
        s->clken[1] = value & 0x00000007;
2454
        /* TODO update clocks */
2455
        break;
2456
    case 0x210:        /* CM_ICLKEN1_CORE */
2457
        s->clken[2] = value & 0xfffffff9;
2458
        /* TODO update clocks */
2459
        break;
2460
    case 0x214:        /* CM_ICLKEN2_CORE */
2461
        s->clken[3] = value & 0x00000007;
2462
        /* TODO update clocks */
2463
        break;
2464
    case 0x21c:        /* CM_ICLKEN4_CORE */
2465
        s->clken[4] = value & 0x0000001f;
2466
        /* TODO update clocks */
2467
        break;
2468

    
2469
    case 0x230:        /* CM_AUTOIDLE1_CORE */
2470
        s->clkidle[0] = value & 0xfffffff9;
2471
        /* TODO update clocks */
2472
        break;
2473
    case 0x234:        /* CM_AUTOIDLE2_CORE */
2474
        s->clkidle[1] = value & 0x00000007;
2475
        /* TODO update clocks */
2476
        break;
2477
    case 0x238:        /* CM_AUTOIDLE3_CORE */
2478
        s->clkidle[2] = value & 0x00000007;
2479
        /* TODO update clocks */
2480
        break;
2481
    case 0x23c:        /* CM_AUTOIDLE4_CORE */
2482
        s->clkidle[3] = value & 0x0000001f;
2483
        /* TODO update clocks */
2484
        break;
2485

    
2486
    case 0x240:        /* CM_CLKSEL1_CORE */
2487
        s->clksel[1] = value & 0x0fffbf7f;
2488
        /* TODO update clocks */
2489
        break;
2490

    
2491
    case 0x244:        /* CM_CLKSEL2_CORE */
2492
        s->clksel[2] = value & 0x00fffffc;
2493
        /* TODO update clocks */
2494
        break;
2495

    
2496
    case 0x248:        /* CM_CLKSTCTRL_CORE */
2497
        s->clkctrl[1] = value & 0x7;
2498
        break;
2499

    
2500
    case 0x2a0:        /* PM_WKEN1_CORE */
2501
        s->wken[0] = value & 0x04667ff8;
2502
        break;
2503
    case 0x2a4:        /* PM_WKEN2_CORE */
2504
        s->wken[1] = value & 0x00000005;
2505
        break;
2506

    
2507
    case 0x2b0:        /* PM_WKST1_CORE */
2508
        s->wkst[0] &= ~value;
2509
        break;
2510
    case 0x2b4:        /* PM_WKST2_CORE */
2511
        s->wkst[1] &= ~value;
2512
        break;
2513

    
2514
    case 0x2e0:        /* PM_PWSTCTRL_CORE */
2515
        s->power[1] = (value & 0x00fc3f) | (1 << 2);
2516
        break;
2517

    
2518
    case 0x300:        /* CM_FCLKEN_GFX */
2519
        s->clken[5] = value & 6;
2520
        /* TODO update clocks */
2521
        break;
2522
    case 0x310:        /* CM_ICLKEN_GFX */
2523
        s->clken[6] = value & 1;
2524
        /* TODO update clocks */
2525
        break;
2526
    case 0x340:        /* CM_CLKSEL_GFX */
2527
        s->clksel[3] = value & 7;
2528
        /* TODO update clocks */
2529
        break;
2530
    case 0x348:        /* CM_CLKSTCTRL_GFX */
2531
        s->clkctrl[2] = value & 1;
2532
        break;
2533
    case 0x350:        /* RM_RSTCTRL_GFX */
2534
        s->rstctrl[0] = value & 1;
2535
        /* TODO: reset */
2536
        break;
2537
    case 0x358:        /* RM_RSTST_GFX */
2538
        s->rst[1] &= ~value;
2539
        break;
2540
    case 0x3c8:        /* PM_WKDEP_GFX */
2541
        s->wkup[1] = value & 0x13;
2542
        break;
2543
    case 0x3e0:        /* PM_PWSTCTRL_GFX */
2544
        s->power[2] = (value & 0x00c0f) | (3 << 2);
2545
        break;
2546

    
2547
    case 0x400:        /* CM_FCLKEN_WKUP */
2548
        s->clken[7] = value & 0xd;
2549
        /* TODO update clocks */
2550
        break;
2551
    case 0x410:        /* CM_ICLKEN_WKUP */
2552
        s->clken[8] = value & 0x3f;
2553
        /* TODO update clocks */
2554
        break;
2555
    case 0x430:        /* CM_AUTOIDLE_WKUP */
2556
        s->clkidle[4] = value & 0x0000003f;
2557
        /* TODO update clocks */
2558
        break;
2559
    case 0x440:        /* CM_CLKSEL_WKUP */
2560
        s->clksel[4] = value & 3;
2561
        /* TODO update clocks */
2562
        break;
2563
    case 0x450:        /* RM_RSTCTRL_WKUP */
2564
        /* TODO: reset */
2565
        if (value & 2)
2566
            qemu_system_reset_request();
2567
        break;
2568
    case 0x454:        /* RM_RSTTIME_WKUP */
2569
        s->rsttime_wkup = value & 0x1fff;
2570
        break;
2571
    case 0x458:        /* RM_RSTST_WKUP */
2572
        s->rst[2] &= ~value;
2573
        break;
2574
    case 0x4a0:        /* PM_WKEN_WKUP */
2575
        s->wken[2] = value & 0x00000005;
2576
        break;
2577
    case 0x4b0:        /* PM_WKST_WKUP */
2578
        s->wkst[2] &= ~value;
2579
        break;
2580

    
2581
    case 0x500:        /* CM_CLKEN_PLL */
2582
        s->clken[9] = value & 0xcf;
2583
        /* TODO update clocks */
2584
        break;
2585
    case 0x530:        /* CM_AUTOIDLE_PLL */
2586
        s->clkidle[5] = value & 0x000000cf;
2587
        /* TODO update clocks */
2588
        break;
2589
    case 0x540:        /* CM_CLKSEL1_PLL */
2590
        s->clksel[5] = value & 0x03bfff28;
2591
        /* TODO update clocks */
2592
        break;
2593
    case 0x544:        /* CM_CLKSEL2_PLL */
2594
        s->clksel[6] = value & 3;
2595
        /* TODO update clocks */
2596
        break;
2597

    
2598
    case 0x800:        /* CM_FCLKEN_DSP */
2599
        s->clken[10] = value & 0x501;
2600
        /* TODO update clocks */
2601
        break;
2602
    case 0x810:        /* CM_ICLKEN_DSP */
2603
        s->clken[11] = value & 0x2;
2604
        /* TODO update clocks */
2605
        break;
2606
    case 0x830:        /* CM_AUTOIDLE_DSP */
2607
        s->clkidle[6] = value & 0x2;
2608
        /* TODO update clocks */
2609
        break;
2610
    case 0x840:        /* CM_CLKSEL_DSP */
2611
        s->clksel[7] = value & 0x3fff;
2612
        /* TODO update clocks */
2613
        break;
2614
    case 0x848:        /* CM_CLKSTCTRL_DSP */
2615
        s->clkctrl[3] = value & 0x101;
2616
        break;
2617
    case 0x850:        /* RM_RSTCTRL_DSP */
2618
        /* TODO: reset */
2619
        break;
2620
    case 0x858:        /* RM_RSTST_DSP */
2621
        s->rst[3] &= ~value;
2622
        break;
2623
    case 0x8c8:        /* PM_WKDEP_DSP */
2624
        s->wkup[2] = value & 0x13;
2625
        break;
2626
    case 0x8e0:        /* PM_PWSTCTRL_DSP */
2627
        s->power[3] = (value & 0x03017) | (3 << 2);
2628
        break;
2629

    
2630
    case 0x8f0:        /* PRCM_IRQSTATUS_DSP */
2631
        s->irqst[1] &= ~value;
2632
        omap_prcm_int_update(s, 1);
2633
        break;
2634
    case 0x8f4:        /* PRCM_IRQENABLE_DSP */
2635
        s->irqen[1] = value & 0x7;
2636
        omap_prcm_int_update(s, 1);
2637
        break;
2638

    
2639
    case 0x8f8:        /* PRCM_IRQSTATUS_IVA */
2640
        s->irqst[2] &= ~value;
2641
        omap_prcm_int_update(s, 2);
2642
        break;
2643
    case 0x8fc:        /* PRCM_IRQENABLE_IVA */
2644
        s->irqen[2] = value & 0x7;
2645
        omap_prcm_int_update(s, 2);
2646
        break;
2647

    
2648
    default:
2649
        OMAP_BAD_REG(addr);
2650
        return;
2651
    }
2652
}
2653

    
2654
static CPUReadMemoryFunc *omap_prcm_readfn[] = {
2655
    omap_badwidth_read32,
2656
    omap_badwidth_read32,
2657
    omap_prcm_read,
2658
};
2659

    
2660
static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
2661
    omap_badwidth_write32,
2662
    omap_badwidth_write32,
2663
    omap_prcm_write,
2664
};
2665

    
2666
static void omap_prcm_reset(struct omap_prcm_s *s)
2667
{
2668
    s->sysconfig = 0;
2669
    s->irqst[0] = 0;
2670
    s->irqst[1] = 0;
2671
    s->irqst[2] = 0;
2672
    s->irqen[0] = 0;
2673
    s->irqen[1] = 0;
2674
    s->irqen[2] = 0;
2675
    s->voltctrl = 0x1040;
2676
    s->ev = 0x14;
2677
    s->evtime[0] = 0;
2678
    s->evtime[1] = 0;
2679
    s->clkctrl[0] = 0;
2680
    s->clkctrl[1] = 0;
2681
    s->clkctrl[2] = 0;
2682
    s->clkctrl[3] = 0;
2683
    s->clken[1] = 7;
2684
    s->clken[3] = 7;
2685
    s->clken[4] = 0;
2686
    s->clken[5] = 0;
2687
    s->clken[6] = 0;
2688
    s->clken[7] = 0xc;
2689
    s->clken[8] = 0x3e;
2690
    s->clken[9] = 0x0d;
2691
    s->clken[10] = 0;
2692
    s->clken[11] = 0;
2693
    s->clkidle[0] = 0;
2694
    s->clkidle[2] = 7;
2695
    s->clkidle[3] = 0;
2696
    s->clkidle[4] = 0;
2697
    s->clkidle[5] = 0x0c;
2698
    s->clkidle[6] = 0;
2699
    s->clksel[0] = 0x01;
2700
    s->clksel[1] = 0x02100121;
2701
    s->clksel[2] = 0x00000000;
2702
    s->clksel[3] = 0x01;
2703
    s->clksel[4] = 0;
2704
    s->clksel[7] = 0x0121;
2705
    s->wkup[0] = 0x15;
2706
    s->wkup[1] = 0x13;
2707
    s->wkup[2] = 0x13;
2708
    s->wken[0] = 0x04667ff8;
2709
    s->wken[1] = 0x00000005;
2710
    s->wken[2] = 5;
2711
    s->wkst[0] = 0;
2712
    s->wkst[1] = 0;
2713
    s->wkst[2] = 0;
2714
    s->power[0] = 0x00c;
2715
    s->power[1] = 4;
2716
    s->power[2] = 0x0000c;
2717
    s->power[3] = 0x14;
2718
    s->rstctrl[0] = 1;
2719
    s->rst[3] = 1;
2720
}
2721

    
2722
static void omap_prcm_coldreset(struct omap_prcm_s *s)
2723
{
2724
    s->setuptime[0] = 0;
2725
    s->setuptime[1] = 0;
2726
    memset(&s->scratch, 0, sizeof(s->scratch));
2727
    s->rst[0] = 0x01;
2728
    s->rst[1] = 0x00;
2729
    s->rst[2] = 0x01;
2730
    s->clken[0] = 0;
2731
    s->clken[2] = 0;
2732
    s->clkidle[1] = 0;
2733
    s->clksel[5] = 0;
2734
    s->clksel[6] = 2;
2735
    s->clksrc[0] = 0x43;
2736
    s->clkout[0] = 0x0303;
2737
    s->clkemul[0] = 0;
2738
    s->clkpol[0] = 0x100;
2739
    s->rsttime_wkup = 0x1002;
2740

    
2741
    omap_prcm_reset(s);
2742
}
2743

    
2744
struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
2745
                qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
2746
                struct omap_mpu_state_s *mpu)
2747
{
2748
    int iomemtype;
2749
    struct omap_prcm_s *s = (struct omap_prcm_s *)
2750
            qemu_mallocz(sizeof(struct omap_prcm_s));
2751

    
2752
    s->irq[0] = mpu_int;
2753
    s->irq[1] = dsp_int;
2754
    s->irq[2] = iva_int;
2755
    s->mpu = mpu;
2756
    omap_prcm_coldreset(s);
2757

    
2758
    iomemtype = cpu_register_io_memory(0, omap_prcm_readfn,
2759
                    omap_prcm_writefn, s);
2760
    s->base = omap_l4_attach(ta, 0, iomemtype);
2761
    omap_l4_attach(ta, 1, iomemtype);
2762

    
2763
    return s;
2764
}
2765

    
2766
/* System and Pinout control */
2767
struct omap_sysctl_s {
2768
    target_phys_addr_t base;
2769
    struct omap_mpu_state_s *mpu;
2770

    
2771
    uint32_t sysconfig;
2772
    uint32_t devconfig;
2773
    uint32_t psaconfig;
2774
    uint32_t padconf[0x45];
2775
    uint8_t obs;
2776
    uint32_t msuspendmux[5];
2777
};
2778

    
2779
static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
2780
{
2781
    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2782
    int offset = addr - s->base;
2783

    
2784
    switch (offset) {
2785
    case 0x000:        /* CONTROL_REVISION */
2786
        return 0x20;
2787

    
2788
    case 0x010:        /* CONTROL_SYSCONFIG */
2789
        return s->sysconfig;
2790

    
2791
    case 0x030 ... 0x140:        /* CONTROL_PADCONF - only used in the POP */
2792
        return s->padconf[(offset - 0x30) >> 2];
2793

    
2794
    case 0x270:        /* CONTROL_DEBOBS */
2795
        return s->obs;
2796

    
2797
    case 0x274:        /* CONTROL_DEVCONF */
2798
        return s->devconfig;
2799

    
2800
    case 0x28c:        /* CONTROL_EMU_SUPPORT */
2801
        return 0;
2802

    
2803
    case 0x290:        /* CONTROL_MSUSPENDMUX_0 */
2804
        return s->msuspendmux[0];
2805
    case 0x294:        /* CONTROL_MSUSPENDMUX_1 */
2806
        return s->msuspendmux[1];
2807
    case 0x298:        /* CONTROL_MSUSPENDMUX_2 */
2808
        return s->msuspendmux[2];
2809
    case 0x29c:        /* CONTROL_MSUSPENDMUX_3 */
2810
        return s->msuspendmux[3];
2811
    case 0x2a0:        /* CONTROL_MSUSPENDMUX_4 */
2812
        return s->msuspendmux[4];
2813
    case 0x2a4:        /* CONTROL_MSUSPENDMUX_5 */
2814
        return 0;
2815

    
2816
    case 0x2b8:        /* CONTROL_PSA_CTRL */
2817
        return s->psaconfig;
2818
    case 0x2bc:        /* CONTROL_PSA_CMD */
2819
    case 0x2c0:        /* CONTROL_PSA_VALUE */
2820
        return 0;
2821

    
2822
    case 0x2b0:        /* CONTROL_SEC_CTRL */
2823
        return 0x800000f1;
2824
    case 0x2d0:        /* CONTROL_SEC_EMU */
2825
        return 0x80000015;
2826
    case 0x2d4:        /* CONTROL_SEC_TAP */
2827
        return 0x8000007f;
2828
    case 0x2b4:        /* CONTROL_SEC_TEST */
2829
    case 0x2f0:        /* CONTROL_SEC_STATUS */
2830
    case 0x2f4:        /* CONTROL_SEC_ERR_STATUS */
2831
        /* Secure mode is not present on general-pusrpose device.  Outside
2832
         * secure mode these values cannot be read or written.  */
2833
        return 0;
2834

    
2835
    case 0x2d8:        /* CONTROL_OCM_RAM_PERM */
2836
        return 0xff;
2837
    case 0x2dc:        /* CONTROL_OCM_PUB_RAM_ADD */
2838
    case 0x2e0:        /* CONTROL_EXT_SEC_RAM_START_ADD */
2839
    case 0x2e4:        /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2840
        /* No secure mode so no Extended Secure RAM present.  */
2841
        return 0;
2842

    
2843
    case 0x2f8:        /* CONTROL_STATUS */
2844
        /* Device Type => General-purpose */
2845
        return 0x0300;
2846
    case 0x2fc:        /* CONTROL_GENERAL_PURPOSE_STATUS */
2847

    
2848
    case 0x300:        /* CONTROL_RPUB_KEY_H_0 */
2849
    case 0x304:        /* CONTROL_RPUB_KEY_H_1 */
2850
    case 0x308:        /* CONTROL_RPUB_KEY_H_2 */
2851
    case 0x30c:        /* CONTROL_RPUB_KEY_H_3 */
2852
        return 0xdecafbad;
2853

    
2854
    case 0x310:        /* CONTROL_RAND_KEY_0 */
2855
    case 0x314:        /* CONTROL_RAND_KEY_1 */
2856
    case 0x318:        /* CONTROL_RAND_KEY_2 */
2857
    case 0x31c:        /* CONTROL_RAND_KEY_3 */
2858
    case 0x320:        /* CONTROL_CUST_KEY_0 */
2859
    case 0x324:        /* CONTROL_CUST_KEY_1 */
2860
    case 0x330:        /* CONTROL_TEST_KEY_0 */
2861
    case 0x334:        /* CONTROL_TEST_KEY_1 */
2862
    case 0x338:        /* CONTROL_TEST_KEY_2 */
2863
    case 0x33c:        /* CONTROL_TEST_KEY_3 */
2864
    case 0x340:        /* CONTROL_TEST_KEY_4 */
2865
    case 0x344:        /* CONTROL_TEST_KEY_5 */
2866
    case 0x348:        /* CONTROL_TEST_KEY_6 */
2867
    case 0x34c:        /* CONTROL_TEST_KEY_7 */
2868
    case 0x350:        /* CONTROL_TEST_KEY_8 */
2869
    case 0x354:        /* CONTROL_TEST_KEY_9 */
2870
        /* Can only be accessed in secure mode and when C_FieldAccEnable
2871
         * bit is set in CONTROL_SEC_CTRL.
2872
         * TODO: otherwise an interconnect access error is generated.  */
2873
        return 0;
2874
    }
2875

    
2876
    OMAP_BAD_REG(addr);
2877
    return 0;
2878
}
2879

    
2880
static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
2881
                uint32_t value)
2882
{
2883
    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2884
    int offset = addr - s->base;
2885

    
2886
    switch (offset) {
2887
    case 0x000:        /* CONTROL_REVISION */
2888
    case 0x2a4:        /* CONTROL_MSUSPENDMUX_5 */
2889
    case 0x2c0:        /* CONTROL_PSA_VALUE */
2890
    case 0x2f8:        /* CONTROL_STATUS */
2891
    case 0x2fc:        /* CONTROL_GENERAL_PURPOSE_STATUS */
2892
    case 0x300:        /* CONTROL_RPUB_KEY_H_0 */
2893
    case 0x304:        /* CONTROL_RPUB_KEY_H_1 */
2894
    case 0x308:        /* CONTROL_RPUB_KEY_H_2 */
2895
    case 0x30c:        /* CONTROL_RPUB_KEY_H_3 */
2896
    case 0x310:        /* CONTROL_RAND_KEY_0 */
2897
    case 0x314:        /* CONTROL_RAND_KEY_1 */
2898
    case 0x318:        /* CONTROL_RAND_KEY_2 */
2899
    case 0x31c:        /* CONTROL_RAND_KEY_3 */
2900
    case 0x320:        /* CONTROL_CUST_KEY_0 */
2901
    case 0x324:        /* CONTROL_CUST_KEY_1 */
2902
    case 0x330:        /* CONTROL_TEST_KEY_0 */
2903
    case 0x334:        /* CONTROL_TEST_KEY_1 */
2904
    case 0x338:        /* CONTROL_TEST_KEY_2 */
2905
    case 0x33c:        /* CONTROL_TEST_KEY_3 */
2906
    case 0x340:        /* CONTROL_TEST_KEY_4 */
2907
    case 0x344:        /* CONTROL_TEST_KEY_5 */
2908
    case 0x348:        /* CONTROL_TEST_KEY_6 */
2909
    case 0x34c:        /* CONTROL_TEST_KEY_7 */
2910
    case 0x350:        /* CONTROL_TEST_KEY_8 */
2911
    case 0x354:        /* CONTROL_TEST_KEY_9 */
2912
        OMAP_RO_REG(addr);
2913
        return;
2914

    
2915
    case 0x010:        /* CONTROL_SYSCONFIG */
2916
        s->sysconfig = value & 0x1e;
2917
        break;
2918

    
2919
    case 0x030 ... 0x140:        /* CONTROL_PADCONF - only used in the POP */
2920
        /* XXX: should check constant bits */
2921
        s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f;
2922
        break;
2923

    
2924
    case 0x270:        /* CONTROL_DEBOBS */
2925
        s->obs = value & 0xff;
2926
        break;
2927

    
2928
    case 0x274:        /* CONTROL_DEVCONF */
2929
        s->devconfig = value & 0xffffc7ff;
2930
        break;
2931

    
2932
    case 0x28c:        /* CONTROL_EMU_SUPPORT */
2933
        break;
2934

    
2935
    case 0x290:        /* CONTROL_MSUSPENDMUX_0 */
2936
        s->msuspendmux[0] = value & 0x3fffffff;
2937
        break;
2938
    case 0x294:        /* CONTROL_MSUSPENDMUX_1 */
2939
        s->msuspendmux[1] = value & 0x3fffffff;
2940
        break;
2941
    case 0x298:        /* CONTROL_MSUSPENDMUX_2 */
2942
        s->msuspendmux[2] = value & 0x3fffffff;
2943
        break;
2944
    case 0x29c:        /* CONTROL_MSUSPENDMUX_3 */
2945
        s->msuspendmux[3] = value & 0x3fffffff;
2946
        break;
2947
    case 0x2a0:        /* CONTROL_MSUSPENDMUX_4 */
2948
        s->msuspendmux[4] = value & 0x3fffffff;
2949
        break;
2950

    
2951
    case 0x2b8:        /* CONTROL_PSA_CTRL */
2952
        s->psaconfig = value & 0x1c;
2953
        s->psaconfig |= (value & 0x20) ? 2 : 1;
2954
        break;
2955
    case 0x2bc:        /* CONTROL_PSA_CMD */
2956
        break;
2957

    
2958
    case 0x2b0:        /* CONTROL_SEC_CTRL */
2959
    case 0x2b4:        /* CONTROL_SEC_TEST */
2960
    case 0x2d0:        /* CONTROL_SEC_EMU */
2961
    case 0x2d4:        /* CONTROL_SEC_TAP */
2962
    case 0x2d8:        /* CONTROL_OCM_RAM_PERM */
2963
    case 0x2dc:        /* CONTROL_OCM_PUB_RAM_ADD */
2964
    case 0x2e0:        /* CONTROL_EXT_SEC_RAM_START_ADD */
2965
    case 0x2e4:        /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2966
    case 0x2f0:        /* CONTROL_SEC_STATUS */
2967
    case 0x2f4:        /* CONTROL_SEC_ERR_STATUS */
2968
        break;
2969

    
2970
    default:
2971
        OMAP_BAD_REG(addr);
2972
        return;
2973
    }
2974
}
2975

    
2976
static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
2977
    omap_badwidth_read32,        /* TODO */
2978
    omap_badwidth_read32,        /* TODO */
2979
    omap_sysctl_read,
2980
};
2981

    
2982
static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
2983
    omap_badwidth_write32,        /* TODO */
2984
    omap_badwidth_write32,        /* TODO */
2985
    omap_sysctl_write,
2986
};
2987

    
2988
static void omap_sysctl_reset(struct omap_sysctl_s *s)
2989
{
2990
    /* (power-on reset) */
2991
    s->sysconfig = 0;
2992
    s->obs = 0;
2993
    s->devconfig = 0x0c000000;
2994
    s->msuspendmux[0] = 0x00000000;
2995
    s->msuspendmux[1] = 0x00000000;
2996
    s->msuspendmux[2] = 0x00000000;
2997
    s->msuspendmux[3] = 0x00000000;
2998
    s->msuspendmux[4] = 0x00000000;
2999
    s->psaconfig = 1;
3000

    
3001
    s->padconf[0x00] = 0x000f0f0f;
3002
    s->padconf[0x01] = 0x00000000;
3003
    s->padconf[0x02] = 0x00000000;
3004
    s->padconf[0x03] = 0x00000000;
3005
    s->padconf[0x04] = 0x00000000;
3006
    s->padconf[0x05] = 0x00000000;
3007
    s->padconf[0x06] = 0x00000000;
3008
    s->padconf[0x07] = 0x00000000;
3009
    s->padconf[0x08] = 0x08080800;
3010
    s->padconf[0x09] = 0x08080808;
3011
    s->padconf[0x0a] = 0x08080808;
3012
    s->padconf[0x0b] = 0x08080808;
3013
    s->padconf[0x0c] = 0x08080808;
3014
    s->padconf[0x0d] = 0x08080800;
3015
    s->padconf[0x0e] = 0x08080808;
3016
    s->padconf[0x0f] = 0x08080808;
3017
    s->padconf[0x10] = 0x18181808;        /* | 0x07070700 if SBoot3 */
3018
    s->padconf[0x11] = 0x18181818;        /* | 0x07070707 if SBoot3 */
3019
    s->padconf[0x12] = 0x18181818;        /* | 0x07070707 if SBoot3 */
3020
    s->padconf[0x13] = 0x18181818;        /* | 0x07070707 if SBoot3 */
3021
    s->padconf[0x14] = 0x18181818;        /* | 0x00070707 if SBoot3 */
3022
    s->padconf[0x15] = 0x18181818;
3023
    s->padconf[0x16] = 0x18181818;        /* | 0x07000000 if SBoot3 */
3024
    s->padconf[0x17] = 0x1f001f00;
3025
    s->padconf[0x18] = 0x1f1f1f1f;
3026
    s->padconf[0x19] = 0x00000000;
3027
    s->padconf[0x1a] = 0x1f180000;
3028
    s->padconf[0x1b] = 0x00001f1f;
3029
    s->padconf[0x1c] = 0x1f001f00;
3030
    s->padconf[0x1d] = 0x00000000;
3031
    s->padconf[0x1e] = 0x00000000;
3032
    s->padconf[0x1f] = 0x08000000;
3033
    s->padconf[0x20] = 0x08080808;
3034
    s->padconf[0x21] = 0x08080808;
3035
    s->padconf[0x22] = 0x0f080808;
3036
    s->padconf[0x23] = 0x0f0f0f0f;
3037
    s->padconf[0x24] = 0x000f0f0f;
3038
    s->padconf[0x25] = 0x1f1f1f0f;
3039
    s->padconf[0x26] = 0x080f0f1f;
3040
    s->padconf[0x27] = 0x070f1808;
3041
    s->padconf[0x28] = 0x0f070707;
3042
    s->padconf[0x29] = 0x000f0f1f;
3043
    s->padconf[0x2a] = 0x0f0f0f1f;
3044
    s->padconf[0x2b] = 0x08000000;
3045
    s->padconf[0x2c] = 0x0000001f;
3046
    s->padconf[0x2d] = 0x0f0f1f00;
3047
    s->padconf[0x2e] = 0x1f1f0f0f;
3048
    s->padconf[0x2f] = 0x0f1f1f1f;
3049
    s->padconf[0x30] = 0x0f0f0f0f;
3050
    s->padconf[0x31] = 0x0f1f0f1f;
3051
    s->padconf[0x32] = 0x0f0f0f0f;
3052
    s->padconf[0x33] = 0x0f1f0f1f;
3053
    s->padconf[0x34] = 0x1f1f0f0f;
3054
    s->padconf[0x35] = 0x0f0f1f1f;
3055
    s->padconf[0x36] = 0x0f0f1f0f;
3056
    s->padconf[0x37] = 0x0f0f0f0f;
3057
    s->padconf[0x38] = 0x1f18180f;
3058
    s->padconf[0x39] = 0x1f1f1f1f;
3059
    s->padconf[0x3a] = 0x00001f1f;
3060
    s->padconf[0x3b] = 0x00000000;
3061
    s->padconf[0x3c] = 0x00000000;
3062
    s->padconf[0x3d] = 0x0f0f0f0f;
3063
    s->padconf[0x3e] = 0x18000f0f;
3064
    s->padconf[0x3f] = 0x00070000;
3065
    s->padconf[0x40] = 0x00000707;
3066
    s->padconf[0x41] = 0x0f1f0700;
3067
    s->padconf[0x42] = 0x1f1f070f;
3068
    s->padconf[0x43] = 0x0008081f;
3069
    s->padconf[0x44] = 0x00000800;
3070
}
3071

    
3072
struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3073
                omap_clk iclk, struct omap_mpu_state_s *mpu)
3074
{
3075
    int iomemtype;
3076
    struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3077
            qemu_mallocz(sizeof(struct omap_sysctl_s));
3078

    
3079
    s->mpu = mpu;
3080
    omap_sysctl_reset(s);
3081

    
3082
    iomemtype = cpu_register_io_memory(0, omap_sysctl_readfn,
3083
                    omap_sysctl_writefn, s);
3084
    s->base = omap_l4_attach(ta, 0, iomemtype);
3085
    omap_l4_attach(ta, 0, iomemtype);
3086

    
3087
    return s;
3088
}
3089

    
3090
/* SDRAM Controller Subsystem */
3091
struct omap_sdrc_s {
3092
    target_phys_addr_t base;
3093

    
3094
    uint8_t config;
3095
};
3096

    
3097
static void omap_sdrc_reset(struct omap_sdrc_s *s)
3098
{
3099
    s->config = 0x10;
3100
}
3101

    
3102
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3103
{
3104
    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3105
    int offset = addr - s->base;
3106

    
3107
    switch (offset) {
3108
    case 0x00:        /* SDRC_REVISION */
3109
        return 0x20;
3110

    
3111
    case 0x10:        /* SDRC_SYSCONFIG */
3112
        return s->config;
3113

    
3114
    case 0x14:        /* SDRC_SYSSTATUS */
3115
        return 1;                                                /* RESETDONE */
3116

    
3117
    case 0x40:        /* SDRC_CS_CFG */
3118
    case 0x44:        /* SDRC_SHARING */
3119
    case 0x48:        /* SDRC_ERR_ADDR */
3120
    case 0x4c:        /* SDRC_ERR_TYPE */
3121
    case 0x60:        /* SDRC_DLLA_SCTRL */
3122
    case 0x64:        /* SDRC_DLLA_STATUS */
3123
    case 0x68:        /* SDRC_DLLB_CTRL */
3124
    case 0x6c:        /* SDRC_DLLB_STATUS */
3125
    case 0x70:        /* SDRC_POWER */
3126
    case 0x80:        /* SDRC_MCFG_0 */
3127
    case 0x84:        /* SDRC_MR_0 */
3128
    case 0x88:        /* SDRC_EMR1_0 */
3129
    case 0x8c:        /* SDRC_EMR2_0 */
3130
    case 0x90:        /* SDRC_EMR3_0 */
3131
    case 0x94:        /* SDRC_DCDL1_CTRL */
3132
    case 0x98:        /* SDRC_DCDL2_CTRL */
3133
    case 0x9c:        /* SDRC_ACTIM_CTRLA_0 */
3134
    case 0xa0:        /* SDRC_ACTIM_CTRLB_0 */
3135
    case 0xa4:        /* SDRC_RFR_CTRL_0 */
3136
    case 0xa8:        /* SDRC_MANUAL_0 */
3137
    case 0xb0:        /* SDRC_MCFG_1 */
3138
    case 0xb4:        /* SDRC_MR_1 */
3139
    case 0xb8:        /* SDRC_EMR1_1 */
3140
    case 0xbc:        /* SDRC_EMR2_1 */
3141
    case 0xc0:        /* SDRC_EMR3_1 */
3142
    case 0xc4:        /* SDRC_ACTIM_CTRLA_1 */
3143
    case 0xc8:        /* SDRC_ACTIM_CTRLB_1 */
3144
    case 0xd4:        /* SDRC_RFR_CTRL_1 */
3145
    case 0xd8:        /* SDRC_MANUAL_1 */
3146
        return 0x00;
3147
    }
3148

    
3149
    OMAP_BAD_REG(addr);
3150
    return 0;
3151
}
3152

    
3153
static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3154
                uint32_t value)
3155
{
3156
    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3157
    int offset = addr - s->base;
3158

    
3159
    switch (offset) {
3160
    case 0x00:        /* SDRC_REVISION */
3161
    case 0x14:        /* SDRC_SYSSTATUS */
3162
    case 0x48:        /* SDRC_ERR_ADDR */
3163
    case 0x64:        /* SDRC_DLLA_STATUS */
3164
    case 0x6c:        /* SDRC_DLLB_STATUS */
3165
        OMAP_RO_REG(addr);
3166
        return;
3167

    
3168
    case 0x10:        /* SDRC_SYSCONFIG */
3169
        if ((value >> 3) != 0x2)
3170
            fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3171
                            __FUNCTION__, value >> 3);
3172
        if (value & 2)
3173
            omap_sdrc_reset(s);
3174
        s->config = value & 0x18;
3175
        break;
3176

    
3177
    case 0x40:        /* SDRC_CS_CFG */
3178
    case 0x44:        /* SDRC_SHARING */
3179
    case 0x4c:        /* SDRC_ERR_TYPE */
3180
    case 0x60:        /* SDRC_DLLA_SCTRL */
3181
    case 0x68:        /* SDRC_DLLB_CTRL */
3182
    case 0x70:        /* SDRC_POWER */
3183
    case 0x80:        /* SDRC_MCFG_0 */
3184
    case 0x84:        /* SDRC_MR_0 */
3185
    case 0x88:        /* SDRC_EMR1_0 */
3186
    case 0x8c:        /* SDRC_EMR2_0 */
3187
    case 0x90:        /* SDRC_EMR3_0 */
3188
    case 0x94:        /* SDRC_DCDL1_CTRL */
3189
    case 0x98:        /* SDRC_DCDL2_CTRL */
3190
    case 0x9c:        /* SDRC_ACTIM_CTRLA_0 */
3191
    case 0xa0:        /* SDRC_ACTIM_CTRLB_0 */
3192
    case 0xa4:        /* SDRC_RFR_CTRL_0 */
3193
    case 0xa8:        /* SDRC_MANUAL_0 */
3194
    case 0xb0:        /* SDRC_MCFG_1 */
3195
    case 0xb4:        /* SDRC_MR_1 */
3196
    case 0xb8:        /* SDRC_EMR1_1 */
3197
    case 0xbc:        /* SDRC_EMR2_1 */
3198
    case 0xc0:        /* SDRC_EMR3_1 */
3199
    case 0xc4:        /* SDRC_ACTIM_CTRLA_1 */
3200
    case 0xc8:        /* SDRC_ACTIM_CTRLB_1 */
3201
    case 0xd4:        /* SDRC_RFR_CTRL_1 */
3202
    case 0xd8:        /* SDRC_MANUAL_1 */
3203
        break;
3204

    
3205
    default:
3206
        OMAP_BAD_REG(addr);
3207
        return;
3208
    }
3209
}
3210

    
3211
static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
3212
    omap_badwidth_read32,
3213
    omap_badwidth_read32,
3214
    omap_sdrc_read,
3215
};
3216

    
3217
static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
3218
    omap_badwidth_write32,
3219
    omap_badwidth_write32,
3220
    omap_sdrc_write,
3221
};
3222

    
3223
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
3224
{
3225
    int iomemtype;
3226
    struct omap_sdrc_s *s = (struct omap_sdrc_s *)
3227
            qemu_mallocz(sizeof(struct omap_sdrc_s));
3228

    
3229
    s->base = base;
3230
    omap_sdrc_reset(s);
3231

    
3232
    iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
3233
                    omap_sdrc_writefn, s);
3234
    cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3235

    
3236
    return s;
3237
}
3238

    
3239
/* General-Purpose Memory Controller */
3240
struct omap_gpmc_s {
3241
    target_phys_addr_t base;
3242
    qemu_irq irq;
3243

    
3244
    uint8_t sysconfig;
3245
    uint16_t irqst;
3246
    uint16_t irqen;
3247
    uint16_t timeout;
3248
    uint16_t config;
3249
    uint32_t prefconfig[2];
3250
    int prefcontrol;
3251
    int preffifo;
3252
    int prefcount;
3253
    struct omap_gpmc_cs_file_s {
3254
        uint32_t config[7];
3255
        target_phys_addr_t base;
3256
        size_t size;
3257
        int iomemtype;
3258
        void (*base_update)(void *opaque, target_phys_addr_t new);
3259
        void (*unmap)(void *opaque);
3260
        void *opaque;
3261
    } cs_file[8];
3262
    int ecc_cs;
3263
    int ecc_ptr;
3264
    uint32_t ecc_cfg;
3265
    struct ecc_state_s ecc[9];
3266
};
3267

    
3268
static void omap_gpmc_int_update(struct omap_gpmc_s *s)
3269
{
3270
    qemu_set_irq(s->irq, s->irqen & s->irqst);
3271
}
3272

    
3273
static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
3274
{
3275
    /* TODO: check for overlapping regions and report access errors */
3276
    if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
3277
                    (base < 0 || base >= 0x40) ||
3278
                    (base & 0x0f & ~mask)) {
3279
        fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
3280
                        __FUNCTION__);
3281
        return;
3282
    }
3283

    
3284
    if (!f->opaque)
3285
        return;
3286

    
3287
    f->base = base << 24;
3288
    f->size = (0x0fffffff & ~(mask << 24)) + 1;
3289
    /* TODO: rather than setting the size of the mapping (which should be
3290
     * constant), the mask should cause wrapping of the address space, so
3291
     * that the same memory becomes accessible at every <i>size</i> bytes
3292
     * starting from <i>base</i>.  */
3293
    if (f->iomemtype)
3294
        cpu_register_physical_memory(f->base, f->size, f->iomemtype);
3295

    
3296
    if (f->base_update)
3297
        f->base_update(f->opaque, f->base);
3298
}
3299

    
3300
static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
3301
{
3302
    if (f->size) {
3303
        if (f->unmap)
3304
            f->unmap(f->opaque);
3305
        if (f->iomemtype)
3306
            cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
3307
        f->base = 0;
3308
        f->size = 0;
3309
    }
3310
}
3311

    
3312
static void omap_gpmc_reset(struct omap_gpmc_s *s)
3313
{
3314
    int i;
3315

    
3316
    s->sysconfig = 0;
3317
    s->irqst = 0;
3318
    s->irqen = 0;
3319
    omap_gpmc_int_update(s);
3320
    s->timeout = 0;
3321
    s->config = 0xa00;
3322
    s->prefconfig[0] = 0x00004000;
3323
    s->prefconfig[1] = 0x00000000;
3324
    s->prefcontrol = 0;
3325
    s->preffifo = 0;
3326
    s->prefcount = 0;
3327
    for (i = 0; i < 8; i ++) {
3328
        if (s->cs_file[i].config[6] & (1 << 6))                        /* CSVALID */
3329
            omap_gpmc_cs_unmap(s->cs_file + i);
3330
        s->cs_file[i].config[0] = i ? 1 << 12 : 0;
3331
        s->cs_file[i].config[1] = 0x101001;
3332
        s->cs_file[i].config[2] = 0x020201;
3333
        s->cs_file[i].config[3] = 0x10031003;
3334
        s->cs_file[i].config[4] = 0x10f1111;
3335
        s->cs_file[i].config[5] = 0;
3336
        s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
3337
        if (s->cs_file[i].config[6] & (1 << 6))                        /* CSVALID */
3338
            omap_gpmc_cs_map(&s->cs_file[i],
3339
                            s->cs_file[i].config[6] & 0x1f,        /* MASKADDR */
3340
                        (s->cs_file[i].config[6] >> 8 & 0xf));        /* BASEADDR */
3341
    }
3342
    omap_gpmc_cs_map(s->cs_file, 0, 0xf);
3343
    s->ecc_cs = 0;
3344
    s->ecc_ptr = 0;
3345
    s->ecc_cfg = 0x3fcff000;
3346
    for (i = 0; i < 9; i ++)
3347
        ecc_reset(&s->ecc[i]);
3348
}
3349

    
3350
static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
3351
{
3352
    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3353
    int offset = addr - s->base;
3354
    int cs;
3355
    struct omap_gpmc_cs_file_s *f;
3356

    
3357
    switch (offset) {
3358
    case 0x000:        /* GPMC_REVISION */
3359
        return 0x20;
3360

    
3361
    case 0x010:        /* GPMC_SYSCONFIG */
3362
        return s->sysconfig;
3363

    
3364
    case 0x014:        /* GPMC_SYSSTATUS */
3365
        return 1;                                                /* RESETDONE */
3366

    
3367
    case 0x018:        /* GPMC_IRQSTATUS */
3368
        return s->irqst;
3369

    
3370
    case 0x01c:        /* GPMC_IRQENABLE */
3371
        return s->irqen;
3372

    
3373
    case 0x040:        /* GPMC_TIMEOUT_CONTROL */
3374
        return s->timeout;
3375

    
3376
    case 0x044:        /* GPMC_ERR_ADDRESS */
3377
    case 0x048:        /* GPMC_ERR_TYPE */
3378
        return 0;
3379

    
3380
    case 0x050:        /* GPMC_CONFIG */
3381
        return s->config;
3382

    
3383
    case 0x054:        /* GPMC_STATUS */
3384
        return 0x001;
3385

    
3386
    case 0x060 ... 0x1d4:
3387
        cs = (offset - 0x060) / 0x30;
3388
        offset -= cs * 0x30;
3389
        f = s->cs_file + cs;
3390
        switch (offset - cs * 0x30) {
3391
            case 0x60:        /* GPMC_CONFIG1 */
3392
                return f->config[0];
3393
            case 0x64:        /* GPMC_CONFIG2 */
3394
                return f->config[1];
3395
            case 0x68:        /* GPMC_CONFIG3 */
3396
                return f->config[2];
3397
            case 0x6c:        /* GPMC_CONFIG4 */
3398
                return f->config[3];
3399
            case 0x70:        /* GPMC_CONFIG5 */
3400
                return f->config[4];
3401
            case 0x74:        /* GPMC_CONFIG6 */
3402
                return f->config[5];
3403
            case 0x78:        /* GPMC_CONFIG7 */
3404
                return f->config[6];
3405
            case 0x84:        /* GPMC_NAND_DATA */
3406
                return 0;
3407
        }
3408
        break;
3409

    
3410
    case 0x1e0:        /* GPMC_PREFETCH_CONFIG1 */
3411
        return s->prefconfig[0];
3412
    case 0x1e4:        /* GPMC_PREFETCH_CONFIG2 */
3413
        return s->prefconfig[1];
3414
    case 0x1ec:        /* GPMC_PREFETCH_CONTROL */
3415
        return s->prefcontrol;
3416
    case 0x1f0:        /* GPMC_PREFETCH_STATUS */
3417
        return (s->preffifo << 24) |
3418
                ((s->preffifo >
3419
                  ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
3420
                s->prefcount;
3421

    
3422
    case 0x1f4:        /* GPMC_ECC_CONFIG */
3423
        return s->ecc_cs;
3424
    case 0x1f8:        /* GPMC_ECC_CONTROL */
3425
        return s->ecc_ptr;
3426
    case 0x1fc:        /* GPMC_ECC_SIZE_CONFIG */
3427
        return s->ecc_cfg;
3428
    case 0x200 ... 0x220:        /* GPMC_ECC_RESULT */
3429
        cs = (offset & 0x1f) >> 2;
3430
        /* TODO: check correctness */
3431
        return
3432
                ((s->ecc[cs].cp    &  0x07) <<  0) |
3433
                ((s->ecc[cs].cp    &  0x38) << 13) |
3434
                ((s->ecc[cs].lp[0] & 0x1ff) <<  3) |
3435
                ((s->ecc[cs].lp[1] & 0x1ff) << 19);
3436

    
3437
    case 0x230:        /* GPMC_TESTMODE_CTRL */
3438
        return 0;
3439
    case 0x234:        /* GPMC_PSA_LSB */
3440
    case 0x238:        /* GPMC_PSA_MSB */
3441
        return 0x00000000;
3442
    }
3443

    
3444
    OMAP_BAD_REG(addr);
3445
    return 0;
3446
}
3447

    
3448
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
3449
                uint32_t value)
3450
{
3451
    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3452
    int offset = addr - s->base;
3453
    int cs;
3454
    struct omap_gpmc_cs_file_s *f;
3455

    
3456
    switch (offset) {
3457
    case 0x000:        /* GPMC_REVISION */
3458
    case 0x014:        /* GPMC_SYSSTATUS */
3459
    case 0x054:        /* GPMC_STATUS */
3460
    case 0x1f0:        /* GPMC_PREFETCH_STATUS */
3461
    case 0x200 ... 0x220:        /* GPMC_ECC_RESULT */
3462
    case 0x234:        /* GPMC_PSA_LSB */
3463
    case 0x238:        /* GPMC_PSA_MSB */
3464
        OMAP_RO_REG(addr);
3465
        break;
3466

    
3467
    case 0x010:        /* GPMC_SYSCONFIG */
3468
        if ((value >> 3) == 0x3)
3469
            fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3470
                            __FUNCTION__, value >> 3);
3471
        if (value & 2)
3472
            omap_gpmc_reset(s);
3473
        s->sysconfig = value & 0x19;
3474
        break;
3475

    
3476
    case 0x018:        /* GPMC_IRQSTATUS */
3477
        s->irqen = ~value;
3478
        omap_gpmc_int_update(s);
3479
        break;
3480

    
3481
    case 0x01c:        /* GPMC_IRQENABLE */
3482
        s->irqen = value & 0xf03;
3483
        omap_gpmc_int_update(s);
3484
        break;
3485

    
3486
    case 0x040:        /* GPMC_TIMEOUT_CONTROL */
3487
        s->timeout = value & 0x1ff1;
3488
        break;
3489

    
3490
    case 0x044:        /* GPMC_ERR_ADDRESS */
3491
    case 0x048:        /* GPMC_ERR_TYPE */
3492
        break;
3493

    
3494
    case 0x050:        /* GPMC_CONFIG */
3495
        s->config = value & 0xf13;
3496
        break;
3497

    
3498
    case 0x060 ... 0x1d4:
3499
        cs = (offset - 0x060) / 0x30;
3500
        offset -= cs * 0x30;
3501
        f = s->cs_file + cs;
3502
        switch (offset) {
3503
            case 0x60:        /* GPMC_CONFIG1 */
3504
                f->config[0] = value & 0xffef3e13;
3505
                break;
3506
            case 0x64:        /* GPMC_CONFIG2 */
3507
                f->config[1] = value & 0x001f1f8f;
3508
                break;
3509
            case 0x68:        /* GPMC_CONFIG3 */
3510
                f->config[2] = value & 0x001f1f8f;
3511
                break;
3512
            case 0x6c:        /* GPMC_CONFIG4 */
3513
                f->config[3] = value & 0x1f8f1f8f;
3514
                break;
3515
            case 0x70:        /* GPMC_CONFIG5 */
3516
                f->config[4] = value & 0x0f1f1f1f;
3517
                break;
3518
            case 0x74:        /* GPMC_CONFIG6 */
3519
                f->config[5] = value & 0x00000fcf;
3520
                break;
3521
            case 0x78:        /* GPMC_CONFIG7 */
3522
                if ((f->config[6] ^ value) & 0xf7f) {
3523
                    if (f->config[6] & (1 << 6))                /* CSVALID */
3524
                        omap_gpmc_cs_unmap(f);
3525
                    if (value & (1 << 6))                        /* CSVALID */
3526
                        omap_gpmc_cs_map(f, value & 0x1f,        /* MASKADDR */
3527
                                        (value >> 8 & 0xf));        /* BASEADDR */
3528
                }
3529
                f->config[6] = value & 0x00000f7f;
3530
                break;
3531
            case 0x7c:        /* GPMC_NAND_COMMAND */
3532
            case 0x80:        /* GPMC_NAND_ADDRESS */
3533
            case 0x84:        /* GPMC_NAND_DATA */
3534
                break;
3535

    
3536
            default:
3537
                goto bad_reg;
3538
        }
3539
        break;
3540

    
3541
    case 0x1e0:        /* GPMC_PREFETCH_CONFIG1 */
3542
        s->prefconfig[0] = value & 0x7f8f7fbf;
3543
        /* TODO: update interrupts, fifos, dmas */
3544
        break;
3545

    
3546
    case 0x1e4:        /* GPMC_PREFETCH_CONFIG2 */
3547
        s->prefconfig[1] = value & 0x3fff;
3548
        break;
3549

    
3550
    case 0x1ec:        /* GPMC_PREFETCH_CONTROL */
3551
        s->prefcontrol = value & 1;
3552
        if (s->prefcontrol) {
3553
            if (s->prefconfig[0] & 1)
3554
                s->preffifo = 0x40;
3555
            else
3556
                s->preffifo = 0x00;
3557
        }
3558
        /* TODO: start */
3559
        break;
3560

    
3561
    case 0x1f4:        /* GPMC_ECC_CONFIG */
3562
        s->ecc_cs = 0x8f;
3563
        break;
3564
    case 0x1f8:        /* GPMC_ECC_CONTROL */
3565
        if (value & (1 << 8))
3566
            for (cs = 0; cs < 9; cs ++)
3567
                ecc_reset(&s->ecc[cs]);
3568
        s->ecc_ptr = value & 0xf;
3569
        if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
3570
            s->ecc_ptr = 0;
3571
            s->ecc_cs &= ~1;
3572
        }
3573
        break;
3574
    case 0x1fc:        /* GPMC_ECC_SIZE_CONFIG */
3575
        s->ecc_cfg = value & 0x3fcff1ff;
3576
        break;
3577
    case 0x230:        /* GPMC_TESTMODE_CTRL */
3578
        if (value & 7)
3579
            fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
3580
        break;
3581

    
3582
    default:
3583
    bad_reg:
3584
        OMAP_BAD_REG(addr);
3585
        return;
3586
    }
3587
}
3588

    
3589
static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
3590
    omap_badwidth_read32,        /* TODO */
3591
    omap_badwidth_read32,        /* TODO */
3592
    omap_gpmc_read,
3593
};
3594

    
3595
static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
3596
    omap_badwidth_write32,        /* TODO */
3597
    omap_badwidth_write32,        /* TODO */
3598
    omap_gpmc_write,
3599
};
3600

    
3601
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
3602
{
3603
    int iomemtype;
3604
    struct omap_gpmc_s *s = (struct omap_gpmc_s *)
3605
            qemu_mallocz(sizeof(struct omap_gpmc_s));
3606

    
3607
    s->base = base;
3608
    omap_gpmc_reset(s);
3609

    
3610
    iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
3611
                    omap_gpmc_writefn, s);
3612
    cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3613

    
3614
    return s;
3615
}
3616

    
3617
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
3618
                void (*base_upd)(void *opaque, target_phys_addr_t new),
3619
                void (*unmap)(void *opaque), void *opaque)
3620
{
3621
    struct omap_gpmc_cs_file_s *f;
3622

    
3623
    if (cs < 0 || cs >= 8) {
3624
        fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
3625
        exit(-1);
3626
    }
3627
    f = &s->cs_file[cs];
3628

    
3629
    f->iomemtype = iomemtype;
3630
    f->base_update = base_upd;
3631
    f->unmap = unmap;
3632
    f->opaque = opaque;
3633

    
3634
    if (f->config[6] & (1 << 6))                                /* CSVALID */
3635
        omap_gpmc_cs_map(f, f->config[6] & 0x1f,                /* MASKADDR */
3636
                        (f->config[6] >> 8 & 0xf));                /* BASEADDR */
3637
}
3638

    
3639
/* General chip reset */
3640
static void omap2_mpu_reset(void *opaque)
3641
{
3642
    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3643

    
3644
    omap_inth_reset(mpu->ih[0]);
3645
    omap_dma_reset(mpu->dma);
3646
    omap_prcm_reset(mpu->prcm);
3647
    omap_sysctl_reset(mpu->sysc);
3648
    omap_gp_timer_reset(mpu->gptimer[0]);
3649
    omap_gp_timer_reset(mpu->gptimer[1]);
3650
    omap_gp_timer_reset(mpu->gptimer[2]);
3651
    omap_gp_timer_reset(mpu->gptimer[3]);
3652
    omap_gp_timer_reset(mpu->gptimer[4]);
3653
    omap_gp_timer_reset(mpu->gptimer[5]);
3654
    omap_gp_timer_reset(mpu->gptimer[6]);
3655
    omap_gp_timer_reset(mpu->gptimer[7]);
3656
    omap_gp_timer_reset(mpu->gptimer[8]);
3657
    omap_gp_timer_reset(mpu->gptimer[9]);
3658
    omap_gp_timer_reset(mpu->gptimer[10]);
3659
    omap_gp_timer_reset(mpu->gptimer[11]);
3660
    omap_synctimer_reset(&mpu->synctimer);
3661
    omap_sdrc_reset(mpu->sdrc);
3662
    omap_gpmc_reset(mpu->gpmc);
3663
    omap_dss_reset(mpu->dss);
3664
    omap_uart_reset(mpu->uart[0]);
3665
    omap_uart_reset(mpu->uart[1]);
3666
    omap_uart_reset(mpu->uart[2]);
3667
    omap_mmc_reset(mpu->mmc);
3668
    omap_gpif_reset(mpu->gpif);
3669
    omap_mcspi_reset(mpu->mcspi[0]);
3670
    omap_mcspi_reset(mpu->mcspi[1]);
3671
    omap_i2c_reset(mpu->i2c[0]);
3672
    omap_i2c_reset(mpu->i2c[1]);
3673
    cpu_reset(mpu->env);
3674
}
3675

    
3676
static int omap2_validate_addr(struct omap_mpu_state_s *s,
3677
                target_phys_addr_t addr)
3678
{
3679
    return 1;
3680
}
3681

    
3682
static const struct dma_irq_map omap2_dma_irq_map[] = {
3683
    { 0, OMAP_INT_24XX_SDMA_IRQ0 },
3684
    { 0, OMAP_INT_24XX_SDMA_IRQ1 },
3685
    { 0, OMAP_INT_24XX_SDMA_IRQ2 },
3686
    { 0, OMAP_INT_24XX_SDMA_IRQ3 },
3687
};
3688

    
3689
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
3690
                DisplayState *ds, const char *core)
3691
{
3692
    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3693
            qemu_mallocz(sizeof(struct omap_mpu_state_s));
3694
    ram_addr_t sram_base, q2_base;
3695
    qemu_irq *cpu_irq;
3696
    qemu_irq dma_irqs[4];
3697
    omap_clk gpio_clks[4];
3698
    int sdindex;
3699
    int i;
3700

    
3701
    /* Core */
3702
    s->mpu_model = omap2420;
3703
    s->env = cpu_init(core ?: "arm1136-r2");
3704
    if (!s->env) {
3705
        fprintf(stderr, "Unable to find CPU definition\n");
3706
        exit(1);
3707
    }
3708
    s->sdram_size = sdram_size;
3709
    s->sram_size = OMAP242X_SRAM_SIZE;
3710

    
3711
    s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3712

    
3713
    /* Clocks */
3714
    omap_clk_init(s);
3715

    
3716
    /* Memory-mapped stuff */
3717
    cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
3718
                    (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
3719
    cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
3720
                    (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
3721

    
3722
    s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
3723

    
3724
    /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
3725
    cpu_irq = arm_pic_init_cpu(s->env);
3726
    s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
3727
                    cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
3728
                    omap_findclk(s, "mpu_intc_fclk"),
3729
                    omap_findclk(s, "mpu_intc_iclk"));
3730

    
3731
    s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
3732
                    s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
3733

    
3734
    s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
3735
                    omap_findclk(s, "omapctrl_iclk"), s);
3736

    
3737
    for (i = 0; i < 4; i ++)
3738
        dma_irqs[i] =
3739
                s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
3740
    s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
3741
                    omap_findclk(s, "sdma_iclk"),
3742
                    omap_findclk(s, "sdma_fclk"));
3743
    s->port->addr_valid = omap2_validate_addr;
3744

    
3745
    s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
3746
                    s->irq[0][OMAP_INT_24XX_UART1_IRQ],
3747
                    omap_findclk(s, "uart1_fclk"),
3748
                    omap_findclk(s, "uart1_iclk"),
3749
                    s->drq[OMAP24XX_DMA_UART1_TX],
3750
                    s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
3751
    s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
3752
                    s->irq[0][OMAP_INT_24XX_UART2_IRQ],
3753
                    omap_findclk(s, "uart2_fclk"),
3754
                    omap_findclk(s, "uart2_iclk"),
3755
                    s->drq[OMAP24XX_DMA_UART2_TX],
3756
                    s->drq[OMAP24XX_DMA_UART2_RX],
3757
                    serial_hds[0] ? serial_hds[1] : 0);
3758
    s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
3759
                    s->irq[0][OMAP_INT_24XX_UART3_IRQ],
3760
                    omap_findclk(s, "uart3_fclk"),
3761
                    omap_findclk(s, "uart3_iclk"),
3762
                    s->drq[OMAP24XX_DMA_UART3_TX],
3763
                    s->drq[OMAP24XX_DMA_UART3_RX],
3764
                    serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
3765

    
3766
    s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
3767
                    s->irq[0][OMAP_INT_24XX_GPTIMER1],
3768
                    omap_findclk(s, "wu_gpt1_clk"),
3769
                    omap_findclk(s, "wu_l4_iclk"));
3770
    s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
3771
                    s->irq[0][OMAP_INT_24XX_GPTIMER2],
3772
                    omap_findclk(s, "core_gpt2_clk"),
3773
                    omap_findclk(s, "core_l4_iclk"));
3774
    s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
3775
                    s->irq[0][OMAP_INT_24XX_GPTIMER3],
3776
                    omap_findclk(s, "core_gpt3_clk"),
3777
                    omap_findclk(s, "core_l4_iclk"));
3778
    s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
3779
                    s->irq[0][OMAP_INT_24XX_GPTIMER4],
3780
                    omap_findclk(s, "core_gpt4_clk"),
3781
                    omap_findclk(s, "core_l4_iclk"));
3782
    s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
3783
                    s->irq[0][OMAP_INT_24XX_GPTIMER5],
3784
                    omap_findclk(s, "core_gpt5_clk"),
3785
                    omap_findclk(s, "core_l4_iclk"));
3786
    s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
3787
                    s->irq[0][OMAP_INT_24XX_GPTIMER6],
3788
                    omap_findclk(s, "core_gpt6_clk"),
3789
                    omap_findclk(s, "core_l4_iclk"));
3790
    s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
3791
                    s->irq[0][OMAP_INT_24XX_GPTIMER7],
3792
                    omap_findclk(s, "core_gpt7_clk"),
3793
                    omap_findclk(s, "core_l4_iclk"));
3794
    s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
3795
                    s->irq[0][OMAP_INT_24XX_GPTIMER8],
3796
                    omap_findclk(s, "core_gpt8_clk"),
3797
                    omap_findclk(s, "core_l4_iclk"));
3798
    s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
3799
                    s->irq[0][OMAP_INT_24XX_GPTIMER9],
3800
                    omap_findclk(s, "core_gpt9_clk"),
3801
                    omap_findclk(s, "core_l4_iclk"));
3802
    s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
3803
                    s->irq[0][OMAP_INT_24XX_GPTIMER10],
3804
                    omap_findclk(s, "core_gpt10_clk"),
3805
                    omap_findclk(s, "core_l4_iclk"));
3806
    s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
3807
                    s->irq[0][OMAP_INT_24XX_GPTIMER11],
3808
                    omap_findclk(s, "core_gpt11_clk"),
3809
                    omap_findclk(s, "core_l4_iclk"));
3810
    s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
3811
                    s->irq[0][OMAP_INT_24XX_GPTIMER12],
3812
                    omap_findclk(s, "core_gpt12_clk"),
3813
                    omap_findclk(s, "core_l4_iclk"));
3814

    
3815
    omap_tap_init(omap_l4ta(s->l4, 2), s);
3816

    
3817
    omap_synctimer_init(omap_l4tao(s->l4, 2), s,
3818
                    omap_findclk(s, "clk32-kHz"),
3819
                    omap_findclk(s, "core_l4_iclk"));
3820

    
3821
    s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
3822
                    s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
3823
                    &s->drq[OMAP24XX_DMA_I2C1_TX],
3824
                    omap_findclk(s, "i2c1.fclk"),
3825
                    omap_findclk(s, "i2c1.iclk"));
3826
    s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
3827
                    s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
3828
                    &s->drq[OMAP24XX_DMA_I2C2_TX],
3829
                    omap_findclk(s, "i2c2.fclk"),
3830
                    omap_findclk(s, "i2c2.iclk"));
3831

    
3832
    gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
3833
    gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
3834
    gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
3835
    gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
3836
    s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
3837
                    &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
3838
                    gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
3839

    
3840
    s->sdrc = omap_sdrc_init(0x68009000);
3841
    s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
3842

    
3843
    sdindex = drive_get_index(IF_SD, 0, 0);
3844
    if (sdindex == -1) {
3845
        fprintf(stderr, "qemu: missing SecureDigital device\n");
3846
        exit(1);
3847
    }
3848
    s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
3849
                    s->irq[0][OMAP_INT_24XX_MMC_IRQ],
3850
                    &s->drq[OMAP24XX_DMA_MMC1_TX],
3851
                    omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
3852

    
3853
    s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
3854
                    s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ], 
3855
                    &s->drq[OMAP24XX_DMA_SPI1_TX0],
3856
                    omap_findclk(s, "spi1_fclk"),
3857
                    omap_findclk(s, "spi1_iclk"));
3858
    s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
3859
                    s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ], 
3860
                    &s->drq[OMAP24XX_DMA_SPI2_TX0],
3861
                    omap_findclk(s, "spi2_fclk"),
3862
                    omap_findclk(s, "spi2_iclk"));
3863

    
3864
    s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds,
3865
                    /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
3866
                    s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
3867
                    omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
3868
                    omap_findclk(s, "dss_54m_clk"),
3869
                    omap_findclk(s, "dss_l3_iclk"),
3870
                    omap_findclk(s, "dss_l4_iclk"));
3871

    
3872
    omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
3873
                    s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
3874
                    serial_hds[0] && serial_hds[1] && serial_hds[2] ?
3875
                    serial_hds[3] : 0);
3876

    
3877
    /* All register mappings (includin those not currenlty implemented):
3878
     * SystemControlMod        48000000 - 48000fff
3879
     * SystemControlL4        48001000 - 48001fff
3880
     * 32kHz Timer Mod        48004000 - 48004fff
3881
     * 32kHz Timer L4        48005000 - 48005fff
3882
     * PRCM ModA        48008000 - 480087ff
3883
     * PRCM ModB        48008800 - 48008fff
3884
     * PRCM L4                48009000 - 48009fff
3885
     * TEST-BCM Mod        48012000 - 48012fff
3886
     * TEST-BCM L4        48013000 - 48013fff
3887
     * TEST-TAP Mod        48014000 - 48014fff
3888
     * TEST-TAP L4        48015000 - 48015fff
3889
     * GPIO1 Mod        48018000 - 48018fff
3890
     * GPIO Top                48019000 - 48019fff
3891
     * GPIO2 Mod        4801a000 - 4801afff
3892
     * GPIO L4                4801b000 - 4801bfff
3893
     * GPIO3 Mod        4801c000 - 4801cfff
3894
     * GPIO4 Mod        4801e000 - 4801efff
3895
     * WDTIMER1 Mod        48020000 - 48010fff
3896
     * WDTIMER Top        48021000 - 48011fff
3897
     * WDTIMER2 Mod        48022000 - 48012fff
3898
     * WDTIMER L4        48023000 - 48013fff
3899
     * WDTIMER3 Mod        48024000 - 48014fff
3900
     * WDTIMER3 L4        48025000 - 48015fff
3901
     * WDTIMER4 Mod        48026000 - 48016fff
3902
     * WDTIMER4 L4        48027000 - 48017fff
3903
     * GPTIMER1 Mod        48028000 - 48018fff
3904
     * GPTIMER1 L4        48029000 - 48019fff
3905
     * GPTIMER2 Mod        4802a000 - 4801afff
3906
     * GPTIMER2 L4        4802b000 - 4801bfff
3907
     * L4-Config AP        48040000 - 480407ff
3908
     * L4-Config IP        48040800 - 48040fff
3909
     * L4-Config LA        48041000 - 48041fff
3910
     * ARM11ETB Mod        48048000 - 48049fff
3911
     * ARM11ETB L4        4804a000 - 4804afff
3912
     * DISPLAY Top        48050000 - 480503ff
3913
     * DISPLAY DISPC        48050400 - 480507ff
3914
     * DISPLAY RFBI        48050800 - 48050bff
3915
     * DISPLAY VENC        48050c00 - 48050fff
3916
     * DISPLAY L4        48051000 - 48051fff
3917
     * CAMERA Top        48052000 - 480523ff
3918
     * CAMERA core        48052400 - 480527ff
3919
     * CAMERA DMA        48052800 - 48052bff
3920
     * CAMERA MMU        48052c00 - 48052fff
3921
     * CAMERA L4        48053000 - 48053fff
3922
     * SDMA Mod                48056000 - 48056fff
3923
     * SDMA L4                48057000 - 48057fff
3924
     * SSI Top                48058000 - 48058fff
3925
     * SSI GDD                48059000 - 48059fff
3926
     * SSI Port1        4805a000 - 4805afff
3927
     * SSI Port2        4805b000 - 4805bfff
3928
     * SSI L4                4805c000 - 4805cfff
3929
     * USB Mod                4805e000 - 480fefff
3930
     * USB L4                4805f000 - 480fffff
3931
     * WIN_TRACER1 Mod        48060000 - 48060fff
3932
     * WIN_TRACER1 L4        48061000 - 48061fff
3933
     * WIN_TRACER2 Mod        48062000 - 48062fff
3934
     * WIN_TRACER2 L4        48063000 - 48063fff
3935
     * WIN_TRACER3 Mod        48064000 - 48064fff
3936
     * WIN_TRACER3 L4        48065000 - 48065fff
3937
     * WIN_TRACER4 Top        48066000 - 480660ff
3938
     * WIN_TRACER4 ETT        48066100 - 480661ff
3939
     * WIN_TRACER4 WT        48066200 - 480662ff
3940
     * WIN_TRACER4 L4        48067000 - 48067fff
3941
     * XTI Mod                48068000 - 48068fff
3942
     * XTI L4                48069000 - 48069fff
3943
     * UART1 Mod        4806a000 - 4806afff
3944
     * UART1 L4                4806b000 - 4806bfff
3945
     * UART2 Mod        4806c000 - 4806cfff
3946
     * UART2 L4                4806d000 - 4806dfff
3947
     * UART3 Mod        4806e000 - 4806efff
3948
     * UART3 L4                4806f000 - 4806ffff
3949
     * I2C1 Mod                48070000 - 48070fff
3950
     * I2C1 L4                48071000 - 48071fff
3951
     * I2C2 Mod                48072000 - 48072fff
3952
     * I2C2 L4                48073000 - 48073fff
3953
     * McBSP1 Mod        48074000 - 48074fff
3954
     * McBSP1 L4        48075000 - 48075fff
3955
     * McBSP2 Mod        48076000 - 48076fff
3956
     * McBSP2 L4        48077000 - 48077fff
3957
     * GPTIMER3 Mod        48078000 - 48078fff
3958
     * GPTIMER3 L4        48079000 - 48079fff
3959
     * GPTIMER4 Mod        4807a000 - 4807afff
3960
     * GPTIMER4 L4        4807b000 - 4807bfff
3961
     * GPTIMER5 Mod        4807c000 - 4807cfff
3962
     * GPTIMER5 L4        4807d000 - 4807dfff
3963
     * GPTIMER6 Mod        4807e000 - 4807efff
3964
     * GPTIMER6 L4        4807f000 - 4807ffff
3965
     * GPTIMER7 Mod        48080000 - 48080fff
3966
     * GPTIMER7 L4        48081000 - 48081fff
3967
     * GPTIMER8 Mod        48082000 - 48082fff
3968
     * GPTIMER8 L4        48083000 - 48083fff
3969
     * GPTIMER9 Mod        48084000 - 48084fff
3970
     * GPTIMER9 L4        48085000 - 48085fff
3971
     * GPTIMER10 Mod        48086000 - 48086fff
3972
     * GPTIMER10 L4        48087000 - 48087fff
3973
     * GPTIMER11 Mod        48088000 - 48088fff
3974
     * GPTIMER11 L4        48089000 - 48089fff
3975
     * GPTIMER12 Mod        4808a000 - 4808afff
3976
     * GPTIMER12 L4        4808b000 - 4808bfff
3977
     * EAC Mod                48090000 - 48090fff
3978
     * EAC L4                48091000 - 48091fff
3979
     * FAC Mod                48092000 - 48092fff
3980
     * FAC L4                48093000 - 48093fff
3981
     * MAILBOX Mod        48094000 - 48094fff
3982
     * MAILBOX L4        48095000 - 48095fff
3983
     * SPI1 Mod                48098000 - 48098fff
3984
     * SPI1 L4                48099000 - 48099fff
3985
     * SPI2 Mod                4809a000 - 4809afff
3986
     * SPI2 L4                4809b000 - 4809bfff
3987
     * MMC/SDIO Mod        4809c000 - 4809cfff
3988
     * MMC/SDIO L4        4809d000 - 4809dfff
3989
     * MS_PRO Mod        4809e000 - 4809efff
3990
     * MS_PRO L4        4809f000 - 4809ffff
3991
     * RNG Mod                480a0000 - 480a0fff
3992
     * RNG L4                480a1000 - 480a1fff
3993
     * DES3DES Mod        480a2000 - 480a2fff
3994
     * DES3DES L4        480a3000 - 480a3fff
3995
     * SHA1MD5 Mod        480a4000 - 480a4fff
3996
     * SHA1MD5 L4        480a5000 - 480a5fff
3997
     * AES Mod                480a6000 - 480a6fff
3998
     * AES L4                480a7000 - 480a7fff
3999
     * PKA Mod                480a8000 - 480a9fff
4000
     * PKA L4                480aa000 - 480aafff
4001
     * MG Mod                480b0000 - 480b0fff
4002
     * MG L4                480b1000 - 480b1fff
4003
     * HDQ/1-wire Mod        480b2000 - 480b2fff
4004
     * HDQ/1-wire L4        480b3000 - 480b3fff
4005
     * MPU interrupt        480fe000 - 480fefff
4006
     * STI channel base        54000000 - 5400ffff
4007
     * IVA RAM                5c000000 - 5c01ffff
4008
     * IVA ROM                5c020000 - 5c027fff
4009
     * IMG_BUF_A        5c040000 - 5c040fff
4010
     * IMG_BUF_B        5c042000 - 5c042fff
4011
     * VLCDS                5c048000 - 5c0487ff
4012
     * IMX_COEF                5c049000 - 5c04afff
4013
     * IMX_CMD                5c051000 - 5c051fff
4014
     * VLCDQ                5c053000 - 5c0533ff
4015
     * VLCDH                5c054000 - 5c054fff
4016
     * SEQ_CMD                5c055000 - 5c055fff
4017
     * IMX_REG                5c056000 - 5c0560ff
4018
     * VLCD_REG                5c056100 - 5c0561ff
4019
     * SEQ_REG                5c056200 - 5c0562ff
4020
     * IMG_BUF_REG        5c056300 - 5c0563ff
4021
     * SEQIRQ_REG        5c056400 - 5c0564ff
4022
     * OCP_REG                5c060000 - 5c060fff
4023
     * SYSC_REG                5c070000 - 5c070fff
4024
     * MMU_REG                5d000000 - 5d000fff
4025
     * sDMA R                68000400 - 680005ff
4026
     * sDMA W                68000600 - 680007ff
4027
     * Display Control        68000800 - 680009ff
4028
     * DSP subsystem        68000a00 - 68000bff
4029
     * MPU subsystem        68000c00 - 68000dff
4030
     * IVA subsystem        68001000 - 680011ff
4031
     * USB                68001200 - 680013ff
4032
     * Camera                68001400 - 680015ff
4033
     * VLYNQ (firewall)        68001800 - 68001bff
4034
     * VLYNQ                68001e00 - 68001fff
4035
     * SSI                68002000 - 680021ff
4036
     * L4                68002400 - 680025ff
4037
     * DSP (firewall)        68002800 - 68002bff
4038
     * DSP subsystem        68002e00 - 68002fff
4039
     * IVA (firewall)        68003000 - 680033ff
4040
     * IVA                68003600 - 680037ff
4041
     * GFX                68003a00 - 68003bff
4042
     * CMDWR emulation        68003c00 - 68003dff
4043
     * SMS                68004000 - 680041ff
4044
     * OCM                68004200 - 680043ff
4045
     * GPMC                68004400 - 680045ff
4046
     * RAM (firewall)        68005000 - 680053ff
4047
     * RAM (err login)        68005400 - 680057ff
4048
     * ROM (firewall)        68005800 - 68005bff
4049
     * ROM (err login)        68005c00 - 68005fff
4050
     * GPMC (firewall)        68006000 - 680063ff
4051
     * GPMC (err login)        68006400 - 680067ff
4052
     * SMS (err login)        68006c00 - 68006fff
4053
     * SMS registers        68008000 - 68008fff
4054
     * SDRC registers        68009000 - 68009fff
4055
     * GPMC registers        6800a000   6800afff
4056
     */
4057

    
4058
    qemu_register_reset(omap2_mpu_reset, s);
4059

    
4060
    return s;
4061
}