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1
/*
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 * ACPI implementation
3
 *
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 * Copyright (c) 2006 Fabrice Bellard
5
 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>
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 */
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#include "hw.h"
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#include "pc.h"
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#include "apm.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "acpi.h"
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#include "sysemu.h"
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#include "range.h"
26

    
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//#define DEBUG
28

    
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...)     do { } while (0)
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#endif
34

    
35
#define ACPI_DBG_IO_ADDR  0xb044
36

    
37
#define GPE_BASE 0xafe0
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#define PCI_BASE 0xae00
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#define PCI_EJ_BASE 0xae08
40

    
41
#define PIIX4_PCI_HOTPLUG_STATUS 2
42

    
43
struct gpe_regs {
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    uint16_t sts; /* status */
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    uint16_t en;  /* enabled */
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};
47

    
48
struct pci_status {
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    uint32_t up;
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    uint32_t down;
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};
52

    
53
typedef struct PIIX4PMState {
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    PCIDevice dev;
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    uint16_t pmsts;
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    uint16_t pmen;
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    uint16_t pmcntrl;
58

    
59
    APMState apm;
60

    
61
    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
63

    
64
    PMSMBus smb;
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    uint32_t smb_io_base;
66

    
67
    qemu_irq irq;
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    qemu_irq cmos_s3;
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    qemu_irq smi_irq;
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    int kvm_enabled;
71

    
72
    /* for pci hotplug */
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    struct gpe_regs gpe;
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    struct pci_status pci0_status;
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} PIIX4PMState;
76

    
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
78

    
79
#define ACPI_ENABLE 0xf1
80
#define ACPI_DISABLE 0xf0
81

    
82
static uint32_t get_pmtmr(PIIX4PMState *s)
83
{
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    uint32_t d;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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    return d & 0xffffff;
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}
88

    
89
static int get_pmsts(PIIX4PMState *s)
90
{
91
    int64_t d;
92

    
93
    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
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                 get_ticks_per_sec());
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    if (d >= s->tmr_overflow_time)
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        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
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    return s->pmsts;
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}
99

    
100
static void pm_update_sci(PIIX4PMState *s)
101
{
102
    int sci_level, pmsts;
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    int64_t expire_time;
104

    
105
    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) &
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                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
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                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
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                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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        (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
112

    
113
    qemu_set_irq(s->irq, sci_level);
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    /* schedule a timer interruption if needed */
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    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
116
        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
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        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
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                               PM_TIMER_FREQUENCY);
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        qemu_mod_timer(s->tmr_timer, expire_time);
120
    } else {
121
        qemu_del_timer(s->tmr_timer);
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    }
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}
124

    
125
static void pm_tmr_timer(void *opaque)
126
{
127
    PIIX4PMState *s = opaque;
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    pm_update_sci(s);
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}
130

    
131
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
132
{
133
    PIIX4PMState *s = opaque;
134
    addr &= 0x3f;
135
    switch(addr) {
136
    case 0x00:
137
        {
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            int64_t d;
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            int pmsts;
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            pmsts = get_pmsts(s);
141
            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
142
                /* if TMRSTS is reset, then compute the new overflow time */
143
                d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
144
                             get_ticks_per_sec());
145
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
146
            }
147
            s->pmsts &= ~val;
148
            pm_update_sci(s);
149
        }
150
        break;
151
    case 0x02:
152
        s->pmen = val;
153
        pm_update_sci(s);
154
        break;
155
    case 0x04:
156
        {
157
            int sus_typ;
158
            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
159
            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
160
                /* change suspend type */
161
                sus_typ = (val >> 10) & 7;
162
                switch(sus_typ) {
163
                case 0: /* soft power off */
164
                    qemu_system_shutdown_request();
165
                    break;
166
                case 1:
167
                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
168
                       Pretend that resume was caused by power button */
169
                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
170
                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
171
                    qemu_system_reset_request();
172
                    if (s->cmos_s3) {
173
                        qemu_irq_raise(s->cmos_s3);
174
                    }
175
                default:
176
                    break;
177
                }
178
            }
179
        }
180
        break;
181
    default:
182
        break;
183
    }
184
    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
185
}
186

    
187
static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
188
{
189
    PIIX4PMState *s = opaque;
190
    uint32_t val;
191

    
192
    addr &= 0x3f;
193
    switch(addr) {
194
    case 0x00:
195
        val = get_pmsts(s);
196
        break;
197
    case 0x02:
198
        val = s->pmen;
199
        break;
200
    case 0x04:
201
        val = s->pmcntrl;
202
        break;
203
    default:
204
        val = 0;
205
        break;
206
    }
207
    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
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    return val;
209
}
210

    
211
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
212
{
213
    //    PIIX4PMState *s = opaque;
214
    PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
215
}
216

    
217
static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
218
{
219
    PIIX4PMState *s = opaque;
220
    uint32_t val;
221

    
222
    addr &= 0x3f;
223
    switch(addr) {
224
    case 0x08:
225
        val = get_pmtmr(s);
226
        break;
227
    default:
228
        val = 0;
229
        break;
230
    }
231
    PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
232
    return val;
233
}
234

    
235
static void apm_ctrl_changed(uint32_t val, void *arg)
236
{
237
    PIIX4PMState *s = arg;
238

    
239
    /* ACPI specs 3.0, 4.7.2.5 */
240
    if (val == ACPI_ENABLE) {
241
        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
242
    } else if (val == ACPI_DISABLE) {
243
        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
244
    }
245

    
246
    if (s->dev.config[0x5b] & (1 << 1)) {
247
        if (s->smi_irq) {
248
            qemu_irq_raise(s->smi_irq);
249
        }
250
    }
251
}
252

    
253
static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
254
{
255
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
256
}
257

    
258
static void pm_io_space_update(PIIX4PMState *s)
259
{
260
    uint32_t pm_io_base;
261

    
262
    if (s->dev.config[0x80] & 1) {
263
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
264
        pm_io_base &= 0xffc0;
265

    
266
        /* XXX: need to improve memory and ioport allocation */
267
        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
268
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
269
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
270
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
271
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
272
    }
273
}
274

    
275
static void pm_write_config(PCIDevice *d,
276
                            uint32_t address, uint32_t val, int len)
277
{
278
    pci_default_write_config(d, address, val, len);
279
    if (range_covers_byte(address, len, 0x80))
280
        pm_io_space_update((PIIX4PMState *)d);
281
}
282

    
283
static int vmstate_acpi_post_load(void *opaque, int version_id)
284
{
285
    PIIX4PMState *s = opaque;
286

    
287
    pm_io_space_update(s);
288
    return 0;
289
}
290

    
291
static const VMStateDescription vmstate_gpe = {
292
    .name = "gpe",
293
    .version_id = 1,
294
    .minimum_version_id = 1,
295
    .minimum_version_id_old = 1,
296
    .fields      = (VMStateField []) {
297
        VMSTATE_UINT16(sts, struct gpe_regs),
298
        VMSTATE_UINT16(en, struct gpe_regs),
299
        VMSTATE_END_OF_LIST()
300
    }
301
};
302

    
303
static const VMStateDescription vmstate_pci_status = {
304
    .name = "pci_status",
305
    .version_id = 1,
306
    .minimum_version_id = 1,
307
    .minimum_version_id_old = 1,
308
    .fields      = (VMStateField []) {
309
        VMSTATE_UINT32(up, struct pci_status),
310
        VMSTATE_UINT32(down, struct pci_status),
311
        VMSTATE_END_OF_LIST()
312
    }
313
};
314

    
315
static const VMStateDescription vmstate_acpi = {
316
    .name = "piix4_pm",
317
    .version_id = 2,
318
    .minimum_version_id = 1,
319
    .minimum_version_id_old = 1,
320
    .post_load = vmstate_acpi_post_load,
321
    .fields      = (VMStateField []) {
322
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
323
        VMSTATE_UINT16(pmsts, PIIX4PMState),
324
        VMSTATE_UINT16(pmen, PIIX4PMState),
325
        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
326
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
327
        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
328
        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
329
        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
330
        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
331
                       struct pci_status),
332
        VMSTATE_END_OF_LIST()
333
    }
334
};
335

    
336
static void piix4_reset(void *opaque)
337
{
338
    PIIX4PMState *s = opaque;
339
    uint8_t *pci_conf = s->dev.config;
340

    
341
    pci_conf[0x58] = 0;
342
    pci_conf[0x59] = 0;
343
    pci_conf[0x5a] = 0;
344
    pci_conf[0x5b] = 0;
345

    
346
    if (s->kvm_enabled) {
347
        /* Mark SMM as already inited (until KVM supports SMM). */
348
        pci_conf[0x5B] = 0x02;
349
    }
350
}
351

    
352
static void piix4_powerdown(void *opaque, int irq, int power_failing)
353
{
354
    PIIX4PMState *s = opaque;
355

    
356
    if (!s) {
357
        qemu_system_shutdown_request();
358
    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
359
        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
360
        pm_update_sci(s);
361
    }
362
}
363

    
364
static int piix4_pm_initfn(PCIDevice *dev)
365
{
366
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
367
    uint8_t *pci_conf;
368

    
369
    pci_conf = s->dev.config;
370
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
371
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
372
    pci_conf[0x06] = 0x80;
373
    pci_conf[0x07] = 0x02;
374
    pci_conf[0x08] = 0x03; // revision number
375
    pci_conf[0x09] = 0x00;
376
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
377
    pci_conf[0x3d] = 0x01; // interrupt pin 1
378

    
379
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
380

    
381
    /* APM */
382
    apm_init(&s->apm, apm_ctrl_changed, s);
383

    
384
    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
385

    
386
    if (s->kvm_enabled) {
387
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
388
         * support SMM mode. */
389
        pci_conf[0x5B] = 0x02;
390
    }
391

    
392
    /* XXX: which specification is used ? The i82731AB has different
393
       mappings */
394
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
395
    pci_conf[0x63] = 0x60;
396
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
397
        (serial_hds[1] != NULL ? 0x90 : 0);
398

    
399
    pci_conf[0x90] = s->smb_io_base | 1;
400
    pci_conf[0x91] = s->smb_io_base >> 8;
401
    pci_conf[0xd2] = 0x09;
402
    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
403
    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
404

    
405
    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
406

    
407
    qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
408

    
409
    pm_smbus_init(&s->dev.qdev, &s->smb);
410
    qemu_register_reset(piix4_reset, s);
411
    piix4_acpi_system_hot_add_init(dev->bus, s);
412

    
413
    return 0;
414
}
415

    
416
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
417
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
418
                       int kvm_enabled)
419
{
420
    PCIDevice *dev;
421
    PIIX4PMState *s;
422

    
423
    dev = pci_create(bus, devfn, "PIIX4_PM");
424
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
425

    
426
    s = DO_UPCAST(PIIX4PMState, dev, dev);
427
    s->irq = sci_irq;
428
    s->cmos_s3 = cmos_s3;
429
    s->smi_irq = smi_irq;
430
    s->kvm_enabled = kvm_enabled;
431

    
432
    qdev_init_nofail(&dev->qdev);
433

    
434
    return s->smb.smbus;
435
}
436

    
437
static PCIDeviceInfo piix4_pm_info = {
438
    .qdev.name          = "PIIX4_PM",
439
    .qdev.desc          = "PM",
440
    .qdev.size          = sizeof(PIIX4PMState),
441
    .qdev.vmsd          = &vmstate_acpi,
442
    .init               = piix4_pm_initfn,
443
    .config_write       = pm_write_config,
444
    .qdev.props         = (Property[]) {
445
        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
446
        DEFINE_PROP_END_OF_LIST(),
447
    }
448
};
449

    
450
static void piix4_pm_register(void)
451
{
452
    pci_qdev_register(&piix4_pm_info);
453
}
454

    
455
device_init(piix4_pm_register);
456

    
457
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
458
{
459
    if (addr & 1)
460
        return (val >> 8) & 0xff;
461
    return val & 0xff;
462
}
463

    
464
static uint32_t gpe_readb(void *opaque, uint32_t addr)
465
{
466
    uint32_t val = 0;
467
    PIIX4PMState *s = opaque;
468
    struct gpe_regs *g = &s->gpe;
469

    
470
    switch (addr) {
471
        case GPE_BASE:
472
        case GPE_BASE + 1:
473
            val = gpe_read_val(g->sts, addr);
474
            break;
475
        case GPE_BASE + 2:
476
        case GPE_BASE + 3:
477
            val = gpe_read_val(g->en, addr);
478
            break;
479
        default:
480
            break;
481
    }
482

    
483
    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
484
    return val;
485
}
486

    
487
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
488
{
489
    if (addr & 1)
490
        *cur = (*cur & 0xff) | (val << 8);
491
    else
492
        *cur = (*cur & 0xff00) | (val & 0xff);
493
}
494

    
495
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
496
{
497
    uint16_t x1, x0 = val & 0xff;
498
    int shift = (addr & 1) ? 8 : 0;
499

    
500
    x1 = (*cur >> shift) & 0xff;
501

    
502
    x1 = x1 & ~x0;
503

    
504
    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
505
}
506

    
507
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
508
{
509
    PIIX4PMState *s = opaque;
510
    struct gpe_regs *g = &s->gpe;
511

    
512
    switch (addr) {
513
        case GPE_BASE:
514
        case GPE_BASE + 1:
515
            gpe_reset_val(&g->sts, addr, val);
516
            break;
517
        case GPE_BASE + 2:
518
        case GPE_BASE + 3:
519
            gpe_write_val(&g->en, addr, val);
520
            break;
521
        default:
522
            break;
523
    }
524

    
525
    pm_update_sci(s);
526

    
527
    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
528
}
529

    
530
static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
531
{
532
    uint32_t val = 0;
533
    struct pci_status *g = opaque;
534
    switch (addr) {
535
        case PCI_BASE:
536
            val = g->up;
537
            break;
538
        case PCI_BASE + 4:
539
            val = g->down;
540
            break;
541
        default:
542
            break;
543
    }
544

    
545
    PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
546
    return val;
547
}
548

    
549
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
550
{
551
    struct pci_status *g = opaque;
552
    switch (addr) {
553
        case PCI_BASE:
554
            g->up = val;
555
            break;
556
        case PCI_BASE + 4:
557
            g->down = val;
558
            break;
559
   }
560

    
561
    PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
562
}
563

    
564
static uint32_t pciej_read(void *opaque, uint32_t addr)
565
{
566
    PIIX4_DPRINTF("pciej read %x\n", addr);
567
    return 0;
568
}
569

    
570
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
571
{
572
    BusState *bus = opaque;
573
    DeviceState *qdev, *next;
574
    PCIDevice *dev;
575
    int slot = ffs(val) - 1;
576

    
577
    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
578
        dev = DO_UPCAST(PCIDevice, qdev, qdev);
579
        if (PCI_SLOT(dev->devfn) == slot) {
580
            qdev_free(qdev);
581
        }
582
    }
583

    
584

    
585
    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
586
}
587

    
588
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
589
                                PCIHotplugState state);
590

    
591
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
592
{
593
    struct pci_status *pci0_status = &s->pci0_status;
594

    
595
    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
596
    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
597

    
598
    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
599
    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
600

    
601
    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
602
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
603

    
604
    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
605
}
606

    
607
static void enable_device(PIIX4PMState *s, int slot)
608
{
609
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
610
    s->pci0_status.up |= (1 << slot);
611
}
612

    
613
static void disable_device(PIIX4PMState *s, int slot)
614
{
615
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
616
    s->pci0_status.down |= (1 << slot);
617
}
618

    
619
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
620
                                PCIHotplugState state)
621
{
622
    int slot = PCI_SLOT(dev->devfn);
623
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
624
                                DO_UPCAST(PCIDevice, qdev, qdev));
625

    
626
    /* Don't send event when device is enabled during qemu machine creation:
627
     * it is present on boot, no hotplug event is necessary. We do send an
628
     * event when the device is disabled later. */
629
    if (state == PCI_COLDPLUG_ENABLED) {
630
        return 0;
631
    }
632

    
633
    s->pci0_status.up = 0;
634
    s->pci0_status.down = 0;
635
    if (state == PCI_HOTPLUG_ENABLED) {
636
        enable_device(s, slot);
637
    } else {
638
        disable_device(s, slot);
639
    }
640

    
641
    pm_update_sci(s);
642

    
643
    return 0;
644
}