root / hw / sh7750.c @ e96e2044
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1 | 27c7ca7e | bellard | /*
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2 | 27c7ca7e | bellard | * SH7750 device
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3 | 5fafdf24 | ths | *
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4 | 80f515e6 | balrog | * Copyright (c) 2007 Magnus Damm
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5 | 27c7ca7e | bellard | * Copyright (c) 2005 Samuel Tardieu
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6 | 5fafdf24 | ths | *
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7 | 27c7ca7e | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 27c7ca7e | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 27c7ca7e | bellard | * in the Software without restriction, including without limitation the rights
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10 | 27c7ca7e | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 27c7ca7e | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 27c7ca7e | bellard | * furnished to do so, subject to the following conditions:
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13 | 27c7ca7e | bellard | *
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14 | 27c7ca7e | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 27c7ca7e | bellard | * all copies or substantial portions of the Software.
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16 | 27c7ca7e | bellard | *
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17 | 27c7ca7e | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 27c7ca7e | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 27c7ca7e | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 27c7ca7e | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 27c7ca7e | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 27c7ca7e | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 27c7ca7e | bellard | * THE SOFTWARE.
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24 | 27c7ca7e | bellard | */
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25 | 27c7ca7e | bellard | #include <stdio.h> |
26 | 27c7ca7e | bellard | #include <assert.h> |
27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 27c7ca7e | bellard | #include "sh7750_regs.h" |
31 | 27c7ca7e | bellard | #include "sh7750_regnames.h" |
32 | 80f515e6 | balrog | #include "sh_intc.h" |
33 | 27c7ca7e | bellard | |
34 | 27c7ca7e | bellard | #define NB_DEVICES 4 |
35 | 27c7ca7e | bellard | |
36 | 27c7ca7e | bellard | typedef struct SH7750State { |
37 | 27c7ca7e | bellard | /* CPU */
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38 | 27c7ca7e | bellard | CPUSH4State *cpu; |
39 | 27c7ca7e | bellard | /* Peripheral frequency in Hz */
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40 | 27c7ca7e | bellard | uint32_t periph_freq; |
41 | 27c7ca7e | bellard | /* SDRAM controller */
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42 | 27c7ca7e | bellard | uint16_t rfcr; |
43 | 27c7ca7e | bellard | /* IO ports */
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44 | 27c7ca7e | bellard | uint16_t gpioic; |
45 | 27c7ca7e | bellard | uint32_t pctra; |
46 | 27c7ca7e | bellard | uint32_t pctrb; |
47 | 27c7ca7e | bellard | uint16_t portdira; /* Cached */
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48 | 27c7ca7e | bellard | uint16_t portpullupa; /* Cached */
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49 | 27c7ca7e | bellard | uint16_t portdirb; /* Cached */
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50 | 27c7ca7e | bellard | uint16_t portpullupb; /* Cached */
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51 | 27c7ca7e | bellard | uint16_t pdtra; |
52 | 27c7ca7e | bellard | uint16_t pdtrb; |
53 | 27c7ca7e | bellard | uint16_t periph_pdtra; /* Imposed by the peripherals */
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54 | 27c7ca7e | bellard | uint16_t periph_portdira; /* Direction seen from the peripherals */
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55 | 27c7ca7e | bellard | uint16_t periph_pdtrb; /* Imposed by the peripherals */
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56 | 27c7ca7e | bellard | uint16_t periph_portdirb; /* Direction seen from the peripherals */
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57 | 27c7ca7e | bellard | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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58 | 3464c589 | ths | |
59 | 3464c589 | ths | uint16_t icr; |
60 | 27c7ca7e | bellard | /* Cache */
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61 | 27c7ca7e | bellard | uint32_t ccr; |
62 | 27c7ca7e | bellard | |
63 | 80f515e6 | balrog | struct intc_desc intc;
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64 | cd1a3f68 | ths | } SH7750State; |
65 | 27c7ca7e | bellard | |
66 | 27c7ca7e | bellard | |
67 | 27c7ca7e | bellard | /**********************************************************************
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68 | 27c7ca7e | bellard | I/O ports
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69 | 27c7ca7e | bellard | **********************************************************************/
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70 | 27c7ca7e | bellard | |
71 | 27c7ca7e | bellard | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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72 | 27c7ca7e | bellard | { |
73 | 27c7ca7e | bellard | int i;
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74 | 27c7ca7e | bellard | |
75 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
76 | 27c7ca7e | bellard | if (s->devices[i] == NULL) { |
77 | 27c7ca7e | bellard | s->devices[i] = device; |
78 | 27c7ca7e | bellard | return 0; |
79 | 27c7ca7e | bellard | } |
80 | 27c7ca7e | bellard | } |
81 | 27c7ca7e | bellard | return -1; |
82 | 27c7ca7e | bellard | } |
83 | 27c7ca7e | bellard | |
84 | 27c7ca7e | bellard | static uint16_t portdir(uint32_t v)
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85 | 27c7ca7e | bellard | { |
86 | 27c7ca7e | bellard | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
87 | 27c7ca7e | bellard | return
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88 | 27c7ca7e | bellard | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
89 | 27c7ca7e | bellard | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
90 | 27c7ca7e | bellard | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
91 | 27c7ca7e | bellard | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
92 | 27c7ca7e | bellard | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
93 | 27c7ca7e | bellard | EVENPORTMASK(0);
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94 | 27c7ca7e | bellard | } |
95 | 27c7ca7e | bellard | |
96 | 27c7ca7e | bellard | static uint16_t portpullup(uint32_t v)
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97 | 27c7ca7e | bellard | { |
98 | 27c7ca7e | bellard | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
99 | 27c7ca7e | bellard | return
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100 | 27c7ca7e | bellard | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
101 | 27c7ca7e | bellard | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
102 | 27c7ca7e | bellard | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
103 | 27c7ca7e | bellard | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
104 | 27c7ca7e | bellard | ODDPORTMASK(1) | ODDPORTMASK(0); |
105 | 27c7ca7e | bellard | } |
106 | 27c7ca7e | bellard | |
107 | 27c7ca7e | bellard | static uint16_t porta_lines(SH7750State * s)
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108 | 27c7ca7e | bellard | { |
109 | 27c7ca7e | bellard | return (s->portdira & s->pdtra) | /* CPU */ |
110 | 27c7ca7e | bellard | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
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111 | 27c7ca7e | bellard | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
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112 | 27c7ca7e | bellard | } |
113 | 27c7ca7e | bellard | |
114 | 27c7ca7e | bellard | static uint16_t portb_lines(SH7750State * s)
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115 | 27c7ca7e | bellard | { |
116 | 27c7ca7e | bellard | return (s->portdirb & s->pdtrb) | /* CPU */ |
117 | 27c7ca7e | bellard | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
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118 | 27c7ca7e | bellard | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
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119 | 27c7ca7e | bellard | } |
120 | 27c7ca7e | bellard | |
121 | 27c7ca7e | bellard | static void gen_port_interrupts(SH7750State * s) |
122 | 27c7ca7e | bellard | { |
123 | 27c7ca7e | bellard | /* XXXXX interrupts not generated */
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124 | 27c7ca7e | bellard | } |
125 | 27c7ca7e | bellard | |
126 | 27c7ca7e | bellard | static void porta_changed(SH7750State * s, uint16_t prev) |
127 | 27c7ca7e | bellard | { |
128 | 27c7ca7e | bellard | uint16_t currenta, changes; |
129 | 27c7ca7e | bellard | int i, r = 0; |
130 | 27c7ca7e | bellard | |
131 | 27c7ca7e | bellard | #if 0
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132 | 27c7ca7e | bellard | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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133 | 27c7ca7e | bellard | prev, porta_lines(s));
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134 | 27c7ca7e | bellard | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
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135 | 27c7ca7e | bellard | #endif
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136 | 27c7ca7e | bellard | currenta = porta_lines(s); |
137 | 27c7ca7e | bellard | if (currenta == prev)
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138 | 27c7ca7e | bellard | return;
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139 | 27c7ca7e | bellard | changes = currenta ^ prev; |
140 | 27c7ca7e | bellard | |
141 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
142 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
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143 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
144 | 27c7ca7e | bellard | &s->periph_pdtra, |
145 | 27c7ca7e | bellard | &s->periph_portdira, |
146 | 27c7ca7e | bellard | &s->periph_pdtrb, |
147 | 27c7ca7e | bellard | &s->periph_portdirb); |
148 | 27c7ca7e | bellard | } |
149 | 27c7ca7e | bellard | } |
150 | 27c7ca7e | bellard | |
151 | 27c7ca7e | bellard | if (r)
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152 | 27c7ca7e | bellard | gen_port_interrupts(s); |
153 | 27c7ca7e | bellard | } |
154 | 27c7ca7e | bellard | |
155 | 27c7ca7e | bellard | static void portb_changed(SH7750State * s, uint16_t prev) |
156 | 27c7ca7e | bellard | { |
157 | 27c7ca7e | bellard | uint16_t currentb, changes; |
158 | 27c7ca7e | bellard | int i, r = 0; |
159 | 27c7ca7e | bellard | |
160 | 27c7ca7e | bellard | currentb = portb_lines(s); |
161 | 27c7ca7e | bellard | if (currentb == prev)
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162 | 27c7ca7e | bellard | return;
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163 | 27c7ca7e | bellard | changes = currentb ^ prev; |
164 | 27c7ca7e | bellard | |
165 | 27c7ca7e | bellard | for (i = 0; i < NB_DEVICES; i++) { |
166 | 27c7ca7e | bellard | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
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167 | 27c7ca7e | bellard | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
168 | 27c7ca7e | bellard | &s->periph_pdtra, |
169 | 27c7ca7e | bellard | &s->periph_portdira, |
170 | 27c7ca7e | bellard | &s->periph_pdtrb, |
171 | 27c7ca7e | bellard | &s->periph_portdirb); |
172 | 27c7ca7e | bellard | } |
173 | 27c7ca7e | bellard | } |
174 | 27c7ca7e | bellard | |
175 | 27c7ca7e | bellard | if (r)
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176 | 27c7ca7e | bellard | gen_port_interrupts(s); |
177 | 27c7ca7e | bellard | } |
178 | 27c7ca7e | bellard | |
179 | 27c7ca7e | bellard | /**********************************************************************
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180 | 27c7ca7e | bellard | Memory
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181 | 27c7ca7e | bellard | **********************************************************************/
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182 | 27c7ca7e | bellard | |
183 | 27c7ca7e | bellard | static void error_access(const char *kind, target_phys_addr_t addr) |
184 | 27c7ca7e | bellard | { |
185 | 27c7ca7e | bellard | fprintf(stderr, "%s to %s (0x%08x) not supported\n",
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186 | 27c7ca7e | bellard | kind, regname(addr), addr); |
187 | 27c7ca7e | bellard | } |
188 | 27c7ca7e | bellard | |
189 | 27c7ca7e | bellard | static void ignore_access(const char *kind, target_phys_addr_t addr) |
190 | 27c7ca7e | bellard | { |
191 | 27c7ca7e | bellard | fprintf(stderr, "%s to %s (0x%08x) ignored\n",
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192 | 27c7ca7e | bellard | kind, regname(addr), addr); |
193 | 27c7ca7e | bellard | } |
194 | 27c7ca7e | bellard | |
195 | 27c7ca7e | bellard | static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
196 | 27c7ca7e | bellard | { |
197 | 27c7ca7e | bellard | switch (addr) {
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198 | 27c7ca7e | bellard | default:
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199 | 27c7ca7e | bellard | error_access("byte read", addr);
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200 | 27c7ca7e | bellard | assert(0);
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201 | 27c7ca7e | bellard | } |
202 | 27c7ca7e | bellard | } |
203 | 27c7ca7e | bellard | |
204 | 27c7ca7e | bellard | static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
205 | 27c7ca7e | bellard | { |
206 | 27c7ca7e | bellard | SH7750State *s = opaque; |
207 | 27c7ca7e | bellard | |
208 | 27c7ca7e | bellard | switch (addr) {
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209 | ed8e0a4d | ths | case SH7750_FRQCR_A7:
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210 | ed8e0a4d | ths | return 0; |
211 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
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212 | 27c7ca7e | bellard | fprintf(stderr, |
213 | 27c7ca7e | bellard | "Read access to refresh count register, incrementing\n");
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214 | 27c7ca7e | bellard | return s->rfcr++;
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215 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
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216 | 27c7ca7e | bellard | return porta_lines(s);
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217 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
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218 | 27c7ca7e | bellard | return portb_lines(s);
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219 | 3464c589 | ths | case 0x1fd00000: |
220 | 3464c589 | ths | return s->icr;
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221 | 27c7ca7e | bellard | default:
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222 | 27c7ca7e | bellard | error_access("word read", addr);
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223 | 27c7ca7e | bellard | assert(0);
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224 | 27c7ca7e | bellard | } |
225 | 27c7ca7e | bellard | } |
226 | 27c7ca7e | bellard | |
227 | 27c7ca7e | bellard | static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
228 | 27c7ca7e | bellard | { |
229 | 27c7ca7e | bellard | SH7750State *s = opaque; |
230 | 27c7ca7e | bellard | |
231 | 27c7ca7e | bellard | switch (addr) {
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232 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
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233 | 27c7ca7e | bellard | return s->cpu->mmucr;
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234 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
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235 | 27c7ca7e | bellard | return s->cpu->pteh;
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236 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
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237 | 27c7ca7e | bellard | return s->cpu->ptel;
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238 | 27c7ca7e | bellard | case SH7750_TTB_A7:
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239 | 27c7ca7e | bellard | return s->cpu->ttb;
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240 | 27c7ca7e | bellard | case SH7750_TEA_A7:
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241 | 27c7ca7e | bellard | return s->cpu->tea;
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242 | 27c7ca7e | bellard | case SH7750_TRA_A7:
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243 | 27c7ca7e | bellard | return s->cpu->tra;
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244 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
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245 | 27c7ca7e | bellard | return s->cpu->expevt;
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246 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
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247 | 27c7ca7e | bellard | return s->cpu->intevt;
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248 | 27c7ca7e | bellard | case SH7750_CCR_A7:
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249 | 27c7ca7e | bellard | return s->ccr;
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250 | 27c7ca7e | bellard | case 0x1f000030: /* Processor version PVR */ |
251 | 27c7ca7e | bellard | return 0x00050000; /* SH7750R */ |
252 | 27c7ca7e | bellard | case 0x1f000040: /* Processor version CVR */ |
253 | 27c7ca7e | bellard | return 0x00110000; /* Minimum caches */ |
254 | 27c7ca7e | bellard | case 0x1f000044: /* Processor version PRR */ |
255 | 27c7ca7e | bellard | return 0x00000100; /* SH7750R */ |
256 | 27c7ca7e | bellard | default:
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257 | 27c7ca7e | bellard | error_access("long read", addr);
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258 | 27c7ca7e | bellard | assert(0);
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259 | 27c7ca7e | bellard | } |
260 | 27c7ca7e | bellard | } |
261 | 27c7ca7e | bellard | |
262 | 27c7ca7e | bellard | static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
263 | 27c7ca7e | bellard | uint32_t mem_value) |
264 | 27c7ca7e | bellard | { |
265 | 27c7ca7e | bellard | switch (addr) {
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266 | 27c7ca7e | bellard | /* PRECHARGE ? XXXXX */
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267 | 27c7ca7e | bellard | case SH7750_PRECHARGE0_A7:
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268 | 27c7ca7e | bellard | case SH7750_PRECHARGE1_A7:
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269 | 27c7ca7e | bellard | ignore_access("byte write", addr);
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270 | 27c7ca7e | bellard | return;
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271 | 27c7ca7e | bellard | default:
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272 | 27c7ca7e | bellard | error_access("byte write", addr);
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273 | 27c7ca7e | bellard | assert(0);
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274 | 27c7ca7e | bellard | } |
275 | 27c7ca7e | bellard | } |
276 | 27c7ca7e | bellard | |
277 | 27c7ca7e | bellard | static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
278 | 27c7ca7e | bellard | uint32_t mem_value) |
279 | 27c7ca7e | bellard | { |
280 | 27c7ca7e | bellard | SH7750State *s = opaque; |
281 | 27c7ca7e | bellard | uint16_t temp; |
282 | 27c7ca7e | bellard | |
283 | 27c7ca7e | bellard | switch (addr) {
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284 | 27c7ca7e | bellard | /* SDRAM controller */
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285 | 27c7ca7e | bellard | case SH7750_BCR2_A7:
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286 | 27c7ca7e | bellard | case SH7750_BCR3_A7:
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287 | 27c7ca7e | bellard | case SH7750_RTCOR_A7:
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288 | 27c7ca7e | bellard | case SH7750_RTCNT_A7:
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289 | 27c7ca7e | bellard | case SH7750_RTCSR_A7:
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290 | 27c7ca7e | bellard | ignore_access("word write", addr);
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291 | 27c7ca7e | bellard | return;
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292 | 27c7ca7e | bellard | /* IO ports */
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293 | 27c7ca7e | bellard | case SH7750_PDTRA_A7:
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294 | 27c7ca7e | bellard | temp = porta_lines(s); |
295 | 27c7ca7e | bellard | s->pdtra = mem_value; |
296 | 27c7ca7e | bellard | porta_changed(s, temp); |
297 | 27c7ca7e | bellard | return;
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298 | 27c7ca7e | bellard | case SH7750_PDTRB_A7:
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299 | 27c7ca7e | bellard | temp = portb_lines(s); |
300 | 27c7ca7e | bellard | s->pdtrb = mem_value; |
301 | 27c7ca7e | bellard | portb_changed(s, temp); |
302 | 27c7ca7e | bellard | return;
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303 | 27c7ca7e | bellard | case SH7750_RFCR_A7:
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304 | 27c7ca7e | bellard | fprintf(stderr, "Write access to refresh count register\n");
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305 | 27c7ca7e | bellard | s->rfcr = mem_value; |
306 | 27c7ca7e | bellard | return;
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307 | 27c7ca7e | bellard | case SH7750_GPIOIC_A7:
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308 | 27c7ca7e | bellard | s->gpioic = mem_value; |
309 | 27c7ca7e | bellard | if (mem_value != 0) { |
310 | 27c7ca7e | bellard | fprintf(stderr, "I/O interrupts not implemented\n");
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311 | 27c7ca7e | bellard | assert(0);
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312 | 27c7ca7e | bellard | } |
313 | 27c7ca7e | bellard | return;
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314 | 3464c589 | ths | case 0x1fd00000: |
315 | 3464c589 | ths | s->icr = mem_value; |
316 | 3464c589 | ths | return;
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317 | 27c7ca7e | bellard | default:
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318 | 27c7ca7e | bellard | error_access("word write", addr);
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319 | 27c7ca7e | bellard | assert(0);
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320 | 27c7ca7e | bellard | } |
321 | 27c7ca7e | bellard | } |
322 | 27c7ca7e | bellard | |
323 | 27c7ca7e | bellard | static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
324 | 27c7ca7e | bellard | uint32_t mem_value) |
325 | 27c7ca7e | bellard | { |
326 | 27c7ca7e | bellard | SH7750State *s = opaque; |
327 | 27c7ca7e | bellard | uint16_t temp; |
328 | 27c7ca7e | bellard | |
329 | 27c7ca7e | bellard | switch (addr) {
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330 | 27c7ca7e | bellard | /* SDRAM controller */
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331 | 27c7ca7e | bellard | case SH7750_BCR1_A7:
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332 | 27c7ca7e | bellard | case SH7750_BCR4_A7:
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333 | 27c7ca7e | bellard | case SH7750_WCR1_A7:
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334 | 27c7ca7e | bellard | case SH7750_WCR2_A7:
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335 | 27c7ca7e | bellard | case SH7750_WCR3_A7:
|
336 | 27c7ca7e | bellard | case SH7750_MCR_A7:
|
337 | 27c7ca7e | bellard | ignore_access("long write", addr);
|
338 | 27c7ca7e | bellard | return;
|
339 | 27c7ca7e | bellard | /* IO ports */
|
340 | 27c7ca7e | bellard | case SH7750_PCTRA_A7:
|
341 | 27c7ca7e | bellard | temp = porta_lines(s); |
342 | 27c7ca7e | bellard | s->pctra = mem_value; |
343 | 27c7ca7e | bellard | s->portdira = portdir(mem_value); |
344 | 27c7ca7e | bellard | s->portpullupa = portpullup(mem_value); |
345 | 27c7ca7e | bellard | porta_changed(s, temp); |
346 | 27c7ca7e | bellard | return;
|
347 | 27c7ca7e | bellard | case SH7750_PCTRB_A7:
|
348 | 27c7ca7e | bellard | temp = portb_lines(s); |
349 | 27c7ca7e | bellard | s->pctrb = mem_value; |
350 | 27c7ca7e | bellard | s->portdirb = portdir(mem_value); |
351 | 27c7ca7e | bellard | s->portpullupb = portpullup(mem_value); |
352 | 27c7ca7e | bellard | portb_changed(s, temp); |
353 | 27c7ca7e | bellard | return;
|
354 | 27c7ca7e | bellard | case SH7750_MMUCR_A7:
|
355 | 27c7ca7e | bellard | s->cpu->mmucr = mem_value; |
356 | 27c7ca7e | bellard | return;
|
357 | 27c7ca7e | bellard | case SH7750_PTEH_A7:
|
358 | 27c7ca7e | bellard | s->cpu->pteh = mem_value; |
359 | 27c7ca7e | bellard | return;
|
360 | 27c7ca7e | bellard | case SH7750_PTEL_A7:
|
361 | 27c7ca7e | bellard | s->cpu->ptel = mem_value; |
362 | 27c7ca7e | bellard | return;
|
363 | 27c7ca7e | bellard | case SH7750_TTB_A7:
|
364 | 27c7ca7e | bellard | s->cpu->ttb = mem_value; |
365 | 27c7ca7e | bellard | return;
|
366 | 27c7ca7e | bellard | case SH7750_TEA_A7:
|
367 | 27c7ca7e | bellard | s->cpu->tea = mem_value; |
368 | 27c7ca7e | bellard | return;
|
369 | 27c7ca7e | bellard | case SH7750_TRA_A7:
|
370 | 27c7ca7e | bellard | s->cpu->tra = mem_value & 0x000007ff;
|
371 | 27c7ca7e | bellard | return;
|
372 | 27c7ca7e | bellard | case SH7750_EXPEVT_A7:
|
373 | 27c7ca7e | bellard | s->cpu->expevt = mem_value & 0x000007ff;
|
374 | 27c7ca7e | bellard | return;
|
375 | 27c7ca7e | bellard | case SH7750_INTEVT_A7:
|
376 | 27c7ca7e | bellard | s->cpu->intevt = mem_value & 0x000007ff;
|
377 | 27c7ca7e | bellard | return;
|
378 | 27c7ca7e | bellard | case SH7750_CCR_A7:
|
379 | 27c7ca7e | bellard | s->ccr = mem_value; |
380 | 27c7ca7e | bellard | return;
|
381 | 27c7ca7e | bellard | default:
|
382 | 27c7ca7e | bellard | error_access("long write", addr);
|
383 | 27c7ca7e | bellard | assert(0);
|
384 | 27c7ca7e | bellard | } |
385 | 27c7ca7e | bellard | } |
386 | 27c7ca7e | bellard | |
387 | 27c7ca7e | bellard | static CPUReadMemoryFunc *sh7750_mem_read[] = {
|
388 | 27c7ca7e | bellard | sh7750_mem_readb, |
389 | 27c7ca7e | bellard | sh7750_mem_readw, |
390 | 27c7ca7e | bellard | sh7750_mem_readl |
391 | 27c7ca7e | bellard | }; |
392 | 27c7ca7e | bellard | |
393 | 27c7ca7e | bellard | static CPUWriteMemoryFunc *sh7750_mem_write[] = {
|
394 | 27c7ca7e | bellard | sh7750_mem_writeb, |
395 | 27c7ca7e | bellard | sh7750_mem_writew, |
396 | 27c7ca7e | bellard | sh7750_mem_writel |
397 | 27c7ca7e | bellard | }; |
398 | 27c7ca7e | bellard | |
399 | 80f515e6 | balrog | /* sh775x interrupt controller tables for sh_intc.c
|
400 | 80f515e6 | balrog | * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
|
401 | 80f515e6 | balrog | */
|
402 | 80f515e6 | balrog | |
403 | 80f515e6 | balrog | enum {
|
404 | 80f515e6 | balrog | UNUSED = 0,
|
405 | 80f515e6 | balrog | |
406 | 80f515e6 | balrog | /* interrupt sources */
|
407 | 80f515e6 | balrog | IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
|
408 | 80f515e6 | balrog | HUDI, GPIOI, |
409 | 80f515e6 | balrog | DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, |
410 | 80f515e6 | balrog | DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, |
411 | 80f515e6 | balrog | DMAC_DMAE, |
412 | 80f515e6 | balrog | PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
413 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, |
414 | 80f515e6 | balrog | TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, |
415 | 80f515e6 | balrog | RTC_ATI, RTC_PRI, RTC_CUI, |
416 | 80f515e6 | balrog | SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, |
417 | 80f515e6 | balrog | SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, |
418 | 80f515e6 | balrog | WDT, |
419 | 80f515e6 | balrog | REF_RCMI, REF_ROVI, |
420 | 80f515e6 | balrog | |
421 | 80f515e6 | balrog | /* interrupt groups */
|
422 | 80f515e6 | balrog | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
423 | 80f515e6 | balrog | |
424 | 80f515e6 | balrog | NR_SOURCES, |
425 | 80f515e6 | balrog | }; |
426 | 80f515e6 | balrog | |
427 | 80f515e6 | balrog | static struct intc_vect vectors[] = { |
428 | 80f515e6 | balrog | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
429 | 80f515e6 | balrog | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
430 | 80f515e6 | balrog | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
431 | 80f515e6 | balrog | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
432 | 80f515e6 | balrog | INTC_VECT(RTC_CUI, 0x4c0),
|
433 | 80f515e6 | balrog | INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), |
434 | 80f515e6 | balrog | INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), |
435 | 80f515e6 | balrog | INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), |
436 | 80f515e6 | balrog | INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), |
437 | 80f515e6 | balrog | INTC_VECT(WDT, 0x560),
|
438 | 80f515e6 | balrog | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
439 | 80f515e6 | balrog | }; |
440 | 80f515e6 | balrog | |
441 | 80f515e6 | balrog | static struct intc_group groups[] = { |
442 | 80f515e6 | balrog | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
443 | 80f515e6 | balrog | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
444 | 80f515e6 | balrog | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
445 | 80f515e6 | balrog | INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), |
446 | 80f515e6 | balrog | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
447 | 80f515e6 | balrog | }; |
448 | 80f515e6 | balrog | |
449 | 80f515e6 | balrog | static struct intc_prio_reg prio_registers[] = { |
450 | 80f515e6 | balrog | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
451 | 80f515e6 | balrog | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
452 | 80f515e6 | balrog | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
453 | 80f515e6 | balrog | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
454 | 80f515e6 | balrog | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, |
455 | 80f515e6 | balrog | TMU4, TMU3, |
456 | 80f515e6 | balrog | PCIC1, PCIC0_PCISERR } }, |
457 | 80f515e6 | balrog | }; |
458 | 80f515e6 | balrog | |
459 | 80f515e6 | balrog | /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
460 | 80f515e6 | balrog | |
461 | 80f515e6 | balrog | static struct intc_vect vectors_dma4[] = { |
462 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
463 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
464 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
465 | 80f515e6 | balrog | }; |
466 | 80f515e6 | balrog | |
467 | 80f515e6 | balrog | static struct intc_group groups_dma4[] = { |
468 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
469 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMAE), |
470 | 80f515e6 | balrog | }; |
471 | 80f515e6 | balrog | |
472 | 80f515e6 | balrog | /* SH7750R and SH7751R both have 8-channel DMA controllers */
|
473 | 80f515e6 | balrog | |
474 | 80f515e6 | balrog | static struct intc_vect vectors_dma8[] = { |
475 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
476 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
477 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
478 | 80f515e6 | balrog | INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), |
479 | 80f515e6 | balrog | INTC_VECT(DMAC_DMAE, 0x6c0),
|
480 | 80f515e6 | balrog | }; |
481 | 80f515e6 | balrog | |
482 | 80f515e6 | balrog | static struct intc_group groups_dma8[] = { |
483 | 80f515e6 | balrog | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
484 | 80f515e6 | balrog | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
485 | 80f515e6 | balrog | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
486 | 80f515e6 | balrog | }; |
487 | 80f515e6 | balrog | |
488 | 80f515e6 | balrog | /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
|
489 | 80f515e6 | balrog | |
490 | 80f515e6 | balrog | static struct intc_vect vectors_tmu34[] = { |
491 | 80f515e6 | balrog | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
492 | 80f515e6 | balrog | }; |
493 | 80f515e6 | balrog | |
494 | 80f515e6 | balrog | static struct intc_mask_reg mask_registers[] = { |
495 | 80f515e6 | balrog | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
496 | 80f515e6 | balrog | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
497 | 80f515e6 | balrog | 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
498 | 80f515e6 | balrog | PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
499 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, |
500 | 80f515e6 | balrog | PCIC1_PCIDMA3, PCIC0_PCISERR } }, |
501 | 80f515e6 | balrog | }; |
502 | 80f515e6 | balrog | |
503 | 80f515e6 | balrog | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
|
504 | 80f515e6 | balrog | |
505 | 80f515e6 | balrog | static struct intc_vect vectors_irlm[] = { |
506 | 80f515e6 | balrog | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
507 | 80f515e6 | balrog | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
508 | 80f515e6 | balrog | }; |
509 | 80f515e6 | balrog | |
510 | 80f515e6 | balrog | /* SH7751 and SH7751R both have PCI */
|
511 | 80f515e6 | balrog | |
512 | 80f515e6 | balrog | static struct intc_vect vectors_pci[] = { |
513 | 80f515e6 | balrog | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
514 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
515 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
516 | 80f515e6 | balrog | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
517 | 80f515e6 | balrog | }; |
518 | 80f515e6 | balrog | |
519 | 80f515e6 | balrog | static struct intc_group groups_pci[] = { |
520 | 80f515e6 | balrog | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
521 | 80f515e6 | balrog | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
522 | 80f515e6 | balrog | }; |
523 | 80f515e6 | balrog | |
524 | 80f515e6 | balrog | #define SH_CPU_SH7750 (1 << 0) |
525 | 80f515e6 | balrog | #define SH_CPU_SH7750S (1 << 1) |
526 | 80f515e6 | balrog | #define SH_CPU_SH7750R (1 << 2) |
527 | 80f515e6 | balrog | #define SH_CPU_SH7751 (1 << 3) |
528 | 80f515e6 | balrog | #define SH_CPU_SH7751R (1 << 4) |
529 | 80f515e6 | balrog | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
|
530 | 80f515e6 | balrog | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
|
531 | 80f515e6 | balrog | |
532 | 27c7ca7e | bellard | SH7750State *sh7750_init(CPUSH4State * cpu) |
533 | 27c7ca7e | bellard | { |
534 | 27c7ca7e | bellard | SH7750State *s; |
535 | 27c7ca7e | bellard | int sh7750_io_memory;
|
536 | 80f515e6 | balrog | int cpu_model = SH_CPU_SH7751R; /* for now */ |
537 | 27c7ca7e | bellard | |
538 | 27c7ca7e | bellard | s = qemu_mallocz(sizeof(SH7750State));
|
539 | 27c7ca7e | bellard | s->cpu = cpu; |
540 | 27c7ca7e | bellard | s->periph_freq = 60000000; /* 60MHz */ |
541 | 27c7ca7e | bellard | sh7750_io_memory = cpu_register_io_memory(0,
|
542 | 27c7ca7e | bellard | sh7750_mem_read, |
543 | 27c7ca7e | bellard | sh7750_mem_write, s); |
544 | 27c7ca7e | bellard | cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory); |
545 | 2f062c72 | ths | |
546 | 80f515e6 | balrog | sh_intc_init(&s->intc, NR_SOURCES, |
547 | 80f515e6 | balrog | _INTC_ARRAY(mask_registers), |
548 | 80f515e6 | balrog | _INTC_ARRAY(prio_registers)); |
549 | 80f515e6 | balrog | |
550 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
551 | 80f515e6 | balrog | _INTC_ARRAY(vectors), |
552 | 80f515e6 | balrog | _INTC_ARRAY(groups)); |
553 | 80f515e6 | balrog | |
554 | e96e2044 | ths | cpu->intc_handle = &s->intc; |
555 | e96e2044 | ths | |
556 | 2f062c72 | ths | sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]); |
557 | 2f062c72 | ths | sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
|
558 | 2f062c72 | ths | s->periph_freq, serial_hds[1]);
|
559 | cd1a3f68 | ths | |
560 | cd1a3f68 | ths | tmu012_init(0x1fd80000,
|
561 | cd1a3f68 | ths | TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
562 | cd1a3f68 | ths | s->periph_freq); |
563 | 80f515e6 | balrog | |
564 | 80f515e6 | balrog | |
565 | 80f515e6 | balrog | if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
|
566 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
567 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma4), |
568 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma4)); |
569 | 80f515e6 | balrog | } |
570 | 80f515e6 | balrog | |
571 | 80f515e6 | balrog | if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
|
572 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
573 | 80f515e6 | balrog | _INTC_ARRAY(vectors_dma8), |
574 | 80f515e6 | balrog | _INTC_ARRAY(groups_dma8)); |
575 | 80f515e6 | balrog | } |
576 | 80f515e6 | balrog | |
577 | 80f515e6 | balrog | if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
|
578 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
579 | 80f515e6 | balrog | _INTC_ARRAY(vectors_tmu34), |
580 | f26ae302 | bellard | NULL, 0); |
581 | 80f515e6 | balrog | tmu012_init(0x1e100000, 0, s->periph_freq); |
582 | 80f515e6 | balrog | } |
583 | 80f515e6 | balrog | |
584 | 80f515e6 | balrog | if (cpu_model & (SH_CPU_SH7751_ALL)) {
|
585 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
586 | 80f515e6 | balrog | _INTC_ARRAY(vectors_pci), |
587 | 80f515e6 | balrog | _INTC_ARRAY(groups_pci)); |
588 | 80f515e6 | balrog | } |
589 | 80f515e6 | balrog | |
590 | 80f515e6 | balrog | if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
|
591 | 80f515e6 | balrog | sh_intc_register_sources(&s->intc, |
592 | 80f515e6 | balrog | _INTC_ARRAY(vectors_irlm), |
593 | f26ae302 | bellard | NULL, 0); |
594 | 80f515e6 | balrog | } |
595 | 80f515e6 | balrog | |
596 | 27c7ca7e | bellard | return s;
|
597 | 27c7ca7e | bellard | } |