Archipelago » qemu

/*

 *  PowerPC emulation cpu definitions for qemu.

 * 

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#if !defined (__CPU_PPC_H__)

#define __CPU_PPC_H__

#include "config.h"

#include <inttypes.h>

#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)

/* When using 64 bits temporary registers,

 * we can use 64 bits GPR with no extra cost

 */

#define TARGET_PPCSPE

#endif

#if defined (TARGET_PPC64)

typedef uint64_t ppc_gpr_t;

#define TARGET_LONG_BITS 64

#define TARGET_GPR_BITS  64

#define REGX "%016" PRIx64

#elif defined(TARGET_PPCSPE)

/* e500v2 have 36 bits physical address space */

#define TARGET_PHYS_ADDR_BITS 64

/* GPR are 64 bits: used by vector extension */

typedef uint64_t ppc_gpr_t;

#define TARGET_LONG_BITS 32

#define TARGET_GPR_BITS  64

#define REGX "%016" PRIx64

#else

typedef uint32_t ppc_gpr_t;

#define TARGET_LONG_BITS 32

#define TARGET_GPR_BITS  32

#define REGX "%08" PRIx32

#endif

#include "cpu-defs.h"

#define ADDRX TARGET_FMT_lx

#define PADDRX TARGET_FMT_plx

#include <setjmp.h>

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if defined (TARGET_PPC64)

#define ELF_MACHINE     EM_PPC64

#else

#define ELF_MACHINE     EM_PPC

#endif

/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC

 *                              have different cache line sizes

 */

#define ICACHE_LINE_SIZE 32

#define DCACHE_LINE_SIZE 32

/* XXX: put this in a common place */

#define likely(x)   __builtin_expect(!!(x), 1)

#define unlikely(x) __builtin_expect(!!(x), 0)

/*****************************************************************************/

/* PVR definitions for most known PowerPC */

enum {

    /* PowerPC 401 cores */

    CPU_PPC_401A1     = 0x00210000,

    CPU_PPC_401B2     = 0x00220000,

    CPU_PPC_401C2     = 0x00230000,

    CPU_PPC_401D2     = 0x00240000,

    CPU_PPC_401E2     = 0x00250000,

    CPU_PPC_401F2     = 0x00260000,

    CPU_PPC_401G2     = 0x00270000,

#define CPU_PPC_401 CPU_PPC_401G2

    CPU_PPC_IOP480    = 0x40100000, /* 401B2 ? */

    CPU_PPC_COBRA     = 0x10100000, /* IBM Processor for Network Resources */

    /* PowerPC 403 cores */

    CPU_PPC_403GA     = 0x00200011,

    CPU_PPC_403GB     = 0x00200100,

    CPU_PPC_403GC     = 0x00200200,

    CPU_PPC_403GCX    = 0x00201400,

#define CPU_PPC_403 CPU_PPC_403GCX

    /* PowerPC 405 cores */

    CPU_PPC_405CR     = 0x40110145,

#define CPU_PPC_405GP CPU_PPC_405CR

    CPU_PPC_405EP     = 0x51210950,

    CPU_PPC_405GPR    = 0x50910951,

    CPU_PPC_405D2     = 0x20010000,

    CPU_PPC_405D4     = 0x41810000,

#define CPU_PPC_405 CPU_PPC_405D4

    CPU_PPC_NPE405H   = 0x414100C0,

    CPU_PPC_NPE405H2  = 0x41410140,

    CPU_PPC_NPE405L   = 0x416100C0,

    /* XXX: missing 405LP, LC77700 */

    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */

#if 0

    CPU_PPC_STB01000  = xxx,

#endif

#if 0

    CPU_PPC_STB01010  = xxx,

#endif

#if 0

    CPU_PPC_STB0210   = xxx,

#endif

    CPU_PPC_STB03     = 0x40310000,

#if 0

    CPU_PPC_STB043    = xxx,

#endif

#if 0

    CPU_PPC_STB045    = xxx,

#endif

    CPU_PPC_STB25     = 0x51510950,

#if 0

    CPU_PPC_STB130    = xxx,

#endif

    /* Xilinx cores */

    CPU_PPC_X2VP4     = 0x20010820,

#define CPU_PPC_X2VP7 CPU_PPC_X2VP4

    CPU_PPC_X2VP20    = 0x20010860,

#define CPU_PPC_X2VP50 CPU_PPC_X2VP20

    /* PowerPC 440 cores */

    CPU_PPC_440EP     = 0x422218D3,

#define CPU_PPC_440GR CPU_PPC_440EP

    CPU_PPC_440GP     = 0x40120481,

    CPU_PPC_440GX     = 0x51B21850,

    CPU_PPC_440GXc    = 0x51B21892,

    CPU_PPC_440GXf    = 0x51B21894,

    CPU_PPC_440SP     = 0x53221850,

    CPU_PPC_440SP2    = 0x53221891,

    CPU_PPC_440SPE    = 0x53421890,

    /* XXX: missing 440GRX */

    /* PowerPC 460 cores - TODO */

    /* PowerPC MPC 5xx cores */

    CPU_PPC_5xx       = 0x00020020,

    /* PowerPC MPC 8xx cores (aka PowerQUICC) */

    CPU_PPC_8xx       = 0x00500000,

    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */

    CPU_PPC_82xx_HIP3 = 0x00810101,

    CPU_PPC_82xx_HIP4 = 0x80811014,

    CPU_PPC_827x      = 0x80822013,

    /* eCores */

    CPU_PPC_e200      = 0x81120000,

    CPU_PPC_e500v110  = 0x80200010,

    CPU_PPC_e500v120  = 0x80200020,

    CPU_PPC_e500v210  = 0x80210010,

    CPU_PPC_e500v220  = 0x80210020,

#define CPU_PPC_e500 CPU_PPC_e500v220

    CPU_PPC_e600      = 0x80040010,

    /* PowerPC 6xx cores */

    CPU_PPC_601       = 0x00010001,

    CPU_PPC_602       = 0x00050100,

    CPU_PPC_603       = 0x00030100,

    CPU_PPC_603E      = 0x00060101,

    CPU_PPC_603P      = 0x00070000,

    CPU_PPC_603E7v    = 0x00070100,

    CPU_PPC_603E7v2   = 0x00070201,

    CPU_PPC_603E7     = 0x00070200,

    CPU_PPC_603R      = 0x00071201,

    CPU_PPC_G2        = 0x00810011,

    CPU_PPC_G2H4      = 0x80811010,

    CPU_PPC_G2gp      = 0x80821010,

    CPU_PPC_G2ls      = 0x90810010,

    CPU_PPC_G2LE      = 0x80820010,

    CPU_PPC_G2LEgp    = 0x80822010,

    CPU_PPC_G2LEls    = 0xA0822010,

    CPU_PPC_604       = 0x00040000,

    CPU_PPC_604E      = 0x00090100, /* Also 2110 & 2120 */

    CPU_PPC_604R      = 0x000a0101,

    /* PowerPC 74x/75x cores (aka G3) */

    CPU_PPC_74x       = 0x00080000,

    CPU_PPC_740E      = 0x00080100,

    CPU_PPC_750E      = 0x00080200,

    CPU_PPC_755_10    = 0x00083100,

    CPU_PPC_755_11    = 0x00083101,

    CPU_PPC_755_20    = 0x00083200,

    CPU_PPC_755D      = 0x00083202,

    CPU_PPC_755E      = 0x00083203,

#define CPU_PPC_755 CPU_PPC_755E

    CPU_PPC_74xP      = 0x10080000,

    CPU_PPC_750CXE21  = 0x00082201,

    CPU_PPC_750CXE22  = 0x00082212,

    CPU_PPC_750CXE23  = 0x00082203,

    CPU_PPC_750CXE24  = 0x00082214,

    CPU_PPC_750CXE24b = 0x00083214,

    CPU_PPC_750CXE31  = 0x00083211,

    CPU_PPC_750CXE31b = 0x00083311,

#define CPU_PPC_750CXE CPU_PPC_750CXE31b

    CPU_PPC_750CXR    = 0x00083410,

    CPU_PPC_750FX10   = 0x70000100,

    CPU_PPC_750FX20   = 0x70000200,

    CPU_PPC_750FX21   = 0x70000201,

    CPU_PPC_750FX22   = 0x70000202,

    CPU_PPC_750FX23   = 0x70000203,

#define CPU_PPC_750FX CPU_PPC_750FX23

    CPU_PPC_750FL     = 0x700A0203,

    CPU_PPC_750GX10   = 0x70020100,

    CPU_PPC_750GX11   = 0x70020101,

    CPU_PPC_750GX12   = 0x70020102,

#define CPU_PPC_750GX CPU_PPC_750GX12

    CPU_PPC_750GL     = 0x70020102,

    CPU_PPC_750L30    = 0x00088300,

    CPU_PPC_750L32    = 0x00088302,

    CPU_PPC_750CL     = 0x00087200,

    /* PowerPC 74xx cores (aka G4) */

    CPU_PPC_7400      = 0x000C0100,

    CPU_PPC_7410C     = 0x800C1102,

    CPU_PPC_7410D     = 0x800C1103,

    CPU_PPC_7410E     = 0x800C1104,

    CPU_PPC_7441      = 0x80000210,

    CPU_PPC_7445      = 0x80010100,

    CPU_PPC_7447      = 0x80020100,

    CPU_PPC_7447A     = 0x80030101,

    CPU_PPC_7448      = 0x80040100,

    CPU_PPC_7450      = 0x80000200,

    CPU_PPC_7450b     = 0x80000201,

    CPU_PPC_7451      = 0x80000203,

    CPU_PPC_7451G     = 0x80000210,

    CPU_PPC_7455      = 0x80010201,

    CPU_PPC_7455F     = 0x80010303,

    CPU_PPC_7455G     = 0x80010304,

    CPU_PPC_7457      = 0x80020101,

    CPU_PPC_7457C     = 0x80020102,

    CPU_PPC_7457A     = 0x80030000,

    /* 64 bits PowerPC */

    CPU_PPC_620       = 0x00140000,

    CPU_PPC_630       = 0x00400000,

    CPU_PPC_631       = 0x00410000,

    CPU_PPC_POWER4    = 0x00350000,

    CPU_PPC_POWER4P   = 0x00380000,

    CPU_PPC_POWER5    = 0x003A0000,

    CPU_PPC_POWER5P   = 0x003B0000,

    CPU_PPC_970       = 0x00390000,

    CPU_PPC_970FX10   = 0x00391100,

    CPU_PPC_970FX20   = 0x003C0200,

    CPU_PPC_970FX21   = 0x003C0201,

    CPU_PPC_970FX30   = 0x003C0300,

    CPU_PPC_970FX31   = 0x003C0301,

#define CPU_PPC_970FX CPU_PPC_970FX31

    CPU_PPC_970MP10   = 0x00440100,

    CPU_PPC_970MP11   = 0x00440101,

#define CPU_PPC_970MP CPU_PPC_970MP11

    CPU_PPC_CELL10    = 0x00700100,

    CPU_PPC_CELL20    = 0x00700400,

    CPU_PPC_CELL30    = 0x00700500,

    CPU_PPC_CELL31    = 0x00700501,

#define CPU_PPC_CELL32 CPU_PPC_CELL31

#define CPU_PPC_CELL CPU_PPC_CELL32

    CPU_PPC_RS64      = 0x00330000,

    CPU_PPC_RS64II    = 0x00340000,

    CPU_PPC_RS64III   = 0x00360000,

    CPU_PPC_RS64IV    = 0x00370000,

    /* Original POWER */

    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,

     * POWER2 (RIOS2) & RSC2 (P2SC) here

     */

#if 0

    CPU_POWER         = xxx,

#endif

#if 0

    CPU_POWER2        = xxx,

#endif

};

/* System version register (used on MPC 8xxx) */

enum {

    PPC_SVR_8540      = 0x80300000,

    PPC_SVR_8541E     = 0x807A0010,

    PPC_SVR_8543v10   = 0x80320010,

    PPC_SVR_8543v11   = 0x80320011,

    PPC_SVR_8543v20   = 0x80320020,

    PPC_SVR_8543Ev10  = 0x803A0010,

    PPC_SVR_8543Ev11  = 0x803A0011,

    PPC_SVR_8543Ev20  = 0x803A0020,

    PPC_SVR_8545      = 0x80310220,

    PPC_SVR_8545E     = 0x80390220,

    PPC_SVR_8547E     = 0x80390120,

    PPC_SCR_8548v10   = 0x80310010,

    PPC_SCR_8548v11   = 0x80310011,

    PPC_SCR_8548v20   = 0x80310020,

    PPC_SVR_8548Ev10  = 0x80390010,

    PPC_SVR_8548Ev11  = 0x80390011,

    PPC_SVR_8548Ev20  = 0x80390020,

    PPC_SVR_8555E     = 0x80790010,

    PPC_SVR_8560v10   = 0x80700010,

    PPC_SVR_8560v20   = 0x80700020,

};

/*****************************************************************************/

/* Instruction types */

enum {

    PPC_NONE        = 0x00000000,

    /* integer operations instructions             */

    /* flow control instructions                   */

    /* virtual memory instructions                 */

    /* ld/st with reservation instructions         */

    /* cache control instructions                  */

    /* spr/msr access instructions                 */

    PPC_INSNS_BASE  = 0x0000000000000001ULL,

#define PPC_INTEGER PPC_INSNS_BASE

#define PPC_FLOW    PPC_INSNS_BASE

#define PPC_MEM     PPC_INSNS_BASE

#define PPC_RES     PPC_INSNS_BASE

#define PPC_CACHE   PPC_INSNS_BASE

#define PPC_MISC    PPC_INSNS_BASE

    /* floating point operations instructions      */

    PPC_FLOAT       = 0x0000000000000002ULL,

    /* more floating point operations instructions */

    PPC_FLOAT_EXT   = 0x0000000000000004ULL,

    /* external control instructions               */

    PPC_EXTERN      = 0x0000000000000008ULL,

    /* segment register access instructions        */

    PPC_SEGMENT     = 0x0000000000000010ULL,

    /* Optional cache control instructions         */

    PPC_CACHE_OPT   = 0x0000000000000020ULL,

    /* Optional floating point op instructions     */

    PPC_FLOAT_OPT   = 0x0000000000000040ULL,

    /* Optional memory control instructions        */

    PPC_MEM_TLBIA   = 0x0000000000000080ULL,

    PPC_MEM_TLBIE   = 0x0000000000000100ULL,

    PPC_MEM_TLBSYNC = 0x0000000000000200ULL,

    /* eieio & sync                                */

    PPC_MEM_SYNC    = 0x0000000000000400ULL,

    /* PowerPC 6xx TLB management instructions     */

    PPC_6xx_TLB     = 0x0000000000000800ULL,

    /* Altivec support                             */

    PPC_ALTIVEC     = 0x0000000000001000ULL,

    /* Time base support                           */

    PPC_TB          = 0x0000000000002000ULL,

    /* Embedded PowerPC dedicated instructions     */

    PPC_EMB_COMMON  = 0x0000000000004000ULL,

    /* PowerPC 40x exception model                 */

    PPC_40x_EXCP    = 0x0000000000008000ULL,

    /* PowerPC 40x specific instructions           */

    PPC_40x_SPEC    = 0x0000000000010000ULL,

    /* PowerPC 405 Mac instructions                */

    PPC_405_MAC     = 0x0000000000020000ULL,

    /* PowerPC 440 specific instructions           */

    PPC_440_SPEC    = 0x0000000000040000ULL,

    /* Specific extensions */

    /* Power-to-PowerPC bridge (601)               */

    PPC_POWER_BR    = 0x0000000000080000ULL,

    /* PowerPC 602 specific */

    PPC_602_SPEC    = 0x0000000000100000ULL,

    /* Deprecated instructions                     */

    /* Original POWER instruction set              */

    PPC_POWER       = 0x0000000000200000ULL,

    /* POWER2 instruction set extension            */

    PPC_POWER2      = 0x0000000000400000ULL,

    /* Power RTC support */

    PPC_POWER_RTC   = 0x0000000000800000ULL,

    /* 64 bits PowerPC instructions                */

    /* 64 bits PowerPC instruction set             */

    PPC_64B         = 0x0000000001000000ULL,

    /* 64 bits hypervisor extensions               */

    PPC_64H         = 0x0000000002000000ULL,

    /* 64 bits PowerPC "bridge" features           */

    PPC_64_BRIDGE   = 0x0000000004000000ULL,

    /* BookE (embedded) PowerPC specification      */

    PPC_BOOKE       = 0x0000000008000000ULL,

    /* eieio */

    PPC_MEM_EIEIO   = 0x0000000010000000ULL,

    /* e500 vector instructions */

    PPC_E500_VECTOR = 0x0000000020000000ULL,

    /* PowerPC 4xx dedicated instructions     */

    PPC_4xx_COMMON  = 0x0000000040000000ULL,

    /* PowerPC 2.03 specification extensions */

    PPC_203         = 0x0000000080000000ULL,

    /* PowerPC 2.03 SPE extension */

    PPC_SPE         = 0x0000000100000000ULL,

    /* PowerPC 2.03 SPE floating-point extension */

    PPC_SPEFPU      = 0x0000000200000000ULL,

    /* SLB management */

    PPC_SLBI        = 0x0000000400000000ULL,

};

/* CPU run-time flags (MMU and exception model) */

enum {

    /* MMU model */

    PPC_FLAGS_MMU_MASK     = 0x0000000F,

    /* Standard 32 bits PowerPC MMU */

    PPC_FLAGS_MMU_32B      = 0x00000000,

    /* Standard 64 bits PowerPC MMU */

    PPC_FLAGS_MMU_64B      = 0x00000001,

    /* PowerPC 601 MMU */

    PPC_FLAGS_MMU_601      = 0x00000002,

    /* PowerPC 6xx MMU with software TLB */

    PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,

    /* PowerPC 4xx MMU with software TLB */

    PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,

    /* PowerPC 403 MMU */

    PPC_FLAGS_MMU_403      = 0x00000005,

    /* Freescale e500 MMU model */

    PPC_FLAGS_MMU_e500     = 0x00000006,

    /* BookE MMU model */

    PPC_FLAGS_MMU_BOOKE    = 0x00000007,

    /* Exception model */

    PPC_FLAGS_EXCP_MASK    = 0x000000F0,

    /* Standard PowerPC exception model */

    PPC_FLAGS_EXCP_STD     = 0x00000000,

    /* PowerPC 40x exception model */

    PPC_FLAGS_EXCP_40x     = 0x00000010,

    /* PowerPC 601 exception model */

    PPC_FLAGS_EXCP_601     = 0x00000020,

    /* PowerPC 602 exception model */

    PPC_FLAGS_EXCP_602     = 0x00000030,

    /* PowerPC 603 exception model */

    PPC_FLAGS_EXCP_603     = 0x00000040,

    /* PowerPC 604 exception model */

    PPC_FLAGS_EXCP_604     = 0x00000050,

    /* PowerPC 7x0 exception model */

    PPC_FLAGS_EXCP_7x0     = 0x00000060,

    /* PowerPC 7x5 exception model */

    PPC_FLAGS_EXCP_7x5     = 0x00000070,

    /* PowerPC 74xx exception model */

    PPC_FLAGS_EXCP_74xx    = 0x00000080,

    /* PowerPC 970 exception model */

    PPC_FLAGS_EXCP_970     = 0x00000090,

    /* BookE exception model */

    PPC_FLAGS_EXCP_BOOKE   = 0x000000A0,

};

#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)

#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)

/*****************************************************************************/

/* Supported instruction set definitions */

/* This generates an empty opcode table... */

#define PPC_INSNS_TODO (PPC_NONE)

#define PPC_FLAGS_TODO (0x00000000)

/* PowerPC 40x instruction set */

#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)

/* PowerPC 401 */

#define PPC_INSNS_401 (PPC_INSNS_TODO)

#define PPC_FLAGS_401 (PPC_FLAGS_TODO)

/* PowerPC 403 */

#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \

                       PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP |        \

                       PPC_40x_SPEC)

#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)

/* PowerPC 405 */

#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \

                       PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB |               \

                       PPC_4xx_COMMON | PPC_40x_SPEC |  PPC_40x_EXCP |        \

                       PPC_405_MAC)

#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)

/* PowerPC 440 */

#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE |            \

                       PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)

#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)

/* Generic BookE PowerPC */

#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |          \

                         PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)

#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)

/* e500 core */

#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |           \

                        PPC_CACHE_OPT | PPC_E500_VECTOR)

#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)

/* Non-embedded PowerPC */

#define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \

                            PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)

/* PowerPC 601 */

#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)

#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)

/* PowerPC 602 */

#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \

                       PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)

#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)

/* PowerPC 603 */

#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \

                       PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)

#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)

/* PowerPC G2 */

#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \

                      PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)

#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)

/* PowerPC 604 */

#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \

                       PPC_MEM_TLBSYNC | PPC_TB)

#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)

/* PowerPC 740/750 (aka G3) */

#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \

                       PPC_MEM_TLBSYNC | PPC_TB)

#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)

/* PowerPC 745/755 */

#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \

                       PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)

#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)

/* PowerPC 74xx (aka G4) */

#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \

                        PPC_MEM_TLBSYNC | PPC_TB)

#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)

/* PowerPC 970 (aka G5) */

#define PPC_INSNS_970  (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT |    \

                        PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB |              \

                        PPC_64B | PPC_64_BRIDGE | PPC_SLBI)

#define PPC_FLAGS_970  (PPC_FLAGS_MMU_64B | PPC_FLAGS_EXCP_970)

/* Default PowerPC will be 604/970 */

#define PPC_INSNS_PPC32 PPC_INSNS_604

#define PPC_FLAGS_PPC32 PPC_FLAGS_604

#define PPC_INSNS_PPC64 PPC_INSNS_970

#define PPC_FLAGS_PPC64 PPC_FLAGS_970

#define PPC_INSNS_DEFAULT PPC_INSNS_604

#define PPC_FLAGS_DEFAULT PPC_FLAGS_604

typedef struct ppc_def_t ppc_def_t;

/*****************************************************************************/

/* Types used to describe some PowerPC registers */

typedef struct CPUPPCState CPUPPCState;

typedef struct opc_handler_t opc_handler_t;

typedef struct ppc_tb_t ppc_tb_t;

typedef struct ppc_spr_t ppc_spr_t;

typedef struct ppc_dcr_t ppc_dcr_t;

typedef struct ppc_avr_t ppc_avr_t;

typedef union ppc_tlb_t ppc_tlb_t;

/* SPR access micro-ops generations callbacks */

struct ppc_spr_t {

    void (*uea_read)(void *opaque, int spr_num);

    void (*uea_write)(void *opaque, int spr_num);

#if !defined(CONFIG_USER_ONLY)

    void (*oea_read)(void *opaque, int spr_num);

    void (*oea_write)(void *opaque, int spr_num);

#endif

    const unsigned char *name;

};

/* Altivec registers (128 bits) */

struct ppc_avr_t {

    uint32_t u[4];

};

/* Software TLB cache */

typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;

struct ppc6xx_tlb_t {

    target_ulong pte0;

    target_ulong pte1;

    target_ulong EPN;

};

typedef struct ppcemb_tlb_t ppcemb_tlb_t;

struct ppcemb_tlb_t {

    target_ulong RPN;

    target_ulong EPN;

    target_ulong PID;

    int size;

    int prot;

    int attr; /* Storage attributes */

};

union ppc_tlb_t {

    ppc6xx_tlb_t tlb6;

    ppcemb_tlb_t tlbe;

};

/*****************************************************************************/

/* Machine state register bits definition                                    */

#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */

#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */

#define MSR_HV   60 /* hypervisor state                               hflags */

#define MSR_CM   31 /* Computation mode for BookE                     hflags */

#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */

#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */

#define MSR_VR   25 /* altivec available                              hflags */

#define MSR_SPE  25 /* SPE enable for BookE                           hflags */

#define MSR_AP   23 /* Access privilege state on 602                  hflags */

#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */

#define MSR_KEY  19 /* key bit on 603e                                       */

#define MSR_POW  18 /* Power management                                      */

#define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */

#define MSR_TGPR 17 /* TGPR usage on 602/603                                 */

#define MSR_TLB  17 /* TLB update on ?                                       */

#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */

#define MSR_ILE  16 /* Interrupt little-endian mode                          */

#define MSR_EE   15 /* External interrupt enable                             */

#define MSR_PR   14 /* Problem state                                  hflags */

#define MSR_FP   13 /* Floating point available                       hflags */

#define MSR_ME   12 /* Machine check interrupt enable                        */

#define MSR_FE0  11 /* Floating point exception mode 0                hflags */

#define MSR_SE   10 /* Single-step trace enable                       hflags */

#define MSR_DWE  10 /* Debug wait enable on 405                              */

#define MSR_UBLE 10 /* User BTB lock enable on e500                          */

#define MSR_BE   9  /* Branch trace enable                            hflags */

#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */

#define MSR_FE1  8  /* Floating point exception mode 1                hflags */

#define MSR_AL   7  /* AL bit on POWER                                       */

#define MSR_IP   6  /* Interrupt prefix                                      */

#define MSR_IR   5  /* Instruction relocate                                  */

#define MSR_IS   5  /* Instruction address space on embedded PowerPC         */

#define MSR_DR   4  /* Data relocate                                         */

#define MSR_DS   4  /* Data address space on embedded PowerPC                */

#define MSR_PE   3  /* Protection enable on 403                              */

#define MSR_EP   3  /* Exception prefix on 601                               */

#define MSR_PX   2  /* Protection exclusive on 403                           */

#define MSR_PMM  2  /* Performance monitor mark on POWER                     */

#define MSR_RI   1  /* Recoverable interrupt                                 */

#define MSR_LE   0  /* Little-endian mode                             hflags */

#define msr_sf   env->msr[MSR_SF]

#define msr_isf  env->msr[MSR_ISF]

#define msr_hv   env->msr[MSR_HV]

#define msr_cm   env->msr[MSR_CM]

#define msr_icm  env->msr[MSR_ICM]

#define msr_ucle env->msr[MSR_UCLE]

#define msr_vr   env->msr[MSR_VR]

#define msr_spe  env->msr[MSR_SPE]

#define msr_ap   env->msr[MSR_AP]

#define msr_sa   env->msr[MSR_SA]

#define msr_key  env->msr[MSR_KEY]

#define msr_pow  env->msr[MSR_POW]

#define msr_we   env->msr[MSR_WE]

#define msr_tgpr env->msr[MSR_TGPR]

#define msr_tlb  env->msr[MSR_TLB]

#define msr_ce   env->msr[MSR_CE]

#define msr_ile  env->msr[MSR_ILE]

#define msr_ee   env->msr[MSR_EE]

#define msr_pr   env->msr[MSR_PR]

#define msr_fp   env->msr[MSR_FP]

#define msr_me   env->msr[MSR_ME]

#define msr_fe0  env->msr[MSR_FE0]

#define msr_se   env->msr[MSR_SE]

#define msr_dwe  env->msr[MSR_DWE]

#define msr_uble env->msr[MSR_UBLE]

#define msr_be   env->msr[MSR_BE]

#define msr_de   env->msr[MSR_DE]

#define msr_fe1  env->msr[MSR_FE1]

#define msr_al   env->msr[MSR_AL]

#define msr_ip   env->msr[MSR_IP]

#define msr_ir   env->msr[MSR_IR]

#define msr_is   env->msr[MSR_IS]

#define msr_dr   env->msr[MSR_DR]

#define msr_ds   env->msr[MSR_DS]

#define msr_pe   env->msr[MSR_PE]

#define msr_ep   env->msr[MSR_EP]

#define msr_px   env->msr[MSR_PX]

#define msr_pmm  env->msr[MSR_PMM]

#define msr_ri   env->msr[MSR_RI]

#define msr_le   env->msr[MSR_LE]

/*****************************************************************************/

/* The whole PowerPC CPU context */

struct CPUPPCState {

    /* First are the most commonly used resources

     * during translated code execution

     */

#if TARGET_GPR_BITS > HOST_LONG_BITS

    /* temporary fixed-point registers

     * used to emulate 64 bits target on 32 bits hosts

     */ 

    target_ulong t0, t1, t2;

#endif

    ppc_avr_t t0_avr, t1_avr, t2_avr;

    /* general purpose registers */

    ppc_gpr_t gpr[32];

    /* LR */

    target_ulong lr;

    /* CTR */

    target_ulong ctr;

    /* condition register */

    uint8_t crf[8];

    /* XER */

    /* XXX: We use only 5 fields, but we want to keep the structure aligned */

    uint8_t xer[8];

    /* Reservation address */

    target_ulong reserve;

    /* Those ones are used in supervisor mode only */

    /* machine state register */

    uint8_t msr[64];

    /* temporary general purpose registers */

    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */

    /* Floating point execution context */

    /* temporary float registers */

    float64 ft0;

    float64 ft1;

    float64 ft2;

    float_status fp_status;

    /* floating point registers */

    float64 fpr[32];

    /* floating point status and control register */

    uint8_t fpscr[8];

    CPU_COMMON

    int halted; /* TRUE if the CPU is in suspend state */

    int access_type; /* when a memory exception occurs, the access

                        type is stored here */

    /* MMU context */

    /* Address space register */

    target_ulong asr;

    /* segment registers */

    target_ulong sdr1;

    target_ulong sr[16];

    /* BATs */

    int nb_BATs;

    target_ulong DBAT[2][8];

    target_ulong IBAT[2][8];

    /* Other registers */

    /* Special purpose registers */

    target_ulong spr[1024];

    /* Altivec registers */

    ppc_avr_t avr[32];

    uint32_t vscr;

    /* SPE registers */

    ppc_gpr_t spe_acc;

    float_status spe_status;

    uint32_t spe_fscr;

    /* Internal devices resources */

    /* Time base and decrementer */

    ppc_tb_t *tb_env;

    /* Device control registers */

    ppc_dcr_t *dcr_env;

    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */

    int nb_tlb;      /* Total number of TLB                                  */

    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */

    int nb_ways;     /* Number of ways in the TLB set                        */

    int last_way;    /* Last used way used to allocate TLB in a LRU way      */

    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */

    int nb_pids;     /* Number of available PID registers                    */

    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */

    /* Callbacks for specific checks on some implementations */

    int (*tlb_check_more)(CPUPPCState *env, ppc_tlb_t *tlb, int *prot,

                          target_ulong vaddr, int rw, int acc_type,

                          int is_user);

    /* 403 dedicated access protection registers */

    target_ulong pb[4];

    /* Those resources are used during exception processing */

    /* CPU model definition */

    uint64_t msr_mask;

    uint32_t flags;

    int exception_index;

    int error_code;

    int interrupt_request;

    uint32_t pending_interrupts;

#if !defined(CONFIG_USER_ONLY)

    /* This is the IRQ controller, which is implementation dependant

     * and only relevant when emulating a complete machine.

     */

    uint32_t irq_input_state;

    void **irq_inputs;

#endif

    /* Those resources are used only during code translation */

    /* Next instruction pointer */

    target_ulong nip;

    /* SPR translation callbacks */

    ppc_spr_t spr_cb[1024];

    /* opcode handlers */

    opc_handler_t *opcodes[0x40];

    /* Those resources are used only in Qemu core */

    jmp_buf jmp_env;

    int user_mode_only; /* user mode only simulation */

    uint32_t hflags;

    /* Power management */

    int power_mode;

    /* temporary hack to handle OSI calls (only used if non NULL) */

    int (*osi_call)(struct CPUPPCState *env);

};

/* Context used internally during MMU translations */

typedef struct mmu_ctx_t mmu_ctx_t;

struct mmu_ctx_t {

    target_phys_addr_t raddr;      /* Real address              */

    int prot;                      /* Protection bits           */

    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */

    target_ulong ptem;             /* Virtual segment ID | API  */

    int key;                       /* Access key                */

};

/*****************************************************************************/

CPUPPCState *cpu_ppc_init(void);

int cpu_ppc_exec(CPUPPCState *s);

void cpu_ppc_close(CPUPPCState *s);

/* you can call this signal handler from your SIGBUS and SIGSEGV

   signal handlers to inform the virtual CPU of exceptions. non zero

   is returned if the signal was handled by the virtual CPU.  */

int cpu_ppc_signal_handler(int host_signum, void *pinfo, 

                           void *puc);

void do_interrupt (CPUPPCState *env);

void ppc_hw_interrupt (CPUPPCState *env);

void cpu_loop_exit(void);

void dump_stack (CPUPPCState *env);

#if !defined(CONFIG_USER_ONLY)

target_ulong do_load_ibatu (CPUPPCState *env, int nr);

target_ulong do_load_ibatl (CPUPPCState *env, int nr);

void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);

void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);

target_ulong do_load_dbatu (CPUPPCState *env, int nr);

target_ulong do_load_dbatl (CPUPPCState *env, int nr);

void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);

void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);

target_ulong do_load_sdr1 (CPUPPCState *env);

void do_store_sdr1 (CPUPPCState *env, target_ulong value);

#if defined(TARGET_PPC64)

target_ulong ppc_load_asr (CPUPPCState *env);

void ppc_store_asr (CPUPPCState *env, target_ulong value);

#endif

target_ulong do_load_sr (CPUPPCState *env, int srnum);

void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);

#endif

uint32_t ppc_load_xer (CPUPPCState *env);

void ppc_store_xer (CPUPPCState *env, uint32_t value);

target_ulong do_load_msr (CPUPPCState *env);

void do_store_msr (CPUPPCState *env, target_ulong value);

void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);

void do_compute_hflags (CPUPPCState *env);

int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);

int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);

void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);

/* Time-base and decrementer management */

#ifndef NO_CPU_IO_DEFS

uint32_t cpu_ppc_load_tbl (CPUPPCState *env);

uint32_t cpu_ppc_load_tbu (CPUPPCState *env);

void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);

void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);

uint32_t cpu_ppc_load_decr (CPUPPCState *env);

void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);

uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);

uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);

#if !defined(CONFIG_USER_ONLY)

void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);

void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);

target_ulong load_40x_pit (CPUPPCState *env);

void store_40x_pit (CPUPPCState *env, target_ulong val);

void store_booke_tcr (CPUPPCState *env, target_ulong val);

void store_booke_tsr (CPUPPCState *env, target_ulong val);

#endif

#endif

/* Device control registers */

int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);

int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);

#define TARGET_PAGE_BITS 12

#include "cpu-all.h"

/*****************************************************************************/

/* Registers definitions */

#define ugpr(n) (env->gpr[n])