root / hw / pflash_cfi02.c @ e96efcfc
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/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement boot blocs with reduced size
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "vl.h" |
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//#define PFLASH_DEBUG
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, args...) \
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do { \
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printf("PFLASH: " fmt , ##args); \ |
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} while (0) |
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#else
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#define DPRINTF(fmt, args...) do { } while (0) |
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#endif
|
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|
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struct pflash_t {
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BlockDriverState *bs; |
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target_ulong base; |
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target_ulong sector_len; |
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target_ulong total_len; |
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int width;
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int wcycle; /* if 0, the flash is read normally */ |
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int bypass;
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int ro;
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uint8_t cmd; |
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uint8_t status; |
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uint16_t ident[4];
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52];
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QEMUTimer *timer; |
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ram_addr_t off; |
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int fl_mem;
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void *storage;
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}; |
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|
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static void pflash_timer (void *opaque) |
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{ |
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pflash_t *pfl = opaque; |
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|
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
|
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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cpu_register_physical_memory(pfl->base, pfl->total_len, |
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pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
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pfl->wcycle = 0;
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} |
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pfl->cmd = 0;
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} |
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|
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static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) |
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{ |
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target_ulong boff; |
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uint32_t ret; |
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uint8_t *p; |
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|
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DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset); |
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ret = -1;
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offset -= pfl->base; |
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boff = offset & 0xFF;
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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case 0x80: |
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/* We accept reads during second unlock sequence... */
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case 0x00: |
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flash_read:
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/* Flash area read */
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p = pfl->storage; |
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switch (width) {
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case 1: |
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ret = p[offset]; |
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2: |
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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#endif
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4: |
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16; |
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ret |= p[offset + 2] << 8; |
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ret |= p[offset + 3];
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#else
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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ret |= p[offset + 2] << 16; |
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ret |= p[offset + 3] << 24; |
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#endif
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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} |
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break;
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case 0x90: |
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/* flash ID read */
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switch (boff) {
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case 0x00: |
149 |
case 0x01: |
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ret = pfl->ident[boff & 0x01];
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break;
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case 0x02: |
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ret = 0x00; /* Pretend all sectors are unprotected */ |
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break;
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case 0x0E: |
156 |
case 0x0F: |
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if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
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goto flash_read;
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ret = pfl->ident[2 + (boff & 0x01)]; |
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break;
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default:
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goto flash_read;
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} |
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DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret); |
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break;
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case 0xA0: |
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case 0x10: |
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case 0x30: |
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/* Status register read */
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ret = pfl->status; |
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DPRINTF("%s: status %x\n", __func__, ret);
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/* Toggle bit 6 */
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pfl->status ^= 0x40;
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break;
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case 0x98: |
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/* CFI query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff]; |
181 |
break;
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} |
183 |
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return ret;
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} |
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset, |
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int size)
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{ |
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int offset_end;
|
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if (pfl->bs) {
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offset_end = offset + size; |
194 |
/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9; |
197 |
bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset); |
199 |
} |
200 |
} |
201 |
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static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, |
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int width)
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{ |
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target_ulong boff; |
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uint8_t *p; |
207 |
uint8_t cmd; |
208 |
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/* WARNING: when the memory area is in ROMD mode, the offset is a
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ram offset, not a physical address */
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if (pfl->wcycle == 0) |
212 |
offset -= (target_ulong)(long)pfl->storage;
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else
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offset -= pfl->base; |
215 |
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cmd = value; |
217 |
DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__, |
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offset, value, width); |
219 |
if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
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DPRINTF("%s: flash reset asked (%02x %02x)\n",
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__func__, pfl->cmd, cmd); |
222 |
goto reset_flash;
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} |
224 |
/* Set the device in I/O access mode */
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cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
230 |
boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0: |
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/* We're in read mode */
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check_unlock0:
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if (boff == 0x55 && cmd == 0x98) { |
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enter_CFI_mode:
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/* Enter CFI query mode */
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pfl->wcycle = 7;
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pfl->cmd = 0x98;
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return;
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} |
242 |
if (boff != 0x555 || cmd != 0xAA) { |
243 |
DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n", |
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__func__, boff, cmd, 0x555);
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goto reset_flash;
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} |
247 |
DPRINTF("%s: unlock sequence started\n", __func__);
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break;
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case 1: |
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/* We started an unlock sequence */
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check_unlock1:
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if (boff != 0x2AA || cmd != 0x55) { |
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DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__, |
254 |
boff, cmd); |
255 |
goto reset_flash;
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} |
257 |
DPRINTF("%s: unlock sequence done\n", __func__);
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break;
|
259 |
case 2: |
260 |
/* We finished an unlock sequence */
|
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if (!pfl->bypass && boff != 0x555) { |
262 |
DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__, |
263 |
boff, cmd); |
264 |
goto reset_flash;
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} |
266 |
switch (cmd) {
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267 |
case 0x20: |
268 |
pfl->bypass = 1;
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goto do_bypass;
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270 |
case 0x80: |
271 |
case 0x90: |
272 |
case 0xA0: |
273 |
pfl->cmd = cmd; |
274 |
DPRINTF("%s: starting command %02x\n", __func__, cmd);
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275 |
break;
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276 |
default:
|
277 |
DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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goto reset_flash;
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} |
280 |
break;
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281 |
case 3: |
282 |
switch (pfl->cmd) {
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283 |
case 0x80: |
284 |
/* We need another unlock sequence */
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285 |
goto check_unlock0;
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286 |
case 0xA0: |
287 |
DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n", |
288 |
__func__, offset, value, width); |
289 |
p = pfl->storage; |
290 |
switch (width) {
|
291 |
case 1: |
292 |
p[offset] &= value; |
293 |
pflash_update(pfl, offset, 1);
|
294 |
break;
|
295 |
case 2: |
296 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
297 |
p[offset] &= value >> 8;
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298 |
p[offset + 1] &= value;
|
299 |
#else
|
300 |
p[offset] &= value; |
301 |
p[offset + 1] &= value >> 8; |
302 |
#endif
|
303 |
pflash_update(pfl, offset, 2);
|
304 |
break;
|
305 |
case 4: |
306 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
307 |
p[offset] &= value >> 24;
|
308 |
p[offset + 1] &= value >> 16; |
309 |
p[offset + 2] &= value >> 8; |
310 |
p[offset + 3] &= value;
|
311 |
#else
|
312 |
p[offset] &= value; |
313 |
p[offset + 1] &= value >> 8; |
314 |
p[offset + 2] &= value >> 16; |
315 |
p[offset + 3] &= value >> 24; |
316 |
#endif
|
317 |
pflash_update(pfl, offset, 4);
|
318 |
break;
|
319 |
} |
320 |
pfl->status = 0x00 | ~(value & 0x80); |
321 |
/* Let's pretend write is immediate */
|
322 |
if (pfl->bypass)
|
323 |
goto do_bypass;
|
324 |
goto reset_flash;
|
325 |
case 0x90: |
326 |
if (pfl->bypass && cmd == 0x00) { |
327 |
/* Unlock bypass reset */
|
328 |
goto reset_flash;
|
329 |
} |
330 |
/* We can enter CFI query mode from autoselect mode */
|
331 |
if (boff == 0x55 && cmd == 0x98) |
332 |
goto enter_CFI_mode;
|
333 |
/* No break here */
|
334 |
default:
|
335 |
DPRINTF("%s: invalid write for command %02x\n",
|
336 |
__func__, pfl->cmd); |
337 |
goto reset_flash;
|
338 |
} |
339 |
case 4: |
340 |
switch (pfl->cmd) {
|
341 |
case 0xA0: |
342 |
/* Ignore writes while flash data write is occuring */
|
343 |
/* As we suppose write is immediate, this should never happen */
|
344 |
return;
|
345 |
case 0x80: |
346 |
goto check_unlock1;
|
347 |
default:
|
348 |
/* Should never happen */
|
349 |
DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
350 |
__func__, pfl->cmd); |
351 |
goto reset_flash;
|
352 |
} |
353 |
break;
|
354 |
case 5: |
355 |
switch (cmd) {
|
356 |
case 0x10: |
357 |
if (boff != 0x555) { |
358 |
DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n", |
359 |
__func__, offset); |
360 |
goto reset_flash;
|
361 |
} |
362 |
/* Chip erase */
|
363 |
DPRINTF("%s: start chip erase\n", __func__);
|
364 |
memset(pfl->storage, 0xFF, pfl->total_len);
|
365 |
pfl->status = 0x00;
|
366 |
pflash_update(pfl, 0, pfl->total_len);
|
367 |
/* Let's wait 5 seconds before chip erase is done */
|
368 |
qemu_mod_timer(pfl->timer, |
369 |
qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
|
370 |
break;
|
371 |
case 0x30: |
372 |
/* Sector erase */
|
373 |
p = pfl->storage; |
374 |
offset &= ~(pfl->sector_len - 1);
|
375 |
DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__, |
376 |
offset); |
377 |
memset(p + offset, 0xFF, pfl->sector_len);
|
378 |
pflash_update(pfl, offset, pfl->sector_len); |
379 |
pfl->status = 0x00;
|
380 |
/* Let's wait 1/2 second before sector erase is done */
|
381 |
qemu_mod_timer(pfl->timer, |
382 |
qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
|
383 |
break;
|
384 |
default:
|
385 |
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
386 |
goto reset_flash;
|
387 |
} |
388 |
pfl->cmd = cmd; |
389 |
break;
|
390 |
case 6: |
391 |
switch (pfl->cmd) {
|
392 |
case 0x10: |
393 |
/* Ignore writes during chip erase */
|
394 |
return;
|
395 |
case 0x30: |
396 |
/* Ignore writes during sector erase */
|
397 |
return;
|
398 |
default:
|
399 |
/* Should never happen */
|
400 |
DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
401 |
__func__, pfl->cmd); |
402 |
goto reset_flash;
|
403 |
} |
404 |
break;
|
405 |
case 7: /* Special value for CFI queries */ |
406 |
DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
407 |
goto reset_flash;
|
408 |
default:
|
409 |
/* Should never happen */
|
410 |
DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
411 |
goto reset_flash;
|
412 |
} |
413 |
pfl->wcycle++; |
414 |
|
415 |
return;
|
416 |
|
417 |
/* Reset flash */
|
418 |
reset_flash:
|
419 |
if (pfl->wcycle != 0) { |
420 |
cpu_register_physical_memory(pfl->base, pfl->total_len, |
421 |
pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
422 |
} |
423 |
pfl->bypass = 0;
|
424 |
pfl->wcycle = 0;
|
425 |
pfl->cmd = 0;
|
426 |
return;
|
427 |
|
428 |
do_bypass:
|
429 |
pfl->wcycle = 2;
|
430 |
pfl->cmd = 0;
|
431 |
return;
|
432 |
} |
433 |
|
434 |
|
435 |
static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
436 |
{ |
437 |
return pflash_read(opaque, addr, 1); |
438 |
} |
439 |
|
440 |
static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
441 |
{ |
442 |
pflash_t *pfl = opaque; |
443 |
|
444 |
return pflash_read(pfl, addr, 2); |
445 |
} |
446 |
|
447 |
static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
448 |
{ |
449 |
pflash_t *pfl = opaque; |
450 |
|
451 |
return pflash_read(pfl, addr, 4); |
452 |
} |
453 |
|
454 |
static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
455 |
uint32_t value) |
456 |
{ |
457 |
pflash_write(opaque, addr, value, 1);
|
458 |
} |
459 |
|
460 |
static void pflash_writew (void *opaque, target_phys_addr_t addr, |
461 |
uint32_t value) |
462 |
{ |
463 |
pflash_t *pfl = opaque; |
464 |
|
465 |
pflash_write(pfl, addr, value, 2);
|
466 |
} |
467 |
|
468 |
static void pflash_writel (void *opaque, target_phys_addr_t addr, |
469 |
uint32_t value) |
470 |
{ |
471 |
pflash_t *pfl = opaque; |
472 |
|
473 |
pflash_write(pfl, addr, value, 4);
|
474 |
} |
475 |
|
476 |
static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
477 |
&pflash_writeb, |
478 |
&pflash_writew, |
479 |
&pflash_writel, |
480 |
}; |
481 |
|
482 |
static CPUReadMemoryFunc *pflash_read_ops[] = {
|
483 |
&pflash_readb, |
484 |
&pflash_readw, |
485 |
&pflash_readl, |
486 |
}; |
487 |
|
488 |
/* Count trailing zeroes of a 32 bits quantity */
|
489 |
static int ctz32 (uint32_t n) |
490 |
{ |
491 |
int ret;
|
492 |
|
493 |
ret = 0;
|
494 |
if (!(n & 0xFFFF)) { |
495 |
ret += 16;
|
496 |
n = n >> 16;
|
497 |
} |
498 |
if (!(n & 0xFF)) { |
499 |
ret += 8;
|
500 |
n = n >> 8;
|
501 |
} |
502 |
if (!(n & 0xF)) { |
503 |
ret += 4;
|
504 |
n = n >> 4;
|
505 |
} |
506 |
if (!(n & 0x3)) { |
507 |
ret += 2;
|
508 |
n = n >> 2;
|
509 |
} |
510 |
if (!(n & 0x1)) { |
511 |
ret++; |
512 |
n = n >> 1;
|
513 |
} |
514 |
#if 0 /* This is not necessary as n is never 0 */
|
515 |
if (!n)
|
516 |
ret++;
|
517 |
#endif
|
518 |
|
519 |
return ret;
|
520 |
} |
521 |
|
522 |
pflash_t *pflash_register (target_ulong base, ram_addr_t off, |
523 |
BlockDriverState *bs, |
524 |
target_ulong sector_len, int nb_blocs, int width, |
525 |
uint16_t id0, uint16_t id1, |
526 |
uint16_t id2, uint16_t id3) |
527 |
{ |
528 |
pflash_t *pfl; |
529 |
target_long total_len; |
530 |
|
531 |
total_len = sector_len * nb_blocs; |
532 |
/* XXX: to be fixed */
|
533 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
534 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) |
535 |
return NULL; |
536 |
pfl = qemu_mallocz(sizeof(pflash_t));
|
537 |
if (pfl == NULL) |
538 |
return NULL; |
539 |
pfl->storage = phys_ram_base + off; |
540 |
pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, pfl);
|
541 |
pfl->off = off; |
542 |
cpu_register_physical_memory(base, total_len, |
543 |
off | pfl->fl_mem | IO_MEM_ROMD); |
544 |
pfl->bs = bs; |
545 |
if (pfl->bs) {
|
546 |
/* read the initial flash content */
|
547 |
bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
548 |
} |
549 |
#if 0 /* XXX: there should be a bit to set up read-only,
|
550 |
* the same way the hardware does (with WP pin).
|
551 |
*/
|
552 |
pfl->ro = 1;
|
553 |
#else
|
554 |
pfl->ro = 0;
|
555 |
#endif
|
556 |
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
557 |
pfl->base = base; |
558 |
pfl->sector_len = sector_len; |
559 |
pfl->total_len = total_len; |
560 |
pfl->width = width; |
561 |
pfl->wcycle = 0;
|
562 |
pfl->cmd = 0;
|
563 |
pfl->status = 0;
|
564 |
pfl->ident[0] = id0;
|
565 |
pfl->ident[1] = id1;
|
566 |
pfl->ident[2] = id2;
|
567 |
pfl->ident[3] = id3;
|
568 |
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
569 |
pfl->cfi_len = 0x52;
|
570 |
/* Standard "QRY" string */
|
571 |
pfl->cfi_table[0x10] = 'Q'; |
572 |
pfl->cfi_table[0x11] = 'R'; |
573 |
pfl->cfi_table[0x12] = 'Y'; |
574 |
/* Command set (AMD/Fujitsu) */
|
575 |
pfl->cfi_table[0x13] = 0x02; |
576 |
pfl->cfi_table[0x14] = 0x00; |
577 |
/* Primary extended table address (none) */
|
578 |
pfl->cfi_table[0x15] = 0x00; |
579 |
pfl->cfi_table[0x16] = 0x00; |
580 |
/* Alternate command set (none) */
|
581 |
pfl->cfi_table[0x17] = 0x00; |
582 |
pfl->cfi_table[0x18] = 0x00; |
583 |
/* Alternate extended table (none) */
|
584 |
pfl->cfi_table[0x19] = 0x00; |
585 |
pfl->cfi_table[0x1A] = 0x00; |
586 |
/* Vcc min */
|
587 |
pfl->cfi_table[0x1B] = 0x27; |
588 |
/* Vcc max */
|
589 |
pfl->cfi_table[0x1C] = 0x36; |
590 |
/* Vpp min (no Vpp pin) */
|
591 |
pfl->cfi_table[0x1D] = 0x00; |
592 |
/* Vpp max (no Vpp pin) */
|
593 |
pfl->cfi_table[0x1E] = 0x00; |
594 |
/* Reserved */
|
595 |
pfl->cfi_table[0x1F] = 0x07; |
596 |
/* Timeout for min size buffer write (16 ?s) */
|
597 |
pfl->cfi_table[0x20] = 0x04; |
598 |
/* Typical timeout for block erase (512 ms) */
|
599 |
pfl->cfi_table[0x21] = 0x09; |
600 |
/* Typical timeout for full chip erase (4096 ms) */
|
601 |
pfl->cfi_table[0x22] = 0x0C; |
602 |
/* Reserved */
|
603 |
pfl->cfi_table[0x23] = 0x01; |
604 |
/* Max timeout for buffer write */
|
605 |
pfl->cfi_table[0x24] = 0x04; |
606 |
/* Max timeout for block erase */
|
607 |
pfl->cfi_table[0x25] = 0x0A; |
608 |
/* Max timeout for chip erase */
|
609 |
pfl->cfi_table[0x26] = 0x0D; |
610 |
/* Device size */
|
611 |
pfl->cfi_table[0x27] = ctz32(total_len) + 1; |
612 |
/* Flash device interface (8 & 16 bits) */
|
613 |
pfl->cfi_table[0x28] = 0x02; |
614 |
pfl->cfi_table[0x29] = 0x00; |
615 |
/* Max number of bytes in multi-bytes write */
|
616 |
pfl->cfi_table[0x2A] = 0x05; |
617 |
pfl->cfi_table[0x2B] = 0x00; |
618 |
/* Number of erase block regions (uniform) */
|
619 |
pfl->cfi_table[0x2C] = 0x01; |
620 |
/* Erase block region 1 */
|
621 |
pfl->cfi_table[0x2D] = nb_blocs - 1; |
622 |
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
623 |
pfl->cfi_table[0x2F] = sector_len >> 8; |
624 |
pfl->cfi_table[0x30] = sector_len >> 16; |
625 |
|
626 |
return pfl;
|
627 |
} |