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/*
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* QEMU generic PowerPC hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "m48t59.h" |
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//#define PPC_DEBUG_IRQ
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extern FILE *logfile;
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extern int loglevel; |
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void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
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{
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if (level) {
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env->pending_interrupts |= 1 << n_IRQ;
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} else {
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env->pending_interrupts &= ~(1 << n_IRQ);
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if (env->pending_interrupts == 0) |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
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env, n_IRQ, level, env->pending_interrupts, env->interrupt_request); |
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#endif
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} |
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/* PowerPC 6xx / 7xx internal IRQ controller */
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static void ppc6xx_set_irq (void *opaque, int pin, int level) |
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{
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CPUState *env = opaque; |
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int cur_level;
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|
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
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switch (pin) {
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case PPC6xx_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the external IRQ state to %d\n", __func__, level);
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
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break;
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case PPC6xx_INPUT_SMI:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the SMI IRQ state to %d\n", __func__, level);
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
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break;
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case PPC6xx_INPUT_MCP:
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/* Negative edge sensitive */
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/* XXX: TODO: actual reaction may depends on HID0 status
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* 603/604/740/750: check HID0[EMCP]
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*/
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if (cur_level == 1 && level == 0) { |
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: raise machine check state\n", __func__);
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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} |
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break;
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case PPC6xx_INPUT_CKSTP_IN:
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/* Level sensitive - active low */
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/* XXX: TODO: relay the signal to CKSTP_OUT pin */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: stop the CPU\n", __func__);
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: restart the CPU\n", __func__);
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#endif
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env->halted = 0;
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} |
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break;
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case PPC6xx_INPUT_HRESET:
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/* Level sensitive - active low */
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if (level) {
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#if 0 // XXX: TOFIX
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: reset the CPU\n", __func__);
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#endif
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cpu_reset(env); |
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#endif
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} |
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break;
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case PPC6xx_INPUT_SRESET:
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the RESET IRQ state to %d\n", __func__, level);
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: unknown IRQ pin %d\n", __func__, pin);
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#endif
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return;
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} |
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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} |
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} |
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void ppc6xx_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6); |
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} |
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/* PowerPC 405 internal IRQ controller */
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static void ppc405_set_irq (void *opaque, int pin, int level) |
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{
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CPUState *env = opaque; |
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int cur_level;
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
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switch (pin) {
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case PPC405_INPUT_RESET_SYS:
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/* XXX: TODO: reset all peripherals */
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/* No break here */
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case PPC405_INPUT_RESET_CHIP:
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/* XXX: TODO: reset on-chip peripherals */
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/* No break here */
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case PPC405_INPUT_RESET_CORE:
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/* XXX: TODO: update DBSR[MRR] */
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if (level) {
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#if 0 // XXX: TOFIX
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: reset the CPU\n", __func__);
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#endif
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cpu_reset(env); |
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#endif
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} |
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break;
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case PPC405_INPUT_CINT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the critical IRQ state to %d\n", __func__, level);
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#endif
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/* XXX: TOFIX */
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
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break;
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case PPC405_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the external IRQ state to %d\n", __func__, level);
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
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break;
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case PPC405_INPUT_HALT:
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/* Level sensitive - active low */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: stop the CPU\n", __func__);
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: restart the CPU\n", __func__);
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#endif
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env->halted = 0;
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} |
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break;
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case PPC405_INPUT_DEBUG:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: set the external IRQ state to %d\n", __func__, level);
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#endif
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ppc_set_irq(env, EXCP_40x_DEBUG, level); |
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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printf("%s: unknown IRQ pin %d\n", __func__, pin);
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#endif
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return;
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} |
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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} |
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} |
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void ppc405_irq_init (CPUState *env)
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{
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printf("%s\n", __func__);
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7); |
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} |
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/*****************************************************************************/
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/* PowerPC time base and decrementer emulation */
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//#define DEBUG_TB
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struct ppc_tb_t {
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/* Time base management */
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int64_t tb_offset; /* Compensation */
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uint32_t tb_freq; /* TB frequency */
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/* Decrementer management */
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uint64_t decr_next; /* Tick for next decr interrupt */
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struct QEMUTimer *decr_timer;
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void *opaque;
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}; |
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static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) |
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{
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/* TB time in tb periods */
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return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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tb_env->tb_freq, ticks_per_sec); |
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} |
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uint32_t cpu_ppc_load_tbl (CPUState *env) |
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{
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t tb; |
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tb = cpu_ppc_get_tb(tb_env); |
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#ifdef DEBUG_TB
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{
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static int last_time; |
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int now;
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now = time(NULL);
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if (last_time != now) {
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last_time = now; |
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printf("%s: tb=0x%016lx %d %08lx\n",
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__func__, tb, now, tb_env->tb_offset); |
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} |
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} |
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#endif
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return tb & 0xFFFFFFFF; |
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} |
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uint32_t cpu_ppc_load_tbu (CPUState *env) |
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{
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t tb; |
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tb = cpu_ppc_get_tb(tb_env); |
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx\n", __func__, tb);
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#endif
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return tb >> 32; |
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} |
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static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) |
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{
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tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
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- qemu_get_clock(vm_clock); |
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
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#endif
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} |
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void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
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{
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ppc_tb_t *tb_env = env->tb_env; |
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cpu_ppc_store_tb(tb_env, |
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((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
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} |
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void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
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{
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ppc_tb_t *tb_env = env->tb_env; |
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cpu_ppc_store_tb(tb_env, |
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((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
|
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} |
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|
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uint32_t cpu_ppc_load_decr (CPUState *env) |
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{
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ppc_tb_t *tb_env = env->tb_env; |
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uint32_t decr; |
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int64_t diff; |
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|
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diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
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if (diff >= 0) |
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decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
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else
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decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); |
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#if defined(DEBUG_TB)
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printf("%s: 0x%08x\n", __func__, decr);
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#endif
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return decr;
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} |
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|
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/* When decrementer expires,
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* all we need to do is generate or queue a CPU exception
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*/
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static inline void cpu_ppc_decr_excp (CPUState *env) |
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{
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/* Raise it */
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#ifdef DEBUG_TB
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printf("raise decrementer exception\n");
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
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} |
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|
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static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
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uint32_t value, int is_excp)
|
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{
|
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t now, next; |
| 340 |
|
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#ifdef DEBUG_TB
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printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
|
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#endif
|
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now = qemu_get_clock(vm_clock); |
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next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); |
| 346 |
if (is_excp)
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next += tb_env->decr_next - now; |
| 348 |
if (next == now)
|
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next++; |
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tb_env->decr_next = next; |
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/* Adjust timer */
|
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qemu_mod_timer(tb_env->decr_timer, next); |
| 353 |
/* If we set a negative value and the decrementer was positive,
|
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* raise an exception.
|
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*/
|
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if ((value & 0x80000000) && !(decr & 0x80000000)) |
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cpu_ppc_decr_excp(env); |
| 358 |
} |
| 359 |
|
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void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
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{
|
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_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
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} |
| 364 |
|
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static void cpu_ppc_decr_cb (void *opaque) |
| 366 |
{
|
| 367 |
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
| 368 |
} |
| 369 |
|
| 370 |
/* Set up (once) timebase frequency (in Hz) */
|
| 371 |
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
| 372 |
{
|
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ppc_tb_t *tb_env; |
| 374 |
|
| 375 |
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
| 376 |
if (tb_env == NULL) |
| 377 |
return NULL; |
| 378 |
env->tb_env = tb_env; |
| 379 |
if (tb_env->tb_freq == 0 || 1) { |
| 380 |
tb_env->tb_freq = freq; |
| 381 |
/* Create new timer */
|
| 382 |
tb_env->decr_timer = |
| 383 |
qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
| 384 |
/* There is a bug in Linux 2.4 kernels:
|
| 385 |
* if a decrementer exception is pending when it enables msr_ee,
|
| 386 |
* it's not ready to handle it...
|
| 387 |
*/
|
| 388 |
_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
| 389 |
} |
| 390 |
|
| 391 |
return tb_env;
|
| 392 |
} |
| 393 |
|
| 394 |
/* Specific helpers for POWER & PowerPC 601 RTC */
|
| 395 |
ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env) |
| 396 |
{
|
| 397 |
return cpu_ppc_tb_init(env, 7812500); |
| 398 |
} |
| 399 |
|
| 400 |
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
| 401 |
__attribute__ (( alias ("cpu_ppc_store_tbu") ));
|
| 402 |
|
| 403 |
uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
| 404 |
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
|
| 405 |
|
| 406 |
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
| 407 |
{
|
| 408 |
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
| 409 |
} |
| 410 |
|
| 411 |
uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
| 412 |
{
|
| 413 |
return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
| 414 |
} |
| 415 |
|
| 416 |
/*****************************************************************************/
|
| 417 |
/* Embedded PowerPC timers */
|
| 418 |
|
| 419 |
/* PIT, FIT & WDT */
|
| 420 |
typedef struct ppcemb_timer_t ppcemb_timer_t; |
| 421 |
struct ppcemb_timer_t {
|
| 422 |
uint64_t pit_reload; /* PIT auto-reload value */
|
| 423 |
uint64_t fit_next; /* Tick for next FIT interrupt */
|
| 424 |
struct QEMUTimer *fit_timer;
|
| 425 |
uint64_t wdt_next; /* Tick for next WDT interrupt */
|
| 426 |
struct QEMUTimer *wdt_timer;
|
| 427 |
}; |
| 428 |
|
| 429 |
/* Fixed interval timer */
|
| 430 |
static void cpu_4xx_fit_cb (void *opaque) |
| 431 |
{
|
| 432 |
CPUState *env; |
| 433 |
ppc_tb_t *tb_env; |
| 434 |
ppcemb_timer_t *ppcemb_timer; |
| 435 |
uint64_t now, next; |
| 436 |
|
| 437 |
env = opaque; |
| 438 |
tb_env = env->tb_env; |
| 439 |
ppcemb_timer = tb_env->opaque; |
| 440 |
now = qemu_get_clock(vm_clock); |
| 441 |
switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
| 442 |
case 0: |
| 443 |
next = 1 << 9; |
| 444 |
break;
|
| 445 |
case 1: |
| 446 |
next = 1 << 13; |
| 447 |
break;
|
| 448 |
case 2: |
| 449 |
next = 1 << 17; |
| 450 |
break;
|
| 451 |
case 3: |
| 452 |
next = 1 << 21; |
| 453 |
break;
|
| 454 |
default:
|
| 455 |
/* Cannot occur, but makes gcc happy */
|
| 456 |
return;
|
| 457 |
} |
| 458 |
next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
| 459 |
if (next == now)
|
| 460 |
next++; |
| 461 |
qemu_mod_timer(ppcemb_timer->fit_timer, next); |
| 462 |
tb_env->decr_next = next; |
| 463 |
env->spr[SPR_40x_TSR] |= 1 << 26; |
| 464 |
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
| 465 |
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
| 466 |
if (loglevel) {
|
| 467 |
fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
| 468 |
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
| 469 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 470 |
} |
| 471 |
} |
| 472 |
|
| 473 |
/* Programmable interval timer */
|
| 474 |
static void cpu_4xx_pit_cb (void *opaque) |
| 475 |
{
|
| 476 |
CPUState *env; |
| 477 |
ppc_tb_t *tb_env; |
| 478 |
ppcemb_timer_t *ppcemb_timer; |
| 479 |
uint64_t now, next; |
| 480 |
|
| 481 |
env = opaque; |
| 482 |
tb_env = env->tb_env; |
| 483 |
ppcemb_timer = tb_env->opaque; |
| 484 |
now = qemu_get_clock(vm_clock); |
| 485 |
if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) { |
| 486 |
/* Auto reload */
|
| 487 |
next = now + muldiv64(ppcemb_timer->pit_reload, |
| 488 |
ticks_per_sec, tb_env->tb_freq); |
| 489 |
if (next == now)
|
| 490 |
next++; |
| 491 |
qemu_mod_timer(tb_env->decr_timer, next); |
| 492 |
tb_env->decr_next = next; |
| 493 |
} |
| 494 |
env->spr[SPR_40x_TSR] |= 1 << 27; |
| 495 |
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
| 496 |
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
| 497 |
if (loglevel) {
|
| 498 |
fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
| 499 |
"%016" PRIx64 "\n", __func__, |
| 500 |
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
| 501 |
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
| 502 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
| 503 |
ppcemb_timer->pit_reload); |
| 504 |
} |
| 505 |
} |
| 506 |
|
| 507 |
/* Watchdog timer */
|
| 508 |
static void cpu_4xx_wdt_cb (void *opaque) |
| 509 |
{
|
| 510 |
CPUState *env; |
| 511 |
ppc_tb_t *tb_env; |
| 512 |
ppcemb_timer_t *ppcemb_timer; |
| 513 |
uint64_t now, next; |
| 514 |
|
| 515 |
env = opaque; |
| 516 |
tb_env = env->tb_env; |
| 517 |
ppcemb_timer = tb_env->opaque; |
| 518 |
now = qemu_get_clock(vm_clock); |
| 519 |
switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
| 520 |
case 0: |
| 521 |
next = 1 << 17; |
| 522 |
break;
|
| 523 |
case 1: |
| 524 |
next = 1 << 21; |
| 525 |
break;
|
| 526 |
case 2: |
| 527 |
next = 1 << 25; |
| 528 |
break;
|
| 529 |
case 3: |
| 530 |
next = 1 << 29; |
| 531 |
break;
|
| 532 |
default:
|
| 533 |
/* Cannot occur, but makes gcc happy */
|
| 534 |
return;
|
| 535 |
} |
| 536 |
next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
| 537 |
if (next == now)
|
| 538 |
next++; |
| 539 |
if (loglevel) {
|
| 540 |
fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
| 541 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 542 |
} |
| 543 |
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
| 544 |
case 0x0: |
| 545 |
case 0x1: |
| 546 |
qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
| 547 |
ppcemb_timer->wdt_next = next; |
| 548 |
env->spr[SPR_40x_TSR] |= 1 << 31; |
| 549 |
break;
|
| 550 |
case 0x2: |
| 551 |
qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
| 552 |
ppcemb_timer->wdt_next = next; |
| 553 |
env->spr[SPR_40x_TSR] |= 1 << 30; |
| 554 |
if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
| 555 |
ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
| 556 |
break;
|
| 557 |
case 0x3: |
| 558 |
env->spr[SPR_40x_TSR] &= ~0x30000000;
|
| 559 |
env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
| 560 |
switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
| 561 |
case 0x0: |
| 562 |
/* No reset */
|
| 563 |
break;
|
| 564 |
case 0x1: /* Core reset */ |
| 565 |
case 0x2: /* Chip reset */ |
| 566 |
case 0x3: /* System reset */ |
| 567 |
qemu_system_reset_request(); |
| 568 |
return;
|
| 569 |
} |
| 570 |
} |
| 571 |
} |
| 572 |
|
| 573 |
void store_40x_pit (CPUState *env, target_ulong val)
|
| 574 |
{
|
| 575 |
ppc_tb_t *tb_env; |
| 576 |
ppcemb_timer_t *ppcemb_timer; |
| 577 |
uint64_t now, next; |
| 578 |
|
| 579 |
tb_env = env->tb_env; |
| 580 |
ppcemb_timer = tb_env->opaque; |
| 581 |
if (loglevel)
|
| 582 |
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
| 583 |
ppcemb_timer->pit_reload = val; |
| 584 |
if (val == 0) { |
| 585 |
/* Stop PIT */
|
| 586 |
if (loglevel)
|
| 587 |
fprintf(logfile, "%s: stop PIT\n", __func__);
|
| 588 |
qemu_del_timer(tb_env->decr_timer); |
| 589 |
} else {
|
| 590 |
if (loglevel)
|
| 591 |
fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val); |
| 592 |
now = qemu_get_clock(vm_clock); |
| 593 |
next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq); |
| 594 |
if (next == now)
|
| 595 |
next++; |
| 596 |
qemu_mod_timer(tb_env->decr_timer, next); |
| 597 |
tb_env->decr_next = next; |
| 598 |
} |
| 599 |
} |
| 600 |
|
| 601 |
target_ulong load_40x_pit (CPUState *env) |
| 602 |
{
|
| 603 |
return cpu_ppc_load_decr(env);
|
| 604 |
} |
| 605 |
|
| 606 |
void store_booke_tsr (CPUState *env, target_ulong val)
|
| 607 |
{
|
| 608 |
env->spr[SPR_40x_TSR] = val & 0xFC000000;
|
| 609 |
} |
| 610 |
|
| 611 |
void store_booke_tcr (CPUState *env, target_ulong val)
|
| 612 |
{
|
| 613 |
/* We don't update timers now. Maybe we should... */
|
| 614 |
env->spr[SPR_40x_TCR] = val & 0xFF800000;
|
| 615 |
} |
| 616 |
|
| 617 |
void ppc_emb_timers_init (CPUState *env)
|
| 618 |
{
|
| 619 |
ppc_tb_t *tb_env; |
| 620 |
ppcemb_timer_t *ppcemb_timer; |
| 621 |
|
| 622 |
tb_env = env->tb_env; |
| 623 |
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
| 624 |
tb_env->opaque = ppcemb_timer; |
| 625 |
if (loglevel)
|
| 626 |
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
| 627 |
if (ppcemb_timer != NULL) { |
| 628 |
/* We use decr timer for PIT */
|
| 629 |
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
| 630 |
ppcemb_timer->fit_timer = |
| 631 |
qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
| 632 |
ppcemb_timer->wdt_timer = |
| 633 |
qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
| 634 |
} |
| 635 |
} |
| 636 |
|
| 637 |
/*****************************************************************************/
|
| 638 |
/* Embedded PowerPC Device Control Registers */
|
| 639 |
typedef struct ppc_dcrn_t ppc_dcrn_t; |
| 640 |
struct ppc_dcrn_t {
|
| 641 |
dcr_read_cb dcr_read; |
| 642 |
dcr_write_cb dcr_write; |
| 643 |
void *opaque;
|
| 644 |
}; |
| 645 |
|
| 646 |
#define DCRN_NB 1024 |
| 647 |
struct ppc_dcr_t {
|
| 648 |
ppc_dcrn_t dcrn[DCRN_NB]; |
| 649 |
int (*read_error)(int dcrn); |
| 650 |
int (*write_error)(int dcrn); |
| 651 |
}; |
| 652 |
|
| 653 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
| 654 |
{
|
| 655 |
ppc_dcrn_t *dcr; |
| 656 |
|
| 657 |
if (dcrn < 0 || dcrn >= DCRN_NB) |
| 658 |
goto error;
|
| 659 |
dcr = &dcr_env->dcrn[dcrn]; |
| 660 |
if (dcr->dcr_read == NULL) |
| 661 |
goto error;
|
| 662 |
*valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
| 663 |
|
| 664 |
return 0; |
| 665 |
|
| 666 |
error:
|
| 667 |
if (dcr_env->read_error != NULL) |
| 668 |
return (*dcr_env->read_error)(dcrn);
|
| 669 |
|
| 670 |
return -1; |
| 671 |
} |
| 672 |
|
| 673 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
| 674 |
{
|
| 675 |
ppc_dcrn_t *dcr; |
| 676 |
|
| 677 |
if (dcrn < 0 || dcrn >= DCRN_NB) |
| 678 |
goto error;
|
| 679 |
dcr = &dcr_env->dcrn[dcrn]; |
| 680 |
if (dcr->dcr_write == NULL) |
| 681 |
goto error;
|
| 682 |
(*dcr->dcr_write)(dcr->opaque, dcrn, val); |
| 683 |
|
| 684 |
return 0; |
| 685 |
|
| 686 |
error:
|
| 687 |
if (dcr_env->write_error != NULL) |
| 688 |
return (*dcr_env->write_error)(dcrn);
|
| 689 |
|
| 690 |
return -1; |
| 691 |
} |
| 692 |
|
| 693 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
| 694 |
dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
| 695 |
{
|
| 696 |
ppc_dcr_t *dcr_env; |
| 697 |
ppc_dcrn_t *dcr; |
| 698 |
|
| 699 |
dcr_env = env->dcr_env; |
| 700 |
if (dcr_env == NULL) |
| 701 |
return -1; |
| 702 |
if (dcrn < 0 || dcrn >= DCRN_NB) |
| 703 |
return -1; |
| 704 |
dcr = &dcr_env->dcrn[dcrn]; |
| 705 |
if (dcr->opaque != NULL || |
| 706 |
dcr->dcr_read != NULL ||
|
| 707 |
dcr->dcr_write != NULL)
|
| 708 |
return -1; |
| 709 |
dcr->opaque = opaque; |
| 710 |
dcr->dcr_read = dcr_read; |
| 711 |
dcr->dcr_write = dcr_write; |
| 712 |
|
| 713 |
return 0; |
| 714 |
} |
| 715 |
|
| 716 |
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
| 717 |
int (*write_error)(int dcrn)) |
| 718 |
{
|
| 719 |
ppc_dcr_t *dcr_env; |
| 720 |
|
| 721 |
dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
| 722 |
if (dcr_env == NULL) |
| 723 |
return -1; |
| 724 |
dcr_env->read_error = read_error; |
| 725 |
dcr_env->write_error = write_error; |
| 726 |
env->dcr_env = dcr_env; |
| 727 |
|
| 728 |
return 0; |
| 729 |
} |
| 730 |
|
| 731 |
|
| 732 |
#if 0
|
| 733 |
/*****************************************************************************/
|
| 734 |
/* Handle system reset (for now, just stop emulation) */
|
| 735 |
void cpu_ppc_reset (CPUState *env)
|
| 736 |
{
|
| 737 |
printf("Reset asked... Stop emulation\n");
|
| 738 |
abort();
|
| 739 |
}
|
| 740 |
#endif
|
| 741 |
|
| 742 |
/*****************************************************************************/
|
| 743 |
/* Debug port */
|
| 744 |
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
| 745 |
{
|
| 746 |
addr &= 0xF;
|
| 747 |
switch (addr) {
|
| 748 |
case 0: |
| 749 |
printf("%c", val);
|
| 750 |
break;
|
| 751 |
case 1: |
| 752 |
printf("\n");
|
| 753 |
fflush(stdout); |
| 754 |
break;
|
| 755 |
case 2: |
| 756 |
printf("Set loglevel to %04x\n", val);
|
| 757 |
cpu_set_log(val | 0x100);
|
| 758 |
break;
|
| 759 |
} |
| 760 |
} |
| 761 |
|
| 762 |
/*****************************************************************************/
|
| 763 |
/* NVRAM helpers */
|
| 764 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
| 765 |
{
|
| 766 |
m48t59_write(nvram, addr, value); |
| 767 |
} |
| 768 |
|
| 769 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
| 770 |
{
|
| 771 |
return m48t59_read(nvram, addr);
|
| 772 |
} |
| 773 |
|
| 774 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
| 775 |
{
|
| 776 |
m48t59_write(nvram, addr, value >> 8);
|
| 777 |
m48t59_write(nvram, addr + 1, value & 0xFF); |
| 778 |
} |
| 779 |
|
| 780 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
| 781 |
{
|
| 782 |
uint16_t tmp; |
| 783 |
|
| 784 |
tmp = m48t59_read(nvram, addr) << 8;
|
| 785 |
tmp |= m48t59_read(nvram, addr + 1);
|
| 786 |
return tmp;
|
| 787 |
} |
| 788 |
|
| 789 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
| 790 |
{
|
| 791 |
m48t59_write(nvram, addr, value >> 24);
|
| 792 |
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| 793 |
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
| 794 |
m48t59_write(nvram, addr + 3, value & 0xFF); |
| 795 |
} |
| 796 |
|
| 797 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
| 798 |
{
|
| 799 |
uint32_t tmp; |
| 800 |
|
| 801 |
tmp = m48t59_read(nvram, addr) << 24;
|
| 802 |
tmp |= m48t59_read(nvram, addr + 1) << 16; |
| 803 |
tmp |= m48t59_read(nvram, addr + 2) << 8; |
| 804 |
tmp |= m48t59_read(nvram, addr + 3);
|
| 805 |
|
| 806 |
return tmp;
|
| 807 |
} |
| 808 |
|
| 809 |
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
| 810 |
const unsigned char *str, uint32_t max) |
| 811 |
{
|
| 812 |
int i;
|
| 813 |
|
| 814 |
for (i = 0; i < max && str[i] != '\0'; i++) { |
| 815 |
m48t59_write(nvram, addr + i, str[i]); |
| 816 |
} |
| 817 |
m48t59_write(nvram, addr + max - 1, '\0'); |
| 818 |
} |
| 819 |
|
| 820 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
| 821 |
{
|
| 822 |
int i;
|
| 823 |
|
| 824 |
memset(dst, 0, max);
|
| 825 |
for (i = 0; i < max; i++) { |
| 826 |
dst[i] = NVRAM_get_byte(nvram, addr + i); |
| 827 |
if (dst[i] == '\0') |
| 828 |
break;
|
| 829 |
} |
| 830 |
|
| 831 |
return i;
|
| 832 |
} |
| 833 |
|
| 834 |
static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
| 835 |
{
|
| 836 |
uint16_t tmp; |
| 837 |
uint16_t pd, pd1, pd2; |
| 838 |
|
| 839 |
tmp = prev >> 8;
|
| 840 |
pd = prev ^ value; |
| 841 |
pd1 = pd & 0x000F;
|
| 842 |
pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
| 843 |
tmp ^= (pd1 << 3) | (pd1 << 8); |
| 844 |
tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
| 845 |
|
| 846 |
return tmp;
|
| 847 |
} |
| 848 |
|
| 849 |
uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
| 850 |
{
|
| 851 |
uint32_t i; |
| 852 |
uint16_t crc = 0xFFFF;
|
| 853 |
int odd;
|
| 854 |
|
| 855 |
odd = count & 1;
|
| 856 |
count &= ~1;
|
| 857 |
for (i = 0; i != count; i++) { |
| 858 |
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
| 859 |
} |
| 860 |
if (odd) {
|
| 861 |
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
| 862 |
} |
| 863 |
|
| 864 |
return crc;
|
| 865 |
} |
| 866 |
|
| 867 |
#define CMDLINE_ADDR 0x017ff000 |
| 868 |
|
| 869 |
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
| 870 |
const unsigned char *arch, |
| 871 |
uint32_t RAM_size, int boot_device,
|
| 872 |
uint32_t kernel_image, uint32_t kernel_size, |
| 873 |
const char *cmdline, |
| 874 |
uint32_t initrd_image, uint32_t initrd_size, |
| 875 |
uint32_t NVRAM_image, |
| 876 |
int width, int height, int depth) |
| 877 |
{
|
| 878 |
uint16_t crc; |
| 879 |
|
| 880 |
/* Set parameters for Open Hack'Ware BIOS */
|
| 881 |
NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 882 |
NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
| 883 |
NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
| 884 |
NVRAM_set_string(nvram, 0x20, arch, 16); |
| 885 |
NVRAM_set_lword(nvram, 0x30, RAM_size);
|
| 886 |
NVRAM_set_byte(nvram, 0x34, boot_device);
|
| 887 |
NVRAM_set_lword(nvram, 0x38, kernel_image);
|
| 888 |
NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
| 889 |
if (cmdline) {
|
| 890 |
/* XXX: put the cmdline in NVRAM too ? */
|
| 891 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
| 892 |
NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
| 893 |
NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
| 894 |
} else {
|
| 895 |
NVRAM_set_lword(nvram, 0x40, 0); |
| 896 |
NVRAM_set_lword(nvram, 0x44, 0); |
| 897 |
} |
| 898 |
NVRAM_set_lword(nvram, 0x48, initrd_image);
|
| 899 |
NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
| 900 |
NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
| 901 |
|
| 902 |
NVRAM_set_word(nvram, 0x54, width);
|
| 903 |
NVRAM_set_word(nvram, 0x56, height);
|
| 904 |
NVRAM_set_word(nvram, 0x58, depth);
|
| 905 |
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
| 906 |
NVRAM_set_word(nvram, 0xFC, crc);
|
| 907 |
|
| 908 |
return 0; |
| 909 |
} |