root / hw / ppc_chrp.c @ e96efcfc
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/*
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* QEMU PPC CHRP/PMAC hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1 |
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#define BIOS_FILENAME "ppc_rom.bin" |
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#define VGABIOS_FILENAME "video.x" |
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#define NVRAM_SIZE 0x2000 |
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#define KERNEL_LOAD_ADDR 0x01000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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NVRAM */
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static int dbdma_mem_index; |
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static int cuda_mem_index; |
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static int ide0_mem_index = -1; |
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static int ide1_mem_index = -1; |
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static int openpic_mem_index = -1; |
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static int heathrow_pic_mem_index = -1; |
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static int macio_nvram_mem_index = -1; |
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|
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/* DBDMA: currently no op - should suffice right now */
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static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value); |
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} |
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static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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|
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static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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|
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static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr); |
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return 0; |
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} |
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|
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static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static CPUWriteMemoryFunc *dbdma_write[] = {
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&dbdma_writeb, |
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&dbdma_writew, |
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&dbdma_writel, |
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}; |
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static CPUReadMemoryFunc *dbdma_read[] = {
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&dbdma_readb, |
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&dbdma_readw, |
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&dbdma_readl, |
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}; |
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/* macio style NVRAM device */
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typedef struct MacIONVRAMState { |
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uint8_t data[0x2000];
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} MacIONVRAMState; |
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static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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MacIONVRAMState *s = opaque; |
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addr = (addr >> 4) & 0x1fff; |
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s->data[addr] = value; |
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// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
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} |
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static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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MacIONVRAMState *s = opaque; |
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uint32_t value; |
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addr = (addr >> 4) & 0x1fff; |
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value = s->data[addr]; |
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// printf("macio_nvram_readb %04x = %02x\n", addr, value);
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return value;
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} |
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static CPUWriteMemoryFunc *macio_nvram_write[] = {
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&macio_nvram_writeb, |
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&macio_nvram_writeb, |
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&macio_nvram_writeb, |
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}; |
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static CPUReadMemoryFunc *macio_nvram_read[] = {
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&macio_nvram_readb, |
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&macio_nvram_readb, |
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&macio_nvram_readb, |
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}; |
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static MacIONVRAMState *macio_nvram_init(void) |
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{ |
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MacIONVRAMState *s; |
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s = qemu_mallocz(sizeof(MacIONVRAMState));
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if (!s)
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return NULL; |
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macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
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macio_nvram_write, s); |
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return s;
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} |
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static void macio_map(PCIDevice *pci_dev, int region_num, |
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uint32_t addr, uint32_t size, int type)
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{ |
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if (heathrow_pic_mem_index >= 0) { |
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cpu_register_physical_memory(addr + 0x00000, 0x1000, |
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heathrow_pic_mem_index); |
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} |
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); |
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if (ide0_mem_index >= 0) |
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); |
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if (ide1_mem_index >= 0) |
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); |
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if (openpic_mem_index >= 0) { |
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cpu_register_physical_memory(addr + 0x40000, 0x40000, |
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openpic_mem_index); |
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} |
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if (macio_nvram_mem_index >= 0) |
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cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index); |
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} |
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static void macio_init(PCIBus *bus, int device_id) |
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{ |
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PCIDevice *d; |
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d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
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-1, NULL, NULL); |
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/* Note: this code is strongly inspirated from the corresponding code
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in PearPC */
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d->config[0x00] = 0x6b; // vendor_id |
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d->config[0x01] = 0x10; |
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d->config[0x02] = device_id;
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d->config[0x03] = device_id >> 8; |
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d->config[0x0a] = 0x00; // class_sub = pci2pci |
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d->config[0x0b] = 0xff; // class_base = bridge |
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d->config[0x0e] = 0x00; // header_type |
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d->config[0x3d] = 0x01; // interrupt on pin 1 |
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dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
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pci_register_io_region(d, 0, 0x80000, |
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PCI_ADDRESS_SPACE_MEM, macio_map); |
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} |
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/* UniN device */
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static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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} |
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static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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return 0; |
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} |
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static CPUWriteMemoryFunc *unin_write[] = {
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&unin_writel, |
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&unin_writel, |
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&unin_writel, |
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}; |
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static CPUReadMemoryFunc *unin_read[] = {
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&unin_readl, |
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&unin_readl, |
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&unin_readl, |
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}; |
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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static int vga_osi_call(CPUState *env) |
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{ |
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static int vga_vbl_enabled; |
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int linesize;
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// printf("osi_call R5=%d\n", env->gpr[5]);
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) { |
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case 4: |
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break;
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case 28: /* set_vmode */ |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) |
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env->gpr[3] = 1; |
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else
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env->gpr[3] = 0; |
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break;
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case 29: /* get_vmode_info */ |
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if (env->gpr[6] != 0) { |
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if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
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env->gpr[3] = 1; |
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break;
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} |
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} |
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env->gpr[3] = 0; |
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
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env->gpr[7] = 85 << 16; /* refresh rate */ |
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
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linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
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linesize = (linesize + 3) & ~3; |
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
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break;
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case 31: /* set_video power */ |
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env->gpr[3] = 0; |
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break;
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case 39: /* video_ctrl */ |
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if (env->gpr[6] == 0 || env->gpr[6] == 1) |
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0; |
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break;
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case 47: |
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break;
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case 59: /* set_color */ |
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0; |
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break;
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case 64: /* get color */ |
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/* R6 = index */
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env->gpr[3] = 0; |
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break;
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case 116: /* set hwcursor */ |
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]); |
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break;
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} |
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return 1; /* osi_call handled */ |
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} |
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static uint8_t nvram_chksum(const uint8_t *buf, int n) |
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{ |
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int sum, i;
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sum = 0;
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for(i = 0; i < n; i++) |
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sum += buf[i]; |
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return (sum & 0xff) + (sum >> 8); |
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} |
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|
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/* set a free Mac OS NVRAM partition */
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void pmac_format_nvram_partition(uint8_t *buf, int len) |
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{ |
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char partition_name[12] = "wwwwwwwwwwww"; |
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buf[0] = 0x7f; /* free partition magic */ |
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buf[1] = 0; /* checksum */ |
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buf[2] = len >> 8; |
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buf[3] = len;
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memcpy(buf + 4, partition_name, 12); |
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buf[1] = nvram_chksum(buf, 16); |
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} |
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device, |
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DisplayState *ds, const char **fd_filename, |
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int snapshot,
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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const char *cpu_model, |
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int is_heathrow)
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{ |
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CPUState *env, *envs[MAX_CPUS]; |
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char buf[1024]; |
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qemu_irq *pic, **openpic_irqs; |
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m48t59_t *nvram; |
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int unin_memory;
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int linux_boot, i;
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unsigned long bios_offset, vga_bios_offset; |
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
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ppc_def_t *def; |
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PCIBus *pci_bus; |
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const char *arch_name; |
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int vga_bios_size, bios_size;
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qemu_irq *dummy_irq; |
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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env = cpu_init(); |
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
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/* Default CPU is a generic 74x/75x */
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if (cpu_model == NULL) |
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cpu_model = "750";
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/* XXX: CPU model (or PVR) should be provided on command line */
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// ppc_find_by_name("750gx", &def); // Linux boot OK
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// ppc_find_by_name("750fx", &def); // Linux boot OK
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/* Linux does not boot on 750cxe (and probably other 750cx based)
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* because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
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*/
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ppc_find_by_name(cpu_model, &def); |
332 |
if (def == NULL) { |
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cpu_abort(env, "Unable to find PowerPC CPU definition\n");
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} |
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for (i = 0; i < smp_cpus; i++) { |
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cpu_ppc_register(env, def); |
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
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env->osi_call = vga_osi_call; |
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envs[i] = env; |
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} |
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|
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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|
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size; |
348 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
349 |
bios_size = load_image(buf, phys_ram_base + bios_offset); |
350 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
351 |
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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} |
354 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
355 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
356 |
bios_size, bios_offset | IO_MEM_ROM); |
357 |
|
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/* allocate and load VGA BIOS */
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vga_bios_offset = bios_offset + bios_size; |
360 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
361 |
vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
|
362 |
if (vga_bios_size < 0) { |
363 |
/* if no bios is present, we can still work */
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fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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vga_bios_size = 0;
|
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} else {
|
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/* set a specific header (XXX: find real Apple format for NDRV
|
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drivers) */
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phys_ram_base[vga_bios_offset] = 'N';
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phys_ram_base[vga_bios_offset + 1] = 'D'; |
371 |
phys_ram_base[vga_bios_offset + 2] = 'R'; |
372 |
phys_ram_base[vga_bios_offset + 3] = 'V'; |
373 |
cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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vga_bios_size); |
375 |
vga_bios_size += 8;
|
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} |
377 |
vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; |
378 |
|
379 |
if (linux_boot) {
|
380 |
kernel_base = KERNEL_LOAD_ADDR; |
381 |
/* now we can load the kernel */
|
382 |
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
383 |
if (kernel_size < 0) { |
384 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
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kernel_filename); |
386 |
exit(1);
|
387 |
} |
388 |
/* load initrd */
|
389 |
if (initrd_filename) {
|
390 |
initrd_base = INITRD_LOAD_ADDR; |
391 |
initrd_size = load_image(initrd_filename, |
392 |
phys_ram_base + initrd_base); |
393 |
if (initrd_size < 0) { |
394 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
395 |
initrd_filename); |
396 |
exit(1);
|
397 |
} |
398 |
} else {
|
399 |
initrd_base = 0;
|
400 |
initrd_size = 0;
|
401 |
} |
402 |
boot_device = 'm';
|
403 |
} else {
|
404 |
kernel_base = 0;
|
405 |
kernel_size = 0;
|
406 |
initrd_base = 0;
|
407 |
initrd_size = 0;
|
408 |
} |
409 |
|
410 |
if (is_heathrow) {
|
411 |
isa_mem_base = 0x80000000;
|
412 |
|
413 |
/* Register 2 MB of ISA IO space */
|
414 |
isa_mmio_init(0xfe000000, 0x00200000); |
415 |
|
416 |
/* init basic PC hardware */
|
417 |
pic = heathrow_pic_init(&heathrow_pic_mem_index); |
418 |
pci_bus = pci_grackle_init(0xfec00000, pic);
|
419 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
420 |
ram_size, vga_ram_size, |
421 |
vga_bios_offset, vga_bios_size); |
422 |
|
423 |
/* XXX: suppress that */
|
424 |
dummy_irq = i8259_init(NULL);
|
425 |
|
426 |
/* XXX: use Mac Serial port */
|
427 |
serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
428 |
|
429 |
for(i = 0; i < nb_nics; i++) { |
430 |
if (!nd_table[i].model)
|
431 |
nd_table[i].model = "ne2k_pci";
|
432 |
pci_nic_init(pci_bus, &nd_table[i], -1);
|
433 |
} |
434 |
|
435 |
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
436 |
|
437 |
/* cuda also initialize ADB */
|
438 |
cuda_mem_index = cuda_init(pic[0x12]);
|
439 |
|
440 |
adb_kbd_init(&adb_bus); |
441 |
adb_mouse_init(&adb_bus); |
442 |
|
443 |
{ |
444 |
MacIONVRAMState *nvr; |
445 |
nvr = macio_nvram_init(); |
446 |
pmac_format_nvram_partition(nvr->data, 0x2000);
|
447 |
} |
448 |
|
449 |
macio_init(pci_bus, 0x0017);
|
450 |
|
451 |
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
452 |
|
453 |
arch_name = "HEATHROW";
|
454 |
} else {
|
455 |
isa_mem_base = 0x80000000;
|
456 |
|
457 |
/* Register 8 MB of ISA IO space */
|
458 |
isa_mmio_init(0xf2000000, 0x00800000); |
459 |
|
460 |
/* UniN init */
|
461 |
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
462 |
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
463 |
|
464 |
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
|
465 |
openpic_irqs[0] =
|
466 |
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
|
467 |
for (i = 0; i < smp_cpus; i++) { |
468 |
/* Mac99 IRQ connection between OpenPIC outputs pins
|
469 |
* and PowerPC input pins
|
470 |
*/
|
471 |
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
472 |
openpic_irqs[i][OPENPIC_OUTPUT_INT] = |
473 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
474 |
openpic_irqs[i][OPENPIC_OUTPUT_CINT] = |
475 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; |
476 |
openpic_irqs[i][OPENPIC_OUTPUT_MCK] = |
477 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; |
478 |
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Not connected ? */ |
479 |
openpic_irqs[i][OPENPIC_OUTPUT_RESET] = |
480 |
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; /* Check this */
|
481 |
} |
482 |
pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
|
483 |
openpic_irqs, NULL);
|
484 |
pci_bus = pci_pmac_init(pic); |
485 |
/* init basic PC hardware */
|
486 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, |
487 |
ram_size, vga_ram_size, |
488 |
vga_bios_offset, vga_bios_size); |
489 |
|
490 |
/* XXX: suppress that */
|
491 |
dummy_irq = i8259_init(NULL);
|
492 |
|
493 |
/* XXX: use Mac Serial port */
|
494 |
serial_init(0x3f8, dummy_irq[4], serial_hds[0]); |
495 |
for(i = 0; i < nb_nics; i++) { |
496 |
if (!nd_table[i].model)
|
497 |
nd_table[i].model = "ne2k_pci";
|
498 |
pci_nic_init(pci_bus, &nd_table[i], -1);
|
499 |
} |
500 |
#if 1 |
501 |
ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]); |
502 |
ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]); |
503 |
#else
|
504 |
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
505 |
#endif
|
506 |
/* cuda also initialize ADB */
|
507 |
cuda_mem_index = cuda_init(pic[0x19]);
|
508 |
|
509 |
adb_kbd_init(&adb_bus); |
510 |
adb_mouse_init(&adb_bus); |
511 |
|
512 |
macio_init(pci_bus, 0x0022);
|
513 |
|
514 |
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
515 |
|
516 |
arch_name = "MAC99";
|
517 |
} |
518 |
|
519 |
if (usb_enabled) {
|
520 |
usb_ohci_init_pci(pci_bus, 3, -1); |
521 |
} |
522 |
|
523 |
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
524 |
graphic_depth = 15;
|
525 |
|
526 |
PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, |
527 |
kernel_base, kernel_size, |
528 |
kernel_cmdline, |
529 |
initrd_base, initrd_size, |
530 |
/* XXX: need an option to load a NVRAM image */
|
531 |
0,
|
532 |
graphic_width, graphic_height, graphic_depth); |
533 |
/* No PCI init: the BIOS will do it */
|
534 |
|
535 |
/* Special port to get debug messages from Open-Firmware */
|
536 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
537 |
} |
538 |
|
539 |
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device, |
540 |
DisplayState *ds, const char **fd_filename, |
541 |
int snapshot,
|
542 |
const char *kernel_filename, |
543 |
const char *kernel_cmdline, |
544 |
const char *initrd_filename, |
545 |
const char *cpu_model) |
546 |
{ |
547 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
548 |
ds, fd_filename, snapshot, |
549 |
kernel_filename, kernel_cmdline, |
550 |
initrd_filename, cpu_model, 0);
|
551 |
} |
552 |
|
553 |
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device, |
554 |
DisplayState *ds, const char **fd_filename, |
555 |
int snapshot,
|
556 |
const char *kernel_filename, |
557 |
const char *kernel_cmdline, |
558 |
const char *initrd_filename, |
559 |
const char *cpu_model) |
560 |
{ |
561 |
ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
562 |
ds, fd_filename, snapshot, |
563 |
kernel_filename, kernel_cmdline, |
564 |
initrd_filename, cpu_model, 1);
|
565 |
} |
566 |
|
567 |
QEMUMachine core99_machine = { |
568 |
"mac99",
|
569 |
"Mac99 based PowerMAC",
|
570 |
ppc_core99_init, |
571 |
}; |
572 |
|
573 |
QEMUMachine heathrow_machine = { |
574 |
"g3bw",
|
575 |
"Heathrow based PowerMAC",
|
576 |
ppc_heathrow_init, |
577 |
}; |