Revision e9c71dd1 target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 781 | 781 |
FORCE_RET(); |
| 782 | 782 |
} |
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/* Multiplication variants of the vr54xx. */ |
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void op_muls (void) |
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{
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CALL_FROM_TB0(do_muls); |
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FORCE_RET(); |
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} |
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void op_mulsu (void) |
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{
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CALL_FROM_TB0(do_mulsu); |
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FORCE_RET(); |
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} |
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void op_macc (void) |
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{
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CALL_FROM_TB0(do_macc); |
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FORCE_RET(); |
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} |
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void op_macchi (void) |
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{
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CALL_FROM_TB0(do_macchi); |
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FORCE_RET(); |
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} |
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void op_maccu (void) |
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{
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CALL_FROM_TB0(do_maccu); |
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FORCE_RET(); |
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} |
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void op_macchiu (void) |
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{
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CALL_FROM_TB0(do_macchiu); |
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FORCE_RET(); |
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} |
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void op_msac (void) |
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{
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CALL_FROM_TB0(do_msac); |
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FORCE_RET(); |
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} |
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void op_msachi (void) |
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{
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CALL_FROM_TB0(do_msachi); |
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FORCE_RET(); |
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} |
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void op_msacu (void) |
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{
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CALL_FROM_TB0(do_msacu); |
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FORCE_RET(); |
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} |
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void op_msachiu (void) |
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{
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CALL_FROM_TB0(do_msachiu); |
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FORCE_RET(); |
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} |
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void op_mulhi (void) |
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{
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CALL_FROM_TB0(do_mulhi); |
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FORCE_RET(); |
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} |
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void op_mulhiu (void) |
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{
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CALL_FROM_TB0(do_mulhiu); |
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FORCE_RET(); |
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} |
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void op_mulshi (void) |
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{
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CALL_FROM_TB0(do_mulshi); |
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FORCE_RET(); |
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} |
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void op_mulshiu (void) |
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{
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CALL_FROM_TB0(do_mulshiu); |
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FORCE_RET(); |
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} |
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| 784 | 868 |
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 785 | 869 |
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static always_inline uint64_t get_HILO (void) |
| ... | ... | |
| 795 | 879 |
env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
| 796 | 880 |
} |
| 797 | 881 |
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static always_inline void set_HIT0_LO (uint64_t HILO) |
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{
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env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
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T0 = env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
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} |
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static always_inline void set_HI_LOT0 (uint64_t HILO) |
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{
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T0 = env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
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} |
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void op_mult (void) |
| 799 | 895 |
{
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set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| ... | ... | |
| 842 | 938 |
set_HILO(get_HILO() - tmp); |
| 843 | 939 |
FORCE_RET(); |
| 844 | 940 |
} |
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/* Multiplication variants of the vr54xx. */ |
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void op_muls (void) |
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{
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set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulsu (void) |
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{
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set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macc (void) |
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{
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set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macchi (void) |
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{
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set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_maccu (void) |
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{
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set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_macchiu (void) |
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{
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set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msac (void) |
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{
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set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msachi (void) |
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{
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set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msacu (void) |
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{
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set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_msachiu (void) |
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{
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set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulhi (void) |
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{
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set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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FORCE_RET(); |
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} |
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void op_mulhiu (void) |
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{
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set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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FORCE_RET(); |
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} |
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void op_mulshi (void) |
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{
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set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
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FORCE_RET(); |
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} |
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void op_mulshiu (void) |
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{
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set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
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FORCE_RET(); |
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} |
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#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 846 | 1028 |
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| 847 | 1029 |
#if defined(TARGET_MIPS64) |
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