Revision e9c71dd1 target-mips/translate_init.c
b/target-mips/translate_init.c | ||
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306 | 306 |
.mmu_type = MMU_TYPE_R4000, |
307 | 307 |
}, |
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{ |
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.name = "VR5432", |
|
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.CP0_PRid = 0x00005400, |
|
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/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
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.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
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.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
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.SYNCI_Step = 16, |
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.CCRes = 2, |
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.CP0_Status_rw_bitmask = 0x3678FFFF, |
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/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
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.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
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.SEGBITS = 40, |
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.PABITS = 32, |
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.insn_flags = CPU_VR54XX, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
|
309 | 325 |
.name = "5Kc", |
310 | 326 |
.CP0_PRid = 0x00018100, |
311 | 327 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
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