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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | a541f297 | bellard | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | fd0bbb12 | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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28 | e9df014c | j_mayer | |
29 | 47103572 | j_mayer | extern FILE *logfile;
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30 | 47103572 | j_mayer | extern int loglevel; |
31 | 47103572 | j_mayer | |
32 | e9df014c | j_mayer | void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
33 | 47103572 | j_mayer | { |
34 | 47103572 | j_mayer | if (level) {
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35 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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36 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
37 | 47103572 | j_mayer | } else {
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38 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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39 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
40 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
41 | 47103572 | j_mayer | } |
42 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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43 | 47103572 | j_mayer | printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
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44 | 47103572 | j_mayer | env, n_IRQ, level, env->pending_interrupts, env->interrupt_request); |
45 | 47103572 | j_mayer | #endif
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46 | 47103572 | j_mayer | } |
47 | 47103572 | j_mayer | |
48 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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49 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
50 | d537cf6c | pbrook | { |
51 | e9df014c | j_mayer | CPUState *env = opaque; |
52 | e9df014c | j_mayer | int cur_level;
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53 | d537cf6c | pbrook | |
54 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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55 | e9df014c | j_mayer | printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
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56 | e9df014c | j_mayer | #endif
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57 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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58 | e9df014c | j_mayer | /* Don't generate spurious events */
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59 | e9df014c | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0) || 0) { |
60 | e9df014c | j_mayer | switch (pin) {
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61 | e9df014c | j_mayer | case PPC_INPUT_INT:
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62 | e9df014c | j_mayer | /* Level sensitive - asserted high */
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63 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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64 | e9df014c | j_mayer | printf("%s: set the external IRQ state to %d\n", __func__, level);
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65 | e9df014c | j_mayer | #endif
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66 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
67 | e9df014c | j_mayer | break;
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68 | e9df014c | j_mayer | case PPC_INPUT_SMI:
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69 | e9df014c | j_mayer | /* Level sensitive - active high */
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70 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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71 | e9df014c | j_mayer | printf("%s: set the SMI IRQ state to %d\n", __func__, level);
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72 | e9df014c | j_mayer | #endif
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73 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
74 | e9df014c | j_mayer | break;
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75 | e9df014c | j_mayer | case PPC_INPUT_MCP:
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76 | e9df014c | j_mayer | /* Negative edge sensitive */
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77 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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78 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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79 | e9df014c | j_mayer | */
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80 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
81 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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82 | e9df014c | j_mayer | printf("%s: raise machine check state\n", __func__);
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83 | e9df014c | j_mayer | #endif
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84 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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85 | e9df014c | j_mayer | } |
86 | e9df014c | j_mayer | break;
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87 | e9df014c | j_mayer | case PPC_INPUT_CKSTP_IN:
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88 | e9df014c | j_mayer | /* Level sensitive - active low */
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89 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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90 | e9df014c | j_mayer | if (level) {
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91 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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92 | e9df014c | j_mayer | printf("%s: stop the CPU\n", __func__);
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93 | e9df014c | j_mayer | #endif
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94 | e9df014c | j_mayer | env->halted = 1;
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95 | e9df014c | j_mayer | } else {
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96 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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97 | e9df014c | j_mayer | printf("%s: restart the CPU\n", __func__);
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98 | e9df014c | j_mayer | #endif
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99 | e9df014c | j_mayer | env->halted = 0;
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100 | e9df014c | j_mayer | } |
101 | e9df014c | j_mayer | break;
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102 | e9df014c | j_mayer | case PPC_INPUT_HRESET:
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103 | e9df014c | j_mayer | /* Level sensitive - active low */
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104 | e9df014c | j_mayer | if (level) {
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105 | e9df014c | j_mayer | #if 0 // XXX: TOFIX
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106 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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107 | e9df014c | j_mayer | printf("%s: reset the CPU\n", __func__);
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108 | e9df014c | j_mayer | #endif
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109 | e9df014c | j_mayer | cpu_reset(env); |
110 | e9df014c | j_mayer | #endif
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111 | e9df014c | j_mayer | } |
112 | e9df014c | j_mayer | break;
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113 | e9df014c | j_mayer | case PPC_INPUT_SRESET:
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114 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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115 | e9df014c | j_mayer | printf("%s: set the RESET IRQ state to %d\n", __func__, level);
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116 | e9df014c | j_mayer | #endif
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117 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
118 | e9df014c | j_mayer | break;
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119 | e9df014c | j_mayer | default:
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120 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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121 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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122 | e9df014c | j_mayer | printf("%s: unknown IRQ pin %d\n", __func__, pin);
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123 | e9df014c | j_mayer | #endif
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124 | e9df014c | j_mayer | return;
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125 | e9df014c | j_mayer | } |
126 | e9df014c | j_mayer | if (level)
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127 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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128 | e9df014c | j_mayer | else
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129 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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130 | d537cf6c | pbrook | } |
131 | d537cf6c | pbrook | } |
132 | d537cf6c | pbrook | |
133 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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134 | 47103572 | j_mayer | { |
135 | e9df014c | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6); |
136 | 47103572 | j_mayer | } |
137 | 47103572 | j_mayer | |
138 | 9fddaa0c | bellard | /*****************************************************************************/
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139 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
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140 | 9fddaa0c | bellard | //#define DEBUG_TB
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141 | 9fddaa0c | bellard | |
142 | 9fddaa0c | bellard | struct ppc_tb_t {
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143 | 9fddaa0c | bellard | /* Time base management */
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144 | 9fddaa0c | bellard | int64_t tb_offset; /* Compensation */
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145 | 9fddaa0c | bellard | uint32_t tb_freq; /* TB frequency */
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146 | 9fddaa0c | bellard | /* Decrementer management */
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147 | 9fddaa0c | bellard | uint64_t decr_next; /* Tick for next decr interrupt */
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148 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
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149 | 47103572 | j_mayer | void *opaque;
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150 | 9fddaa0c | bellard | }; |
151 | 9fddaa0c | bellard | |
152 | 9fddaa0c | bellard | static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) |
153 | 9fddaa0c | bellard | { |
154 | 9fddaa0c | bellard | /* TB time in tb periods */
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155 | 9fddaa0c | bellard | return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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156 | 76a66253 | j_mayer | tb_env->tb_freq, ticks_per_sec); |
157 | 9fddaa0c | bellard | } |
158 | 9fddaa0c | bellard | |
159 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUState *env) |
160 | 9fddaa0c | bellard | { |
161 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
162 | 9fddaa0c | bellard | uint64_t tb; |
163 | 9fddaa0c | bellard | |
164 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
165 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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166 | 9fddaa0c | bellard | { |
167 | 76a66253 | j_mayer | static int last_time; |
168 | 76a66253 | j_mayer | int now;
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169 | 76a66253 | j_mayer | now = time(NULL);
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170 | 76a66253 | j_mayer | if (last_time != now) {
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171 | 76a66253 | j_mayer | last_time = now; |
172 | 76a66253 | j_mayer | printf("%s: tb=0x%016lx %d %08lx\n",
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173 | 76a66253 | j_mayer | __func__, tb, now, tb_env->tb_offset); |
174 | 76a66253 | j_mayer | } |
175 | 9fddaa0c | bellard | } |
176 | 9fddaa0c | bellard | #endif
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177 | 9fddaa0c | bellard | |
178 | 9fddaa0c | bellard | return tb & 0xFFFFFFFF; |
179 | 9fddaa0c | bellard | } |
180 | 9fddaa0c | bellard | |
181 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUState *env) |
182 | 9fddaa0c | bellard | { |
183 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
184 | 9fddaa0c | bellard | uint64_t tb; |
185 | 9fddaa0c | bellard | |
186 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
187 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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188 | 9fddaa0c | bellard | printf("%s: tb=0x%016lx\n", __func__, tb);
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189 | 9fddaa0c | bellard | #endif
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190 | 76a66253 | j_mayer | |
191 | 9fddaa0c | bellard | return tb >> 32; |
192 | 9fddaa0c | bellard | } |
193 | 9fddaa0c | bellard | |
194 | 9fddaa0c | bellard | static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) |
195 | 9fddaa0c | bellard | { |
196 | 9fddaa0c | bellard | tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
197 | 9fddaa0c | bellard | - qemu_get_clock(vm_clock); |
198 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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199 | 9fddaa0c | bellard | printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
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200 | 9fddaa0c | bellard | #endif
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201 | 9fddaa0c | bellard | } |
202 | 9fddaa0c | bellard | |
203 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
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204 | 9fddaa0c | bellard | { |
205 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
206 | 9fddaa0c | bellard | |
207 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
208 | 9fddaa0c | bellard | ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
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209 | 9fddaa0c | bellard | } |
210 | 9fddaa0c | bellard | |
211 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
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212 | 9fddaa0c | bellard | { |
213 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
214 | 9fddaa0c | bellard | |
215 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
216 | 9fddaa0c | bellard | ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
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217 | 9fddaa0c | bellard | } |
218 | 9fddaa0c | bellard | |
219 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUState *env) |
220 | 9fddaa0c | bellard | { |
221 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
222 | 9fddaa0c | bellard | uint32_t decr; |
223 | 4e588a4d | bellard | int64_t diff; |
224 | 9fddaa0c | bellard | |
225 | 4e588a4d | bellard | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
226 | 4e588a4d | bellard | if (diff >= 0) |
227 | 4e588a4d | bellard | decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
228 | 4e588a4d | bellard | else
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229 | 4e588a4d | bellard | decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); |
230 | fd0bbb12 | bellard | #if defined(DEBUG_TB)
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231 | 9fddaa0c | bellard | printf("%s: 0x%08x\n", __func__, decr);
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232 | 9fddaa0c | bellard | #endif
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233 | 76a66253 | j_mayer | |
234 | 9fddaa0c | bellard | return decr;
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235 | 9fddaa0c | bellard | } |
236 | 9fddaa0c | bellard | |
237 | 9fddaa0c | bellard | /* When decrementer expires,
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238 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
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239 | 9fddaa0c | bellard | */
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240 | 9fddaa0c | bellard | static inline void cpu_ppc_decr_excp (CPUState *env) |
241 | 9fddaa0c | bellard | { |
242 | 9fddaa0c | bellard | /* Raise it */
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243 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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244 | 9fddaa0c | bellard | printf("raise decrementer exception\n");
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245 | 9fddaa0c | bellard | #endif
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246 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
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247 | 9fddaa0c | bellard | } |
248 | 9fddaa0c | bellard | |
249 | 9fddaa0c | bellard | static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
250 | 9fddaa0c | bellard | uint32_t value, int is_excp)
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251 | 9fddaa0c | bellard | { |
252 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
253 | 9fddaa0c | bellard | uint64_t now, next; |
254 | 9fddaa0c | bellard | |
255 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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256 | 9fddaa0c | bellard | printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
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257 | 9fddaa0c | bellard | #endif
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258 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
259 | 9fddaa0c | bellard | next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); |
260 | 9fddaa0c | bellard | if (is_excp)
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261 | 9fddaa0c | bellard | next += tb_env->decr_next - now; |
262 | 9fddaa0c | bellard | if (next == now)
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263 | 76a66253 | j_mayer | next++; |
264 | 9fddaa0c | bellard | tb_env->decr_next = next; |
265 | 9fddaa0c | bellard | /* Adjust timer */
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266 | 9fddaa0c | bellard | qemu_mod_timer(tb_env->decr_timer, next); |
267 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
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268 | 9fddaa0c | bellard | * raise an exception.
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269 | 9fddaa0c | bellard | */
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270 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
271 | 76a66253 | j_mayer | cpu_ppc_decr_excp(env); |
272 | 9fddaa0c | bellard | } |
273 | 9fddaa0c | bellard | |
274 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
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275 | 9fddaa0c | bellard | { |
276 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
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277 | 9fddaa0c | bellard | } |
278 | 9fddaa0c | bellard | |
279 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
280 | 9fddaa0c | bellard | { |
281 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
282 | 9fddaa0c | bellard | } |
283 | 9fddaa0c | bellard | |
284 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
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285 | 9fddaa0c | bellard | ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
286 | 9fddaa0c | bellard | { |
287 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
288 | 9fddaa0c | bellard | |
289 | 9fddaa0c | bellard | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
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290 | 9fddaa0c | bellard | if (tb_env == NULL) |
291 | 9fddaa0c | bellard | return NULL; |
292 | 9fddaa0c | bellard | env->tb_env = tb_env; |
293 | 9fddaa0c | bellard | if (tb_env->tb_freq == 0 || 1) { |
294 | 76a66253 | j_mayer | tb_env->tb_freq = freq; |
295 | 76a66253 | j_mayer | /* Create new timer */
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296 | 76a66253 | j_mayer | tb_env->decr_timer = |
297 | 9fddaa0c | bellard | qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
298 | 76a66253 | j_mayer | /* There is a bug in Linux 2.4 kernels:
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299 | 76a66253 | j_mayer | * if a decrementer exception is pending when it enables msr_ee,
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300 | 76a66253 | j_mayer | * it's not ready to handle it...
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301 | 76a66253 | j_mayer | */
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302 | 76a66253 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
303 | 9fddaa0c | bellard | } |
304 | 9fddaa0c | bellard | |
305 | 9fddaa0c | bellard | return tb_env;
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306 | 9fddaa0c | bellard | } |
307 | 9fddaa0c | bellard | |
308 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
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309 | 76a66253 | j_mayer | ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env) |
310 | 76a66253 | j_mayer | { |
311 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500); |
312 | 76a66253 | j_mayer | } |
313 | 76a66253 | j_mayer | |
314 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
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315 | 76a66253 | j_mayer | __attribute__ (( alias ("cpu_ppc_store_tbu") ));
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316 | 76a66253 | j_mayer | |
317 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
318 | 76a66253 | j_mayer | __attribute__ (( alias ("cpu_ppc_load_tbu") ));
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319 | 76a66253 | j_mayer | |
320 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
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321 | 76a66253 | j_mayer | { |
322 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
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323 | 76a66253 | j_mayer | } |
324 | 76a66253 | j_mayer | |
325 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
326 | 76a66253 | j_mayer | { |
327 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
328 | 76a66253 | j_mayer | } |
329 | 76a66253 | j_mayer | |
330 | 636aaad7 | j_mayer | /*****************************************************************************/
|
331 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
332 | 636aaad7 | j_mayer | |
333 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
334 | 636aaad7 | j_mayer | typedef struct ppcemb_timer_t ppcemb_timer_t; |
335 | 636aaad7 | j_mayer | struct ppcemb_timer_t {
|
336 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
337 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
338 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
339 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
340 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
341 | 636aaad7 | j_mayer | }; |
342 | 636aaad7 | j_mayer | |
343 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
344 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
345 | 636aaad7 | j_mayer | { |
346 | 636aaad7 | j_mayer | CPUState *env; |
347 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
348 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
349 | 636aaad7 | j_mayer | uint64_t now, next; |
350 | 636aaad7 | j_mayer | |
351 | 636aaad7 | j_mayer | env = opaque; |
352 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
353 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
354 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
355 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
356 | 636aaad7 | j_mayer | case 0: |
357 | 636aaad7 | j_mayer | next = 1 << 9; |
358 | 636aaad7 | j_mayer | break;
|
359 | 636aaad7 | j_mayer | case 1: |
360 | 636aaad7 | j_mayer | next = 1 << 13; |
361 | 636aaad7 | j_mayer | break;
|
362 | 636aaad7 | j_mayer | case 2: |
363 | 636aaad7 | j_mayer | next = 1 << 17; |
364 | 636aaad7 | j_mayer | break;
|
365 | 636aaad7 | j_mayer | case 3: |
366 | 636aaad7 | j_mayer | next = 1 << 21; |
367 | 636aaad7 | j_mayer | break;
|
368 | 636aaad7 | j_mayer | default:
|
369 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
370 | 636aaad7 | j_mayer | return;
|
371 | 636aaad7 | j_mayer | } |
372 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
373 | 636aaad7 | j_mayer | if (next == now)
|
374 | 636aaad7 | j_mayer | next++; |
375 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
376 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
377 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
378 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
379 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
380 | 636aaad7 | j_mayer | if (loglevel) {
|
381 | 636aaad7 | j_mayer | fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
|
382 | 636aaad7 | j_mayer | (env->spr[SPR_40x_TCR] >> 23) & 0x1, |
383 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
384 | 636aaad7 | j_mayer | } |
385 | 636aaad7 | j_mayer | } |
386 | 636aaad7 | j_mayer | |
387 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
388 | 636aaad7 | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
389 | 76a66253 | j_mayer | { |
390 | 636aaad7 | j_mayer | CPUState *env; |
391 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
392 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
393 | 636aaad7 | j_mayer | uint64_t now, next; |
394 | 636aaad7 | j_mayer | |
395 | 636aaad7 | j_mayer | env = opaque; |
396 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
397 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
398 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
399 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) { |
400 | 636aaad7 | j_mayer | /* Auto reload */
|
401 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
402 | 636aaad7 | j_mayer | ticks_per_sec, tb_env->tb_freq); |
403 | 636aaad7 | j_mayer | if (next == now)
|
404 | 636aaad7 | j_mayer | next++; |
405 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
406 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
407 | 636aaad7 | j_mayer | } |
408 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
409 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
410 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
411 | 636aaad7 | j_mayer | if (loglevel) {
|
412 | 636aaad7 | j_mayer | fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
|
413 | 636aaad7 | j_mayer | (env->spr[SPR_40x_TCR] >> 22) & 0x1, |
414 | 636aaad7 | j_mayer | (env->spr[SPR_40x_TCR] >> 26) & 0x1, |
415 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
416 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload); |
417 | 636aaad7 | j_mayer | } |
418 | 636aaad7 | j_mayer | } |
419 | 636aaad7 | j_mayer | |
420 | 636aaad7 | j_mayer | /* Watchdog timer */
|
421 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
422 | 636aaad7 | j_mayer | { |
423 | 636aaad7 | j_mayer | CPUState *env; |
424 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
425 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
426 | 636aaad7 | j_mayer | uint64_t now, next; |
427 | 636aaad7 | j_mayer | |
428 | 636aaad7 | j_mayer | env = opaque; |
429 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
430 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
431 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
432 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
433 | 636aaad7 | j_mayer | case 0: |
434 | 636aaad7 | j_mayer | next = 1 << 17; |
435 | 636aaad7 | j_mayer | break;
|
436 | 636aaad7 | j_mayer | case 1: |
437 | 636aaad7 | j_mayer | next = 1 << 21; |
438 | 636aaad7 | j_mayer | break;
|
439 | 636aaad7 | j_mayer | case 2: |
440 | 636aaad7 | j_mayer | next = 1 << 25; |
441 | 636aaad7 | j_mayer | break;
|
442 | 636aaad7 | j_mayer | case 3: |
443 | 636aaad7 | j_mayer | next = 1 << 29; |
444 | 636aaad7 | j_mayer | break;
|
445 | 636aaad7 | j_mayer | default:
|
446 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
447 | 636aaad7 | j_mayer | return;
|
448 | 636aaad7 | j_mayer | } |
449 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
450 | 636aaad7 | j_mayer | if (next == now)
|
451 | 636aaad7 | j_mayer | next++; |
452 | 636aaad7 | j_mayer | if (loglevel) {
|
453 | 636aaad7 | j_mayer | fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
|
454 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
455 | 636aaad7 | j_mayer | } |
456 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
457 | 636aaad7 | j_mayer | case 0x0: |
458 | 636aaad7 | j_mayer | case 0x1: |
459 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
460 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
461 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
462 | 636aaad7 | j_mayer | break;
|
463 | 636aaad7 | j_mayer | case 0x2: |
464 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
465 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
466 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
467 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
468 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
469 | 636aaad7 | j_mayer | break;
|
470 | 636aaad7 | j_mayer | case 0x3: |
471 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
472 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
473 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
474 | 636aaad7 | j_mayer | case 0x0: |
475 | 636aaad7 | j_mayer | /* No reset */
|
476 | 636aaad7 | j_mayer | break;
|
477 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
478 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
479 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
480 | 636aaad7 | j_mayer | qemu_system_reset_request(); |
481 | 636aaad7 | j_mayer | return;
|
482 | 636aaad7 | j_mayer | } |
483 | 636aaad7 | j_mayer | } |
484 | 76a66253 | j_mayer | } |
485 | 76a66253 | j_mayer | |
486 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
487 | 76a66253 | j_mayer | { |
488 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
489 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
490 | 636aaad7 | j_mayer | uint64_t now, next; |
491 | 636aaad7 | j_mayer | |
492 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
493 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
494 | 636aaad7 | j_mayer | if (loglevel)
|
495 | 636aaad7 | j_mayer | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
496 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
497 | 636aaad7 | j_mayer | if (val == 0) { |
498 | 636aaad7 | j_mayer | /* Stop PIT */
|
499 | 636aaad7 | j_mayer | if (loglevel)
|
500 | 636aaad7 | j_mayer | fprintf(logfile, "%s: stop PIT\n", __func__);
|
501 | 636aaad7 | j_mayer | qemu_del_timer(tb_env->decr_timer); |
502 | 636aaad7 | j_mayer | } else {
|
503 | 636aaad7 | j_mayer | if (loglevel)
|
504 | 636aaad7 | j_mayer | fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
|
505 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
506 | 636aaad7 | j_mayer | next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq); |
507 | 636aaad7 | j_mayer | if (next == now)
|
508 | 636aaad7 | j_mayer | next++; |
509 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
510 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
511 | 636aaad7 | j_mayer | } |
512 | 76a66253 | j_mayer | } |
513 | 76a66253 | j_mayer | |
514 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
515 | 76a66253 | j_mayer | { |
516 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
517 | 76a66253 | j_mayer | } |
518 | 76a66253 | j_mayer | |
519 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
520 | 76a66253 | j_mayer | { |
521 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] = val & 0xFC000000;
|
522 | 636aaad7 | j_mayer | } |
523 | 636aaad7 | j_mayer | |
524 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
525 | 636aaad7 | j_mayer | { |
526 | 636aaad7 | j_mayer | /* We don't update timers now. Maybe we should... */
|
527 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFF800000;
|
528 | 636aaad7 | j_mayer | } |
529 | 636aaad7 | j_mayer | |
530 | 636aaad7 | j_mayer | void ppc_emb_timers_init (CPUState *env)
|
531 | 636aaad7 | j_mayer | { |
532 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
533 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
534 | 636aaad7 | j_mayer | |
535 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
536 | 636aaad7 | j_mayer | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
537 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
538 | 636aaad7 | j_mayer | if (loglevel)
|
539 | 636aaad7 | j_mayer | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
540 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
541 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
542 | 636aaad7 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
543 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
544 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
545 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
546 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
547 | 636aaad7 | j_mayer | } |
548 | 76a66253 | j_mayer | } |
549 | 76a66253 | j_mayer | |
550 | 9fddaa0c | bellard | #if 0
|
551 | 9fddaa0c | bellard | /*****************************************************************************/
|
552 | 9fddaa0c | bellard | /* Handle system reset (for now, just stop emulation) */
|
553 | 9fddaa0c | bellard | void cpu_ppc_reset (CPUState *env)
|
554 | 9fddaa0c | bellard | {
|
555 | 9fddaa0c | bellard | printf("Reset asked... Stop emulation\n");
|
556 | 9fddaa0c | bellard | abort();
|
557 | 9fddaa0c | bellard | }
|
558 | 9fddaa0c | bellard | #endif
|
559 | 9fddaa0c | bellard | |
560 | 64201201 | bellard | /*****************************************************************************/
|
561 | 64201201 | bellard | /* Debug port */
|
562 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
563 | 64201201 | bellard | { |
564 | 64201201 | bellard | addr &= 0xF;
|
565 | 64201201 | bellard | switch (addr) {
|
566 | 64201201 | bellard | case 0: |
567 | 64201201 | bellard | printf("%c", val);
|
568 | 64201201 | bellard | break;
|
569 | 64201201 | bellard | case 1: |
570 | 64201201 | bellard | printf("\n");
|
571 | 64201201 | bellard | fflush(stdout); |
572 | 64201201 | bellard | break;
|
573 | 64201201 | bellard | case 2: |
574 | 64201201 | bellard | printf("Set loglevel to %04x\n", val);
|
575 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
576 | 64201201 | bellard | break;
|
577 | 64201201 | bellard | } |
578 | 64201201 | bellard | } |
579 | 64201201 | bellard | |
580 | 64201201 | bellard | /*****************************************************************************/
|
581 | 64201201 | bellard | /* NVRAM helpers */
|
582 | 64201201 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
583 | 64201201 | bellard | { |
584 | 819385c5 | bellard | m48t59_write(nvram, addr, value); |
585 | 64201201 | bellard | } |
586 | 64201201 | bellard | |
587 | 64201201 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
588 | 64201201 | bellard | { |
589 | 819385c5 | bellard | return m48t59_read(nvram, addr);
|
590 | 64201201 | bellard | } |
591 | 64201201 | bellard | |
592 | 64201201 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
593 | 64201201 | bellard | { |
594 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 8);
|
595 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, value & 0xFF); |
596 | 64201201 | bellard | } |
597 | 64201201 | bellard | |
598 | 64201201 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
599 | 64201201 | bellard | { |
600 | 64201201 | bellard | uint16_t tmp; |
601 | 64201201 | bellard | |
602 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 8;
|
603 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1);
|
604 | 64201201 | bellard | return tmp;
|
605 | 64201201 | bellard | } |
606 | 64201201 | bellard | |
607 | 64201201 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
608 | 64201201 | bellard | { |
609 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 24);
|
610 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
611 | 819385c5 | bellard | m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
612 | 819385c5 | bellard | m48t59_write(nvram, addr + 3, value & 0xFF); |
613 | 64201201 | bellard | } |
614 | 64201201 | bellard | |
615 | 64201201 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
616 | 64201201 | bellard | { |
617 | 64201201 | bellard | uint32_t tmp; |
618 | 64201201 | bellard | |
619 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 24;
|
620 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1) << 16; |
621 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 2) << 8; |
622 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 3);
|
623 | 76a66253 | j_mayer | |
624 | 64201201 | bellard | return tmp;
|
625 | 64201201 | bellard | } |
626 | 64201201 | bellard | |
627 | 64201201 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
628 | 64201201 | bellard | const unsigned char *str, uint32_t max) |
629 | 64201201 | bellard | { |
630 | 64201201 | bellard | int i;
|
631 | 64201201 | bellard | |
632 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
633 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
634 | 64201201 | bellard | } |
635 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
636 | 64201201 | bellard | } |
637 | 64201201 | bellard | |
638 | 64201201 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
639 | 64201201 | bellard | { |
640 | 64201201 | bellard | int i;
|
641 | 64201201 | bellard | |
642 | 64201201 | bellard | memset(dst, 0, max);
|
643 | 64201201 | bellard | for (i = 0; i < max; i++) { |
644 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
645 | 64201201 | bellard | if (dst[i] == '\0') |
646 | 64201201 | bellard | break;
|
647 | 64201201 | bellard | } |
648 | 64201201 | bellard | |
649 | 64201201 | bellard | return i;
|
650 | 64201201 | bellard | } |
651 | 64201201 | bellard | |
652 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
653 | 64201201 | bellard | { |
654 | 64201201 | bellard | uint16_t tmp; |
655 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
656 | 64201201 | bellard | |
657 | 64201201 | bellard | tmp = prev >> 8;
|
658 | 64201201 | bellard | pd = prev ^ value; |
659 | 64201201 | bellard | pd1 = pd & 0x000F;
|
660 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
661 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
662 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
663 | 64201201 | bellard | |
664 | 64201201 | bellard | return tmp;
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665 | 64201201 | bellard | } |
666 | 64201201 | bellard | |
667 | 64201201 | bellard | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
668 | 64201201 | bellard | { |
669 | 64201201 | bellard | uint32_t i; |
670 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
671 | 64201201 | bellard | int odd;
|
672 | 64201201 | bellard | |
673 | 64201201 | bellard | odd = count & 1;
|
674 | 64201201 | bellard | count &= ~1;
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675 | 64201201 | bellard | for (i = 0; i != count; i++) { |
676 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
677 | 64201201 | bellard | } |
678 | 64201201 | bellard | if (odd) {
|
679 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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680 | 64201201 | bellard | } |
681 | 64201201 | bellard | |
682 | 64201201 | bellard | return crc;
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683 | 64201201 | bellard | } |
684 | 64201201 | bellard | |
685 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
686 | fd0bbb12 | bellard | |
687 | 64201201 | bellard | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
688 | 64201201 | bellard | const unsigned char *arch, |
689 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
690 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
691 | fd0bbb12 | bellard | const char *cmdline, |
692 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
693 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
694 | fd0bbb12 | bellard | int width, int height, int depth) |
695 | 64201201 | bellard | { |
696 | 64201201 | bellard | uint16_t crc; |
697 | 64201201 | bellard | |
698 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
699 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
700 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
701 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
702 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
703 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
704 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
705 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
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706 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
707 | fd0bbb12 | bellard | if (cmdline) {
|
708 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
709 | fd0bbb12 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
710 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
711 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
712 | fd0bbb12 | bellard | } else {
|
713 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
714 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
715 | fd0bbb12 | bellard | } |
716 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
717 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
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718 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
719 | fd0bbb12 | bellard | |
720 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
721 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
722 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
723 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
724 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0xFC, crc);
|
725 | 64201201 | bellard | |
726 | 64201201 | bellard | return 0; |
727 | a541f297 | bellard | } |