Archipelago » qemu

/*

 *  PowerPC CPU initialization for qemu.

 * 

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

/* A lot of PowerPC definition have been included here.

 * Most of them are not usable for now but have been kept

 * inside "#if defined(TODO) ... #endif" statements to make tests easier.

 */

//#define PPC_DUMP_CPU

//#define PPC_DEBUG_SPR

struct ppc_def_t {

    const unsigned char *name;

    uint32_t pvr;

    uint32_t pvr_mask;

    uint64_t insns_flags;

    uint32_t flags;

    uint64_t msr_mask;

};

/* For user-mode emulation, we don't emulate any IRQ controller */

#if defined(CONFIG_USER_ONLY)

#define PPC_IRQ_INIT_FN(name)                                         \

static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \

{                                                                     \

}

#else

#define PPC_IRQ_INIT_FN(name)                                         \

void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);

#endif

PPC_IRQ_INIT_FN(6xx);

/* Generic callbacks:

 * do nothing but store/retrieve spr value

 */

static void spr_read_generic (void *opaque, int sprn)

{

    gen_op_load_spr(sprn);

}

static void spr_write_generic (void *opaque, int sprn)

{

    gen_op_store_spr(sprn);

}

/* SPR common to all PowerPC */

/* XER */

static void spr_read_xer (void *opaque, int sprn)

{

    gen_op_load_xer();

}

static void spr_write_xer (void *opaque, int sprn)

{

    gen_op_store_xer();

}

/* LR */

static void spr_read_lr (void *opaque, int sprn)

{

    gen_op_load_lr();

}

static void spr_write_lr (void *opaque, int sprn)

{

    gen_op_store_lr();

}

/* CTR */

static void spr_read_ctr (void *opaque, int sprn)

{

    gen_op_load_ctr();

}

static void spr_write_ctr (void *opaque, int sprn)

{

    gen_op_store_ctr();

}

/* User read access to SPR */

/* USPRx */

/* UMMCRx */

/* UPMCx */

/* USIA */

/* UDECR */

static void spr_read_ureg (void *opaque, int sprn)

{

    gen_op_load_spr(sprn + 0x10);

}

/* SPR common to all non-embedded PowerPC */

/* DECR */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_decr (void *opaque, int sprn)

{

    gen_op_load_decr();

}

static void spr_write_decr (void *opaque, int sprn)

{

    gen_op_store_decr();

}

#endif

/* SPR common to all non-embedded PowerPC, except 601 */

/* Time base */

static void spr_read_tbl (void *opaque, int sprn)

{

    gen_op_load_tbl();

}

static void spr_read_tbu (void *opaque, int sprn)

{

    gen_op_load_tbu();

}

#if !defined(CONFIG_USER_ONLY)

static void spr_write_tbl (void *opaque, int sprn)

{

    gen_op_store_tbl();

}

static void spr_write_tbu (void *opaque, int sprn)

{

    gen_op_store_tbu();

}

#endif

#if !defined(CONFIG_USER_ONLY)

/* IBAT0U...IBAT0U */

/* IBAT0L...IBAT7L */

static void spr_read_ibat (void *opaque, int sprn)

{

    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);

}

static void spr_read_ibat_h (void *opaque, int sprn)

{

    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);

}

static void spr_write_ibatu (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);

    RET_STOP(ctx);

}

static void spr_write_ibatu_h (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);

    RET_STOP(ctx);

}

static void spr_write_ibatl (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);

    RET_STOP(ctx);

}

static void spr_write_ibatl_h (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);

    RET_STOP(ctx);

}

/* DBAT0U...DBAT7U */

/* DBAT0L...DBAT7L */

static void spr_read_dbat (void *opaque, int sprn)

{

    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);

}

static void spr_read_dbat_h (void *opaque, int sprn)

{

    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);

}

static void spr_write_dbatu (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);

    RET_STOP(ctx);

}

static void spr_write_dbatu_h (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);

    RET_STOP(ctx);

}

static void spr_write_dbatl (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);

    RET_STOP(ctx);

}

static void spr_write_dbatl_h (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);

    RET_STOP(ctx);

}

/* SDR1 */

static void spr_read_sdr1 (void *opaque, int sprn)

{

    gen_op_load_sdr1();

}

static void spr_write_sdr1 (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_sdr1();

    RET_STOP(ctx);

}

/* 64 bits PowerPC specific SPRs */

/* ASR */

#if defined(TARGET_PPC64)

static void spr_read_asr (void *opaque, int sprn)

{

    gen_op_load_asr();

}

static void spr_write_asr (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_asr();

    RET_STOP(ctx);

}

#endif

#endif /* !defined(CONFIG_USER_ONLY) */

/* PowerPC 601 specific registers */

/* RTC */

static void spr_read_601_rtcl (void *opaque, int sprn)

{

    gen_op_load_601_rtcl();

}

static void spr_read_601_rtcu (void *opaque, int sprn)

{

    gen_op_load_601_rtcu();

}

#if !defined(CONFIG_USER_ONLY)

static void spr_write_601_rtcu (void *opaque, int sprn)

{

    gen_op_store_601_rtcu();

}

static void spr_write_601_rtcl (void *opaque, int sprn)

{

    gen_op_store_601_rtcl();

}

#endif

/* Unified bats */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_601_ubat (void *opaque, int sprn)

{

    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);

}

static void spr_write_601_ubatu (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);

    RET_STOP(ctx);

}

static void spr_write_601_ubatl (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);

    RET_STOP(ctx);

}

#endif

/* PowerPC 40x specific registers */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_40x_pit (void *opaque, int sprn)

{

    gen_op_load_40x_pit();

}

static void spr_write_40x_pit (void *opaque, int sprn)

{

    gen_op_store_40x_pit();

}

static void spr_write_booke_tcr (void *opaque, int sprn)

{

    gen_op_store_booke_tcr();

}

static void spr_write_booke_tsr (void *opaque, int sprn)

{

    gen_op_store_booke_tsr();

}

#endif

/* PowerPC 403 specific registers */

/* PBL1 / PBU1 / PBL2 / PBU2 */

#if !defined(CONFIG_USER_ONLY)

static void spr_read_403_pbr (void *opaque, int sprn)

{

    gen_op_load_403_pb(sprn - SPR_403_PBL1);

}

static void spr_write_403_pbr (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_403_pb(sprn - SPR_403_PBL1);

    RET_STOP(ctx);

}

static void spr_write_pir (void *opaque, int sprn)

{

    gen_op_store_pir();

}

#endif

#if defined(CONFIG_USER_ONLY)

#define spr_register(env, num, name, uea_read, uea_write,                     \

                     oea_read, oea_write, initial_value)                      \

do {                                                                          \

     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \

} while (0)

static inline void _spr_register (CPUPPCState *env, int num,

                                  const unsigned char *name,

                                  void (*uea_read)(void *opaque, int sprn),

                                  void (*uea_write)(void *opaque, int sprn),

                                  target_ulong initial_value)

#else

static inline void spr_register (CPUPPCState *env, int num,

                                 const unsigned char *name,

                                 void (*uea_read)(void *opaque, int sprn),

                                 void (*uea_write)(void *opaque, int sprn),

                                 void (*oea_read)(void *opaque, int sprn),

                                 void (*oea_write)(void *opaque, int sprn),

                                 target_ulong initial_value)

#endif

{

    ppc_spr_t *spr;

    spr = &env->spr_cb[num];

    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||

#if !defined(CONFIG_USER_ONLY)

        spr->oea_read != NULL || spr->oea_write != NULL ||

#endif

        spr->uea_read != NULL || spr->uea_write != NULL) {

        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);

        exit(1);

    }

#if defined(PPC_DEBUG_SPR)

    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,

           initial_value);

#endif

    spr->name = name;

    spr->uea_read = uea_read;

    spr->uea_write = uea_write;

#if !defined(CONFIG_USER_ONLY)

    spr->oea_read = oea_read;

    spr->oea_write = oea_write;

#endif

    env->spr[num] = initial_value;

}

/* Generic PowerPC SPRs */

static void gen_spr_generic (CPUPPCState *env)

{

    /* Integer processing */

    spr_register(env, SPR_XER, "XER",

                 &spr_read_xer, &spr_write_xer,

                 &spr_read_xer, &spr_write_xer,

                 0x00000000);

    /* Branch contol */

    spr_register(env, SPR_LR, "LR",

                 &spr_read_lr, &spr_write_lr,

                 &spr_read_lr, &spr_write_lr,

                 0x00000000);

    spr_register(env, SPR_CTR, "CTR",

                 &spr_read_ctr, &spr_write_ctr,

                 &spr_read_ctr, &spr_write_ctr,

                 0x00000000);

    /* Interrupt processing */

    spr_register(env, SPR_SRR0, "SRR0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SRR1, "SRR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Processor control */

    spr_register(env, SPR_SPRG0, "SPRG0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG1, "SPRG1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG2, "SPRG2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG3, "SPRG3",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR common to all non-embedded PowerPC, including 601 */

static void gen_spr_ne_601 (CPUPPCState *env)

{

    /* Exception processing */

    spr_register(env, SPR_DSISR, "DSISR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_DAR, "DAR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Timer */

    spr_register(env, SPR_DECR, "DECR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_decr, &spr_write_decr,

                 0x00000000);

    /* Memory management */

    spr_register(env, SPR_SDR1, "SDR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_sdr1, &spr_write_sdr1,

                 0x00000000);

}

/* BATs 0-3 */

static void gen_low_BATs (CPUPPCState *env)

{

    spr_register(env, SPR_IBAT0U, "IBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT0L, "IBAT0L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT1U, "IBAT1U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT1L, "IBAT1L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT2U, "IBAT2U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT2L, "IBAT2L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_IBAT3U, "IBAT3U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 0x00000000);

    spr_register(env, SPR_IBAT3L, "IBAT3L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatl,

                 0x00000000);

    spr_register(env, SPR_DBAT0U, "DBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT0L, "DBAT0L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT1U, "DBAT1U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT1L, "DBAT1L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT2U, "DBAT2U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT2L, "DBAT2L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    spr_register(env, SPR_DBAT3U, "DBAT3U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatu,

                 0x00000000);

    spr_register(env, SPR_DBAT3L, "DBAT3L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    env->nb_BATs = 4;

}

/* BATs 4-7 */

static void gen_high_BATs (CPUPPCState *env)

{

    spr_register(env, SPR_IBAT4U, "IBAT4U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT4L, "IBAT4L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT5U, "IBAT5U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT5L, "IBAT5L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT6U, "IBAT6U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT6L, "IBAT6L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_IBAT7U, "IBAT7U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 0x00000000);

    spr_register(env, SPR_IBAT7L, "IBAT7L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT4U, "DBAT4U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT4L, "DBAT4L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT5U, "DBAT5U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT5L, "DBAT5L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT6U, "DBAT6U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT6L, "DBAT6L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    spr_register(env, SPR_DBAT7U, "DBAT7U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatu_h,

                 0x00000000);

    spr_register(env, SPR_DBAT7L, "DBAT7L",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    env->nb_BATs = 8;

}

/* Generic PowerPC time base */

static void gen_tbl (CPUPPCState *env)

{

    spr_register(env, SPR_VTBL,  "TBL",

                 &spr_read_tbl, SPR_NOACCESS,

                 &spr_read_tbl, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_TBL,   "TBL",

                 SPR_NOACCESS, SPR_NOACCESS,

                 SPR_NOACCESS, &spr_write_tbl,

                 0x00000000);

    spr_register(env, SPR_VTBU,  "TBU",

                 &spr_read_tbu, SPR_NOACCESS,

                 &spr_read_tbu, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_TBU,   "TBU",

                 SPR_NOACCESS, SPR_NOACCESS,

                 SPR_NOACCESS, &spr_write_tbu,

                 0x00000000);

}

/* Softare table search registers */

static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)

{

    env->nb_tlb = nb_tlbs;

    env->nb_ways = nb_ways;

    env->id_tlbs = 1;

    spr_register(env, SPR_DMISS, "DMISS",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_DCMP, "DCMP",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_HASH1, "HASH1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_HASH2, "HASH2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_IMISS, "IMISS",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_ICMP, "ICMP",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_RPA, "RPA",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR common to MPC755 and G2 */

static void gen_spr_G2_755 (CPUPPCState *env)

{

    /* SGPRs */

    spr_register(env, SPR_SPRG4, "SPRG4",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG5, "SPRG5",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG6, "SPRG6",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    spr_register(env, SPR_SPRG7, "SPRG7",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* External access control */

    /* XXX : not implemented */

    spr_register(env, SPR_EAR, "EAR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR common to all 7xx PowerPC implementations */

static void gen_spr_7xx (CPUPPCState *env)

{

    /* Breakpoints */

    /* XXX : not implemented */

    spr_register(env, SPR_DABR, "DABR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_IABR, "IABR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Cache management */

    /* XXX : not implemented */

    spr_register(env, SPR_ICTC, "ICTC",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_L2CR, "L2CR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Performance monitors */

    /* XXX : not implemented */

    spr_register(env, SPR_MMCR0, "MMCR0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_MMCR1, "MMCR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC1, "PMC1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC2, "PMC2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC3, "PMC3",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC4, "PMC4",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_SIA, "SIA",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UMMCR0, "UMMCR0",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UMMCR1, "UMMCR1",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UPMC1, "UPMC1",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UPMC2, "UPMC2",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UPMC3, "UPMC3",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_UPMC4, "UPMC4",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    spr_register(env, SPR_USIA, "USIA",

                 &spr_read_ureg, SPR_NOACCESS,

                 &spr_read_ureg, SPR_NOACCESS,

                 0x00000000);

    /* Thermal management */

    /* XXX : not implemented */

    spr_register(env, SPR_THRM1, "THRM1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_THRM2, "THRM2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_THRM3, "THRM3",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* External access control */

    /* XXX : not implemented */

    spr_register(env, SPR_EAR, "EAR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR specific to PowerPC 604 implementation */

static void gen_spr_604 (CPUPPCState *env)

{

    /* Processor identification */

    spr_register(env, SPR_PIR, "PIR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_pir,

                 0x00000000);

    /* Breakpoints */

    /* XXX : not implemented */

    spr_register(env, SPR_IABR, "IABR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_DABR, "DABR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Performance counters */

    /* XXX : not implemented */

    spr_register(env, SPR_MMCR0, "MMCR0",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_MMCR1, "MMCR1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC1, "PMC1",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC2, "PMC2",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC3, "PMC3",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_PMC4, "PMC4",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_SIA, "SIA",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    /* XXX : not implemented */

    spr_register(env, SPR_SDA, "SDA",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, SPR_NOACCESS,

                 0x00000000);

    /* External access control */

    /* XXX : not implemented */

    spr_register(env, SPR_EAR, "EAR",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);