Revision e9df014c vl.h
| b/vl.h | ||
|---|---|---|
| 854 | 854 |
int piix4_init(PCIBus *bus, int devfn); |
| 855 | 855 |
|
| 856 | 856 |
/* openpic.c */ |
| 857 |
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ |
|
| 857 | 858 |
enum {
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OPENPIC_EVT_INT = 0, /* IRQ */ |
|
| 859 |
OPENPIC_EVT_CINT, /* critical IRQ */ |
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| 860 |
OPENPIC_EVT_MCK, /* Machine check event */ |
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| 861 |
OPENPIC_EVT_DEBUG, /* Inconditional debug event */ |
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| 862 |
OPENPIC_EVT_RESET, /* Core reset event */ |
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OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
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OPENPIC_OUTPUT_CINT, /* critical IRQ */ |
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| 861 |
OPENPIC_OUTPUT_MCK, /* Machine check event */ |
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ |
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OPENPIC_OUTPUT_RESET, /* Core reset event */ |
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OPENPIC_OUTPUT_NB, |
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| 863 | 865 |
}; |
| 864 |
qemu_irq *openpic_init (PCIBus *bus, SetIRQFunc *set_irq, |
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| 865 |
int *pmem_index, int nb_cpus, |
|
| 866 |
struct CPUState **envp); |
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| 866 |
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
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| 867 |
qemu_irq **irqs, qemu_irq irq_out); |
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| 867 | 868 |
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| 868 | 869 |
/* heathrow_pic.c */ |
| 869 | 870 |
qemu_irq *heathrow_pic_init(int *pmem_index); |
| ... | ... | |
| 1145 | 1146 |
|
| 1146 | 1147 |
#ifdef TARGET_PPC |
| 1147 | 1148 |
/* PowerPC hardware exceptions management helpers */ |
| 1148 |
void cpu_ppc_irq_init_cpu(CPUState *env); |
|
| 1149 |
void ppc_openpic_irq (void *opaque, int n_IRQ, int level); |
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| 1150 |
int ppc_hw_interrupt (CPUState *env); |
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| 1151 | 1149 |
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
| 1152 | 1150 |
#endif |
| 1153 | 1151 |
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
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