root / target-ppc / translate_init.c @ e9df014c
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/*
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* PowerPC CPU initialization for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* A lot of PowerPC definition have been included here.
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* Most of them are not usable for now but have been kept
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* inside "#if defined(TODO) ... #endif" statements to make tests easier.
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*/
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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struct ppc_def_t {
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const unsigned char *name; |
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uint32_t pvr; |
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uint32_t pvr_mask; |
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uint64_t insns_flags; |
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uint32_t flags; |
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uint64_t msr_mask; |
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}; |
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/* For user-mode emulation, we don't emulate any IRQ controller */
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#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name) \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
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{ \ |
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} |
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#else
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#define PPC_IRQ_INIT_FN(name) \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(6xx);
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/* Generic callbacks:
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* do nothing but store/retrieve spr value
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*/
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static void spr_read_generic (void *opaque, int sprn) |
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{ |
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gen_op_load_spr(sprn); |
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} |
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static void spr_write_generic (void *opaque, int sprn) |
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{ |
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gen_op_store_spr(sprn); |
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} |
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int sprn) |
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{ |
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gen_op_load_xer(); |
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} |
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static void spr_write_xer (void *opaque, int sprn) |
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{ |
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gen_op_store_xer(); |
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} |
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/* LR */
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static void spr_read_lr (void *opaque, int sprn) |
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{ |
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gen_op_load_lr(); |
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} |
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static void spr_write_lr (void *opaque, int sprn) |
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{ |
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gen_op_store_lr(); |
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} |
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/* CTR */
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static void spr_read_ctr (void *opaque, int sprn) |
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{ |
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gen_op_load_ctr(); |
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} |
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static void spr_write_ctr (void *opaque, int sprn) |
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{ |
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gen_op_store_ctr(); |
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} |
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/* User read access to SPR */
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/* USPRx */
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/* UMMCRx */
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int sprn) |
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{ |
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gen_op_load_spr(sprn + 0x10);
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} |
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int sprn) |
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{ |
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gen_op_load_decr(); |
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} |
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static void spr_write_decr (void *opaque, int sprn) |
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{ |
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gen_op_store_decr(); |
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} |
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int sprn) |
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{ |
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gen_op_load_tbl(); |
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} |
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static void spr_read_tbu (void *opaque, int sprn) |
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{ |
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gen_op_load_tbu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn) |
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{ |
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gen_op_store_tbl(); |
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} |
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static void spr_write_tbu (void *opaque, int sprn) |
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{ |
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gen_op_store_tbu(); |
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} |
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/* IBAT0U...IBAT0U */
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat (void *opaque, int sprn) |
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{ |
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_read_ibat_h (void *opaque, int sprn) |
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{ |
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2); |
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} |
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static void spr_write_ibatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatu_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* DBAT0U...DBAT7U */
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat (void *opaque, int sprn) |
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{ |
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2); |
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} |
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static void spr_read_dbat_h (void *opaque, int sprn) |
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{ |
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2); |
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} |
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static void spr_write_dbatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatu_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl_h (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* SDR1 */
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static void spr_read_sdr1 (void *opaque, int sprn) |
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{ |
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gen_op_load_sdr1(); |
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} |
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static void spr_write_sdr1 (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_sdr1(); |
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RET_STOP(ctx); |
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} |
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/* 64 bits PowerPC specific SPRs */
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/* ASR */
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#if defined(TARGET_PPC64)
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static void spr_read_asr (void *opaque, int sprn) |
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{ |
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gen_op_load_asr(); |
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} |
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static void spr_write_asr (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_asr(); |
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RET_STOP(ctx); |
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} |
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#endif
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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/* PowerPC 601 specific registers */
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/* RTC */
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static void spr_read_601_rtcl (void *opaque, int sprn) |
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{ |
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gen_op_load_601_rtcl(); |
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} |
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static void spr_read_601_rtcu (void *opaque, int sprn) |
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{ |
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gen_op_load_601_rtcu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_601_rtcu (void *opaque, int sprn) |
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{ |
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gen_op_store_601_rtcu(); |
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} |
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static void spr_write_601_rtcl (void *opaque, int sprn) |
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{ |
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gen_op_store_601_rtcl(); |
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} |
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#endif
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/* Unified bats */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_601_ubat (void *opaque, int sprn) |
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{ |
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gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_write_601_ubatu (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_601_ubatl (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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#endif
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/* PowerPC 40x specific registers */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_40x_pit (void *opaque, int sprn) |
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{ |
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gen_op_load_40x_pit(); |
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} |
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static void spr_write_40x_pit (void *opaque, int sprn) |
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{ |
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gen_op_store_40x_pit(); |
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} |
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static void spr_write_booke_tcr (void *opaque, int sprn) |
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{ |
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gen_op_store_booke_tcr(); |
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} |
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static void spr_write_booke_tsr (void *opaque, int sprn) |
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{ |
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gen_op_store_booke_tsr(); |
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} |
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#endif
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/* PowerPC 403 specific registers */
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/* PBL1 / PBU1 / PBL2 / PBU2 */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_403_pbr (void *opaque, int sprn) |
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{ |
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gen_op_load_403_pb(sprn - SPR_403_PBL1); |
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} |
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static void spr_write_403_pbr (void *opaque, int sprn) |
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{ |
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DisasContext *ctx = opaque; |
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gen_op_store_403_pb(sprn - SPR_403_PBL1); |
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RET_STOP(ctx); |
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} |
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static void spr_write_pir (void *opaque, int sprn) |
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{ |
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gen_op_store_pir(); |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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#define spr_register(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, initial_value) \ |
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do { \
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_spr_register(env, num, name, uea_read, uea_write, initial_value); \ |
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} while (0) |
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static inline void _spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#else
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static inline void spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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void (*oea_read)(void *opaque, int sprn), |
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void (*oea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#endif
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{ |
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ppc_spr_t *spr; |
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spr = &env->spr_cb[num]; |
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if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read != NULL || spr->oea_write != NULL || |
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#endif
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spr->uea_read != NULL || spr->uea_write != NULL) { |
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printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
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exit(1);
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} |
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#if defined(PPC_DEBUG_SPR)
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printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name, |
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initial_value); |
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#endif
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spr->name = name; |
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spr->uea_read = uea_read; |
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spr->uea_write = uea_write; |
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read = oea_read; |
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spr->oea_write = oea_write; |
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#endif
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env->spr[num] = initial_value; |
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} |
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/* Generic PowerPC SPRs */
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static void gen_spr_generic (CPUPPCState *env) |
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{ |
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/* Integer processing */
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spr_register(env, SPR_XER, "XER",
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&spr_read_xer, &spr_write_xer, |
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&spr_read_xer, &spr_write_xer, |
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0x00000000);
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/* Branch contol */
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spr_register(env, SPR_LR, "LR",
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&spr_read_lr, &spr_write_lr, |
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&spr_read_lr, &spr_write_lr, |
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0x00000000);
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spr_register(env, SPR_CTR, "CTR",
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&spr_read_ctr, &spr_write_ctr, |
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&spr_read_ctr, &spr_write_ctr, |
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0x00000000);
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/* Interrupt processing */
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spr_register(env, SPR_SRR0, "SRR0",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SRR1, "SRR1",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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/* Processor control */
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spr_register(env, SPR_SPRG0, "SPRG0",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG1, "SPRG1",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG2, "SPRG2",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG3, "SPRG3",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
448 |
0x00000000);
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} |
450 |
|
451 |
/* SPR common to all non-embedded PowerPC, including 601 */
|
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static void gen_spr_ne_601 (CPUPPCState *env) |
453 |
{ |
454 |
/* Exception processing */
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spr_register(env, SPR_DSISR, "DSISR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
457 |
&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_DAR, "DAR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
461 |
&spr_read_generic, &spr_write_generic, |
462 |
0x00000000);
|
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/* Timer */
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spr_register(env, SPR_DECR, "DECR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
466 |
&spr_read_decr, &spr_write_decr, |
467 |
0x00000000);
|
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/* Memory management */
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spr_register(env, SPR_SDR1, "SDR1",
|
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_sdr1, &spr_write_sdr1, |
472 |
0x00000000);
|
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} |
474 |
|
475 |
/* BATs 0-3 */
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static void gen_low_BATs (CPUPPCState *env) |
477 |
{ |
478 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
480 |
&spr_read_ibat, &spr_write_ibatu, |
481 |
0x00000000);
|
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spr_register(env, SPR_IBAT0L, "IBAT0L",
|
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_ibat, &spr_write_ibatl, |
485 |
0x00000000);
|
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spr_register(env, SPR_IBAT1U, "IBAT1U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
488 |
&spr_read_ibat, &spr_write_ibatu, |
489 |
0x00000000);
|
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spr_register(env, SPR_IBAT1L, "IBAT1L",
|
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SPR_NOACCESS, SPR_NOACCESS, |
492 |
&spr_read_ibat, &spr_write_ibatl, |
493 |
0x00000000);
|
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spr_register(env, SPR_IBAT2U, "IBAT2U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
496 |
&spr_read_ibat, &spr_write_ibatu, |
497 |
0x00000000);
|
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spr_register(env, SPR_IBAT2L, "IBAT2L",
|
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SPR_NOACCESS, SPR_NOACCESS, |
500 |
&spr_read_ibat, &spr_write_ibatl, |
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0x00000000);
|
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spr_register(env, SPR_IBAT3U, "IBAT3U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
504 |
&spr_read_ibat, &spr_write_ibatu, |
505 |
0x00000000);
|
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spr_register(env, SPR_IBAT3L, "IBAT3L",
|
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SPR_NOACCESS, SPR_NOACCESS, |
508 |
&spr_read_ibat, &spr_write_ibatl, |
509 |
0x00000000);
|
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spr_register(env, SPR_DBAT0U, "DBAT0U",
|
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SPR_NOACCESS, SPR_NOACCESS, |
512 |
&spr_read_dbat, &spr_write_dbatu, |
513 |
0x00000000);
|
514 |
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
515 |
SPR_NOACCESS, SPR_NOACCESS, |
516 |
&spr_read_dbat, &spr_write_dbatl, |
517 |
0x00000000);
|
518 |
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
519 |
SPR_NOACCESS, SPR_NOACCESS, |
520 |
&spr_read_dbat, &spr_write_dbatu, |
521 |
0x00000000);
|
522 |
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
523 |
SPR_NOACCESS, SPR_NOACCESS, |
524 |
&spr_read_dbat, &spr_write_dbatl, |
525 |
0x00000000);
|
526 |
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
527 |
SPR_NOACCESS, SPR_NOACCESS, |
528 |
&spr_read_dbat, &spr_write_dbatu, |
529 |
0x00000000);
|
530 |
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
531 |
SPR_NOACCESS, SPR_NOACCESS, |
532 |
&spr_read_dbat, &spr_write_dbatl, |
533 |
0x00000000);
|
534 |
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
535 |
SPR_NOACCESS, SPR_NOACCESS, |
536 |
&spr_read_dbat, &spr_write_dbatu, |
537 |
0x00000000);
|
538 |
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
539 |
SPR_NOACCESS, SPR_NOACCESS, |
540 |
&spr_read_dbat, &spr_write_dbatl, |
541 |
0x00000000);
|
542 |
env->nb_BATs = 4;
|
543 |
} |
544 |
|
545 |
/* BATs 4-7 */
|
546 |
static void gen_high_BATs (CPUPPCState *env) |
547 |
{ |
548 |
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
549 |
SPR_NOACCESS, SPR_NOACCESS, |
550 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
551 |
0x00000000);
|
552 |
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
553 |
SPR_NOACCESS, SPR_NOACCESS, |
554 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
555 |
0x00000000);
|
556 |
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
557 |
SPR_NOACCESS, SPR_NOACCESS, |
558 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
559 |
0x00000000);
|
560 |
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
561 |
SPR_NOACCESS, SPR_NOACCESS, |
562 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
563 |
0x00000000);
|
564 |
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
565 |
SPR_NOACCESS, SPR_NOACCESS, |
566 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
567 |
0x00000000);
|
568 |
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
569 |
SPR_NOACCESS, SPR_NOACCESS, |
570 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
571 |
0x00000000);
|
572 |
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
573 |
SPR_NOACCESS, SPR_NOACCESS, |
574 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
575 |
0x00000000);
|
576 |
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
577 |
SPR_NOACCESS, SPR_NOACCESS, |
578 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
579 |
0x00000000);
|
580 |
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
581 |
SPR_NOACCESS, SPR_NOACCESS, |
582 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
583 |
0x00000000);
|
584 |
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
585 |
SPR_NOACCESS, SPR_NOACCESS, |
586 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
587 |
0x00000000);
|
588 |
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
589 |
SPR_NOACCESS, SPR_NOACCESS, |
590 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
591 |
0x00000000);
|
592 |
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
593 |
SPR_NOACCESS, SPR_NOACCESS, |
594 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
595 |
0x00000000);
|
596 |
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
597 |
SPR_NOACCESS, SPR_NOACCESS, |
598 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
599 |
0x00000000);
|
600 |
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
601 |
SPR_NOACCESS, SPR_NOACCESS, |
602 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
603 |
0x00000000);
|
604 |
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
605 |
SPR_NOACCESS, SPR_NOACCESS, |
606 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
607 |
0x00000000);
|
608 |
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
609 |
SPR_NOACCESS, SPR_NOACCESS, |
610 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
611 |
0x00000000);
|
612 |
env->nb_BATs = 8;
|
613 |
} |
614 |
|
615 |
/* Generic PowerPC time base */
|
616 |
static void gen_tbl (CPUPPCState *env) |
617 |
{ |
618 |
spr_register(env, SPR_VTBL, "TBL",
|
619 |
&spr_read_tbl, SPR_NOACCESS, |
620 |
&spr_read_tbl, SPR_NOACCESS, |
621 |
0x00000000);
|
622 |
spr_register(env, SPR_TBL, "TBL",
|
623 |
SPR_NOACCESS, SPR_NOACCESS, |
624 |
SPR_NOACCESS, &spr_write_tbl, |
625 |
0x00000000);
|
626 |
spr_register(env, SPR_VTBU, "TBU",
|
627 |
&spr_read_tbu, SPR_NOACCESS, |
628 |
&spr_read_tbu, SPR_NOACCESS, |
629 |
0x00000000);
|
630 |
spr_register(env, SPR_TBU, "TBU",
|
631 |
SPR_NOACCESS, SPR_NOACCESS, |
632 |
SPR_NOACCESS, &spr_write_tbu, |
633 |
0x00000000);
|
634 |
} |
635 |
|
636 |
/* Softare table search registers */
|
637 |
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
638 |
{ |
639 |
env->nb_tlb = nb_tlbs; |
640 |
env->nb_ways = nb_ways; |
641 |
env->id_tlbs = 1;
|
642 |
spr_register(env, SPR_DMISS, "DMISS",
|
643 |
SPR_NOACCESS, SPR_NOACCESS, |
644 |
&spr_read_generic, SPR_NOACCESS, |
645 |
0x00000000);
|
646 |
spr_register(env, SPR_DCMP, "DCMP",
|
647 |
SPR_NOACCESS, SPR_NOACCESS, |
648 |
&spr_read_generic, SPR_NOACCESS, |
649 |
0x00000000);
|
650 |
spr_register(env, SPR_HASH1, "HASH1",
|
651 |
SPR_NOACCESS, SPR_NOACCESS, |
652 |
&spr_read_generic, SPR_NOACCESS, |
653 |
0x00000000);
|
654 |
spr_register(env, SPR_HASH2, "HASH2",
|
655 |
SPR_NOACCESS, SPR_NOACCESS, |
656 |
&spr_read_generic, SPR_NOACCESS, |
657 |
0x00000000);
|
658 |
spr_register(env, SPR_IMISS, "IMISS",
|
659 |
SPR_NOACCESS, SPR_NOACCESS, |
660 |
&spr_read_generic, SPR_NOACCESS, |
661 |
0x00000000);
|
662 |
spr_register(env, SPR_ICMP, "ICMP",
|
663 |
SPR_NOACCESS, SPR_NOACCESS, |
664 |
&spr_read_generic, SPR_NOACCESS, |
665 |
0x00000000);
|
666 |
spr_register(env, SPR_RPA, "RPA",
|
667 |
SPR_NOACCESS, SPR_NOACCESS, |
668 |
&spr_read_generic, &spr_write_generic, |
669 |
0x00000000);
|
670 |
} |
671 |
|
672 |
/* SPR common to MPC755 and G2 */
|
673 |
static void gen_spr_G2_755 (CPUPPCState *env) |
674 |
{ |
675 |
/* SGPRs */
|
676 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
677 |
SPR_NOACCESS, SPR_NOACCESS, |
678 |
&spr_read_generic, &spr_write_generic, |
679 |
0x00000000);
|
680 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
681 |
SPR_NOACCESS, SPR_NOACCESS, |
682 |
&spr_read_generic, &spr_write_generic, |
683 |
0x00000000);
|
684 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
685 |
SPR_NOACCESS, SPR_NOACCESS, |
686 |
&spr_read_generic, &spr_write_generic, |
687 |
0x00000000);
|
688 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
689 |
SPR_NOACCESS, SPR_NOACCESS, |
690 |
&spr_read_generic, &spr_write_generic, |
691 |
0x00000000);
|
692 |
/* External access control */
|
693 |
/* XXX : not implemented */
|
694 |
spr_register(env, SPR_EAR, "EAR",
|
695 |
SPR_NOACCESS, SPR_NOACCESS, |
696 |
&spr_read_generic, &spr_write_generic, |
697 |
0x00000000);
|
698 |
} |
699 |
|
700 |
/* SPR common to all 7xx PowerPC implementations */
|
701 |
static void gen_spr_7xx (CPUPPCState *env) |
702 |
{ |
703 |
/* Breakpoints */
|
704 |
/* XXX : not implemented */
|
705 |
spr_register(env, SPR_DABR, "DABR",
|
706 |
SPR_NOACCESS, SPR_NOACCESS, |
707 |
&spr_read_generic, &spr_write_generic, |
708 |
0x00000000);
|
709 |
/* XXX : not implemented */
|
710 |
spr_register(env, SPR_IABR, "IABR",
|
711 |
SPR_NOACCESS, SPR_NOACCESS, |
712 |
&spr_read_generic, &spr_write_generic, |
713 |
0x00000000);
|
714 |
/* Cache management */
|
715 |
/* XXX : not implemented */
|
716 |
spr_register(env, SPR_ICTC, "ICTC",
|
717 |
SPR_NOACCESS, SPR_NOACCESS, |
718 |
&spr_read_generic, &spr_write_generic, |
719 |
0x00000000);
|
720 |
/* XXX : not implemented */
|
721 |
spr_register(env, SPR_L2CR, "L2CR",
|
722 |
SPR_NOACCESS, SPR_NOACCESS, |
723 |
&spr_read_generic, &spr_write_generic, |
724 |
0x00000000);
|
725 |
/* Performance monitors */
|
726 |
/* XXX : not implemented */
|
727 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
728 |
SPR_NOACCESS, SPR_NOACCESS, |
729 |
&spr_read_generic, &spr_write_generic, |
730 |
0x00000000);
|
731 |
/* XXX : not implemented */
|
732 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
733 |
SPR_NOACCESS, SPR_NOACCESS, |
734 |
&spr_read_generic, &spr_write_generic, |
735 |
0x00000000);
|
736 |
/* XXX : not implemented */
|
737 |
spr_register(env, SPR_PMC1, "PMC1",
|
738 |
SPR_NOACCESS, SPR_NOACCESS, |
739 |
&spr_read_generic, &spr_write_generic, |
740 |
0x00000000);
|
741 |
/* XXX : not implemented */
|
742 |
spr_register(env, SPR_PMC2, "PMC2",
|
743 |
SPR_NOACCESS, SPR_NOACCESS, |
744 |
&spr_read_generic, &spr_write_generic, |
745 |
0x00000000);
|
746 |
/* XXX : not implemented */
|
747 |
spr_register(env, SPR_PMC3, "PMC3",
|
748 |
SPR_NOACCESS, SPR_NOACCESS, |
749 |
&spr_read_generic, &spr_write_generic, |
750 |
0x00000000);
|
751 |
/* XXX : not implemented */
|
752 |
spr_register(env, SPR_PMC4, "PMC4",
|
753 |
SPR_NOACCESS, SPR_NOACCESS, |
754 |
&spr_read_generic, &spr_write_generic, |
755 |
0x00000000);
|
756 |
/* XXX : not implemented */
|
757 |
spr_register(env, SPR_SIA, "SIA",
|
758 |
SPR_NOACCESS, SPR_NOACCESS, |
759 |
&spr_read_generic, SPR_NOACCESS, |
760 |
0x00000000);
|
761 |
spr_register(env, SPR_UMMCR0, "UMMCR0",
|
762 |
&spr_read_ureg, SPR_NOACCESS, |
763 |
&spr_read_ureg, SPR_NOACCESS, |
764 |
0x00000000);
|
765 |
spr_register(env, SPR_UMMCR1, "UMMCR1",
|
766 |
&spr_read_ureg, SPR_NOACCESS, |
767 |
&spr_read_ureg, SPR_NOACCESS, |
768 |
0x00000000);
|
769 |
spr_register(env, SPR_UPMC1, "UPMC1",
|
770 |
&spr_read_ureg, SPR_NOACCESS, |
771 |
&spr_read_ureg, SPR_NOACCESS, |
772 |
0x00000000);
|
773 |
spr_register(env, SPR_UPMC2, "UPMC2",
|
774 |
&spr_read_ureg, SPR_NOACCESS, |
775 |
&spr_read_ureg, SPR_NOACCESS, |
776 |
0x00000000);
|
777 |
spr_register(env, SPR_UPMC3, "UPMC3",
|
778 |
&spr_read_ureg, SPR_NOACCESS, |
779 |
&spr_read_ureg, SPR_NOACCESS, |
780 |
0x00000000);
|
781 |
spr_register(env, SPR_UPMC4, "UPMC4",
|
782 |
&spr_read_ureg, SPR_NOACCESS, |
783 |
&spr_read_ureg, SPR_NOACCESS, |
784 |
0x00000000);
|
785 |
spr_register(env, SPR_USIA, "USIA",
|
786 |
&spr_read_ureg, SPR_NOACCESS, |
787 |
&spr_read_ureg, SPR_NOACCESS, |
788 |
0x00000000);
|
789 |
/* Thermal management */
|
790 |
/* XXX : not implemented */
|
791 |
spr_register(env, SPR_THRM1, "THRM1",
|
792 |
SPR_NOACCESS, SPR_NOACCESS, |
793 |
&spr_read_generic, &spr_write_generic, |
794 |
0x00000000);
|
795 |
/* XXX : not implemented */
|
796 |
spr_register(env, SPR_THRM2, "THRM2",
|
797 |
SPR_NOACCESS, SPR_NOACCESS, |
798 |
&spr_read_generic, &spr_write_generic, |
799 |
0x00000000);
|
800 |
/* XXX : not implemented */
|
801 |
spr_register(env, SPR_THRM3, "THRM3",
|
802 |
SPR_NOACCESS, SPR_NOACCESS, |
803 |
&spr_read_generic, &spr_write_generic, |
804 |
0x00000000);
|
805 |
/* External access control */
|
806 |
/* XXX : not implemented */
|
807 |
spr_register(env, SPR_EAR, "EAR",
|
808 |
SPR_NOACCESS, SPR_NOACCESS, |
809 |
&spr_read_generic, &spr_write_generic, |
810 |
0x00000000);
|
811 |
} |
812 |
|
813 |
/* SPR specific to PowerPC 604 implementation */
|
814 |
static void gen_spr_604 (CPUPPCState *env) |
815 |
{ |
816 |
/* Processor identification */
|
817 |
spr_register(env, SPR_PIR, "PIR",
|
818 |
SPR_NOACCESS, SPR_NOACCESS, |
819 |
&spr_read_generic, &spr_write_pir, |
820 |
0x00000000);
|
821 |
/* Breakpoints */
|
822 |
/* XXX : not implemented */
|
823 |
spr_register(env, SPR_IABR, "IABR",
|
824 |
SPR_NOACCESS, SPR_NOACCESS, |
825 |
&spr_read_generic, &spr_write_generic, |
826 |
0x00000000);
|
827 |
/* XXX : not implemented */
|
828 |
spr_register(env, SPR_DABR, "DABR",
|
829 |
SPR_NOACCESS, SPR_NOACCESS, |
830 |
&spr_read_generic, &spr_write_generic, |
831 |
0x00000000);
|
832 |
/* Performance counters */
|
833 |
/* XXX : not implemented */
|
834 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
835 |
SPR_NOACCESS, SPR_NOACCESS, |
836 |
&spr_read_generic, &spr_write_generic, |
837 |
0x00000000);
|
838 |
/* XXX : not implemented */
|
839 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
840 |
SPR_NOACCESS, SPR_NOACCESS, |
841 |
&spr_read_generic, &spr_write_generic, |
842 |
0x00000000);
|
843 |
/* XXX : not implemented */
|
844 |
spr_register(env, SPR_PMC1, "PMC1",
|
845 |
SPR_NOACCESS, SPR_NOACCESS, |
846 |
&spr_read_generic, &spr_write_generic, |
847 |
0x00000000);
|
848 |
/* XXX : not implemented */
|
849 |
spr_register(env, SPR_PMC2, "PMC2",
|
850 |
SPR_NOACCESS, SPR_NOACCESS, |
851 |
&spr_read_generic, &spr_write_generic, |
852 |
0x00000000);
|
853 |
/* XXX : not implemented */
|
854 |
spr_register(env, SPR_PMC3, "PMC3",
|
855 |
SPR_NOACCESS, SPR_NOACCESS, |
856 |
&spr_read_generic, &spr_write_generic, |
857 |
0x00000000);
|
858 |
/* XXX : not implemented */
|
859 |
spr_register(env, SPR_PMC4, "PMC4",
|
860 |
SPR_NOACCESS, SPR_NOACCESS, |
861 |
&spr_read_generic, &spr_write_generic, |
862 |
0x00000000);
|
863 |
/* XXX : not implemented */
|
864 |
spr_register(env, SPR_SIA, "SIA",
|
865 |
SPR_NOACCESS, SPR_NOACCESS, |
866 |
&spr_read_generic, SPR_NOACCESS, |
867 |
0x00000000);
|
868 |
/* XXX : not implemented */
|
869 |
spr_register(env, SPR_SDA, "SDA",
|
870 |
SPR_NOACCESS, SPR_NOACCESS, |
871 |
&spr_read_generic, SPR_NOACCESS, |
872 |
0x00000000);
|
873 |
/* External access control */
|
874 |
/* XXX : not implemented */
|
875 |
spr_register(env, SPR_EAR, "EAR",
|
876 |
SPR_NOACCESS, SPR_NOACCESS, |
877 |
&spr_read_generic, &spr_write_generic, |
878 |
0x00000000);
|
879 |
} |
880 |
|
881 |
/* SPR specific to PowerPC 603 implementation */
|
882 |
static void gen_spr_603 (CPUPPCState *env) |
883 |
{ |
884 |
/* External access control */
|
885 |
/* XXX : not implemented */
|
886 |
spr_register(env, SPR_EAR, "EAR",
|
887 |
SPR_NOACCESS, SPR_NOACCESS, |
888 |
&spr_read_generic, &spr_write_generic, |
889 |
0x00000000);
|
890 |
} |
891 |
|
892 |
/* SPR specific to PowerPC G2 implementation */
|
893 |
static void gen_spr_G2 (CPUPPCState *env) |
894 |
{ |
895 |
/* Memory base address */
|
896 |
/* MBAR */
|
897 |
spr_register(env, SPR_MBAR, "MBAR",
|
898 |
SPR_NOACCESS, SPR_NOACCESS, |
899 |
&spr_read_generic, &spr_write_generic, |
900 |
0x00000000);
|
901 |
/* System version register */
|
902 |
/* SVR */
|
903 |
spr_register(env, SPR_SVR, "SVR",
|
904 |
SPR_NOACCESS, SPR_NOACCESS, |
905 |
&spr_read_generic, SPR_NOACCESS, |
906 |
0x00000000);
|
907 |
/* Exception processing */
|
908 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
909 |
SPR_NOACCESS, SPR_NOACCESS, |
910 |
&spr_read_generic, &spr_write_generic, |
911 |
0x00000000);
|
912 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
913 |
SPR_NOACCESS, SPR_NOACCESS, |
914 |
&spr_read_generic, &spr_write_generic, |
915 |
0x00000000);
|
916 |
/* Breakpoints */
|
917 |
/* XXX : not implemented */
|
918 |
spr_register(env, SPR_DABR, "DABR",
|
919 |
SPR_NOACCESS, SPR_NOACCESS, |
920 |
&spr_read_generic, &spr_write_generic, |
921 |
0x00000000);
|
922 |
/* XXX : not implemented */
|
923 |
spr_register(env, SPR_DABR2, "DABR2",
|
924 |
SPR_NOACCESS, SPR_NOACCESS, |
925 |
&spr_read_generic, &spr_write_generic, |
926 |
0x00000000);
|
927 |
/* XXX : not implemented */
|
928 |
spr_register(env, SPR_IABR, "IABR",
|
929 |
SPR_NOACCESS, SPR_NOACCESS, |
930 |
&spr_read_generic, &spr_write_generic, |
931 |
0x00000000);
|
932 |
/* XXX : not implemented */
|
933 |
spr_register(env, SPR_IABR2, "IABR2",
|
934 |
SPR_NOACCESS, SPR_NOACCESS, |
935 |
&spr_read_generic, &spr_write_generic, |
936 |
0x00000000);
|
937 |
/* XXX : not implemented */
|
938 |
spr_register(env, SPR_IBCR, "IBCR",
|
939 |
SPR_NOACCESS, SPR_NOACCESS, |
940 |
&spr_read_generic, &spr_write_generic, |
941 |
0x00000000);
|
942 |
/* XXX : not implemented */
|
943 |
spr_register(env, SPR_DBCR, "DBCR",
|
944 |
SPR_NOACCESS, SPR_NOACCESS, |
945 |
&spr_read_generic, &spr_write_generic, |
946 |
0x00000000);
|
947 |
} |
948 |
|
949 |
/* SPR specific to PowerPC 602 implementation */
|
950 |
static void gen_spr_602 (CPUPPCState *env) |
951 |
{ |
952 |
/* ESA registers */
|
953 |
/* XXX : not implemented */
|
954 |
spr_register(env, SPR_SER, "SER",
|
955 |
SPR_NOACCESS, SPR_NOACCESS, |
956 |
&spr_read_generic, &spr_write_generic, |
957 |
0x00000000);
|
958 |
/* XXX : not implemented */
|
959 |
spr_register(env, SPR_SEBR, "SEBR",
|
960 |
SPR_NOACCESS, SPR_NOACCESS, |
961 |
&spr_read_generic, &spr_write_generic, |
962 |
0x00000000);
|
963 |
/* XXX : not implemented */
|
964 |
spr_register(env, SPR_ESASR, "ESASR",
|
965 |
SPR_NOACCESS, SPR_NOACCESS, |
966 |
&spr_read_generic, &spr_write_generic, |
967 |
0x00000000);
|
968 |
/* Floating point status */
|
969 |
/* XXX : not implemented */
|
970 |
spr_register(env, SPR_SP, "SP",
|
971 |
SPR_NOACCESS, SPR_NOACCESS, |
972 |
&spr_read_generic, &spr_write_generic, |
973 |
0x00000000);
|
974 |
/* XXX : not implemented */
|
975 |
spr_register(env, SPR_LT, "LT",
|
976 |
SPR_NOACCESS, SPR_NOACCESS, |
977 |
&spr_read_generic, &spr_write_generic, |
978 |
0x00000000);
|
979 |
/* Watchdog timer */
|
980 |
/* XXX : not implemented */
|
981 |
spr_register(env, SPR_TCR, "TCR",
|
982 |
SPR_NOACCESS, SPR_NOACCESS, |
983 |
&spr_read_generic, &spr_write_generic, |
984 |
0x00000000);
|
985 |
/* Interrupt base */
|
986 |
spr_register(env, SPR_IBR, "IBR",
|
987 |
SPR_NOACCESS, SPR_NOACCESS, |
988 |
&spr_read_generic, &spr_write_generic, |
989 |
0x00000000);
|
990 |
} |
991 |
|
992 |
/* SPR specific to PowerPC 601 implementation */
|
993 |
static void gen_spr_601 (CPUPPCState *env) |
994 |
{ |
995 |
/* Multiplication/division register */
|
996 |
/* MQ */
|
997 |
spr_register(env, SPR_MQ, "MQ",
|
998 |
&spr_read_generic, &spr_write_generic, |
999 |
&spr_read_generic, &spr_write_generic, |
1000 |
0x00000000);
|
1001 |
/* RTC registers */
|
1002 |
spr_register(env, SPR_601_RTCU, "RTCU",
|
1003 |
SPR_NOACCESS, SPR_NOACCESS, |
1004 |
SPR_NOACCESS, &spr_write_601_rtcu, |
1005 |
0x00000000);
|
1006 |
spr_register(env, SPR_601_VRTCU, "RTCU",
|
1007 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1008 |
&spr_read_601_rtcu, SPR_NOACCESS, |
1009 |
0x00000000);
|
1010 |
spr_register(env, SPR_601_RTCL, "RTCL",
|
1011 |
SPR_NOACCESS, SPR_NOACCESS, |
1012 |
SPR_NOACCESS, &spr_write_601_rtcl, |
1013 |
0x00000000);
|
1014 |
spr_register(env, SPR_601_VRTCL, "RTCL",
|
1015 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1016 |
&spr_read_601_rtcl, SPR_NOACCESS, |
1017 |
0x00000000);
|
1018 |
/* Timer */
|
1019 |
#if 0 /* ? */
|
1020 |
spr_register(env, SPR_601_UDECR, "UDECR",
|
1021 |
&spr_read_decr, SPR_NOACCESS,
|
1022 |
&spr_read_decr, SPR_NOACCESS,
|
1023 |
0x00000000);
|
1024 |
#endif
|
1025 |
/* External access control */
|
1026 |
/* XXX : not implemented */
|
1027 |
spr_register(env, SPR_EAR, "EAR",
|
1028 |
SPR_NOACCESS, SPR_NOACCESS, |
1029 |
&spr_read_generic, &spr_write_generic, |
1030 |
0x00000000);
|
1031 |
/* Memory management */
|
1032 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
1033 |
SPR_NOACCESS, SPR_NOACCESS, |
1034 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1035 |
0x00000000);
|
1036 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
1037 |
SPR_NOACCESS, SPR_NOACCESS, |
1038 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1039 |
0x00000000);
|
1040 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
1041 |
SPR_NOACCESS, SPR_NOACCESS, |
1042 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1043 |
0x00000000);
|
1044 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
1045 |
SPR_NOACCESS, SPR_NOACCESS, |
1046 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1047 |
0x00000000);
|
1048 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
1049 |
SPR_NOACCESS, SPR_NOACCESS, |
1050 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1051 |
0x00000000);
|
1052 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
1053 |
SPR_NOACCESS, SPR_NOACCESS, |
1054 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1055 |
0x00000000);
|
1056 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
1057 |
SPR_NOACCESS, SPR_NOACCESS, |
1058 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
1059 |
0x00000000);
|
1060 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
1061 |
SPR_NOACCESS, SPR_NOACCESS, |
1062 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
1063 |
0x00000000);
|
1064 |
} |
1065 |
|
1066 |
/* PowerPC BookE SPR */
|
1067 |
static void gen_spr_BookE (CPUPPCState *env) |
1068 |
{ |
1069 |
/* Processor identification */
|
1070 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
1071 |
SPR_NOACCESS, SPR_NOACCESS, |
1072 |
&spr_read_generic, &spr_write_pir, |
1073 |
0x00000000);
|
1074 |
/* Interrupt processing */
|
1075 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
1076 |
SPR_NOACCESS, SPR_NOACCESS, |
1077 |
&spr_read_generic, &spr_write_generic, |
1078 |
0x00000000);
|
1079 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
1080 |
SPR_NOACCESS, SPR_NOACCESS, |
1081 |
&spr_read_generic, &spr_write_generic, |
1082 |
0x00000000);
|
1083 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
1084 |
SPR_NOACCESS, SPR_NOACCESS, |
1085 |
&spr_read_generic, &spr_write_generic, |
1086 |
0x00000000);
|
1087 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
1088 |
SPR_NOACCESS, SPR_NOACCESS, |
1089 |
&spr_read_generic, &spr_write_generic, |
1090 |
0x00000000);
|
1091 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
1092 |
SPR_NOACCESS, SPR_NOACCESS, |
1093 |
&spr_read_generic, &spr_write_generic, |
1094 |
0x00000000);
|
1095 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
1096 |
SPR_NOACCESS, SPR_NOACCESS, |
1097 |
&spr_read_generic, &spr_write_generic, |
1098 |
0x00000000);
|
1099 |
/* Debug */
|
1100 |
/* XXX : not implemented */
|
1101 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
|
1102 |
SPR_NOACCESS, SPR_NOACCESS, |
1103 |
&spr_read_generic, &spr_write_generic, |
1104 |
0x00000000);
|
1105 |
/* XXX : not implemented */
|
1106 |
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
|
1107 |
SPR_NOACCESS, SPR_NOACCESS, |
1108 |
&spr_read_generic, &spr_write_generic, |
1109 |
0x00000000);
|
1110 |
/* XXX : not implemented */
|
1111 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
1112 |
SPR_NOACCESS, SPR_NOACCESS, |
1113 |
&spr_read_generic, &spr_write_generic, |
1114 |
0x00000000);
|
1115 |
/* XXX : not implemented */
|
1116 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
1117 |
SPR_NOACCESS, SPR_NOACCESS, |
1118 |
&spr_read_generic, &spr_write_generic, |
1119 |
0x00000000);
|
1120 |
/* XXX : not implemented */
|
1121 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
|
1122 |
SPR_NOACCESS, SPR_NOACCESS, |
1123 |
&spr_read_generic, &spr_write_generic, |
1124 |
0x00000000);
|
1125 |
/* XXX : not implemented */
|
1126 |
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
|
1127 |
SPR_NOACCESS, SPR_NOACCESS, |
1128 |
&spr_read_generic, &spr_write_generic, |
1129 |
0x00000000);
|
1130 |
/* XXX : not implemented */
|
1131 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
1132 |
SPR_NOACCESS, SPR_NOACCESS, |
1133 |
&spr_read_generic, &spr_write_generic, |
1134 |
0x00000000);
|
1135 |
/* XXX : not implemented */
|
1136 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
1137 |
SPR_NOACCESS, SPR_NOACCESS, |
1138 |
&spr_read_generic, &spr_write_generic, |
1139 |
0x00000000);
|
1140 |
/* XXX : not implemented */
|
1141 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
|
1142 |
SPR_NOACCESS, SPR_NOACCESS, |
1143 |
&spr_read_generic, &spr_write_generic, |
1144 |
0x00000000);
|
1145 |
/* XXX : not implemented */
|
1146 |
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
|
1147 |
SPR_NOACCESS, SPR_NOACCESS, |
1148 |
&spr_read_generic, &spr_write_generic, |
1149 |
0x00000000);
|
1150 |
/* XXX : not implemented */
|
1151 |
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
|
1152 |
SPR_NOACCESS, SPR_NOACCESS, |
1153 |
&spr_read_generic, &spr_write_generic, |
1154 |
0x00000000);
|
1155 |
/* XXX : not implemented */
|
1156 |
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
|
1157 |
SPR_NOACCESS, SPR_NOACCESS, |
1158 |
&spr_read_generic, &spr_write_generic, |
1159 |
0x00000000);
|
1160 |
spr_register(env, SPR_BOOKE_DEAR, "DEAR",
|
1161 |
SPR_NOACCESS, SPR_NOACCESS, |
1162 |
&spr_read_generic, &spr_write_generic, |
1163 |
0x00000000);
|
1164 |
spr_register(env, SPR_BOOKE_ESR, "ESR",
|
1165 |
SPR_NOACCESS, SPR_NOACCESS, |
1166 |
&spr_read_generic, &spr_write_generic, |
1167 |
0x00000000);
|
1168 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
1169 |
SPR_NOACCESS, SPR_NOACCESS, |
1170 |
&spr_read_generic, &spr_write_generic, |
1171 |
0x00000000);
|
1172 |
/* Exception vectors */
|
1173 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
1174 |
SPR_NOACCESS, SPR_NOACCESS, |
1175 |
&spr_read_generic, &spr_write_generic, |
1176 |
0x00000000);
|
1177 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
|
1178 |
SPR_NOACCESS, SPR_NOACCESS, |
1179 |
&spr_read_generic, &spr_write_generic, |
1180 |
0x00000000);
|
1181 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
|
1182 |
SPR_NOACCESS, SPR_NOACCESS, |
1183 |
&spr_read_generic, &spr_write_generic, |
1184 |
0x00000000);
|
1185 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
|
1186 |
SPR_NOACCESS, SPR_NOACCESS, |
1187 |
&spr_read_generic, &spr_write_generic, |
1188 |
0x00000000);
|
1189 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
|
1190 |
SPR_NOACCESS, SPR_NOACCESS, |
1191 |
&spr_read_generic, &spr_write_generic, |
1192 |
0x00000000);
|
1193 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
|
1194 |
SPR_NOACCESS, SPR_NOACCESS, |
1195 |
&spr_read_generic, &spr_write_generic, |
1196 |
0x00000000);
|
1197 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
|
1198 |
SPR_NOACCESS, SPR_NOACCESS, |
1199 |
&spr_read_generic, &spr_write_generic, |
1200 |
0x00000000);
|
1201 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
|
1202 |
SPR_NOACCESS, SPR_NOACCESS, |
1203 |
&spr_read_generic, &spr_write_generic, |
1204 |
0x00000000);
|
1205 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
|
1206 |
SPR_NOACCESS, SPR_NOACCESS, |
1207 |
&spr_read_generic, &spr_write_generic, |
1208 |
0x00000000);
|
1209 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
|
1210 |
SPR_NOACCESS, SPR_NOACCESS, |
1211 |
&spr_read_generic, &spr_write_generic, |
1212 |
0x00000000);
|
1213 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
|
1214 |
SPR_NOACCESS, SPR_NOACCESS, |
1215 |
&spr_read_generic, &spr_write_generic, |
1216 |
0x00000000);
|
1217 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
|
1218 |
SPR_NOACCESS, SPR_NOACCESS, |
1219 |
&spr_read_generic, &spr_write_generic, |
1220 |
0x00000000);
|
1221 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
|
1222 |
SPR_NOACCESS, SPR_NOACCESS, |
1223 |
&spr_read_generic, &spr_write_generic, |
1224 |
0x00000000);
|
1225 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
|
1226 |
SPR_NOACCESS, SPR_NOACCESS, |
1227 |
&spr_read_generic, &spr_write_generic, |
1228 |
0x00000000);
|
1229 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
|
1230 |
SPR_NOACCESS, SPR_NOACCESS, |
1231 |
&spr_read_generic, &spr_write_generic, |
1232 |
0x00000000);
|
1233 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
|
1234 |
SPR_NOACCESS, SPR_NOACCESS, |
1235 |
&spr_read_generic, &spr_write_generic, |
1236 |
0x00000000);
|
1237 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
|
1238 |
SPR_NOACCESS, SPR_NOACCESS, |
1239 |
&spr_read_generic, &spr_write_generic, |
1240 |
0x00000000);
|
1241 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
|
1242 |
SPR_NOACCESS, SPR_NOACCESS, |
1243 |
&spr_read_generic, &spr_write_generic, |
1244 |
0x00000000);
|
1245 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
|
1246 |
SPR_NOACCESS, SPR_NOACCESS, |
1247 |
&spr_read_generic, &spr_write_generic, |
1248 |
0x00000000);
|
1249 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
|
1250 |
SPR_NOACCESS, SPR_NOACCESS, |
1251 |
&spr_read_generic, &spr_write_generic, |
1252 |
0x00000000);
|
1253 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
|
1254 |
SPR_NOACCESS, SPR_NOACCESS, |
1255 |
&spr_read_generic, &spr_write_generic, |
1256 |
0x00000000);
|
1257 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
|
1258 |
SPR_NOACCESS, SPR_NOACCESS, |
1259 |
&spr_read_generic, &spr_write_generic, |
1260 |
0x00000000);
|
1261 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
|
1262 |
SPR_NOACCESS, SPR_NOACCESS, |
1263 |
&spr_read_generic, &spr_write_generic, |
1264 |
0x00000000);
|
1265 |
spr_register(env, SPR_BOOKE_PID, "PID",
|
1266 |
SPR_NOACCESS, SPR_NOACCESS, |
1267 |
&spr_read_generic, &spr_write_generic, |
1268 |
0x00000000);
|
1269 |
spr_register(env, SPR_BOOKE_TCR, "TCR",
|
1270 |
SPR_NOACCESS, SPR_NOACCESS, |
1271 |
&spr_read_generic, &spr_write_booke_tcr, |
1272 |
0x00000000);
|
1273 |
spr_register(env, SPR_BOOKE_TSR, "TSR",
|
1274 |
SPR_NOACCESS, SPR_NOACCESS, |
1275 |
&spr_read_generic, &spr_write_booke_tsr, |
1276 |
0x00000000);
|
1277 |
/* Timer */
|
1278 |
spr_register(env, SPR_DECR, "DECR",
|
1279 |
SPR_NOACCESS, SPR_NOACCESS, |
1280 |
&spr_read_decr, &spr_write_decr, |
1281 |
0x00000000);
|
1282 |
spr_register(env, SPR_BOOKE_DECAR, "DECAR",
|
1283 |
SPR_NOACCESS, SPR_NOACCESS, |
1284 |
SPR_NOACCESS, &spr_write_generic, |
1285 |
0x00000000);
|
1286 |
/* SPRGs */
|
1287 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1288 |
&spr_read_generic, &spr_write_generic, |
1289 |
&spr_read_generic, &spr_write_generic, |
1290 |
0x00000000);
|
1291 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1292 |
SPR_NOACCESS, SPR_NOACCESS, |
1293 |
&spr_read_generic, &spr_write_generic, |
1294 |
0x00000000);
|
1295 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
1296 |
&spr_read_ureg, SPR_NOACCESS, |
1297 |
&spr_read_ureg, SPR_NOACCESS, |
1298 |
0x00000000);
|
1299 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1300 |
SPR_NOACCESS, SPR_NOACCESS, |
1301 |
&spr_read_generic, &spr_write_generic, |
1302 |
0x00000000);
|
1303 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
1304 |
&spr_read_ureg, SPR_NOACCESS, |
1305 |
&spr_read_ureg, SPR_NOACCESS, |
1306 |
0x00000000);
|
1307 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1308 |
SPR_NOACCESS, SPR_NOACCESS, |
1309 |
&spr_read_generic, &spr_write_generic, |
1310 |
0x00000000);
|
1311 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
1312 |
&spr_read_ureg, SPR_NOACCESS, |
1313 |
&spr_read_ureg, SPR_NOACCESS, |
1314 |
0x00000000);
|
1315 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1316 |
SPR_NOACCESS, SPR_NOACCESS, |
1317 |
&spr_read_generic, &spr_write_generic, |
1318 |
0x00000000);
|
1319 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
1320 |
&spr_read_ureg, SPR_NOACCESS, |
1321 |
&spr_read_ureg, SPR_NOACCESS, |
1322 |
0x00000000);
|
1323 |
} |
1324 |
|
1325 |
/* FSL storage control registers */
|
1326 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
1327 |
{ |
1328 |
/* TLB assist registers */
|
1329 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0",
|
1330 |
SPR_NOACCESS, SPR_NOACCESS, |
1331 |
&spr_read_generic, &spr_write_generic, |
1332 |
0x00000000);
|
1333 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2",
|
1334 |
SPR_NOACCESS, SPR_NOACCESS, |
1335 |
&spr_read_generic, &spr_write_generic, |
1336 |
0x00000000);
|
1337 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3",
|
1338 |
SPR_NOACCESS, SPR_NOACCESS, |
1339 |
&spr_read_generic, &spr_write_generic, |
1340 |
0x00000000);
|
1341 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4",
|
1342 |
SPR_NOACCESS, SPR_NOACCESS, |
1343 |
&spr_read_generic, &spr_write_generic, |
1344 |
0x00000000);
|
1345 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5",
|
1346 |
SPR_NOACCESS, SPR_NOACCESS, |
1347 |
&spr_read_generic, &spr_write_generic, |
1348 |
0x00000000);
|
1349 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6",
|
1350 |
SPR_NOACCESS, SPR_NOACCESS, |
1351 |
&spr_read_generic, &spr_write_generic, |
1352 |
0x00000000);
|
1353 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7",
|
1354 |
SPR_NOACCESS, SPR_NOACCESS, |
1355 |
&spr_read_generic, &spr_write_generic, |
1356 |
0x00000000);
|
1357 |
if (env->nb_pids > 1) { |
1358 |
spr_register(env, SPR_BOOKE_PID1, "PID1",
|
1359 |
SPR_NOACCESS, SPR_NOACCESS, |
1360 |
&spr_read_generic, &spr_write_generic, |
1361 |
0x00000000);
|
1362 |
} |
1363 |
if (env->nb_pids > 2) { |
1364 |
spr_register(env, SPR_BOOKE_PID2, "PID2",
|
1365 |
SPR_NOACCESS, SPR_NOACCESS, |
1366 |
&spr_read_generic, &spr_write_generic, |
1367 |
0x00000000);
|
1368 |
} |
1369 |
spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
|
1370 |
SPR_NOACCESS, SPR_NOACCESS, |
1371 |
&spr_read_generic, SPR_NOACCESS, |
1372 |
0x00000000); /* TOFIX */ |
1373 |
spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
|
1374 |
SPR_NOACCESS, SPR_NOACCESS, |
1375 |
&spr_read_generic, &spr_write_generic, |
1376 |
0x00000000); /* TOFIX */ |
1377 |
switch (env->nb_ways) {
|
1378 |
case 4: |
1379 |
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
|
1380 |
SPR_NOACCESS, SPR_NOACCESS, |
1381 |
&spr_read_generic, SPR_NOACCESS, |
1382 |
0x00000000); /* TOFIX */ |
1383 |
/* Fallthru */
|
1384 |
case 3: |
1385 |
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
|
1386 |
SPR_NOACCESS, SPR_NOACCESS, |
1387 |
&spr_read_generic, SPR_NOACCESS, |
1388 |
0x00000000); /* TOFIX */ |
1389 |
/* Fallthru */
|
1390 |
case 2: |
1391 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
1392 |
SPR_NOACCESS, SPR_NOACCESS, |
1393 |
&spr_read_generic, SPR_NOACCESS, |
1394 |
0x00000000); /* TOFIX */ |
1395 |
/* Fallthru */
|
1396 |
case 1: |
1397 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
1398 |
SPR_NOACCESS, SPR_NOACCESS, |
1399 |
&spr_read_generic, SPR_NOACCESS, |
1400 |
0x00000000); /* TOFIX */ |
1401 |
/* Fallthru */
|
1402 |
case 0: |
1403 |
default:
|
1404 |
break;
|
1405 |
} |
1406 |
} |
1407 |
|
1408 |
/* SPR specific to PowerPC 440 implementation */
|
1409 |
static void gen_spr_440 (CPUPPCState *env) |
1410 |
{ |
1411 |
/* Cache control */
|
1412 |
/* XXX : not implemented */
|
1413 |
spr_register(env, SPR_440_DNV0, "DNV0",
|
1414 |
SPR_NOACCESS, SPR_NOACCESS, |
1415 |
&spr_read_generic, &spr_write_generic, |
1416 |
0x00000000);
|
1417 |
/* XXX : not implemented */
|
1418 |
spr_register(env, SPR_440_DNV1, "DNV1",
|
1419 |
SPR_NOACCESS, SPR_NOACCESS, |
1420 |
&spr_read_generic, &spr_write_generic, |
1421 |
0x00000000);
|
1422 |
/* XXX : not implemented */
|
1423 |
spr_register(env, SPR_440_DNV2, "DNV2",
|
1424 |
SPR_NOACCESS, SPR_NOACCESS, |
1425 |
&spr_read_generic, &spr_write_generic, |
1426 |
0x00000000);
|
1427 |
/* XXX : not implemented */
|
1428 |
spr_register(env, SPR_440_DNV3, "DNV3",
|
1429 |
SPR_NOACCESS, SPR_NOACCESS, |
1430 |
&spr_read_generic, &spr_write_generic, |
1431 |
0x00000000);
|
1432 |
/* XXX : not implemented */
|
1433 |
spr_register(env, SPR_440_DVT0, "DVT0",
|
1434 |
SPR_NOACCESS, SPR_NOACCESS, |
1435 |
&spr_read_generic, &spr_write_generic, |
1436 |
0x00000000);
|
1437 |
/* XXX : not implemented */
|
1438 |
spr_register(env, SPR_440_DVT1, "DVT1",
|
1439 |
SPR_NOACCESS, SPR_NOACCESS, |
1440 |
&spr_read_generic, &spr_write_generic, |
1441 |
0x00000000);
|
1442 |
/* XXX : not implemented */
|
1443 |
spr_register(env, SPR_440_DVT2, "DVT2",
|
1444 |
SPR_NOACCESS, SPR_NOACCESS, |
1445 |
&spr_read_generic, &spr_write_generic, |
1446 |
0x00000000);
|
1447 |
/* XXX : not implemented */
|
1448 |
spr_register(env, SPR_440_DVT3, "DVT3",
|
1449 |
SPR_NOACCESS, SPR_NOACCESS, |
1450 |
&spr_read_generic, &spr_write_generic, |
1451 |
0x00000000);
|
1452 |
/* XXX : not implemented */
|
1453 |
spr_register(env, SPR_440_DVLIM, "DVLIM",
|
1454 |
SPR_NOACCESS, SPR_NOACCESS, |
1455 |
&spr_read_generic, &spr_write_generic, |
1456 |
0x00000000);
|
1457 |
/* XXX : not implemented */
|
1458 |
spr_register(env, SPR_440_INV0, "INV0",
|
1459 |
SPR_NOACCESS, SPR_NOACCESS, |
1460 |
&spr_read_generic, &spr_write_generic, |
1461 |
0x00000000);
|
1462 |
/* XXX : not implemented */
|
1463 |
spr_register(env, SPR_440_INV1, "INV1",
|
1464 |
SPR_NOACCESS, SPR_NOACCESS, |
1465 |
&spr_read_generic, &spr_write_generic, |
1466 |
0x00000000);
|
1467 |
/* XXX : not implemented */
|
1468 |
spr_register(env, SPR_440_INV2, "INV2",
|
1469 |
SPR_NOACCESS, SPR_NOACCESS, |
1470 |
&spr_read_generic, &spr_write_generic, |
1471 |
0x00000000);
|
1472 |
/* XXX : not implemented */
|
1473 |
spr_register(env, SPR_440_INV3, "INV3",
|
1474 |
SPR_NOACCESS, SPR_NOACCESS, |
1475 |
&spr_read_generic, &spr_write_generic, |
1476 |
0x00000000);
|
1477 |
/* XXX : not implemented */
|
1478 |
spr_register(env, SPR_440_IVT0, "IVT0",
|
1479 |
SPR_NOACCESS, SPR_NOACCESS, |
1480 |
&spr_read_generic, &spr_write_generic, |
1481 |
0x00000000);
|
1482 |
/* XXX : not implemented */
|
1483 |
spr_register(env, SPR_440_IVT1, "IVT1",
|
1484 |
SPR_NOACCESS, SPR_NOACCESS, |
1485 |
&spr_read_generic, &spr_write_generic, |
1486 |
0x00000000);
|
1487 |
/* XXX : not implemented */
|
1488 |
spr_register(env, SPR_440_IVT2, "IVT2",
|
1489 |
SPR_NOACCESS, SPR_NOACCESS, |
1490 |
&spr_read_generic, &spr_write_generic, |
1491 |
0x00000000);
|
1492 |
/* XXX : not implemented */
|
1493 |
spr_register(env, SPR_440_IVT3, "IVT3",
|
1494 |
SPR_NOACCESS, SPR_NOACCESS, |
1495 |
&spr_read_generic, &spr_write_generic, |
1496 |
0x00000000);
|
1497 |
/* XXX : not implemented */
|
1498 |
spr_register(env, SPR_440_IVLIM, "IVLIM",
|
1499 |
SPR_NOACCESS, SPR_NOACCESS, |
1500 |
&spr_read_generic, &spr_write_generic, |
1501 |
0x00000000);
|
1502 |
/* Cache debug */
|
1503 |
/* XXX : not implemented */
|
1504 |
spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
|
1505 |
SPR_NOACCESS, SPR_NOACCESS, |
1506 |
&spr_read_generic, SPR_NOACCESS, |
1507 |
0x00000000);
|
1508 |
/* XXX : not implemented */
|
1509 |
spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
|
1510 |
SPR_NOACCESS, SPR_NOACCESS, |
1511 |
&spr_read_generic, SPR_NOACCESS, |
1512 |
0x00000000);
|
1513 |
/* XXX : not implemented */
|
1514 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
1515 |
SPR_NOACCESS, SPR_NOACCESS, |
1516 |
&spr_read_generic, SPR_NOACCESS, |
1517 |
0x00000000);
|
1518 |
/* XXX : not implemented */
|
1519 |
spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
|
1520 |
SPR_NOACCESS, SPR_NOACCESS, |
1521 |
&spr_read_generic, SPR_NOACCESS, |
1522 |
0x00000000);
|
1523 |
/* XXX : not implemented */
|
1524 |
spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
|
1525 |
SPR_NOACCESS, SPR_NOACCESS, |
1526 |
&spr_read_generic, SPR_NOACCESS, |
1527 |
0x00000000);
|
1528 |
/* XXX : not implemented */
|
1529 |
spr_register(env, SPR_440_DBDR, "DBDR",
|
1530 |
SPR_NOACCESS, SPR_NOACCESS, |
1531 |
&spr_read_generic, &spr_write_generic, |
1532 |
0x00000000);
|
1533 |
/* Processor control */
|
1534 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1535 |
SPR_NOACCESS, SPR_NOACCESS, |
1536 |
&spr_read_generic, &spr_write_generic, |
1537 |
0x00000000);
|
1538 |
spr_register(env, SPR_440_RSTCFG, "RSTCFG",
|
1539 |
SPR_NOACCESS, SPR_NOACCESS, |
1540 |
&spr_read_generic, SPR_NOACCESS, |
1541 |
0x00000000);
|
1542 |
/* Storage control */
|
1543 |
spr_register(env, SPR_440_MMUCR, "MMUCR",
|
1544 |
SPR_NOACCESS, SPR_NOACCESS, |
1545 |
&spr_read_generic, &spr_write_generic, |
1546 |
0x00000000);
|
1547 |
} |
1548 |
|
1549 |
/* SPR shared between PowerPC 40x implementations */
|
1550 |
static void gen_spr_40x (CPUPPCState *env) |
1551 |
{ |
1552 |
/* Cache */
|
1553 |
/* XXX : not implemented */
|
1554 |
spr_register(env, SPR_40x_DCCR, "DCCR",
|
1555 |
SPR_NOACCESS, SPR_NOACCESS, |
1556 |
&spr_read_generic, &spr_write_generic, |
1557 |
0x00000000);
|
1558 |
/* XXX : not implemented */
|
1559 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
1560 |
SPR_NOACCESS, SPR_NOACCESS, |
1561 |
&spr_read_generic, &spr_write_generic, |
1562 |
0x00000000);
|
1563 |
/* XXX : not implemented */
|
1564 |
spr_register(env, SPR_40x_ICCR, "ICCR",
|
1565 |
SPR_NOACCESS, SPR_NOACCESS, |
1566 |
&spr_read_generic, &spr_write_generic, |
1567 |
0x00000000);
|
1568 |
/* XXX : not implemented */
|
1569 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
1570 |
SPR_NOACCESS, SPR_NOACCESS, |
1571 |
&spr_read_generic, SPR_NOACCESS, |
1572 |
0x00000000);
|
1573 |
/* Bus access control */
|
1574 |
spr_register(env, SPR_40x_SGR, "SGR",
|
1575 |
SPR_NOACCESS, SPR_NOACCESS, |
1576 |
&spr_read_generic, &spr_write_generic, |
1577 |
0xFFFFFFFF);
|
1578 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
1579 |
SPR_NOACCESS, SPR_NOACCESS, |
1580 |
&spr_read_generic, &spr_write_generic, |
1581 |
0x00000000);
|
1582 |
/* MMU */
|
1583 |
spr_register(env, SPR_40x_PID, "PID",
|
1584 |
SPR_NOACCESS, SPR_NOACCESS, |
1585 |
&spr_read_generic, &spr_write_generic, |
1586 |
0x00000000);
|
1587 |
/* Exception */
|
1588 |
spr_register(env, SPR_40x_DEAR, "DEAR",
|
1589 |
SPR_NOACCESS, SPR_NOACCESS, |
1590 |
&spr_read_generic, &spr_write_generic, |
1591 |
0x00000000);
|
1592 |
spr_register(env, SPR_40x_ESR, "ESR",
|
1593 |
SPR_NOACCESS, SPR_NOACCESS, |
1594 |
&spr_read_generic, &spr_write_generic, |
1595 |
0x00000000);
|
1596 |
spr_register(env, SPR_40x_EVPR, "EVPR",
|
1597 |
SPR_NOACCESS, SPR_NOACCESS, |
1598 |
&spr_read_generic, &spr_write_generic, |
1599 |
0x00000000);
|
1600 |
spr_register(env, SPR_40x_SRR2, "SRR2",
|
1601 |
&spr_read_generic, &spr_write_generic, |
1602 |
&spr_read_generic, &spr_write_generic, |
1603 |
0x00000000);
|
1604 |
spr_register(env, SPR_40x_SRR3, "SRR3",
|
1605 |
&spr_read_generic, &spr_write_generic, |
1606 |
&spr_read_generic, &spr_write_generic, |
1607 |
0x00000000);
|
1608 |
/* Timers */
|
1609 |
spr_register(env, SPR_40x_PIT, "PIT",
|
1610 |
SPR_NOACCESS, SPR_NOACCESS, |
1611 |
&spr_read_40x_pit, &spr_write_40x_pit, |
1612 |
0x00000000);
|
1613 |
spr_register(env, SPR_40x_TCR, "TCR",
|
1614 |
SPR_NOACCESS, SPR_NOACCESS, |
1615 |
&spr_read_generic, &spr_write_booke_tcr, |
1616 |
0x00000000);
|
1617 |
spr_register(env, SPR_40x_TSR, "TSR",
|
1618 |
SPR_NOACCESS, SPR_NOACCESS, |
1619 |
&spr_read_generic, &spr_write_booke_tsr, |
1620 |
0x00000000);
|
1621 |
/* Debug interface */
|
1622 |
/* XXX : not implemented */
|
1623 |
spr_register(env, SPR_40x_DAC1, "DAC1",
|
1624 |
SPR_NOACCESS, SPR_NOACCESS, |
1625 |
&spr_read_generic, &spr_write_generic, |
1626 |
0x00000000);
|
1627 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1628 |
SPR_NOACCESS, SPR_NOACCESS, |
1629 |
&spr_read_generic, &spr_write_generic, |
1630 |
0x00000000);
|
1631 |
/* XXX : not implemented */
|
1632 |
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
1633 |
SPR_NOACCESS, SPR_NOACCESS, |
1634 |
&spr_read_generic, &spr_write_generic, |
1635 |
0x00000000);
|
1636 |
/* XXX : not implemented */
|
1637 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
1638 |
SPR_NOACCESS, SPR_NOACCESS, |
1639 |
&spr_read_generic, &spr_write_generic, |
1640 |
/* Last reset was system reset (system boot */
|
1641 |
0x00000300);
|
1642 |
/* XXX : not implemented */
|
1643 |
spr_register(env, SPR_40x_IAC1, "IAC1",
|
1644 |
SPR_NOACCESS, SPR_NOACCESS, |
1645 |
&spr_read_generic, &spr_write_generic, |
1646 |
0x00000000);
|
1647 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1648 |
SPR_NOACCESS, SPR_NOACCESS, |
1649 |
&spr_read_generic, &spr_write_generic, |
1650 |
0x00000000);
|
1651 |
} |
1652 |
|
1653 |
/* SPR specific to PowerPC 405 implementation */
|
1654 |
static void gen_spr_405 (CPUPPCState *env) |
1655 |
{ |
1656 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
1657 |
SPR_NOACCESS, SPR_NOACCESS, |
1658 |
&spr_read_generic, &spr_write_generic, |
1659 |
0x00700000);
|
1660 |
/* Debug */
|
1661 |
/* XXX : not implemented */
|
1662 |
spr_register(env, SPR_405_DBCR1, "DBCR1",
|
1663 |
SPR_NOACCESS, SPR_NOACCESS, |
1664 |
&spr_read_generic, &spr_write_generic, |
1665 |
0x00000000);
|
1666 |
/* XXX : not implemented */
|
1667 |
spr_register(env, SPR_405_DVC1, "DVC1",
|
1668 |
SPR_NOACCESS, SPR_NOACCESS, |
1669 |
&spr_read_generic, &spr_write_generic, |
1670 |
0x00000000);
|
1671 |
/* XXX : not implemented */
|
1672 |
spr_register(env, SPR_405_DVC2, "DVC2",
|
1673 |
SPR_NOACCESS, SPR_NOACCESS, |
1674 |
&spr_read_generic, &spr_write_generic, |
1675 |
0x00000000);
|
1676 |
/* XXX : not implemented */
|
1677 |
spr_register(env, SPR_405_IAC3, "IAC3",
|
1678 |
SPR_NOACCESS, SPR_NOACCESS, |
1679 |
&spr_read_generic, &spr_write_generic, |
1680 |
0x00000000);
|
1681 |
/* XXX : not implemented */
|
1682 |
spr_register(env, SPR_405_IAC4, "IAC4",
|
1683 |
SPR_NOACCESS, SPR_NOACCESS, |
1684 |
&spr_read_generic, &spr_write_generic, |
1685 |
0x00000000);
|
1686 |
/* Storage control */
|
1687 |
/* XXX : not implemented */
|
1688 |
spr_register(env, SPR_405_SLER, "SLER",
|
1689 |
SPR_NOACCESS, SPR_NOACCESS, |
1690 |
&spr_read_generic, &spr_write_generic, |
1691 |
0x00000000);
|
1692 |
/* XXX : not implemented */
|
1693 |
spr_register(env, SPR_405_SU0R, "SU0R",
|
1694 |
SPR_NOACCESS, SPR_NOACCESS, |
1695 |
&spr_read_generic, &spr_write_generic, |
1696 |
0x00000000);
|
1697 |
/* SPRG */
|
1698 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
1699 |
&spr_read_ureg, SPR_NOACCESS, |
1700 |
&spr_read_ureg, SPR_NOACCESS, |
1701 |
0x00000000);
|
1702 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
1703 |
SPR_NOACCESS, SPR_NOACCESS, |
1704 |
SPR_NOACCESS, &spr_write_generic, |
1705 |
0x00000000);
|
1706 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
1707 |
&spr_read_ureg, SPR_NOACCESS, |
1708 |
&spr_read_ureg, SPR_NOACCESS, |
1709 |
0x00000000);
|
1710 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
1711 |
SPR_NOACCESS, SPR_NOACCESS, |
1712 |
SPR_NOACCESS, &spr_write_generic, |
1713 |
0x00000000);
|
1714 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
1715 |
&spr_read_ureg, SPR_NOACCESS, |
1716 |
&spr_read_ureg, SPR_NOACCESS, |
1717 |
0x00000000);
|
1718 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
1719 |
SPR_NOACCESS, SPR_NOACCESS, |
1720 |
SPR_NOACCESS, &spr_write_generic, |
1721 |
0x00000000);
|
1722 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
1723 |
&spr_read_ureg, SPR_NOACCESS, |
1724 |
&spr_read_ureg, SPR_NOACCESS, |
1725 |
0x00000000);
|
1726 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
1727 |
SPR_NOACCESS, SPR_NOACCESS, |
1728 |
SPR_NOACCESS, &spr_write_generic, |
1729 |
0x00000000);
|
1730 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
1731 |
&spr_read_ureg, SPR_NOACCESS, |
1732 |
&spr_read_ureg, SPR_NOACCESS, |
1733 |
0x00000000);
|
1734 |
/* Debug */
|
1735 |
/* XXX : not implemented */
|
1736 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1737 |
SPR_NOACCESS, SPR_NOACCESS, |
1738 |
&spr_read_generic, &spr_write_generic, |
1739 |
0x00000000);
|
1740 |
/* XXX : not implemented */
|
1741 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1742 |
SPR_NOACCESS, SPR_NOACCESS, |
1743 |
&spr_read_generic, &spr_write_generic, |
1744 |
0x00000000);
|
1745 |
} |
1746 |
|
1747 |
/* SPR shared between PowerPC 401 & 403 implementations */
|
1748 |
static void gen_spr_401_403 (CPUPPCState *env) |
1749 |
{ |
1750 |
/* Time base */
|
1751 |
spr_register(env, SPR_403_VTBL, "TBL",
|
1752 |
&spr_read_tbl, SPR_NOACCESS, |
1753 |
&spr_read_tbl, SPR_NOACCESS, |
1754 |
0x00000000);
|
1755 |
spr_register(env, SPR_403_TBL, "TBL",
|
1756 |
SPR_NOACCESS, SPR_NOACCESS, |
1757 |
SPR_NOACCESS, &spr_write_tbl, |
1758 |
0x00000000);
|
1759 |
spr_register(env, SPR_403_VTBU, "TBU",
|
1760 |
&spr_read_tbu, SPR_NOACCESS, |
1761 |
&spr_read_tbu, SPR_NOACCESS, |
1762 |
0x00000000);
|
1763 |
spr_register(env, SPR_403_TBU, "TBU",
|
1764 |
SPR_NOACCESS, SPR_NOACCESS, |
1765 |
SPR_NOACCESS, &spr_write_tbu, |
1766 |
0x00000000);
|
1767 |
/* Debug */
|
1768 |
/* XXX: not implemented */
|
1769 |
spr_register(env, SPR_403_CDBCR, "CDBCR",
|
1770 |
SPR_NOACCESS, SPR_NOACCESS, |
1771 |
&spr_read_generic, &spr_write_generic, |
1772 |
0x00000000);
|
1773 |
} |
1774 |
|
1775 |
/* SPR specific to PowerPC 403 implementation */
|
1776 |
static void gen_spr_403 (CPUPPCState *env) |
1777 |
{ |
1778 |
/* MMU */
|
1779 |
spr_register(env, SPR_403_PBL1, "PBL1",
|
1780 |
SPR_NOACCESS, SPR_NOACCESS, |
1781 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1782 |
0x00000000);
|
1783 |
spr_register(env, SPR_403_PBU1, "PBU1",
|
1784 |
SPR_NOACCESS, SPR_NOACCESS, |
1785 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1786 |
0x00000000);
|
1787 |
spr_register(env, SPR_403_PBL2, "PBL2",
|
1788 |
SPR_NOACCESS, SPR_NOACCESS, |
1789 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1790 |
0x00000000);
|
1791 |
spr_register(env, SPR_403_PBU2, "PBU2",
|
1792 |
SPR_NOACCESS, SPR_NOACCESS, |
1793 |
&spr_read_403_pbr, &spr_write_403_pbr, |
1794 |
0x00000000);
|
1795 |
/* Debug */
|
1796 |
/* XXX : not implemented */
|
1797 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
1798 |
SPR_NOACCESS, SPR_NOACCESS, |
1799 |
&spr_read_generic, &spr_write_generic, |
1800 |
0x00000000);
|
1801 |
/* XXX : not implemented */
|
1802 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
1803 |
SPR_NOACCESS, SPR_NOACCESS, |
1804 |
&spr_read_generic, &spr_write_generic, |
1805 |
0x00000000);
|
1806 |
} |
1807 |
|
1808 |
/* SPR specific to PowerPC compression coprocessor extension */
|
1809 |
#if defined (TODO)
|
1810 |
static void gen_spr_compress (CPUPPCState *env) |
1811 |
{ |
1812 |
spr_register(env, SPR_401_SKR, "SKR",
|
1813 |
SPR_NOACCESS, SPR_NOACCESS, |
1814 |
&spr_read_generic, &spr_write_generic, |
1815 |
0x00000000);
|
1816 |
} |
1817 |
#endif
|
1818 |
|
1819 |
// XXX: TODO (64 bits PowerPC SPRs)
|
1820 |
/*
|
1821 |
* ASR => SPR 280 (64 bits)
|
1822 |
* FPECR => SPR 1022 (?)
|
1823 |
* VRSAVE => SPR 256 (Altivec)
|
1824 |
* SCOMC => SPR 276 (64 bits ?)
|
1825 |
* SCOMD => SPR 277 (64 bits ?)
|
1826 |
* HSPRG0 => SPR 304 (hypervisor)
|
1827 |
* HSPRG1 => SPR 305 (hypervisor)
|
1828 |
* HDEC => SPR 310 (hypervisor)
|
1829 |
* HIOR => SPR 311 (hypervisor)
|
1830 |
* RMOR => SPR 312 (970)
|
1831 |
* HRMOR => SPR 313 (hypervisor)
|
1832 |
* HSRR0 => SPR 314 (hypervisor)
|
1833 |
* HSRR1 => SPR 315 (hypervisor)
|
1834 |
* LPCR => SPR 316 (970)
|
1835 |
* LPIDR => SPR 317 (970)
|
1836 |
* ... and more (thermal management, performance counters, ...)
|
1837 |
*/
|
1838 |
|
1839 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
1840 |
{ |
1841 |
env->reserve = -1;
|
1842 |
/* Default MMU definitions */
|
1843 |
env->nb_BATs = -1;
|
1844 |
env->nb_tlb = 0;
|
1845 |
env->nb_ways = 0;
|
1846 |
/* XXX: missing:
|
1847 |
* 32 bits PowerPC:
|
1848 |
* - MPC5xx(x)
|
1849 |
* - MPC8xx(x)
|
1850 |
* - RCPU (same as MPC5xx ?)
|
1851 |
*/
|
1852 |
spr_register(env, SPR_PVR, "PVR",
|
1853 |
SPR_NOACCESS, SPR_NOACCESS, |
1854 |
&spr_read_generic, SPR_NOACCESS, |
1855 |
def->pvr); |
1856 |
printf("%s: PVR %08x mask %08x => %08x\n", __func__,
|
1857 |
def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); |
1858 |
switch (def->pvr & def->pvr_mask) {
|
1859 |
/* Embedded PowerPC from IBM */
|
1860 |
case CPU_PPC_401A1: /* 401 A1 family */ |
1861 |
case CPU_PPC_401B2: /* 401 B2 family */ |
1862 |
case CPU_PPC_401C2: /* 401 C2 family */ |
1863 |
case CPU_PPC_401D2: /* 401 D2 family */ |
1864 |
case CPU_PPC_401E2: /* 401 E2 family */ |
1865 |
case CPU_PPC_401F2: /* 401 F2 family */ |
1866 |
case CPU_PPC_401G2: /* 401 G2 family */ |
1867 |
case CPU_PPC_IOP480: /* IOP 480 family */ |
1868 |
case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ |
1869 |
gen_spr_generic(env); |
1870 |
gen_spr_40x(env); |
1871 |
gen_spr_401_403(env); |
1872 |
#if defined (TODO)
|
1873 |
/* XXX: optional ? */
|
1874 |
gen_spr_compress(env); |
1875 |
#endif
|
1876 |
env->nb_BATs = 0;
|
1877 |
env->nb_tlb = 64;
|
1878 |
env->nb_ways = 1;
|
1879 |
env->id_tlbs = 0;
|
1880 |
/* XXX: TODO: allocate internal IRQ controller */
|
1881 |
break;
|
1882 |
|
1883 |
case CPU_PPC_403GA: /* 403 GA family */ |
1884 |
case CPU_PPC_403GB: /* 403 GB family */ |
1885 |
case CPU_PPC_403GC: /* 403 GC family */ |
1886 |
case CPU_PPC_403GCX: /* 403 GCX family */ |
1887 |
gen_spr_generic(env); |
1888 |
gen_spr_40x(env); |
1889 |
gen_spr_401_403(env); |
1890 |
gen_spr_403(env); |
1891 |
env->nb_BATs = 0;
|
1892 |
env->nb_tlb = 64;
|
1893 |
env->nb_ways = 1;
|
1894 |
env->id_tlbs = 0;
|
1895 |
/* XXX: TODO: allocate internal IRQ controller */
|
1896 |
break;
|
1897 |
|
1898 |
case CPU_PPC_405CR: /* 405 GP/CR family */ |
1899 |
case CPU_PPC_405EP: /* 405 EP family */ |
1900 |
case CPU_PPC_405GPR: /* 405 GPR family */ |
1901 |
case CPU_PPC_405D2: /* 405 D2 family */ |
1902 |
case CPU_PPC_405D4: /* 405 D4 family */ |
1903 |
gen_spr_generic(env); |
1904 |
/* Time base */
|
1905 |
gen_tbl(env); |
1906 |
gen_spr_40x(env); |
1907 |
gen_spr_405(env); |
1908 |
env->nb_BATs = 0;
|
1909 |
env->nb_tlb = 64;
|
1910 |
env->nb_ways = 1;
|
1911 |
env->id_tlbs = 0;
|
1912 |
/* XXX: TODO: allocate internal IRQ controller */
|
1913 |
break;
|
1914 |
|
1915 |
case CPU_PPC_NPE405H: /* NPe405 H family */ |
1916 |
case CPU_PPC_NPE405H2:
|
1917 |
case CPU_PPC_NPE405L: /* Npe405 L family */ |
1918 |
gen_spr_generic(env); |
1919 |
/* Time base */
|
1920 |
gen_tbl(env); |
1921 |
gen_spr_40x(env); |
1922 |
gen_spr_405(env); |
1923 |
env->nb_BATs = 0;
|
1924 |
env->nb_tlb = 64;
|
1925 |
env->nb_ways = 1;
|
1926 |
env->id_tlbs = 0;
|
1927 |
/* XXX: TODO: allocate internal IRQ controller */
|
1928 |
break;
|
1929 |
|
1930 |
#if defined (TODO)
|
1931 |
case CPU_PPC_STB01000:
|
1932 |
#endif
|
1933 |
#if defined (TODO)
|
1934 |
case CPU_PPC_STB01010:
|
1935 |
#endif
|
1936 |
#if defined (TODO)
|
1937 |
case CPU_PPC_STB0210:
|
1938 |
#endif
|
1939 |
case CPU_PPC_STB03: /* STB03 family */ |
1940 |
#if defined (TODO)
|
1941 |
case CPU_PPC_STB043: /* STB043 family */ |
1942 |
#endif
|
1943 |
#if defined (TODO)
|
1944 |
case CPU_PPC_STB045: /* STB045 family */ |
1945 |
#endif
|
1946 |
case CPU_PPC_STB25: /* STB25 family */ |
1947 |
#if defined (TODO)
|
1948 |
case CPU_PPC_STB130: /* STB130 family */ |
1949 |
#endif
|
1950 |
gen_spr_generic(env); |
1951 |
/* Time base */
|
1952 |
gen_tbl(env); |
1953 |
gen_spr_40x(env); |
1954 |
gen_spr_405(env); |
1955 |
env->nb_BATs = 0;
|
1956 |
env->nb_tlb = 64;
|
1957 |
env->nb_ways = 1;
|
1958 |
env->id_tlbs = 0;
|
1959 |
/* XXX: TODO: allocate internal IRQ controller */
|
1960 |
break;
|
1961 |
|
1962 |
case CPU_PPC_440EP: /* 440 EP family */ |
1963 |
case CPU_PPC_440GP: /* 440 GP family */ |
1964 |
case CPU_PPC_440GX: /* 440 GX family */ |
1965 |
case CPU_PPC_440GXc: /* 440 GXc family */ |
1966 |
case CPU_PPC_440GXf: /* 440 GXf family */ |
1967 |
case CPU_PPC_440SP: /* 440 SP family */ |
1968 |
case CPU_PPC_440SP2:
|
1969 |
case CPU_PPC_440SPE: /* 440 SPE family */ |
1970 |
gen_spr_generic(env); |
1971 |
/* Time base */
|
1972 |
gen_tbl(env); |
1973 |
gen_spr_BookE(env); |
1974 |
gen_spr_440(env); |
1975 |
env->nb_BATs = 0;
|
1976 |
env->nb_tlb = 64;
|
1977 |
env->nb_ways = 1;
|
1978 |
env->id_tlbs = 0;
|
1979 |
/* XXX: TODO: allocate internal IRQ controller */
|
1980 |
break;
|
1981 |
|
1982 |
/* Embedded PowerPC from Freescale */
|
1983 |
#if defined (TODO)
|
1984 |
case CPU_PPC_5xx:
|
1985 |
break;
|
1986 |
#endif
|
1987 |
#if defined (TODO)
|
1988 |
case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ |
1989 |
break;
|
1990 |
#endif
|
1991 |
#if defined (TODO)
|
1992 |
case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ |
1993 |
case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ |
1994 |
break;
|
1995 |
#endif
|
1996 |
#if defined (TODO)
|
1997 |
case CPU_PPC_827x: /* MPC 827x / 828x */ |
1998 |
break;
|
1999 |
#endif
|
2000 |
|
2001 |
/* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
|
2002 |
case CPU_PPC_e500v110:
|
2003 |
case CPU_PPC_e500v120:
|
2004 |
case CPU_PPC_e500v210:
|
2005 |
case CPU_PPC_e500v220:
|
2006 |
gen_spr_generic(env); |
2007 |
/* Time base */
|
2008 |
gen_tbl(env); |
2009 |
gen_spr_BookE(env); |
2010 |
gen_spr_BookE_FSL(env); |
2011 |
env->nb_BATs = 0;
|
2012 |
env->nb_tlb = 64;
|
2013 |
env->nb_ways = 1;
|
2014 |
env->id_tlbs = 0;
|
2015 |
/* XXX: TODO: allocate internal IRQ controller */
|
2016 |
break;
|
2017 |
|
2018 |
#if defined (TODO)
|
2019 |
case CPU_PPC_e600:
|
2020 |
break;
|
2021 |
#endif
|
2022 |
|
2023 |
/* 32 bits PowerPC */
|
2024 |
case CPU_PPC_601: /* PowerPC 601 */ |
2025 |
gen_spr_generic(env); |
2026 |
gen_spr_ne_601(env); |
2027 |
gen_spr_601(env); |
2028 |
/* Hardware implementation registers */
|
2029 |
/* XXX : not implemented */
|
2030 |
spr_register(env, SPR_HID0, "HID0",
|
2031 |
SPR_NOACCESS, SPR_NOACCESS, |
2032 |
&spr_read_generic, &spr_write_generic, |
2033 |
0x00000000);
|
2034 |
/* XXX : not implemented */
|
2035 |
spr_register(env, SPR_HID1, "HID1",
|
2036 |
SPR_NOACCESS, SPR_NOACCESS, |
2037 |
&spr_read_generic, &spr_write_generic, |
2038 |
0x00000000);
|
2039 |
/* XXX : not implemented */
|
2040 |
spr_register(env, SPR_601_HID2, "HID2",
|
2041 |
SPR_NOACCESS, SPR_NOACCESS, |
2042 |
&spr_read_generic, &spr_write_generic, |
2043 |
0x00000000);
|
2044 |
/* XXX : not implemented */
|
2045 |
spr_register(env, SPR_601_HID5, "HID5",
|
2046 |
SPR_NOACCESS, SPR_NOACCESS, |
2047 |
&spr_read_generic, &spr_write_generic, |
2048 |
0x00000000);
|
2049 |
/* XXX : not implemented */
|
2050 |
#if 0 /* ? */
|
2051 |
spr_register(env, SPR_601_HID15, "HID15",
|
2052 |
SPR_NOACCESS, SPR_NOACCESS,
|
2053 |
&spr_read_generic, &spr_write_generic,
|
2054 |
0x00000000);
|
2055 |
#endif
|
2056 |
env->nb_tlb = 64;
|
2057 |
env->nb_ways = 2;
|
2058 |
env->id_tlbs = 0;
|
2059 |
env->id_tlbs = 0;
|
2060 |
/* XXX: TODO: allocate internal IRQ controller */
|
2061 |
break;
|
2062 |
|
2063 |
case CPU_PPC_602: /* PowerPC 602 */ |
2064 |
gen_spr_generic(env); |
2065 |
gen_spr_ne_601(env); |
2066 |
/* Memory management */
|
2067 |
gen_low_BATs(env); |
2068 |
/* Time base */
|
2069 |
gen_tbl(env); |
2070 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2071 |
gen_spr_602(env); |
2072 |
/* hardware implementation registers */
|
2073 |
/* XXX : not implemented */
|
2074 |
spr_register(env, SPR_HID0, "HID0",
|
2075 |
SPR_NOACCESS, SPR_NOACCESS, |
2076 |
&spr_read_generic, &spr_write_generic, |
2077 |
0x00000000);
|
2078 |
/* XXX : not implemented */
|
2079 |
spr_register(env, SPR_HID1, "HID1",
|
2080 |
SPR_NOACCESS, SPR_NOACCESS, |
2081 |
&spr_read_generic, &spr_write_generic, |
2082 |
0x00000000);
|
2083 |
/* Allocate hardware IRQ controller */
|
2084 |
ppc6xx_irq_init(env); |
2085 |
break;
|
2086 |
|
2087 |
case CPU_PPC_603: /* PowerPC 603 */ |
2088 |
case CPU_PPC_603E: /* PowerPC 603e */ |
2089 |
case CPU_PPC_603E7v:
|
2090 |
case CPU_PPC_603E7v2:
|
2091 |
case CPU_PPC_603P: /* PowerPC 603p */ |
2092 |
case CPU_PPC_603R: /* PowerPC 603r */ |
2093 |
gen_spr_generic(env); |
2094 |
gen_spr_ne_601(env); |
2095 |
/* Memory management */
|
2096 |
gen_low_BATs(env); |
2097 |
/* Time base */
|
2098 |
gen_tbl(env); |
2099 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2100 |
gen_spr_603(env); |
2101 |
/* hardware implementation registers */
|
2102 |
/* XXX : not implemented */
|
2103 |
spr_register(env, SPR_HID0, "HID0",
|
2104 |
SPR_NOACCESS, SPR_NOACCESS, |
2105 |
&spr_read_generic, &spr_write_generic, |
2106 |
0x00000000);
|
2107 |
/* XXX : not implemented */
|
2108 |
spr_register(env, SPR_HID1, "HID1",
|
2109 |
SPR_NOACCESS, SPR_NOACCESS, |
2110 |
&spr_read_generic, &spr_write_generic, |
2111 |
0x00000000);
|
2112 |
/* Allocate hardware IRQ controller */
|
2113 |
ppc6xx_irq_init(env); |
2114 |
break;
|
2115 |
|
2116 |
case CPU_PPC_G2: /* PowerPC G2 family */ |
2117 |
case CPU_PPC_G2H4:
|
2118 |
case CPU_PPC_G2gp:
|
2119 |
case CPU_PPC_G2ls:
|
2120 |
case CPU_PPC_G2LE: /* PowerPC G2LE family */ |
2121 |
case CPU_PPC_G2LEgp:
|
2122 |
case CPU_PPC_G2LEls:
|
2123 |
gen_spr_generic(env); |
2124 |
gen_spr_ne_601(env); |
2125 |
/* Memory management */
|
2126 |
gen_low_BATs(env); |
2127 |
/* Time base */
|
2128 |
gen_tbl(env); |
2129 |
/* Memory management */
|
2130 |
gen_high_BATs(env); |
2131 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2132 |
gen_spr_G2_755(env); |
2133 |
gen_spr_G2(env); |
2134 |
/* Hardware implementation register */
|
2135 |
/* XXX : not implemented */
|
2136 |
spr_register(env, SPR_HID0, "HID0",
|
2137 |
SPR_NOACCESS, SPR_NOACCESS, |
2138 |
&spr_read_generic, &spr_write_generic, |
2139 |
0x00000000);
|
2140 |
/* XXX : not implemented */
|
2141 |
spr_register(env, SPR_HID1, "HID1",
|
2142 |
SPR_NOACCESS, SPR_NOACCESS, |
2143 |
&spr_read_generic, &spr_write_generic, |
2144 |
0x00000000);
|
2145 |
/* XXX : not implemented */
|
2146 |
spr_register(env, SPR_HID2, "HID2",
|
2147 |
SPR_NOACCESS, SPR_NOACCESS, |
2148 |
&spr_read_generic, &spr_write_generic, |
2149 |
0x00000000);
|
2150 |
/* Allocate hardware IRQ controller */
|
2151 |
ppc6xx_irq_init(env); |
2152 |
break;
|
2153 |
|
2154 |
case CPU_PPC_604: /* PowerPC 604 */ |
2155 |
case CPU_PPC_604E: /* PowerPC 604e */ |
2156 |
case CPU_PPC_604R: /* PowerPC 604r */ |
2157 |
gen_spr_generic(env); |
2158 |
gen_spr_ne_601(env); |
2159 |
/* Memory management */
|
2160 |
gen_low_BATs(env); |
2161 |
/* Time base */
|
2162 |
gen_tbl(env); |
2163 |
gen_spr_604(env); |
2164 |
/* Hardware implementation registers */
|
2165 |
/* XXX : not implemented */
|
2166 |
spr_register(env, SPR_HID0, "HID0",
|
2167 |
SPR_NOACCESS, SPR_NOACCESS, |
2168 |
&spr_read_generic, &spr_write_generic, |
2169 |
0x00000000);
|
2170 |
/* XXX : not implemented */
|
2171 |
spr_register(env, SPR_HID1, "HID1",
|
2172 |
SPR_NOACCESS, SPR_NOACCESS, |
2173 |
&spr_read_generic, &spr_write_generic, |
2174 |
0x00000000);
|
2175 |
/* Allocate hardware IRQ controller */
|
2176 |
ppc6xx_irq_init(env); |
2177 |
break;
|
2178 |
|
2179 |
case CPU_PPC_74x: /* PowerPC 740 / 750 */ |
2180 |
case CPU_PPC_740E:
|
2181 |
case CPU_PPC_750E:
|
2182 |
case CPU_PPC_74xP: /* PowerPC 740P / 750P */ |
2183 |
case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ |
2184 |
case CPU_PPC_750CXE22:
|
2185 |
case CPU_PPC_750CXE23:
|
2186 |
case CPU_PPC_750CXE24:
|
2187 |
case CPU_PPC_750CXE24b:
|
2188 |
case CPU_PPC_750CXE31:
|
2189 |
case CPU_PPC_750CXE31b:
|
2190 |
case CPU_PPC_750CXR:
|
2191 |
gen_spr_generic(env); |
2192 |
gen_spr_ne_601(env); |
2193 |
/* Memory management */
|
2194 |
gen_low_BATs(env); |
2195 |
/* Time base */
|
2196 |
gen_tbl(env); |
2197 |
gen_spr_7xx(env); |
2198 |
/* Hardware implementation registers */
|
2199 |
/* XXX : not implemented */
|
2200 |
spr_register(env, SPR_HID0, "HID0",
|
2201 |
SPR_NOACCESS, SPR_NOACCESS, |
2202 |
&spr_read_generic, &spr_write_generic, |
2203 |
0x00000000);
|
2204 |
/* XXX : not implemented */
|
2205 |
spr_register(env, SPR_HID1, "HID1",
|
2206 |
SPR_NOACCESS, SPR_NOACCESS, |
2207 |
&spr_read_generic, &spr_write_generic, |
2208 |
0x00000000);
|
2209 |
/* Allocate hardware IRQ controller */
|
2210 |
ppc6xx_irq_init(env); |
2211 |
break;
|
2212 |
|
2213 |
case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ |
2214 |
case CPU_PPC_750FX20:
|
2215 |
case CPU_PPC_750FX21:
|
2216 |
case CPU_PPC_750FX22:
|
2217 |
case CPU_PPC_750FX23:
|
2218 |
case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ |
2219 |
case CPU_PPC_750GX11:
|
2220 |
case CPU_PPC_750GX12:
|
2221 |
gen_spr_generic(env); |
2222 |
gen_spr_ne_601(env); |
2223 |
/* Memory management */
|
2224 |
gen_low_BATs(env); |
2225 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
2226 |
gen_high_BATs(env); |
2227 |
/* Time base */
|
2228 |
gen_tbl(env); |
2229 |
gen_spr_7xx(env); |
2230 |
/* Hardware implementation registers */
|
2231 |
/* XXX : not implemented */
|
2232 |
spr_register(env, SPR_HID0, "HID0",
|
2233 |
SPR_NOACCESS, SPR_NOACCESS, |
2234 |
&spr_read_generic, &spr_write_generic, |
2235 |
0x00000000);
|
2236 |
/* XXX : not implemented */
|
2237 |
spr_register(env, SPR_HID1, "HID1",
|
2238 |
SPR_NOACCESS, SPR_NOACCESS, |
2239 |
&spr_read_generic, &spr_write_generic, |
2240 |
0x00000000);
|
2241 |
/* XXX : not implemented */
|
2242 |
spr_register(env, SPR_750_HID2, "HID2",
|
2243 |
SPR_NOACCESS, SPR_NOACCESS, |
2244 |
&spr_read_generic, &spr_write_generic, |
2245 |
0x00000000);
|
2246 |
/* Allocate hardware IRQ controller */
|
2247 |
ppc6xx_irq_init(env); |
2248 |
break;
|
2249 |
|
2250 |
case CPU_PPC_755_10: /* PowerPC 755 */ |
2251 |
case CPU_PPC_755_11:
|
2252 |
case CPU_PPC_755_20:
|
2253 |
case CPU_PPC_755D:
|
2254 |
case CPU_PPC_755E:
|
2255 |
gen_spr_generic(env); |
2256 |
gen_spr_ne_601(env); |
2257 |
/* Memory management */
|
2258 |
gen_low_BATs(env); |
2259 |
/* Time base */
|
2260 |
gen_tbl(env); |
2261 |
/* Memory management */
|
2262 |
gen_high_BATs(env); |
2263 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
2264 |
gen_spr_G2_755(env); |
2265 |
/* L2 cache control */
|
2266 |
/* XXX : not implemented */
|
2267 |
spr_register(env, SPR_ICTC, "ICTC",
|
2268 |
SPR_NOACCESS, SPR_NOACCESS, |
2269 |
&spr_read_generic, &spr_write_generic, |
2270 |
0x00000000);
|
2271 |
/* XXX : not implemented */
|
2272 |
spr_register(env, SPR_L2PM, "L2PM",
|
2273 |
SPR_NOACCESS, SPR_NOACCESS, |
2274 |
&spr_read_generic, &spr_write_generic, |
2275 |
0x00000000);
|
2276 |
/* Hardware implementation registers */
|
2277 |
/* XXX : not implemented */
|
2278 |
spr_register(env, SPR_HID0, "HID0",
|
2279 |
SPR_NOACCESS, SPR_NOACCESS, |
2280 |
&spr_read_generic, &spr_write_generic, |
2281 |
0x00000000);
|
2282 |
/* XXX : not implemented */
|
2283 |
spr_register(env, SPR_HID1, "HID1",
|
2284 |
SPR_NOACCESS, SPR_NOACCESS, |
2285 |
&spr_read_generic, &spr_write_generic, |
2286 |
0x00000000);
|
2287 |
/* XXX : not implemented */
|
2288 |
spr_register(env, SPR_HID2, "HID2",
|
2289 |
SPR_NOACCESS, SPR_NOACCESS, |
2290 |
&spr_read_generic, &spr_write_generic, |
2291 |
0x00000000);
|
2292 |
/* Allocate hardware IRQ controller */
|
2293 |
ppc6xx_irq_init(env); |
2294 |
break;
|
2295 |
|
2296 |
#if defined (TODO)
|
2297 |
/* G4 family */
|
2298 |
case CPU_PPC_7400: /* PowerPC 7400 */ |
2299 |
case CPU_PPC_7410C: /* PowerPC 7410 */ |
2300 |
case CPU_PPC_7410D:
|
2301 |
case CPU_PPC_7410E:
|
2302 |
case CPU_PPC_7441: /* PowerPC 7441 */ |
2303 |
case CPU_PPC_7445: /* PowerPC 7445 */ |
2304 |
case CPU_PPC_7447: /* PowerPC 7447 */ |
2305 |
case CPU_PPC_7447A: /* PowerPC 7447A */ |
2306 |
case CPU_PPC_7448: /* PowerPC 7448 */ |
2307 |
case CPU_PPC_7450: /* PowerPC 7450 */ |
2308 |
case CPU_PPC_7450b:
|
2309 |
case CPU_PPC_7451: /* PowerPC 7451 */ |
2310 |
case CPU_PPC_7451G:
|
2311 |
case CPU_PPC_7455: /* PowerPC 7455 */ |
2312 |
case CPU_PPC_7455F:
|
2313 |
case CPU_PPC_7455G:
|
2314 |
case CPU_PPC_7457: /* PowerPC 7457 */ |
2315 |
case CPU_PPC_7457C:
|
2316 |
case CPU_PPC_7457A: /* PowerPC 7457A */ |
2317 |
break;
|
2318 |
#endif
|
2319 |
|
2320 |
/* 64 bits PowerPC */
|
2321 |
#if defined (TARGET_PPC64)
|
2322 |
#if defined (TODO)
|
2323 |
case CPU_PPC_620: /* PowerPC 620 */ |
2324 |
case CPU_PPC_630: /* PowerPC 630 (Power 3) */ |
2325 |
case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ |
2326 |
case CPU_PPC_POWER4: /* Power 4 */ |
2327 |
case CPU_PPC_POWER4P: /* Power 4+ */ |
2328 |
case CPU_PPC_POWER5: /* Power 5 */ |
2329 |
case CPU_PPC_POWER5P: /* Power 5+ */ |
2330 |
#endif
|
2331 |
case CPU_PPC_970: /* PowerPC 970 */ |
2332 |
case CPU_PPC_970FX10: /* PowerPC 970 FX */ |
2333 |
case CPU_PPC_970FX20:
|
2334 |
case CPU_PPC_970FX21:
|
2335 |
case CPU_PPC_970FX30:
|
2336 |
case CPU_PPC_970FX31:
|
2337 |
case CPU_PPC_970MP10: /* PowerPC 970 MP */ |
2338 |
case CPU_PPC_970MP11:
|
2339 |
#if defined (TODO)
|
2340 |
case CPU_PPC_CELL10: /* Cell family */ |
2341 |
case CPU_PPC_CELL20:
|
2342 |
case CPU_PPC_CELL30:
|
2343 |
case CPU_PPC_CELL31:
|
2344 |
#endif
|
2345 |
#if defined (TODO)
|
2346 |
case CPU_PPC_RS64: /* Apache (RS64/A35) */ |
2347 |
case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ |
2348 |
case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ |
2349 |
case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ |
2350 |
#endif
|
2351 |
break;
|
2352 |
#endif /* defined (TARGET_PPC64) */ |
2353 |
|
2354 |
#if defined (TODO)
|
2355 |
/* POWER */
|
2356 |
case CPU_POWER: /* POWER */ |
2357 |
case CPU_POWER2: /* POWER2 */ |
2358 |
break;
|
2359 |
#endif
|
2360 |
|
2361 |
default:
|
2362 |
gen_spr_generic(env); |
2363 |
/* XXX: TODO: allocate internal IRQ controller */
|
2364 |
break;
|
2365 |
} |
2366 |
if (env->nb_BATs == -1) |
2367 |
env->nb_BATs = 4;
|
2368 |
/* Allocate TLBs buffer when needed */
|
2369 |
if (env->nb_tlb != 0) { |
2370 |
int nb_tlb = env->nb_tlb;
|
2371 |
if (env->id_tlbs != 0) |
2372 |
nb_tlb *= 2;
|
2373 |
env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
|
2374 |
/* Pre-compute some useful values */
|
2375 |
env->tlb_per_way = env->nb_tlb / env->nb_ways; |
2376 |
} |
2377 |
} |
2378 |
|
2379 |
#if defined(PPC_DUMP_CPU)
|
2380 |
static void dump_sprs (CPUPPCState *env) |
2381 |
{ |
2382 |
ppc_spr_t *spr; |
2383 |
uint32_t pvr = env->spr[SPR_PVR]; |
2384 |
uint32_t sr, sw, ur, uw; |
2385 |
int i, j, n;
|
2386 |
|
2387 |
printf("* SPRs for PVR=%08x\n", pvr);
|
2388 |
for (i = 0; i < 32; i++) { |
2389 |
for (j = 0; j < 32; j++) { |
2390 |
n = (i << 5) | j;
|
2391 |
spr = &env->spr_cb[n]; |
2392 |
#if !defined(CONFIG_USER_ONLY)
|
2393 |
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
2394 |
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
2395 |
#else
|
2396 |
sw = 0;
|
2397 |
sr = 0;
|
2398 |
#endif
|
2399 |
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
2400 |
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
2401 |
if (sw || sr || uw || ur) {
|
2402 |
printf("%4d (%03x) %8s s%c%c u%c%c\n",
|
2403 |
(i << 5) | j, (i << 5) | j, spr->name, |
2404 |
sw ? 'w' : '-', sr ? 'r' : '-', |
2405 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
2406 |
} |
2407 |
} |
2408 |
} |
2409 |
fflush(stdout); |
2410 |
fflush(stderr); |
2411 |
} |
2412 |
#endif
|
2413 |
|
2414 |
/*****************************************************************************/
|
2415 |
#include <stdlib.h> |
2416 |
#include <string.h> |
2417 |
|
2418 |
int fflush (FILE *stream);
|
2419 |
|
2420 |
/* Opcode types */
|
2421 |
enum {
|
2422 |
PPC_DIRECT = 0, /* Opcode routine */ |
2423 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
2424 |
}; |
2425 |
|
2426 |
static inline int is_indirect_opcode (void *handler) |
2427 |
{ |
2428 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
2429 |
} |
2430 |
|
2431 |
static inline opc_handler_t **ind_table(void *handler) |
2432 |
{ |
2433 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
2434 |
} |
2435 |
|
2436 |
/* Instruction table creation */
|
2437 |
/* Opcodes tables creation */
|
2438 |
static void fill_new_table (opc_handler_t **table, int len) |
2439 |
{ |
2440 |
int i;
|
2441 |
|
2442 |
for (i = 0; i < len; i++) |
2443 |
table[i] = &invalid_handler; |
2444 |
} |
2445 |
|
2446 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
2447 |
{ |
2448 |
opc_handler_t **tmp; |
2449 |
|
2450 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
2451 |
if (tmp == NULL) |
2452 |
return -1; |
2453 |
fill_new_table(tmp, 0x20);
|
2454 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
2455 |
|
2456 |
return 0; |
2457 |
} |
2458 |
|
2459 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
2460 |
opc_handler_t *handler) |
2461 |
{ |
2462 |
if (table[idx] != &invalid_handler)
|
2463 |
return -1; |
2464 |
table[idx] = handler; |
2465 |
|
2466 |
return 0; |
2467 |
} |
2468 |
|
2469 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
2470 |
unsigned char idx, opc_handler_t *handler) |
2471 |
{ |
2472 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
2473 |
printf("*** ERROR: opcode %02x already assigned in main "
|
2474 |
"opcode table\n", idx);
|
2475 |
return -1; |
2476 |
} |
2477 |
|
2478 |
return 0; |
2479 |
} |
2480 |
|
2481 |
static int register_ind_in_table (opc_handler_t **table, |
2482 |
unsigned char idx1, unsigned char idx2, |
2483 |
opc_handler_t *handler) |
2484 |
{ |
2485 |
if (table[idx1] == &invalid_handler) {
|
2486 |
if (create_new_table(table, idx1) < 0) { |
2487 |
printf("*** ERROR: unable to create indirect table "
|
2488 |
"idx=%02x\n", idx1);
|
2489 |
return -1; |
2490 |
} |
2491 |
} else {
|
2492 |
if (!is_indirect_opcode(table[idx1])) {
|
2493 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
2494 |
"opcode\n", idx1);
|
2495 |
return -1; |
2496 |
} |
2497 |
} |
2498 |
if (handler != NULL && |
2499 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
2500 |
printf("*** ERROR: opcode %02x already assigned in "
|
2501 |
"opcode table %02x\n", idx2, idx1);
|
2502 |
return -1; |
2503 |
} |
2504 |
|
2505 |
return 0; |
2506 |
} |
2507 |
|
2508 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
2509 |
unsigned char idx1, unsigned char idx2, |
2510 |
opc_handler_t *handler) |
2511 |
{ |
2512 |
int ret;
|
2513 |
|
2514 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
2515 |
|
2516 |
return ret;
|
2517 |
} |
2518 |
|
2519 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
2520 |
unsigned char idx1, unsigned char idx2, |
2521 |
unsigned char idx3, opc_handler_t *handler) |
2522 |
{ |
2523 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
2524 |
printf("*** ERROR: unable to join indirect table idx "
|
2525 |
"[%02x-%02x]\n", idx1, idx2);
|
2526 |
return -1; |
2527 |
} |
2528 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
2529 |
handler) < 0) {
|
2530 |
printf("*** ERROR: unable to insert opcode "
|
2531 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
2532 |
return -1; |
2533 |
} |
2534 |
|
2535 |
return 0; |
2536 |
} |
2537 |
|
2538 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
2539 |
{ |
2540 |
if (insn->opc2 != 0xFF) { |
2541 |
if (insn->opc3 != 0xFF) { |
2542 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
2543 |
insn->opc3, &insn->handler) < 0)
|
2544 |
return -1; |
2545 |
} else {
|
2546 |
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
2547 |
insn->opc2, &insn->handler) < 0)
|
2548 |
return -1; |
2549 |
} |
2550 |
} else {
|
2551 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
2552 |
return -1; |
2553 |
} |
2554 |
|
2555 |
return 0; |
2556 |
} |
2557 |
|
2558 |
static int test_opcode_table (opc_handler_t **table, int len) |
2559 |
{ |
2560 |
int i, count, tmp;
|
2561 |
|
2562 |
for (i = 0, count = 0; i < len; i++) { |
2563 |
/* Consistency fixup */
|
2564 |
if (table[i] == NULL) |
2565 |
table[i] = &invalid_handler; |
2566 |
if (table[i] != &invalid_handler) {
|
2567 |
if (is_indirect_opcode(table[i])) {
|
2568 |
tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
2569 |
if (tmp == 0) { |
2570 |
free(table[i]); |
2571 |
table[i] = &invalid_handler; |
2572 |
} else {
|
2573 |
count++; |
2574 |
} |
2575 |
} else {
|
2576 |
count++; |
2577 |
} |
2578 |
} |
2579 |
} |
2580 |
|
2581 |
return count;
|
2582 |
} |
2583 |
|
2584 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
2585 |
{ |
2586 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
2587 |
printf("*** WARNING: no opcode defined !\n");
|
2588 |
} |
2589 |
|
2590 |
/*****************************************************************************/
|
2591 |
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) |
2592 |
{ |
2593 |
opcode_t *opc, *start, *end; |
2594 |
|
2595 |
fill_new_table(env->opcodes, 0x40);
|
2596 |
#if defined(PPC_DUMP_CPU)
|
2597 |
printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
|
2598 |
" %08x\n",
|
2599 |
def->pvr, def->name, def->insns_flags, def->flags); |
2600 |
#endif
|
2601 |
if (&opc_start < &opc_end) {
|
2602 |
start = &opc_start; |
2603 |
end = &opc_end; |
2604 |
} else {
|
2605 |
start = &opc_end; |
2606 |
end = &opc_start; |
2607 |
} |
2608 |
for (opc = start + 1; opc != end; opc++) { |
2609 |
if ((opc->handler.type & def->insns_flags) != 0) { |
2610 |
if (register_insn(env->opcodes, opc) < 0) { |
2611 |
printf("*** ERROR initializing PowerPC instruction "
|
2612 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
2613 |
opc->opc3); |
2614 |
return -1; |
2615 |
} |
2616 |
#if defined(PPC_DUMP_CPU)
|
2617 |
if (opc1 != 0x00) { |
2618 |
if (opc->opc3 == 0xFF) { |
2619 |
if (opc->opc2 == 0xFF) { |
2620 |
printf(" %02x -- -- (%2d ----) : %s\n",
|
2621 |
opc->opc1, opc->opc1, opc->oname); |
2622 |
} else {
|
2623 |
printf(" %02x %02x -- (%2d %4d) : %s\n",
|
2624 |
opc->opc1, opc->opc2, opc->opc1, opc->opc2, |
2625 |
opc->oname); |
2626 |
} |
2627 |
} else {
|
2628 |
printf(" %02x %02x %02x (%2d %4d) : %s\n",
|
2629 |
opc->opc1, opc->opc2, opc->opc3, |
2630 |
opc->opc1, (opc->opc3 << 5) | opc->opc2,
|
2631 |
opc->oname); |
2632 |
} |
2633 |
} |
2634 |
#endif
|
2635 |
} |
2636 |
} |
2637 |
fix_opcode_tables(env->opcodes); |
2638 |
fflush(stdout); |
2639 |
fflush(stderr); |
2640 |
|
2641 |
return 0; |
2642 |
} |
2643 |
|
2644 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
|
2645 |
{ |
2646 |
env->msr_mask = def->msr_mask; |
2647 |
env->flags = def->flags; |
2648 |
if (create_ppc_opcodes(env, def) < 0) |
2649 |
return -1; |
2650 |
init_ppc_proc(env, def); |
2651 |
#if defined(PPC_DUMP_CPU)
|
2652 |
dump_sprs(env); |
2653 |
if (env->tlb != NULL) { |
2654 |
printf("%d %s TLB in %d ways\n", env->nb_tlb,
|
2655 |
env->id_tlbs ? "splitted" : "merged", env->nb_ways); |
2656 |
} |
2657 |
#endif
|
2658 |
|
2659 |
return 0; |
2660 |
} |
2661 |
|
2662 |
void do_compute_hflags (CPUPPCState *env);
|
2663 |
CPUPPCState *cpu_ppc_init (void)
|
2664 |
{ |
2665 |
CPUPPCState *env; |
2666 |
|
2667 |
env = qemu_mallocz(sizeof(CPUPPCState));
|
2668 |
if (!env)
|
2669 |
return NULL; |
2670 |
cpu_exec_init(env); |
2671 |
tlb_flush(env, 1);
|
2672 |
#if defined (DO_SINGLE_STEP) && 0 |
2673 |
/* Single step trace mode */
|
2674 |
msr_se = 1;
|
2675 |
msr_be = 1;
|
2676 |
#endif
|
2677 |
msr_fp = 1; /* Allow floating point exceptions */ |
2678 |
msr_me = 1; /* Allow machine check exceptions */ |
2679 |
#if defined(CONFIG_USER_ONLY)
|
2680 |
msr_pr = 1;
|
2681 |
#else
|
2682 |
env->nip = 0xFFFFFFFC;
|
2683 |
#endif
|
2684 |
do_compute_hflags(env); |
2685 |
env->reserve = -1;
|
2686 |
return env;
|
2687 |
} |
2688 |
|
2689 |
void cpu_ppc_close(CPUPPCState *env)
|
2690 |
{ |
2691 |
/* Should also remove all opcode tables... */
|
2692 |
free(env); |
2693 |
} |
2694 |
|
2695 |
/*****************************************************************************/
|
2696 |
/* PowerPC CPU definitions */
|
2697 |
static ppc_def_t ppc_defs[] =
|
2698 |
{ |
2699 |
/* Embedded PowerPC */
|
2700 |
#if defined (TODO)
|
2701 |
/* PowerPC 401 */
|
2702 |
{ |
2703 |
.name = "401",
|
2704 |
.pvr = CPU_PPC_401, |
2705 |
.pvr_mask = 0xFFFF0000,
|
2706 |
.insns_flags = PPC_INSNS_401, |
2707 |
.flags = PPC_FLAGS_401, |
2708 |
.msr_mask = xxx, |
2709 |
}, |
2710 |
#endif
|
2711 |
#if defined (TODO)
|
2712 |
/* IOP480 (401 microcontroler) */
|
2713 |
{ |
2714 |
.name = "iop480",
|
2715 |
.pvr = CPU_PPC_IOP480, |
2716 |
.pvr_mask = 0xFFFF0000,
|
2717 |
.insns_flags = PPC_INSNS_401, |
2718 |
.flags = PPC_FLAGS_401, |
2719 |
.msr_mask = xxx, |
2720 |
}, |
2721 |
#endif
|
2722 |
#if defined (TODO)
|
2723 |
/* IBM Processor for Network Resources */
|
2724 |
{ |
2725 |
.name = "Cobra",
|
2726 |
.pvr = CPU_PPC_COBRA, |
2727 |
.pvr_mask = 0xFFFF0000,
|
2728 |
.insns_flags = PPC_INSNS_401, |
2729 |
.flags = PPC_FLAGS_401, |
2730 |
.msr_mask = xxx, |
2731 |
}, |
2732 |
#endif
|
2733 |
#if defined (TODO)
|
2734 |
/* Generic PowerPC 403 */
|
2735 |
{ |
2736 |
.name = "403",
|
2737 |
.pvr = CPU_PPC_403, |
2738 |
.pvr_mask = 0xFFFFFF00,
|
2739 |
.insns_flags = PPC_INSNS_403, |
2740 |
.flags = PPC_FLAGS_403, |
2741 |
.msr_mask = 0x000000000007D23D,
|
2742 |
}, |
2743 |
#endif
|
2744 |
#if defined (TODO)
|
2745 |
/* PowerPC 403 GA */
|
2746 |
{ |
2747 |
.name = "403ga",
|
2748 |
.pvr = CPU_PPC_403GA, |
2749 |
.pvr_mask = 0xFFFFFF00,
|
2750 |
.insns_flags = PPC_INSNS_403, |
2751 |
.flags = PPC_FLAGS_403, |
2752 |
.msr_mask = 0x000000000007D23D,
|
2753 |
}, |
2754 |
#endif
|
2755 |
#if defined (TODO)
|
2756 |
/* PowerPC 403 GB */
|
2757 |
{ |
2758 |
.name = "403gb",
|
2759 |
.pvr = CPU_PPC_403GB, |
2760 |
.pvr_mask = 0xFFFFFF00,
|
2761 |
.insns_flags = PPC_INSNS_403, |
2762 |
.flags = PPC_FLAGS_403, |
2763 |
.msr_mask = 0x000000000007D23D,
|
2764 |
}, |
2765 |
#endif
|
2766 |
#if defined (TODO)
|
2767 |
/* PowerPC 403 GC */
|
2768 |
{ |
2769 |
.name = "403gc",
|
2770 |
.pvr = CPU_PPC_403GC, |
2771 |
.pvr_mask = 0xFFFFFF00,
|
2772 |
.insns_flags = PPC_INSNS_403, |
2773 |
.flags = PPC_FLAGS_403, |
2774 |
.msr_mask = 0x000000000007D23D,
|
2775 |
}, |
2776 |
#endif
|
2777 |
#if defined (TODO)
|
2778 |
/* PowerPC 403 GCX */
|
2779 |
{ |
2780 |
.name = "403gcx",
|
2781 |
.pvr = CPU_PPC_403GCX, |
2782 |
.pvr_mask = 0xFFFFFF00,
|
2783 |
.insns_flags = PPC_INSNS_403, |
2784 |
.flags = PPC_FLAGS_403, |
2785 |
.msr_mask = 0x000000000007D23D,
|
2786 |
}, |
2787 |
#endif
|
2788 |
#if defined (TODO)
|
2789 |
/* Generic PowerPC 405 */
|
2790 |
{ |
2791 |
.name = "405",
|
2792 |
.pvr = CPU_PPC_405, |
2793 |
.pvr_mask = 0xFFFF0000,
|
2794 |
.insns_flags = PPC_INSNS_405, |
2795 |
.flags = PPC_FLAGS_405, |
2796 |
.msr_mask = 0x00000000020EFF30,
|
2797 |
}, |
2798 |
#endif
|
2799 |
#if defined (TODO)
|
2800 |
/* PowerPC 405 CR */
|
2801 |
{ |
2802 |
.name = "405cr",
|
2803 |
.pvr = CPU_PPC_405, |
2804 |
.pvr_mask = 0xFFFF0000,
|
2805 |
.insns_flags = PPC_INSNS_405, |
2806 |
.flags = PPC_FLAGS_405, |
2807 |
.msr_mask = 0x00000000020EFF30,
|
2808 |
}, |
2809 |
#endif
|
2810 |
#if defined (TODO)
|
2811 |
/* PowerPC 405 GP */
|
2812 |
{ |
2813 |
.name = "405gp",
|
2814 |
.pvr = CPU_PPC_405, |
2815 |
.pvr_mask = 0xFFFF0000,
|
2816 |
.insns_flags = PPC_INSNS_405, |
2817 |
.flags = PPC_FLAGS_405, |
2818 |
.msr_mask = 0x00000000020EFF30,
|
2819 |
}, |
2820 |
#endif
|
2821 |
#if defined (TODO)
|
2822 |
/* PowerPC 405 EP */
|
2823 |
{ |
2824 |
.name = "405ep",
|
2825 |
.pvr = CPU_PPC_405EP, |
2826 |
.pvr_mask = 0xFFFF0000,
|
2827 |
.insns_flags = PPC_INSNS_405, |
2828 |
.flags = PPC_FLAGS_405, |
2829 |
.msr_mask = 0x00000000020EFF30,
|
2830 |
}, |
2831 |
#endif
|
2832 |
#if defined (TODO)
|
2833 |
/* PowerPC 405 GPR */
|
2834 |
{ |
2835 |
.name = "405gpr",
|
2836 |
.pvr = CPU_PPC_405GPR, |
2837 |
.pvr_mask = 0xFFFF0000,
|
2838 |
.insns_flags = PPC_INSNS_405, |
2839 |
.flags = PPC_FLAGS_405, |
2840 |
.msr_mask = 0x00000000020EFF30,
|
2841 |
}, |
2842 |
#endif
|
2843 |
#if defined (TODO)
|
2844 |
/* PowerPC 405 D2 */
|
2845 |
{ |
2846 |
.name = "405d2",
|
2847 |
.pvr = CPU_PPC_405D2, |
2848 |
.pvr_mask = 0xFFFF0000,
|
2849 |
.insns_flags = PPC_INSNS_405, |
2850 |
.flags = PPC_FLAGS_405, |
2851 |
.msr_mask = 0x00000000020EFF30,
|
2852 |
}, |
2853 |
#endif
|
2854 |
#if defined (TODO)
|
2855 |
/* PowerPC 405 D4 */
|
2856 |
{ |
2857 |
.name = "405d4",
|
2858 |
.pvr = CPU_PPC_405D4, |
2859 |
.pvr_mask = 0xFFFF0000,
|
2860 |
.insns_flags = PPC_INSNS_405, |
2861 |
.flags = PPC_FLAGS_405, |
2862 |
.msr_mask = 0x00000000020EFF30,
|
2863 |
}, |
2864 |
#endif
|
2865 |
#if defined (TODO)
|
2866 |
/* Npe405 H */
|
2867 |
{ |
2868 |
.name = "Npe405H",
|
2869 |
.pvr = CPU_PPC_NPE405H, |
2870 |
.pvr_mask = 0xFFFF0000,
|
2871 |
.insns_flags = PPC_INSNS_405, |
2872 |
.flags = PPC_FLAGS_405, |
2873 |
.msr_mask = 0x00000000020EFF30,
|
2874 |
}, |
2875 |
#endif
|
2876 |
#if defined (TODO)
|
2877 |
/* Npe405 L */
|
2878 |
{ |
2879 |
.name = "Npe405L",
|
2880 |
.pvr = CPU_PPC_NPE405L, |
2881 |
.pvr_mask = 0xFFFF0000,
|
2882 |
.insns_flags = PPC_INSNS_405, |
2883 |
.flags = PPC_FLAGS_405, |
2884 |
.msr_mask = 0x00000000020EFF30,
|
2885 |
}, |
2886 |
#endif
|
2887 |
#if defined (TODO)
|
2888 |
/* STB010000 */
|
2889 |
{ |
2890 |
.name = "STB01000",
|
2891 |
.pvr = CPU_PPC_STB01000, |
2892 |
.pvr_mask = 0xFFFF0000,
|
2893 |
.insns_flags = PPC_INSNS_405, |
2894 |
.flags = PPC_FLAGS_405, |
2895 |
.msr_mask = 0x00000000020EFF30,
|
2896 |
}, |
2897 |
#endif
|
2898 |
#if defined (TODO)
|
2899 |
/* STB01010 */
|
2900 |
{ |
2901 |
.name = "STB01010",
|
2902 |
.pvr = CPU_PPC_STB01010, |
2903 |
.pvr_mask = 0xFFFF0000,
|
2904 |
.insns_flags = PPC_INSNS_405, |
2905 |
.flags = PPC_FLAGS_405, |
2906 |
.msr_mask = 0x00000000020EFF30,
|
2907 |
}, |
2908 |
#endif
|
2909 |
#if defined (TODO)
|
2910 |
/* STB0210 */
|
2911 |
{ |
2912 |
.name = "STB0210",
|
2913 |
.pvr = CPU_PPC_STB0210, |
2914 |
.pvr_mask = 0xFFFF0000,
|
2915 |
.insns_flags = PPC_INSNS_405, |
2916 |
.flags = PPC_FLAGS_405, |
2917 |
.msr_mask = 0x00000000020EFF30,
|
2918 |
}, |
2919 |
#endif
|
2920 |
#if defined (TODO)
|
2921 |
/* STB03xx */
|
2922 |
{ |
2923 |
.name = "STB03",
|
2924 |
.pvr = CPU_PPC_STB03, |
2925 |
.pvr_mask = 0xFFFF0000,
|
2926 |
.insns_flags = PPC_INSNS_405, |
2927 |
.flags = PPC_FLAGS_405, |
2928 |
.msr_mask = 0x00000000020EFF30,
|
2929 |
}, |
2930 |
#endif
|
2931 |
#if defined (TODO)
|
2932 |
/* STB043x */
|
2933 |
{ |
2934 |
.name = "STB043",
|
2935 |
.pvr = CPU_PPC_STB043, |
2936 |
.pvr_mask = 0xFFFF0000,
|
2937 |
.insns_flags = PPC_INSNS_405, |
2938 |
.flags = PPC_FLAGS_405, |
2939 |
.msr_mask = 0x00000000020EFF30,
|
2940 |
}, |
2941 |
#endif
|
2942 |
#if defined (TODO)
|
2943 |
/* STB045x */
|
2944 |
{ |
2945 |
.name = "STB045",
|
2946 |
.pvr = CPU_PPC_STB045, |
2947 |
.pvr_mask = 0xFFFF0000,
|
2948 |
.insns_flags = PPC_INSNS_405, |
2949 |
.flags = PPC_FLAGS_405, |
2950 |
.msr_mask = 0x00000000020EFF30,
|
2951 |
}, |
2952 |
#endif
|
2953 |
#if defined (TODO)
|
2954 |
/* STB25xx */
|
2955 |
{ |
2956 |
.name = "STB25",
|
2957 |
.pvr = CPU_PPC_STB25, |
2958 |
.pvr_mask = 0xFFFF0000,
|
2959 |
.insns_flags = PPC_INSNS_405, |
2960 |
.flags = PPC_FLAGS_405, |
2961 |
.msr_mask = 0x00000000020EFF30,
|
2962 |
}, |
2963 |
#endif
|
2964 |
#if defined (TODO)
|
2965 |
/* STB130 */
|
2966 |
{ |
2967 |
.name = "STB130",
|
2968 |
.pvr = CPU_PPC_STB130, |
2969 |
.pvr_mask = 0xFFFF0000,
|
2970 |
.insns_flags = PPC_INSNS_405, |
2971 |
.flags = PPC_FLAGS_405, |
2972 |
.msr_mask = 0x00000000020EFF30,
|
2973 |
}, |
2974 |
#endif
|
2975 |
/* Xilinx PowerPC 405 cores */
|
2976 |
#if defined (TODO)
|
2977 |
{ |
2978 |
.name = "x2vp4",
|
2979 |
.pvr = CPU_PPC_X2VP4, |
2980 |
.pvr_mask = 0xFFFF0000,
|
2981 |
.insns_flags = PPC_INSNS_405, |
2982 |
.flags = PPC_FLAGS_405, |
2983 |
.msr_mask = 0x00000000020EFF30,
|
2984 |
}, |
2985 |
{ |
2986 |
.name = "x2vp7",
|
2987 |
.pvr = CPU_PPC_X2VP7, |
2988 |
.pvr_mask = 0xFFFF0000,
|
2989 |
.insns_flags = PPC_INSNS_405, |
2990 |
.flags = PPC_FLAGS_405, |
2991 |
.msr_mask = 0x00000000020EFF30,
|
2992 |
}, |
2993 |
{ |
2994 |
.name = "x2vp20",
|
2995 |
.pvr = CPU_PPC_X2VP20, |
2996 |
.pvr_mask = 0xFFFF0000,
|
2997 |
.insns_flags = PPC_INSNS_405, |
2998 |
.flags = PPC_FLAGS_405, |
2999 |
.msr_mask = 0x00000000020EFF30,
|
3000 |
}, |
3001 |
{ |
3002 |
.name = "x2vp50",
|
3003 |
.pvr = CPU_PPC_X2VP50, |
3004 |
.pvr_mask = 0xFFFF0000,
|
3005 |
.insns_flags = PPC_INSNS_405, |
3006 |
.flags = PPC_FLAGS_405, |
3007 |
.msr_mask = 0x00000000020EFF30,
|
3008 |
}, |
3009 |
#endif
|
3010 |
#if defined (TODO)
|
3011 |
/* PowerPC 440 EP */
|
3012 |
{ |
3013 |
.name = "440ep",
|
3014 |
.pvr = CPU_PPC_440EP, |
3015 |
.pvr_mask = 0xFFFF0000,
|
3016 |
.insns_flags = PPC_INSNS_440, |
3017 |
.flags = PPC_FLAGS_440, |
3018 |
.msr_mask = 0x000000000006D630,
|
3019 |
}, |
3020 |
#endif
|
3021 |
#if defined (TODO)
|
3022 |
/* PowerPC 440 GR */
|
3023 |
{ |
3024 |
.name = "440gr",
|
3025 |
.pvr = CPU_PPC_440GR, |
3026 |
.pvr_mask = 0xFFFF0000,
|
3027 |
.insns_flags = PPC_INSNS_440, |
3028 |
.flags = PPC_FLAGS_440, |
3029 |
.msr_mask = 0x000000000006D630,
|
3030 |
}, |
3031 |
#endif
|
3032 |
#if defined (TODO)
|
3033 |
/* PowerPC 440 GP */
|
3034 |
{ |
3035 |
.name = "440gp",
|
3036 |
.pvr = CPU_PPC_440GP, |
3037 |
.pvr_mask = 0xFFFFFF00,
|
3038 |
.insns_flags = PPC_INSNS_440, |
3039 |
.flags = PPC_FLAGS_440, |
3040 |
.msr_mask = 0x000000000006D630,
|
3041 |
}, |
3042 |
#endif
|
3043 |
#if defined (TODO)
|
3044 |
/* PowerPC 440 GX */
|
3045 |
{ |
3046 |
.name = "440gx",
|
3047 |
.pvr = CPU_PPC_440GX, |
3048 |
.pvr_mask = 0xFFFF0000,
|
3049 |
.insns_flags = PPC_INSNS_405, |
3050 |
.flags = PPC_FLAGS_440, |
3051 |
.msr_mask = 0x000000000006D630,
|
3052 |
}, |
3053 |
#endif
|
3054 |
#if defined (TODO)
|
3055 |
/* PowerPC 440 GXc */
|
3056 |
{ |
3057 |
.name = "440gxc",
|
3058 |
.pvr = CPU_PPC_440GXC, |
3059 |
.pvr_mask = 0xFFFF0000,
|
3060 |
.insns_flags = PPC_INSNS_405, |
3061 |
.flags = PPC_FLAGS_440, |
3062 |
.msr_mask = 0x000000000006D630,
|
3063 |
}, |
3064 |
#endif
|
3065 |
#if defined (TODO)
|
3066 |
/* PowerPC 440 GXf */
|
3067 |
{ |
3068 |
.name = "440gxf",
|
3069 |
.pvr = CPU_PPC_440GXF, |
3070 |
.pvr_mask = 0xFFFF0000,
|
3071 |
.insns_flags = PPC_INSNS_405, |
3072 |
.flags = PPC_FLAGS_440, |
3073 |
.msr_mask = 0x000000000006D630,
|
3074 |
}, |
3075 |
#endif
|
3076 |
#if defined (TODO)
|
3077 |
/* PowerPC 440 SP */
|
3078 |
{ |
3079 |
.name = "440sp",
|
3080 |
.pvr = CPU_PPC_440SP, |
3081 |
.pvr_mask = 0xFFFF0000,
|
3082 |
.insns_flags = PPC_INSNS_405, |
3083 |
.flags = PPC_FLAGS_440, |
3084 |
.msr_mask = 0x000000000006D630,
|
3085 |
}, |
3086 |
#endif
|
3087 |
#if defined (TODO)
|
3088 |
/* PowerPC 440 SP2 */
|
3089 |
{ |
3090 |
.name = "440sp2",
|
3091 |
.pvr = CPU_PPC_440SP2, |
3092 |
.pvr_mask = 0xFFFF0000,
|
3093 |
.insns_flags = PPC_INSNS_405, |
3094 |
.flags = PPC_FLAGS_440, |
3095 |
.msr_mask = 0x000000000006D630,
|
3096 |
}, |
3097 |
#endif
|
3098 |
#if defined (TODO)
|
3099 |
/* PowerPC 440 SPE */
|
3100 |
{ |
3101 |
.name = "440spe",
|
3102 |
.pvr = CPU_PPC_440SPE, |
3103 |
.pvr_mask = 0xFFFF0000,
|
3104 |
.insns_flags = PPC_INSNS_405, |
3105 |
.flags = PPC_FLAGS_440, |
3106 |
.msr_mask = 0x000000000006D630,
|
3107 |
}, |
3108 |
#endif
|
3109 |
/* Fake generic BookE PowerPC */
|
3110 |
{ |
3111 |
.name = "BookE",
|
3112 |
.pvr = CPU_PPC_e500, |
3113 |
.pvr_mask = 0xFFFFFFFF,
|
3114 |
.insns_flags = PPC_INSNS_BOOKE, |
3115 |
.flags = PPC_FLAGS_BOOKE, |
3116 |
.msr_mask = 0x000000000006D630,
|
3117 |
}, |
3118 |
/* PowerPC 460 cores - TODO */
|
3119 |
/* PowerPC MPC 5xx cores - TODO */
|
3120 |
/* PowerPC MPC 8xx cores - TODO */
|
3121 |
/* PowerPC MPC 8xxx cores - TODO */
|
3122 |
/* e200 cores - TODO */
|
3123 |
/* e500 cores - TODO */
|
3124 |
/* e600 cores - TODO */
|
3125 |
|
3126 |
/* 32 bits "classic" PowerPC */
|
3127 |
#if defined (TODO)
|
3128 |
/* PowerPC 601 */
|
3129 |
{ |
3130 |
.name = "601",
|
3131 |
.pvr = CPU_PPC_601, |
3132 |
.pvr_mask = 0xFFFF0000,
|
3133 |
.insns_flags = PPC_INSNS_601, |
3134 |
.flags = PPC_FLAGS_601, |
3135 |
.msr_mask = 0x000000000000FD70,
|
3136 |
}, |
3137 |
#endif
|
3138 |
#if defined (TODO)
|
3139 |
/* PowerPC 602 */
|
3140 |
{ |
3141 |
.name = "602",
|
3142 |
.pvr = CPU_PPC_602, |
3143 |
.pvr_mask = 0xFFFF0000,
|
3144 |
.insns_flags = PPC_INSNS_602, |
3145 |
.flags = PPC_FLAGS_602, |
3146 |
.msr_mask = 0x0000000000C7FF73,
|
3147 |
}, |
3148 |
#endif
|
3149 |
/* PowerPC 603 */
|
3150 |
{ |
3151 |
.name = "603",
|
3152 |
.pvr = CPU_PPC_603, |
3153 |
.pvr_mask = 0xFFFFFFFF,
|
3154 |
.insns_flags = PPC_INSNS_603, |
3155 |
.flags = PPC_FLAGS_603, |
3156 |
.msr_mask = 0x000000000007FF73,
|
3157 |
}, |
3158 |
/* PowerPC 603e */
|
3159 |
{ |
3160 |
.name = "603e",
|
3161 |
.pvr = CPU_PPC_603E, |
3162 |
.pvr_mask = 0xFFFFFFFF,
|
3163 |
.insns_flags = PPC_INSNS_603, |
3164 |
.flags = PPC_FLAGS_603, |
3165 |
.msr_mask = 0x000000000007FF73,
|
3166 |
}, |
3167 |
{ |
3168 |
.name = "Stretch",
|
3169 |
.pvr = CPU_PPC_603E, |
3170 |
.pvr_mask = 0xFFFFFFFF,
|
3171 |
.insns_flags = PPC_INSNS_603, |
3172 |
.flags = PPC_FLAGS_603, |
3173 |
.msr_mask = 0x000000000007FF73,
|
3174 |
}, |
3175 |
/* PowerPC 603p */
|
3176 |
{ |
3177 |
.name = "603p",
|
3178 |
.pvr = CPU_PPC_603P, |
3179 |
.pvr_mask = 0xFFFFFFFF,
|
3180 |
.insns_flags = PPC_INSNS_603, |
3181 |
.flags = PPC_FLAGS_603, |
3182 |
.msr_mask = 0x000000000007FF73,
|
3183 |
}, |
3184 |
/* PowerPC 603e7 */
|
3185 |
{ |
3186 |
.name = "603e7",
|
3187 |
.pvr = CPU_PPC_603E7, |
3188 |
.pvr_mask = 0xFFFFFFFF,
|
3189 |
.insns_flags = PPC_INSNS_603, |
3190 |
.flags = PPC_FLAGS_603, |
3191 |
.msr_mask = 0x000000000007FF73,
|
3192 |
}, |
3193 |
/* PowerPC 603e7v */
|
3194 |
{ |
3195 |
.name = "603e7v",
|
3196 |
.pvr = CPU_PPC_603E7v, |
3197 |
.pvr_mask = 0xFFFFFFFF,
|
3198 |
.insns_flags = PPC_INSNS_603, |
3199 |
.flags = PPC_FLAGS_603, |
3200 |
.msr_mask = 0x000000000007FF73,
|
3201 |
}, |
3202 |
/* PowerPC 603e7v2 */
|
3203 |
{ |
3204 |
.name = "603e7v2",
|
3205 |
.pvr = CPU_PPC_603E7v2, |
3206 |
.pvr_mask = 0xFFFFFFFF,
|
3207 |
.insns_flags = PPC_INSNS_603, |
3208 |
.flags = PPC_FLAGS_603, |
3209 |
.msr_mask = 0x000000000007FF73,
|
3210 |
}, |
3211 |
/* PowerPC 603r */
|
3212 |
{ |
3213 |
.name = "603r",
|
3214 |
.pvr = CPU_PPC_603R, |
3215 |
.pvr_mask = 0xFFFFFFFF,
|
3216 |
.insns_flags = PPC_INSNS_603, |
3217 |
.flags = PPC_FLAGS_603, |
3218 |
.msr_mask = 0x000000000007FF73,
|
3219 |
}, |
3220 |
{ |
3221 |
.name = "Goldeneye",
|
3222 |
.pvr = CPU_PPC_603R, |
3223 |
.pvr_mask = 0xFFFFFFFF,
|
3224 |
.insns_flags = PPC_INSNS_603, |
3225 |
.flags = PPC_FLAGS_603, |
3226 |
.msr_mask = 0x000000000007FF73,
|
3227 |
}, |
3228 |
#if defined (TODO)
|
3229 |
/* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
|
3230 |
{ |
3231 |
.name = "G2",
|
3232 |
.pvr = CPU_PPC_G2, |
3233 |
.pvr_mask = 0xFFFF0000,
|
3234 |
.insns_flags = PPC_INSNS_G2, |
3235 |
.flags = PPC_FLAGS_G2, |
3236 |
.msr_mask = 0x000000000006FFF2,
|
3237 |
}, |
3238 |
{ |
3239 |
.name = "G2h4",
|
3240 |
.pvr = CPU_PPC_G2H4, |
3241 |
.pvr_mask = 0xFFFF0000,
|
3242 |
.insns_flags = PPC_INSNS_G2, |
3243 |
.flags = PPC_FLAGS_G2, |
3244 |
.msr_mask = 0x000000000006FFF2,
|
3245 |
}, |
3246 |
{ |
3247 |
.name = "G2gp",
|
3248 |
.pvr = CPU_PPC_G2gp, |
3249 |
.pvr_mask = 0xFFFF0000,
|
3250 |
.insns_flags = PPC_INSNS_G2, |
3251 |
.flags = PPC_FLAGS_G2, |
3252 |
.msr_mask = 0x000000000006FFF2,
|
3253 |
}, |
3254 |
{ |
3255 |
.name = "G2ls",
|
3256 |
.pvr = CPU_PPC_G2ls, |
3257 |
.pvr_mask = 0xFFFF0000,
|
3258 |
.insns_flags = PPC_INSNS_G2, |
3259 |
.flags = PPC_FLAGS_G2, |
3260 |
.msr_mask = 0x000000000006FFF2,
|
3261 |
}, |
3262 |
{ /* Same as G2, with LE mode support */
|
3263 |
.name = "G2le",
|
3264 |
.pvr = CPU_PPC_G2LE, |
3265 |
.pvr_mask = 0xFFFF0000,
|
3266 |
.insns_flags = PPC_INSNS_G2, |
3267 |
.flags = PPC_FLAGS_G2, |
3268 |
.msr_mask = 0x000000000007FFF3,
|
3269 |
}, |
3270 |
{ |
3271 |
.name = "G2legp",
|
3272 |
.pvr = CPU_PPC_G2LEgp, |
3273 |
.pvr_mask = 0xFFFF0000,
|
3274 |
.insns_flags = PPC_INSNS_G2, |
3275 |
.flags = PPC_FLAGS_G2, |
3276 |
.msr_mask = 0x000000000007FFF3,
|
3277 |
}, |
3278 |
{ |
3279 |
.name = "G2lels",
|
3280 |
.pvr = CPU_PPC_G2LEls, |
3281 |
.pvr_mask = 0xFFFF0000,
|
3282 |
.insns_flags = PPC_INSNS_G2, |
3283 |
.flags = PPC_FLAGS_G2, |
3284 |
.msr_mask = 0x000000000007FFF3,
|
3285 |
}, |
3286 |
#endif
|
3287 |
/* PowerPC 604 */
|
3288 |
{ |
3289 |
.name = "604",
|
3290 |
.pvr = CPU_PPC_604, |
3291 |
.pvr_mask = 0xFFFFFFFF,
|
3292 |
.insns_flags = PPC_INSNS_604, |
3293 |
.flags = PPC_FLAGS_604, |
3294 |
.msr_mask = 0x000000000005FF77,
|
3295 |
}, |
3296 |
/* PowerPC 604e */
|
3297 |
{ |
3298 |
.name = "604e",
|
3299 |
.pvr = CPU_PPC_604E, |
3300 |
.pvr_mask = 0xFFFFFFFF,
|
3301 |
.insns_flags = PPC_INSNS_604, |
3302 |
.flags = PPC_FLAGS_604, |
3303 |
.msr_mask = 0x000000000005FF77,
|
3304 |
}, |
3305 |
/* PowerPC 604r */
|
3306 |
{ |
3307 |
.name = "604r",
|
3308 |
.pvr = CPU_PPC_604R, |
3309 |
.pvr_mask = 0xFFFFFFFF,
|
3310 |
.insns_flags = PPC_INSNS_604, |
3311 |
.flags = PPC_FLAGS_604, |
3312 |
.msr_mask = 0x000000000005FF77,
|
3313 |
}, |
3314 |
/* generic G3 */
|
3315 |
{ |
3316 |
.name = "G3",
|
3317 |
.pvr = CPU_PPC_74x, |
3318 |
.pvr_mask = 0xFFFFFFFF,
|
3319 |
.insns_flags = PPC_INSNS_7x0, |
3320 |
.flags = PPC_FLAGS_7x0, |
3321 |
.msr_mask = 0x000000000007FF77,
|
3322 |
}, |
3323 |
/* MPC740 (G3) */
|
3324 |
{ |
3325 |
.name = "740",
|
3326 |
.pvr = CPU_PPC_74x, |
3327 |
.pvr_mask = 0xFFFFFFFF,
|
3328 |
.insns_flags = PPC_INSNS_7x0, |
3329 |
.flags = PPC_FLAGS_7x0, |
3330 |
.msr_mask = 0x000000000007FF77,
|
3331 |
}, |
3332 |
{ |
3333 |
.name = "Arthur",
|
3334 |
.pvr = CPU_PPC_74x, |
3335 |
.pvr_mask = 0xFFFFFFFF,
|
3336 |
.insns_flags = PPC_INSNS_7x0, |
3337 |
.flags = PPC_FLAGS_7x0, |
3338 |
.msr_mask = 0x000000000007FF77,
|
3339 |
}, |
3340 |
#if defined (TODO)
|
3341 |
/* MPC745 (G3) */
|
3342 |
{ |
3343 |
.name = "745",
|
3344 |
.pvr = CPU_PPC_74x, |
3345 |
.pvr_mask = 0xFFFFF000,
|
3346 |
.insns_flags = PPC_INSNS_7x5, |
3347 |
.flags = PPC_FLAGS_7x5, |
3348 |
.msr_mask = 0x000000000007FF77,
|
3349 |
}, |
3350 |
{ |
3351 |
.name = "Goldfinger",
|
3352 |
.pvr = CPU_PPC_74x, |
3353 |
.pvr_mask = 0xFFFFF000,
|
3354 |
.insns_flags = PPC_INSNS_7x5, |
3355 |
.flags = PPC_FLAGS_7x5, |
3356 |
.msr_mask = 0x000000000007FF77,
|
3357 |
}, |
3358 |
#endif
|
3359 |
/* MPC750 (G3) */
|
3360 |
{ |
3361 |
.name = "750",
|
3362 |
.pvr = CPU_PPC_74x, |
3363 |
.pvr_mask = 0xFFFFFFFF,
|
3364 |
.insns_flags = PPC_INSNS_7x0, |
3365 |
.flags = PPC_FLAGS_7x0, |
3366 |
.msr_mask = 0x000000000007FF77,
|
3367 |
}, |
3368 |
#if defined (TODO)
|
3369 |
/* MPC755 (G3) */
|
3370 |
{ |
3371 |
.name = "755",
|
3372 |
.pvr = CPU_PPC_755, |
3373 |
.pvr_mask = 0xFFFFF000,
|
3374 |
.insns_flags = PPC_INSNS_7x5, |
3375 |
.flags = PPC_FLAGS_7x5, |
3376 |
.msr_mask = 0x000000000007FF77,
|
3377 |
}, |
3378 |
#endif
|
3379 |
/* MPC740P (G3) */
|
3380 |
{ |
3381 |
.name = "740p",
|
3382 |
.pvr = CPU_PPC_74xP, |
3383 |
.pvr_mask = 0xFFFFFFFF,
|
3384 |
.insns_flags = PPC_INSNS_7x0, |
3385 |
.flags = PPC_FLAGS_7x0, |
3386 |
.msr_mask = 0x000000000007FF77,
|
3387 |
}, |
3388 |
{ |
3389 |
.name = "Conan/Doyle",
|
3390 |
.pvr = CPU_PPC_74xP, |
3391 |
.pvr_mask = 0xFFFFFFFF,
|
3392 |
.insns_flags = PPC_INSNS_7x0, |
3393 |
.flags = PPC_FLAGS_7x0, |
3394 |
.msr_mask = 0x000000000007FF77,
|
3395 |
}, |
3396 |
#if defined (TODO)
|
3397 |
/* MPC745P (G3) */
|
3398 |
{ |
3399 |
.name = "745p",
|
3400 |
.pvr = CPU_PPC_74xP, |
3401 |
.pvr_mask = 0xFFFFF000,
|
3402 |
.insns_flags = PPC_INSNS_7x5, |
3403 |
.flags = PPC_FLAGS_7x5, |
3404 |
.msr_mask = 0x000000000007FF77,
|
3405 |
}, |
3406 |
#endif
|
3407 |
/* MPC750P (G3) */
|
3408 |
{ |
3409 |
.name = "750p",
|
3410 |
.pvr = CPU_PPC_74xP, |
3411 |
.pvr_mask = 0xFFFFFFFF,
|
3412 |
.insns_flags = PPC_INSNS_7x0, |
3413 |
.flags = PPC_FLAGS_7x0, |
3414 |
.msr_mask = 0x000000000007FF77,
|
3415 |
}, |
3416 |
#if defined (TODO)
|
3417 |
/* MPC755P (G3) */
|
3418 |
{ |
3419 |
.name = "755p",
|
3420 |
.pvr = CPU_PPC_74xP, |
3421 |
.pvr_mask = 0xFFFFF000,
|
3422 |
.insns_flags = PPC_INSNS_7x5, |
3423 |
.flags = PPC_FLAGS_7x5, |
3424 |
.msr_mask = 0x000000000007FF77,
|
3425 |
}, |
3426 |
#endif
|
3427 |
/* IBM 750CXe (G3 embedded) */
|
3428 |
{ |
3429 |
.name = "750cxe",
|
3430 |
.pvr = CPU_PPC_750CXE, |
3431 |
.pvr_mask = 0xFFFFFFFF,
|
3432 |
.insns_flags = PPC_INSNS_7x0, |
3433 |
.flags = PPC_FLAGS_7x0, |
3434 |
.msr_mask = 0x000000000007FF77,
|
3435 |
}, |
3436 |
/* IBM 750FX (G3 embedded) */
|
3437 |
{ |
3438 |
.name = "750fx",
|
3439 |
.pvr = CPU_PPC_750FX, |
3440 |
.pvr_mask = 0xFFFFFFFF,
|
3441 |
.insns_flags = PPC_INSNS_7x0, |
3442 |
.flags = PPC_FLAGS_7x0, |
3443 |
.msr_mask = 0x000000000007FF77,
|
3444 |
}, |
3445 |
/* IBM 750GX (G3 embedded) */
|
3446 |
{ |
3447 |
.name = "750gx",
|
3448 |
.pvr = CPU_PPC_750GX, |
3449 |
.pvr_mask = 0xFFFFFFFF,
|
3450 |
.insns_flags = PPC_INSNS_7x0, |
3451 |
.flags = PPC_FLAGS_7x0, |
3452 |
.msr_mask = 0x000000000007FF77,
|
3453 |
}, |
3454 |
#if defined (TODO)
|
3455 |
/* generic G4 */
|
3456 |
{ |
3457 |
.name = "G4",
|
3458 |
.pvr = CPU_PPC_7400, |
3459 |
.pvr_mask = 0xFFFF0000,
|
3460 |
.insns_flags = PPC_INSNS_74xx, |
3461 |
.flags = PPC_FLAGS_74xx, |
3462 |
.msr_mask = 0x000000000205FF77,
|
3463 |
}, |
3464 |
#endif
|
3465 |
#if defined (TODO)
|
3466 |
/* PowerPC 7400 (G4) */
|
3467 |
{ |
3468 |
.name = "7400",
|
3469 |
.pvr = CPU_PPC_7400, |
3470 |
.pvr_mask = 0xFFFF0000,
|
3471 |
.insns_flags = PPC_INSNS_74xx, |
3472 |
.flags = PPC_FLAGS_74xx, |
3473 |
.msr_mask = 0x000000000205FF77,
|
3474 |
}, |
3475 |
{ |
3476 |
.name = "Max",
|
3477 |
.pvr = CPU_PPC_7400, |
3478 |
.pvr_mask = 0xFFFF0000,
|
3479 |
.insns_flags = PPC_INSNS_74xx, |
3480 |
.flags = PPC_FLAGS_74xx, |
3481 |
.msr_mask = 0x000000000205FF77,
|
3482 |
}, |
3483 |
#endif
|
3484 |
#if defined (TODO)
|
3485 |
/* PowerPC 7410 (G4) */
|
3486 |
{ |
3487 |
.name = "7410",
|
3488 |
.pvr = CPU_PPC_7410, |
3489 |
.pvr_mask = 0xFFFF0000,
|
3490 |
.insns_flags = PPC_INSNS_74xx, |
3491 |
.flags = PPC_FLAGS_74xx, |
3492 |
.msr_mask = 0x000000000205FF77,
|
3493 |
}, |
3494 |
{ |
3495 |
.name = "Nitro",
|
3496 |
.pvr = CPU_PPC_7410, |
3497 |
.pvr_mask = 0xFFFF0000,
|
3498 |
.insns_flags = PPC_INSNS_74xx, |
3499 |
.flags = PPC_FLAGS_74xx, |
3500 |
.msr_mask = 0x000000000205FF77,
|
3501 |
}, |
3502 |
#endif
|
3503 |
/* XXX: 7441 */
|
3504 |
/* XXX: 7445 */
|
3505 |
/* XXX: 7447 */
|
3506 |
/* XXX: 7447A */
|
3507 |
#if defined (TODO)
|
3508 |
/* PowerPC 7450 (G4) */
|
3509 |
{ |
3510 |
.name = "7450",
|
3511 |
.pvr = CPU_PPC_7450, |
3512 |
.pvr_mask = 0xFFFF0000,
|
3513 |
.insns_flags = PPC_INSNS_74xx, |
3514 |
.flags = PPC_FLAGS_74xx, |
3515 |
.msr_mask = 0x000000000205FF77,
|
3516 |
}, |
3517 |
{ |
3518 |
.name = "Vger",
|
3519 |
.pvr = CPU_PPC_7450, |
3520 |
.pvr_mask = 0xFFFF0000,
|
3521 |
.insns_flags = PPC_INSNS_74xx, |
3522 |
.flags = PPC_FLAGS_74xx, |
3523 |
.msr_mask = 0x000000000205FF77,
|
3524 |
}, |
3525 |
#endif
|
3526 |
/* XXX: 7451 */
|
3527 |
#if defined (TODO)
|
3528 |
/* PowerPC 7455 (G4) */
|
3529 |
{ |
3530 |
.name = "7455",
|
3531 |
.pvr = CPU_PPC_7455, |
3532 |
.pvr_mask = 0xFFFF0000,
|
3533 |
.insns_flags = PPC_INSNS_74xx, |
3534 |
.flags = PPC_FLAGS_74xx, |
3535 |
.msr_mask = 0x000000000205FF77,
|
3536 |
}, |
3537 |
{ |
3538 |
.name = "Apollo 6",
|
3539 |
.pvr = CPU_PPC_7455, |
3540 |
.pvr_mask = 0xFFFF0000,
|
3541 |
.insns_flags = PPC_INSNS_74xx, |
3542 |
.flags = PPC_FLAGS_74xx, |
3543 |
.msr_mask = 0x000000000205FF77,
|
3544 |
}, |
3545 |
#endif
|
3546 |
#if defined (TODO)
|
3547 |
/* PowerPC 7457 (G4) */
|
3548 |
{ |
3549 |
.name = "7457",
|
3550 |
.pvr = CPU_PPC_7457, |
3551 |
.pvr_mask = 0xFFFF0000,
|
3552 |
.insns_flags = PPC_INSNS_74xx, |
3553 |
.flags = PPC_FLAGS_74xx, |
3554 |
.msr_mask = 0x000000000205FF77,
|
3555 |
}, |
3556 |
{ |
3557 |
.name = "Apollo 7",
|
3558 |
.pvr = CPU_PPC_7457, |
3559 |
.pvr_mask = 0xFFFF0000,
|
3560 |
.insns_flags = PPC_INSNS_74xx, |
3561 |
.flags = PPC_FLAGS_74xx, |
3562 |
.msr_mask = 0x000000000205FF77,
|
3563 |
}, |
3564 |
#endif
|
3565 |
#if defined (TODO)
|
3566 |
/* PowerPC 7457A (G4) */
|
3567 |
{ |
3568 |
.name = "7457A",
|
3569 |
.pvr = CPU_PPC_7457A, |
3570 |
.pvr_mask = 0xFFFF0000,
|
3571 |
.insns_flags = PPC_INSNS_74xx, |
3572 |
.flags = PPC_FLAGS_74xx, |
3573 |
.msr_mask = 0x000000000205FF77,
|
3574 |
}, |
3575 |
{ |
3576 |
.name = "Apollo 7 PM",
|
3577 |
.pvr = CPU_PPC_7457A, |
3578 |
.pvr_mask = 0xFFFF0000,
|
3579 |
.insns_flags = PPC_INSNS_74xx, |
3580 |
.flags = PPC_FLAGS_74xx, |
3581 |
.msr_mask = 0x000000000205FF77,
|
3582 |
}, |
3583 |
#endif
|
3584 |
/* 64 bits PowerPC */
|
3585 |
#if defined (TARGET_PPC64)
|
3586 |
#if defined (TODO)
|
3587 |
/* PowerPC 620 */
|
3588 |
{ |
3589 |
.name = "620",
|
3590 |
.pvr = CPU_PPC_620, |
3591 |
.pvr_mask = 0xFFFF0000,
|
3592 |
.insns_flags = PPC_INSNS_620, |
3593 |
.flags = PPC_FLAGS_620, |
3594 |
.msr_mask = 0x800000000005FF73,
|
3595 |
}, |
3596 |
#endif
|
3597 |
#if defined (TODO)
|
3598 |
/* PowerPC 630 (POWER3) */
|
3599 |
{ |
3600 |
.name = "630",
|
3601 |
.pvr = CPU_PPC_630, |
3602 |
.pvr_mask = 0xFFFF0000,
|
3603 |
.insns_flags = PPC_INSNS_630, |
3604 |
.flags = PPC_FLAGS_630, |
3605 |
.msr_mask = xxx, |
3606 |
} |
3607 |
{ |
3608 |
.name = "POWER3",
|
3609 |
.pvr = CPU_PPC_630, |
3610 |
.pvr_mask = 0xFFFF0000,
|
3611 |
.insns_flags = PPC_INSNS_630, |
3612 |
.flags = PPC_FLAGS_630, |
3613 |
.msr_mask = xxx, |
3614 |
} |
3615 |
#endif
|
3616 |
#if defined (TODO)
|
3617 |
/* PowerPC 631 (Power 3+)*/
|
3618 |
{ |
3619 |
.name = "631",
|
3620 |
.pvr = CPU_PPC_631, |
3621 |
.pvr_mask = 0xFFFF0000,
|
3622 |
.insns_flags = PPC_INSNS_631, |
3623 |
.flags = PPC_FLAGS_631, |
3624 |
.msr_mask = xxx, |
3625 |
}, |
3626 |
{ |
3627 |
.name = "POWER3+",
|
3628 |
.pvr = CPU_PPC_631, |
3629 |
.pvr_mask = 0xFFFF0000,
|
3630 |
.insns_flags = PPC_INSNS_631, |
3631 |
.flags = PPC_FLAGS_631, |
3632 |
.msr_mask = xxx, |
3633 |
}, |
3634 |
#endif
|
3635 |
#if defined (TODO)
|
3636 |
/* POWER4 */
|
3637 |
{ |
3638 |
.name = "POWER4",
|
3639 |
.pvr = CPU_PPC_POWER4, |
3640 |
.pvr_mask = 0xFFFF0000,
|
3641 |
.insns_flags = PPC_INSNS_POWER4, |
3642 |
.flags = PPC_FLAGS_POWER4, |
3643 |
.msr_mask = xxx, |
3644 |
}, |
3645 |
#endif
|
3646 |
#if defined (TODO)
|
3647 |
/* POWER4p */
|
3648 |
{ |
3649 |
.name = "POWER4+",
|
3650 |
.pvr = CPU_PPC_POWER4P, |
3651 |
.pvr_mask = 0xFFFF0000,
|
3652 |
.insns_flags = PPC_INSNS_POWER4, |
3653 |
.flags = PPC_FLAGS_POWER4, |
3654 |
.msr_mask = xxx, |
3655 |
}, |
3656 |
#endif
|
3657 |
#if defined (TODO)
|
3658 |
/* POWER5 */
|
3659 |
{ |
3660 |
.name = "POWER5",
|
3661 |
.pvr = CPU_PPC_POWER5, |
3662 |
.pvr_mask = 0xFFFF0000,
|
3663 |
.insns_flags = PPC_INSNS_POWER5, |
3664 |
.flags = PPC_FLAGS_POWER5, |
3665 |
.msr_mask = xxx, |
3666 |
}, |
3667 |
#endif
|
3668 |
#if defined (TODO)
|
3669 |
/* POWER5+ */
|
3670 |
{ |
3671 |
.name = "POWER5+",
|
3672 |
.pvr = CPU_PPC_POWER5P, |
3673 |
.pvr_mask = 0xFFFF0000,
|
3674 |
.insns_flags = PPC_INSNS_POWER5, |
3675 |
.flags = PPC_FLAGS_POWER5, |
3676 |
.msr_mask = xxx, |
3677 |
}, |
3678 |
#endif
|
3679 |
#if defined (TODO)
|
3680 |
/* PowerPC 970 */
|
3681 |
{ |
3682 |
.name = "970",
|
3683 |
.pvr = CPU_PPC_970, |
3684 |
.pvr_mask = 0xFFFF0000,
|
3685 |
.insns_flags = PPC_INSNS_970, |
3686 |
.flags = PPC_FLAGS_970, |
3687 |
.msr_mask = 0x900000000204FF36,
|
3688 |
}, |
3689 |
#endif
|
3690 |
#if defined (TODO)
|
3691 |
/* PowerPC 970FX (G5) */
|
3692 |
{ |
3693 |
.name = "970fx",
|
3694 |
.pvr = CPU_PPC_970FX, |
3695 |
.pvr_mask = 0xFFFF0000,
|
3696 |
.insns_flags = PPC_INSNS_970FX, |
3697 |
.flags = PPC_FLAGS_970FX, |
3698 |
.msr_mask = 0x800000000204FF36,
|
3699 |
}, |
3700 |
#endif
|
3701 |
#if defined (TODO)
|
3702 |
/* RS64 (Apache/A35) */
|
3703 |
/* This one seems to support the whole POWER2 instruction set
|
3704 |
* and the PowerPC 64 one.
|
3705 |
*/
|
3706 |
{ |
3707 |
.name = "RS64",
|
3708 |
.pvr = CPU_PPC_RS64, |
3709 |
.pvr_mask = 0xFFFF0000,
|
3710 |
.insns_flags = PPC_INSNS_RS64, |
3711 |
.flags = PPC_FLAGS_RS64, |
3712 |
.msr_mask = xxx, |
3713 |
}, |
3714 |
{ |
3715 |
.name = "Apache",
|
3716 |
.pvr = CPU_PPC_RS64, |
3717 |
.pvr_mask = 0xFFFF0000,
|
3718 |
.insns_flags = PPC_INSNS_RS64, |
3719 |
.flags = PPC_FLAGS_RS64, |
3720 |
.msr_mask = xxx, |
3721 |
}, |
3722 |
{ |
3723 |
.name = "A35",
|
3724 |
.pvr = CPU_PPC_RS64, |
3725 |
.pvr_mask = 0xFFFF0000,
|
3726 |
.insns_flags = PPC_INSNS_RS64, |
3727 |
.flags = PPC_FLAGS_RS64, |
3728 |
.msr_mask = xxx, |
3729 |
}, |
3730 |
#endif
|
3731 |
#if defined (TODO)
|
3732 |
/* RS64-II (NorthStar/A50) */
|
3733 |
{ |
3734 |
.name = "RS64-II",
|
3735 |
.pvr = CPU_PPC_RS64II, |
3736 |
.pvr_mask = 0xFFFF0000,
|
3737 |
.insns_flags = PPC_INSNS_RS64, |
3738 |
.flags = PPC_FLAGS_RS64, |
3739 |
.msr_mask = xxx, |
3740 |
}, |
3741 |
{ |
3742 |
.name = "NortStar",
|
3743 |
.pvr = CPU_PPC_RS64II, |
3744 |
.pvr_mask = 0xFFFF0000,
|
3745 |
.insns_flags = PPC_INSNS_RS64, |
3746 |
.flags = PPC_FLAGS_RS64, |
3747 |
.msr_mask = xxx, |
3748 |
}, |
3749 |
{ |
3750 |
.name = "A50",
|
3751 |
.pvr = CPU_PPC_RS64II, |
3752 |
.pvr_mask = 0xFFFF0000,
|
3753 |
.insns_flags = PPC_INSNS_RS64, |
3754 |
.flags = PPC_FLAGS_RS64, |
3755 |
.msr_mask = xxx, |
3756 |
}, |
3757 |
#endif
|
3758 |
#if defined (TODO)
|
3759 |
/* RS64-III (Pulsar) */
|
3760 |
{ |
3761 |
.name = "RS64-III",
|
3762 |
.pvr = CPU_PPC_RS64III, |
3763 |
.pvr_mask = 0xFFFF0000,
|
3764 |
.insns_flags = PPC_INSNS_RS64, |
3765 |
.flags = PPC_FLAGS_RS64, |
3766 |
.msr_mask = xxx, |
3767 |
}, |
3768 |
{ |
3769 |
.name = "Pulsar",
|
3770 |
.pvr = CPU_PPC_RS64III, |
3771 |
.pvr_mask = 0xFFFF0000,
|
3772 |
.insns_flags = PPC_INSNS_RS64, |
3773 |
.flags = PPC_FLAGS_RS64, |
3774 |
.msr_mask = xxx, |
3775 |
}, |
3776 |
#endif
|
3777 |
#if defined (TODO)
|
3778 |
/* RS64-IV (IceStar/IStar/SStar) */
|
3779 |
{ |
3780 |
.name = "RS64-IV",
|
3781 |
.pvr = CPU_PPC_RS64IV, |
3782 |
.pvr_mask = 0xFFFF0000,
|
3783 |
.insns_flags = PPC_INSNS_RS64, |
3784 |
.flags = PPC_FLAGS_RS64, |
3785 |
.msr_mask = xxx, |
3786 |
}, |
3787 |
{ |
3788 |
.name = "IceStar",
|
3789 |
.pvr = CPU_PPC_RS64IV, |
3790 |
.pvr_mask = 0xFFFF0000,
|
3791 |
.insns_flags = PPC_INSNS_RS64, |
3792 |
.flags = PPC_FLAGS_RS64, |
3793 |
.msr_mask = xxx, |
3794 |
}, |
3795 |
{ |
3796 |
.name = "IStar",
|
3797 |
.pvr = CPU_PPC_RS64IV, |
3798 |
.pvr_mask = 0xFFFF0000,
|
3799 |
.insns_flags = PPC_INSNS_RS64, |
3800 |
.flags = PPC_FLAGS_RS64, |
3801 |
.msr_mask = xxx, |
3802 |
}, |
3803 |
{ |
3804 |
.name = "SStar",
|
3805 |
.pvr = CPU_PPC_RS64IV, |
3806 |
.pvr_mask = 0xFFFF0000,
|
3807 |
.insns_flags = PPC_INSNS_RS64, |
3808 |
.flags = PPC_FLAGS_RS64, |
3809 |
.msr_mask = xxx, |
3810 |
}, |
3811 |
#endif
|
3812 |
/* POWER */
|
3813 |
#if defined (TODO)
|
3814 |
/* Original POWER */
|
3815 |
{ |
3816 |
.name = "POWER",
|
3817 |
.pvr = CPU_POWER, |
3818 |
.pvr_mask = 0xFFFF0000,
|
3819 |
.insns_flags = PPC_INSNS_POWER, |
3820 |
.flags = PPC_FLAGS_POWER, |
3821 |
.msr_mask = xxx, |
3822 |
}, |
3823 |
#endif
|
3824 |
#endif /* defined (TARGET_PPC64) */ |
3825 |
#if defined (TODO)
|
3826 |
/* POWER2 */
|
3827 |
{ |
3828 |
.name = "POWER2",
|
3829 |
.pvr = CPU_POWER2, |
3830 |
.pvr_mask = 0xFFFF0000,
|
3831 |
.insns_flags = PPC_INSNS_POWER, |
3832 |
.flags = PPC_FLAGS_POWER, |
3833 |
.msr_mask = xxx, |
3834 |
}, |
3835 |
#endif
|
3836 |
/* Generic PowerPCs */
|
3837 |
#if defined (TODO)
|
3838 |
{ |
3839 |
.name = "ppc64",
|
3840 |
.pvr = CPU_PPC_970, |
3841 |
.pvr_mask = 0xFFFF0000,
|
3842 |
.insns_flags = PPC_INSNS_PPC64, |
3843 |
.flags = PPC_FLAGS_PPC64, |
3844 |
.msr_mask = 0xA00000000204FF36,
|
3845 |
}, |
3846 |
#endif
|
3847 |
{ |
3848 |
.name = "ppc32",
|
3849 |
.pvr = CPU_PPC_604, |
3850 |
.pvr_mask = 0xFFFFFFFF,
|
3851 |
.insns_flags = PPC_INSNS_PPC32, |
3852 |
.flags = PPC_FLAGS_PPC32, |
3853 |
.msr_mask = 0x000000000005FF77,
|
3854 |
}, |
3855 |
/* Fallback */
|
3856 |
{ |
3857 |
.name = "ppc",
|
3858 |
.pvr = CPU_PPC_604, |
3859 |
.pvr_mask = 0xFFFFFFFF,
|
3860 |
.insns_flags = PPC_INSNS_PPC32, |
3861 |
.flags = PPC_FLAGS_PPC32, |
3862 |
.msr_mask = 0x000000000005FF77,
|
3863 |
}, |
3864 |
}; |
3865 |
|
3866 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def) |
3867 |
{ |
3868 |
int i, ret;
|
3869 |
|
3870 |
ret = -1;
|
3871 |
*def = NULL;
|
3872 |
for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) { |
3873 |
if (strcasecmp(name, ppc_defs[i].name) == 0) { |
3874 |
*def = &ppc_defs[i]; |
3875 |
ret = 0;
|
3876 |
break;
|
3877 |
} |
3878 |
} |
3879 |
|
3880 |
return ret;
|
3881 |
} |
3882 |
|
3883 |
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
|
3884 |
{ |
3885 |
int i, ret;
|
3886 |
|
3887 |
ret = -1;
|
3888 |
*def = NULL;
|
3889 |
for (i = 0; ppc_defs[i].name != NULL; i++) { |
3890 |
if ((pvr & ppc_defs[i].pvr_mask) ==
|
3891 |
(ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) { |
3892 |
*def = &ppc_defs[i]; |
3893 |
ret = 0;
|
3894 |
break;
|
3895 |
} |
3896 |
} |
3897 |
|
3898 |
return ret;
|
3899 |
} |
3900 |
|
3901 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
3902 |
{ |
3903 |
int i;
|
3904 |
|
3905 |
for (i = 0; ; i++) { |
3906 |
(*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
|
3907 |
ppc_defs[i].name, |
3908 |
ppc_defs[i].pvr, ppc_defs[i].pvr_mask); |
3909 |
if (strcmp(ppc_defs[i].name, "ppc") == 0) |
3910 |
break;
|
3911 |
} |
3912 |
} |