Revision ea2b542a target-sh4/helper.c
| b/target-sh4/helper.c | ||
|---|---|---|
| 193 | 193 |
|
| 194 | 194 |
switch (itlbnb) {
|
| 195 | 195 |
case 0: |
| 196 |
and_mask = 0x7f;
|
|
| 196 |
and_mask = 0x1f;
|
|
| 197 | 197 |
break; |
| 198 | 198 |
case 1: |
| 199 | 199 |
and_mask = 0xe7; |
| ... | ... | |
| 208 | 208 |
break; |
| 209 | 209 |
} |
| 210 | 210 |
|
| 211 |
env->mmucr &= (and_mask << 24); |
|
| 211 |
env->mmucr &= (and_mask << 24) | 0x00ffffff;
|
|
| 212 | 212 |
env->mmucr |= (or_mask << 24); |
| 213 | 213 |
} |
| 214 | 214 |
|
| ... | ... | |
| 216 | 216 |
{
|
| 217 | 217 |
if ((env->mmucr & 0xe0000000) == 0xe0000000) |
| 218 | 218 |
return 0; |
| 219 |
if ((env->mmucr & 0x98000000) == 0x08000000)
|
|
| 219 |
if ((env->mmucr & 0x98000000) == 0x18000000)
|
|
| 220 | 220 |
return 1; |
| 221 | 221 |
if ((env->mmucr & 0x54000000) == 0x04000000) |
| 222 | 222 |
return 2; |
| ... | ... | |
| 264 | 264 |
start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
| 265 | 265 |
end = start + entries[i].size - 1; |
| 266 | 266 |
if (address >= start && address <= end) { /* Match */
|
| 267 |
if (match != -1)
|
|
| 267 |
if (match != MMU_DTLB_MISS)
|
|
| 268 | 268 |
return MMU_DTLB_MULTIPLE; /* Multiple match */ |
| 269 | 269 |
match = i; |
| 270 | 270 |
} |
| ... | ... | |
| 290 | 290 |
n = itlb_replacement(env); |
| 291 | 291 |
env->itlb[n] = env->utlb[e]; |
| 292 | 292 |
e = n; |
| 293 |
} |
|
| 294 |
} |
|
| 293 |
} else if (e == MMU_DTLB_MISS) |
|
| 294 |
e = MMU_ITLB_MISS; |
|
| 295 |
} else if (e == MMU_DTLB_MISS) |
|
| 296 |
e = MMU_ITLB_MISS; |
|
| 295 | 297 |
if (e >= 0) |
| 296 | 298 |
update_itlb_use(env, e); |
| 297 | 299 |
return e; |
| ... | ... | |
| 418 | 420 |
target_ulong physical, page_offset, page_size; |
| 419 | 421 |
int prot, ret, access_type; |
| 420 | 422 |
|
| 423 |
switch (rw) {
|
|
| 424 |
case 0: |
|
| 425 |
rw = PAGE_READ; |
|
| 426 |
break; |
|
| 427 |
case 1: |
|
| 428 |
rw = PAGE_WRITE; |
|
| 429 |
break; |
|
| 430 |
case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */ |
|
| 431 |
rw = PAGE_READ; |
|
| 432 |
break; |
|
| 433 |
default: |
|
| 434 |
/* fatal error */ |
|
| 435 |
assert(0); |
|
| 436 |
} |
|
| 437 |
|
|
| 421 | 438 |
/* XXXXX */ |
| 422 | 439 |
#if 0 |
| 423 | 440 |
fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n", |
| ... | ... | |
| 479 | 496 |
return physical; |
| 480 | 497 |
} |
| 481 | 498 |
|
| 499 |
void cpu_load_tlb(CPUState * env) |
|
| 500 |
{
|
|
| 501 |
int n = cpu_mmucr_urc(env->mmucr); |
|
| 502 |
tlb_t * entry = &env->utlb[n]; |
|
| 503 |
|
|
| 504 |
/* Take values into cpu status from registers. */ |
|
| 505 |
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
|
| 506 |
entry->vpn = cpu_pteh_vpn(env->pteh); |
|
| 507 |
entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
|
| 508 |
entry->ppn = cpu_ptel_ppn(env->ptel); |
|
| 509 |
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
|
| 510 |
switch (entry->sz) {
|
|
| 511 |
case 0: /* 00 */ |
|
| 512 |
entry->size = 1024; /* 1K */ |
|
| 513 |
break; |
|
| 514 |
case 1: /* 01 */ |
|
| 515 |
entry->size = 1024 * 4; /* 4K */ |
|
| 516 |
break; |
|
| 517 |
case 2: /* 10 */ |
|
| 518 |
entry->size = 1024 * 64; /* 64K */ |
|
| 519 |
break; |
|
| 520 |
case 3: /* 11 */ |
|
| 521 |
entry->size = 1024 * 1024; /* 1M */ |
|
| 522 |
break; |
|
| 523 |
default: |
|
| 524 |
assert(0); |
|
| 525 |
break; |
|
| 526 |
} |
|
| 527 |
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
|
| 528 |
entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
|
| 529 |
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
|
| 530 |
entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
|
| 531 |
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
|
| 532 |
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
|
| 533 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
|
| 534 |
} |
|
| 535 |
|
|
| 482 | 536 |
#endif |
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