KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load relatedsynchronization points in favor of four(!) generic hooks:
- cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave)...
Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if thiscode is never executed. Don't print an error message on the console,but keep the message in the log for debugging purposes....
target-ppc: stop translation after a trap instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,not extracted, and so used the wrong shift amounts to sign-extend or padwith zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bitposition. Because of this, the SPE evcmp* family of instructions wouldstore values in the result condition register that were also off by onebit position....
PPC: tell the guest about the time base frequency
Our guest systems need to know by how much the timebase increases every second,so there usually is a "timebase-frequency" property in the cpu leaf of thedevice tree.
This property is missing in OpenBIOS....
PPC: Fix large pages
We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviouslythat breaks, so let's just ignore 1TB SLB entries for now and instead do16MB pages correctly.
This fixes PPC64 Linux boot with -m above 256.
Signed-off-by: Alexander Graf <agraf@suse.de>...
PPC: Add timer when running KVM
For some odd reason we sometimes hang inside KVM forever. I'd guess it'sa race condition where we actually have a level triggered interrupt, butthe infrastructure can't expose that yet, so the guest ACKs it, goes tosleep and never gets notified that there's still an interrupt pending....
target-ppc: change DCR helpers to target_long arguments
The recent transition to always have the DCR helper functions take 32 bitvalues broke the PPC64 target, as target_long became 64 bits there.
This patch changes DCR helpers to target_long arguments, and cast the values...
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused byzone protection bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
ppc-40x: Correct decoding of zone protection bits.
The 40x MMU has 15 zones in the ZPR register.
ppc-40x: Correct check for Endian swapping TLB entries.
Bailout on 40x TLB entries with endianess swapping only if the entryis valid.
ppc-40x: Get TLB attributes from TLBLO.
The ZSEL was incorrectly beeing decoded from TLBHI. Decode it fromTLBLO instead.
PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t topass it along the stacks.
This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, makingit compile without --disable-werror
PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBLshould return a 64-bit value on 64 bit implementations.
PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed usingtwo separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.
On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full64 bits as return value. If we only take the lower ones, fine. But Linux...
target-ppc: fix ppc32 kvm build
My segment sync patch broke compilation on PPC32, because it was trying tosync the SLB even though ppc32 CPUs don't have an SLB.
So let's only sync it when we're on a PP64 one!
target-ppc: Get MMU state on register sync
While x86 only needs to sync cr0-4 to know all about its MMU state and enableqemu to resolve virtual to physical addresses, we need to sync all of thesegment registers on PPC to know which mapping we're in.
So let's grab the segment register contents to be able to use the "x" monitor...
kvm: Add arch reset handler
Will be required by succeeding changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm ppc: Remove unused label
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: rename cpu_ppc_reset to cpu_reset for consistency
PPC: remove unneeded calls to device reset
target-ppc: move often used CPU fields at the top of the structure
target-ppc: simpler definitions for microcontrollers based on e300
No need to alias e300 core for each CPU package.Differences between microcontrollers have to be implemented in a higher layerthan translate_init.c
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>...
target-ppc: add declarations of microcontrollers based on e300
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: better support of e300 CPU core
Declare HID2 register.
Use high BATs for e300 (8 instead of 4).
Fix index of high BATs registers.Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: François Armand <francois.armand@os4i.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-ppc: log instructions start in TCG code
static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Unexport ticks_per_sec variable. Create get_ticks_per_sec() function
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'argument isn't self-explanatory. Simplify it by making it alwayssynchronize the kernel state into qemu, and automatically flush theregisters back to the kernel if they've been synchronized on this...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Replace REGX with PRIx64
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: add cpu_set_tls
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
target-ppc: add exceptions for conditional stores
target-ppc: fix cpu_clone_regs
We only need to make sure that the clone syscall looks like itsucceeded, not clobber 60% of the register set.
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Rename HAVE_FDT to CONFIG_FDT and define it also in Makefile
Use correct input constant
440 and desktop codes use different input constants for interrupt indication.
Let's use the respective ones for KVM.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Set PVR in sregs
We need to tell the kernel about some initial CPU state we don't have yet,so let's use the "sregs" IOCTL for that and simply put the Processor VersionRegister in there.
Now the kernel knows which guest CPU to virtualize.
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Update to a hopefully more future proof FSF address
target-ppc: enable PPC_MFTB for 44x
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's apreserved instruction:
PPC440_UM2013.pdf, p.445, table A-3
when I compile a kernel (2.6.30, bamboo_defconfig/440EP &canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump...
ppc tcg: fix wrong bit/mask of wrteei
Signed-off-by: Baojun Wang <wangbj@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:
evmergelo rX, rX, rY
as:
rX-lo = rY-lorX-hi = rX-lo
which is wrong, because we should be transferring rX-lo first. Thisproblem is fixed by swapping the order in which we write the parts of...
target-ppc: permit linux-user to read PVR
Access to the PVR SPR is normally forbidden from userspace apps. TheLinux kernel, however, fixes up reads in the appropriate trap handler.To permit applications that read PVR to run on QEMU, then, we need toimplement the same handling of PVR reads....
Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be useduninitialized
Replace ELF section hack with normal table
Concentrate rest of table entries to top
Concentrate most table entries to top
Clean up GEN_HANDLER2
Clean up GEN_HANDLER
Fix mingw32 build warnings
Work around buffer and ioctlsocket argument type signedness problemsSuppress a prototype which is unused on mingw32Expand a macro to avoid warnings from some GCC versions
kvm: Add missing bits to support live migration
This patch adds the missing hooks to allow live migration in KVM mode.It adds proper synchronization before/after saving/restoring the VCPUstates (note: PPC is untested), hooks intocpu_physical_memory_set_dirty_tracking() to enable dirty memory logging...
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).Build these files into a convenience library, and use that instead ofbuilding for every target.
Remove and poison various target specific macros to avoid bogus target...
target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on thecapabilities of the CPU we're emulating.
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Signed-off-by: Paul Brook <paul@codesourcery.com>
Fix typo that leads to out of bounds array access on big endian systems
Fix powerpc 604 reset vector
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is setfor hreset and the vector is at offset 0x100 from the exception prefix.
No difference in this area between 604 and 604e.
Signed-off-by: Tristan Gingold <gingold@adacore.com>
Fix PPC reset
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PURE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ppc-softmmu warnings on OpenBSD host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
target-ppc: Explain why the whole TLB is flushed on SR write
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: avoid nop to override next instruction
While searching PC, always store the pc of a new instruction.Instructions that didn't generate tcg code (such as nop) prevented thenext one to be referenced.
Based on patch for target-alpha, r6930.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Make the ELF loader aware of backwards compatibility
Most 64 bit architectures I'm aware of support running 32 bit codeof the same architecture as well.
So x86_64 can run i386 code easily and ppc64 can run ppc code.
Unfortunately, the current checks are pretty strict. So you can only...
target-ppc: use the new bswap* TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix commit r6789
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
targe-ppc: optimize mfcr and mtcrf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: free a tcg temp variable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add support for reading/writing spefscr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one errors for Altivec and SPE registers
Altivec and SPE both have 34 registers in their register sets, not 35with a missing register 32.
GDB would ask for register 32 of the Altivec (resp. SPE) registers andthe code would claim it had zero width. The QEMU GDB stub code would...
Disable BAT for 970
The 970 doesn't know BAT, so let's not search BATs there.This was only in as a hack for OpenHackWare so it wouldwork on PPC64.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mfcr on ppc64-softmmu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Fix NX bit
ctx->nx only got ORed, but never reset. So when one page in thelifetime of the VM was ever NX, all later pages were too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
Fix RFI
The current implementation masks some MSR bits from SRR1 as it isgiven on rfi(d). This looks pretty wrong and breaks Altivec.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
Implement mtfsf.L encoding
Mtfsf can have the L bit set, so all the register contents get storedin FPSCR. Linux uses it, so let's implement it.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
Enable 64bit mode on interrupts
Real 970s enable MSR_SF on all interrupts. The current code didn't dothis until now, so let's activate it!
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
Nop some SPRs on 970fx
Linux tries to access some SPRs on PPC64 boot. Let's just ignore thosefor the 970fx for now to make it happy.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
Implment tlbiel
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLBflush opcode only flushes an entry for the CPU it runs on, not acrossall CPUs in the system.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
Implement large pages
The current SLB/PTE code does not support large pages, which arerequired by Linux, as it boots up with the kernel regions up as large.
This patch implements large page support, so we can run Linux.
Signed-off-by: Alexander Graf <alex@csgraf.de>...
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
Sparse fixes: add extern to ELF opcode tables to avoid warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1- small optimisation of mtcrf- add the name of both opcodes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mtcrf/mfcr
Noticed by Alexander Graf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162