Revision ea86e4e6
| b/hw/mips_timer.c | ||
|---|---|---|
| 2 | 2 |
#include "mips.h" |
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#include "qemu-timer.h" |
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#define TIMER_FREQ 100 * 1000 * 1000 |
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void cpu_mips_irqctrl_init (void) |
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{
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} |
| ... | ... | |
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else |
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return env->CP0_Count + |
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(uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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100 * 1000 * 1000, ticks_per_sec);
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TIMER_FREQ, ticks_per_sec);
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} |
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void cpu_mips_store_count (CPUState *env, uint32_t count)
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static void cpu_mips_timer_update(CPUState *env)
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{
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uint64_t now, next; |
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uint32_t tmp; |
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uint32_t compare = env->CP0_Compare; |
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uint32_t wait; |
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tmp = count; |
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if (count == compare) |
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tmp++; |
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now = qemu_get_clock(vm_clock); |
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
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if (next == now) |
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next++; |
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#if 0 |
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if (logfile) {
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fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n", |
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__func__, now, count, compare, next - now); |
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} |
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#endif |
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/* Store new count and compare registers */ |
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env->CP0_Compare = compare; |
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env->CP0_Count = |
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
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/* Adjust timer */ |
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wait = env->CP0_Compare - env->CP0_Count - |
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(uint32_t)muldiv64(now, TIMER_FREQ, ticks_per_sec); |
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next = now + muldiv64(wait, ticks_per_sec, TIMER_FREQ); |
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qemu_mod_timer(env->timer, next); |
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} |
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static void cpu_mips_update_count (CPUState *env, uint32_t count)
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void cpu_mips_store_count (CPUState *env, uint32_t count)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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return; |
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cpu_mips_store_count(env, count); |
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env->CP0_Count = count; |
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else {
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/* Store new count register */ |
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env->CP0_Count = |
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count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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TIMER_FREQ, ticks_per_sec); |
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/* Update timer timer */ |
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cpu_mips_timer_update(env); |
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} |
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} |
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void cpu_mips_store_compare (CPUState *env, uint32_t value) |
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{
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env->CP0_Compare = value; |
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cpu_mips_update_count(env, cpu_mips_get_count(env)); |
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
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if (!(env->CP0_Cause & (1 << CP0Ca_DC))) |
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cpu_mips_timer_update(env); |
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if (env->insn_flags & ISA_MIPS32R2) |
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env->CP0_Cause &= ~(1 << CP0Ca_TI); |
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qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
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} |
| ... | ... | |
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{
|
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/* Store the current value */ |
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env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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100 * 1000 * 1000, ticks_per_sec);
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TIMER_FREQ, ticks_per_sec);
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} |
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|
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static void mips_timer_cb (void *opaque) |
| ... | ... | |
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if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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return; |
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cpu_mips_update_count(env, cpu_mips_get_count(env));
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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env->CP0_Cause |= 1 << CP0Ca_TI; |
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qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
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} |
| ... | ... | |
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
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env->CP0_Compare = 0; |
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cpu_mips_update_count(env, 1);
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cpu_mips_store_count(env, 1);
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} |
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