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# Date Author Comment
81762d6d 04/01/2011 07:34 pm David Gibson

Clean up PowerPC SLB handling code

Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'. While the layout in these fields does match the
description of the SLB in the architecture document, it is not...

d569956e 04/01/2011 07:34 pm David Gibson

Add a hook to allow hypercalls to be emulated on PowerPC

PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.

qemu currently has stub implementations of hypervisor mode. That...

efdef95f 04/01/2011 07:34 pm David Gibson

Implement PowerPC slbmfee and slbmfev instructions

For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions...

ae0bfb79 10/13/2010 09:38 pm Blue Swirl

ppc: remove video.x

Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.

Remove video.x MoL hacks.

Signed-off-by: Alexander Graf <>
Signed-off-by: Blue Swirl <>

999fa40e 10/05/2010 07:38 pm John Clark

ppc: Minor 40x MMU fixes

  • Fix swapped reading of tlblo/hi.
  • Fix tlb exec permissions

Signed-off-by: John Clark <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Edgar E. Iglesias <>

a586e548 09/24/2010 11:01 pm Edgar E. Iglesias

powerpc: Improve emulation of the BookE MMU

Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <>

41557447 09/15/2010 05:18 pm Alexander Graf

PPC: Redesign interrupt trigger path

According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.

To reflect this, let's redesign the way that MSR value gets calculated....

24e0e38b 09/11/2010 03:29 pm Edgar E. Iglesias

powerpc: Avoid TLB related log spamming

Invalid TLB entries are normal and should not spam the log.

Signed-off-by: Edgar E. Iglesias <>

0f89cc7b 05/31/2010 08:18 pm Thomas Monjalon

target-ppc: remove useless line

This line was a bit clear.
The next lines set or reset this bit (LE) depending of another bit (ILE).
So the first line is useless.

Signed-off-by: Thomas Monjalon <>
Signed-off-by: Aurelien Jarno <>

c3d420ea 05/31/2010 08:17 pm Thomas Monjalon

target-ppc: fix RFI by clearing some bits of MSR

Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
because some interrupt specifics bits of SRR1 are copied to MSR.

SRR1 is a save of MSR during interrupt.
During RFI, MSR must be restored from SRR1....

05f92404 04/25/2010 11:32 pm Blue Swirl

ppc: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>

d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...

4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>

b2eca445 02/14/2010 04:10 pm Alexander Graf

PPC: Fix large pages

We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviously
that breaks, so let's just ignore 1TB SLB entries for now and instead do
16MB pages correctly.

This fixes PPC64 Linux boot with -m above 256.

Signed-off-by: Alexander Graf <>...

dcbc9a70 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct ESR for zone protection faults.

Raise the zone protection fault in ESR for TLB faults caused by
zone protection bits.

Signed-off-by: Edgar E. Iglesias <>

ec5c3e48 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct decoding of zone protection bits.

The 40x MMU has 15 zones in the ZPR register.

Signed-off-by: Edgar E. Iglesias <>

b55a37c9 11/07/2009 12:37 pm Blue Swirl

user: move CPU reset call to main.c for x86/PPC/Sparc

Signed-off-by: Blue Swirl <>

d84bda46 11/07/2009 12:36 pm Blue Swirl

PPC: rename cpu_ppc_reset to cpu_reset for consistency

Signed-off-by: Blue Swirl <>

e4394131 11/07/2009 11:32 am Blue Swirl

PPC: remove unneeded calls to device reset

Signed-off-by: Blue Swirl <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time

Signed-off-by: malc <>

b11ebf64 08/16/2009 02:54 pm Blue Swirl

Replace REGX with PRIx64

Signed-off-by: Blue Swirl <>

90e189ec 08/16/2009 02:13 pm Blue Swirl

Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx

Signed-off-by: Blue Swirl <>

636aa200 08/16/2009 12:06 pm Blue Swirl

Replace always_inline with inline

We define inline as always_inline.

Signed-off-by: Blue Swirl <>

18b21a2f 08/03/2009 07:33 pm Nathan Froyd

target-ppc: retain l{w,d}arx loaded value

We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed. It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <>...

0bf9e31a 07/20/2009 08:19 pm Blue Swirl

Fix most warnings (errors with -Werror) when debugging is enabled

I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*

Signed-off-by: Blue Swirl <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

55616505 05/13/2009 10:54 pm Paul Brook

Include assert.h from qemu-common.h

Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <>

fc1c67bc 04/28/2009 09:00 pm Blue Swirl

Fix PPC reset

0bf46a40 04/24/2009 09:03 pm aliguori

qemu: introduce qemu_init_vcpu (Marcelo Tosatti)

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

bf1752ef 03/29/2009 04:36 pm aurel32

target-ppc: Explain why the whole TLB is flushed on SR write

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

94855937 03/07/2009 10:58 pm blueswir1

Disable BAT for 970

The 970 doesn't know BAT, so let's not search BATs there.
This was only in as a hack for OpenHackWare so it would
work on PPC64.

Signed-off-by: Alexander Graf <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...

29c8ca6f 03/07/2009 10:57 pm blueswir1

Fix NX bit

ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

6ce0ca12 03/07/2009 10:54 pm blueswir1

Enable 64bit mode on interrupts

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

5b5aba4f 03/07/2009 10:51 pm blueswir1

Implement large pages

The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <>...

f6b868fc 03/07/2009 10:50 pm blueswir1

Implement slbmte

In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later....

07c485ce 02/21/2009 07:29 pm blueswir1

Turn MMU off on reset

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

0d0266a5 02/06/2009 12:06 am aliguori

targets: remove error handling from qemu_malloc() callers (Avi Kivity)

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

eca1bdf4 01/26/2009 09:54 pm aliguori

Log reset events (Jan Kiszka)

Original idea&code by Kevin Wolf, split-up in two patches and added more

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <>...

93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

d12d51d5 01/15/2009 11:48 pm aliguori

Clean up debugging code #ifdefs (Eduardo Habkost)

Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later...

da07cf59 01/15/2009 11:24 pm aliguori

powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)

Signed-off-by: Liu Yu <>
Acked-by: Hollis Blanchard <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

d76d1650 12/16/2008 12:43 pm aurel32

target-ppc: Enable KVM for ppcemb.

Implement hooks called by generic KVM code.

Also add code that will copy the host's CPU and timebase frequencies to the
guest, which is necessary on KVM because the guest can directly access the

Signed-off-by: Hollis Blanchard <>...

93220573 12/12/2008 12:42 am aurel32

target-ppc: remove remaining warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

94fa46e2 12/12/2008 12:42 am aurel32

target-ppc: remove unneeded include

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

e06fcd75 12/12/2008 12:42 am aurel32

target-ppc: rework exception code

... also remove two warnings.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

4c2ab988 12/10/2008 05:02 pm aurel32

target-ppc: enable SPE and Altivec in user mode

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

fe463b7d 12/10/2008 05:02 pm aurel32

target-ppc: initialize MSR appropriately in user-mode

Mask the initial MSR with the mask from the PowerPC CPU definition.

Noticed by Nathan Froyd.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b4cec7b4 12/08/2008 08:11 pm aurel32

target-ppc: enable access type in MMU

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

45d827d2 12/07/2008 03:40 pm aurel32

target-ppc: convert SPR accesses to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

74d37793 12/06/2008 11:46 pm aurel32

target-ppc: convert SLB/TLB instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

64adab3f 11/22/2008 12:09 pm aurel32

target-ppc: convert exceptions generation to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

3d7b417e 10/21/2008 02:28 pm aurel32

target-ppc: Convert XER accesses to TCG

Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

e2be8d8d 10/14/2008 10:55 pm aurel32

PPC: convert effective address computation to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

2e70f6ef 06/29/2008 04:03 am pbrook

Add instruction counter.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

ca10f867 04/12/2008 12:35 am aurel32

Remove osdep.c/qemu-img code duplication

(Kevin Wolf)

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

01ba9816 12/09/2007 04:22 am ths

Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

6b542af7 11/24/2007 04:03 am j_mayer

Fix incorrect debug prints (reported by Paul Brook).
Remove obsolete / duplicated debug prints and improve output consistency.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

69facb78 11/24/2007 12:16 am j_mayer

Revert foolish patch.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

9b605b9e 11/23/2007 07:33 pm pbrook

Fix ppc32 register dumps on 64-bit hosts.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

add78955 11/19/2007 01:41 pm j_mayer

PowerPC 620 MMU do not have the same exact behavior as standard
64 bits PowerPC ones.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b4095fed 11/18/2007 12:42 am j_mayer

Define Freescale cores specific MMU model, exceptions and input bus.
(but do not provide any actual implementation).

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

a4f30719 11/17/2007 11:14 pm j_mayer

PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
Remove TARGET_PPC64 dependency and add code provision to be able
to define a fake 32 bits CPU with hypervisor feature support.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b172c56a 11/17/2007 03:37 am j_mayer

Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

3cd7d1dd 11/12/2007 03:56 am j_mayer

Allow use of SPE extension by all PowerPC targets,
adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
and 36 bits physical address space....

6f2d8978 11/12/2007 02:04 am j_mayer

Fix usage of the -1 constant in the PowerPC target code:
fix invalid size casts and/or sign-extensions.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

aaed909a 11/10/2007 05:15 pm bellard

added cpu_model parameter to cpu_init()

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

056401ea 11/04/2007 04:55 am j_mayer

PowerPC 601 need specific callbacks for its BATs setup.
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation....

faadf50e 11/03/2007 03:37 pm j_mayer PowerPC MMU and exception fixes:
  • PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than
    later PowerPC implementation.
  • Bugfix in BATs check: must not stop after 4 BATs when more are provided.
  • Enable POWER 'rac' instruction.
  • Fix exception prefix for all supported PowerPC implementations....
5b52b991 11/03/2007 12:35 am j_mayer

Fix PowerPC program exception that was broken by FPU exception patches
(bug reported by Jason Wessel)

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

a11b8151 10/28/2007 03:55 am j_mayer

PowerPC coding style and inlining fixes.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

7c58044c 10/27/2007 08:54 pm j_mayer

Fix PowerPC FPSCR update and floating-point exception generation
in most useful cases.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

f9fdea6b 10/26/2007 03:38 am j_mayer

Make PowerPC hypervisor resources able to compile, even if not enabled for now.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

2c1ee068 10/26/2007 03:37 am j_mayer

Bugfix: PowerPC 64 slbia never invalidates the first segment entry.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

0411a972 10/26/2007 12:35 am j_mayer

Gprof prooved the PowerPC emulation spent too much time in MSR load and store
routines. Coming back to a raw MSR storage model then speed-up the emulation.
Improve fast MSR updates (wrtee wrteei and mtriee cases).
Share rfi family instructions helpers code to avoid bug in duplicated code....

b227a8e9 10/14/2007 01:21 pm j_mayer

Properly implement non-execute bit on PowerPC segments and PTEs.
Fix page protection bits for PowerPC 64 MMU.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

a13d7523 10/14/2007 12:14 pm j_mayer

There is no need of a specific MMU model for PowerPC 601.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

eacc3249 10/14/2007 12:06 pm j_mayer

Implement PowerPC 64 SLB invalidation helpers.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

e63ecc6f 10/14/2007 11:48 am j_mayer

Do not allow PowerPC CPU restart after entering checkstop mode.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....

25ba3a68 10/08/2007 05:58 am j_mayer

Remove synonymous in PowerPC MSR bits definitions.
Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.

141c8ae2 10/08/2007 05:44 am j_mayer

Real-mode only PowerPC 40x do not have any TLBs.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

4e80effc 10/08/2007 05:35 am j_mayer

Implement exception prefix feature for PowerPC 601.
Fix PowerPC 601 hardware reset vector.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b33c17e1 10/07/2007 08:30 pm j_mayer

PowerPC target coding style fixes.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b068d6a7 10/07/2007 08:13 pm j_mayer

PowerPC target optimisations: make intensive use of always_inline.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

d26bfc9a 10/07/2007 05:41 pm j_mayer

Add MSR bits signification per PowerPC implementation flags (to be continued).
As a side effect, single step and branch step are available again.
Remove irrelevant MSR bits definitions.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

12de9a39 10/06/2007 01:06 am j_mayer

Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces....

1c27f8fb 10/05/2007 04:09 pm j_mayer

PowerPC hardware reset vector is now considered as part of the exception model.
Use it at CPU initialisation time.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

8f793433 10/03/2007 11:19 pm j_mayer

Enable PowerPC 64 MMU model and exceptions.
Cleanups in MMU exceptions generation.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

fe33cc71 10/03/2007 04:06 am j_mayer

Fix PowerPC initialisation and first reset:
reset must occur after we defined the CPU features.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

00af685f 10/03/2007 04:05 am j_mayer

We never have to export ppc_set_irq.
Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

a97fed52 10/02/2007 12:49 am j_mayer

Fix reproductible crash: call cpu_loop_exit from micro-op, not from helper.c

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

7dbe11ac 10/01/2007 08:16 am j_mayer

Handle all MMU models in switches, even if it's just to abort because of lack
of supporting code.
Implement 74xx software TLB model.
Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss
on those processors.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

daf4f96e 10/01/2007 04:51 am j_mayer

Avoid op helpers that would just call helpers for TLB & SLB management:
call the helpers directly from the micro-ops.
Avoid duplicated code for tlbsx. implementation.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

1e6784f9 09/30/2007 06:19 pm j_mayer

Fix PowerPC TLB miss dump code.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

bfa1e5cf 09/30/2007 03:50 am j_mayer

XER is to be treated as a 64 bits register on 64 bits implementations,
according to the PowerPC 2.04 specification.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

e1833e1f 09/29/2007 04:06 pm j_mayer Rework PowerPC exceptions model to make it more versatile:
  • don't use exception vectors as the exception number.
    Use vectors numbers as defined in the PowerPC embedded specification instead
    and extend this model to cover all emulated PowerPC variants exceptions....