Statistics
| Branch: | Revision:

root / target-ppc / translate.c @ eaabeef2

History | View | Annotate | Download (340.6 kB)

1
/*
2
 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18
 */
19
#include <stdarg.h>
20
#include <stdlib.h>
21
#include <stdio.h>
22
#include <string.h>
23
#include <inttypes.h>
24

    
25
#include "cpu.h"
26
#include "exec-all.h"
27
#include "disas.h"
28
#include "tcg-op.h"
29
#include "qemu-common.h"
30
#include "host-utils.h"
31

    
32
#include "helper.h"
33
#define GEN_HELPER 1
34
#include "helper.h"
35

    
36
#define CPU_SINGLE_STEP 0x1
37
#define CPU_BRANCH_STEP 0x2
38
#define GDBSTUB_SINGLE_STEP 0x4
39

    
40
/* Include definitions for instructions classes and implementations flags */
41
//#define PPC_DEBUG_DISAS
42
//#define DO_PPC_STATISTICS
43

    
44
#ifdef PPC_DEBUG_DISAS
45
#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46
#else
47
#  define LOG_DISAS(...) do { } while (0)
48
#endif
49
/*****************************************************************************/
50
/* Code translation helpers                                                  */
51

    
52
/* global register indexes */
53
static TCGv_ptr cpu_env;
54
static char cpu_reg_names[10*3 + 22*4 /* GPR */
55
#if !defined(TARGET_PPC64)
56
    + 10*4 + 22*5 /* SPE GPRh */
57
#endif
58
    + 10*4 + 22*5 /* FPR */
59
    + 2*(10*6 + 22*7) /* AVRh, AVRl */
60
    + 8*5 /* CRF */];
61
static TCGv cpu_gpr[32];
62
#if !defined(TARGET_PPC64)
63
static TCGv cpu_gprh[32];
64
#endif
65
static TCGv_i64 cpu_fpr[32];
66
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67
static TCGv_i32 cpu_crf[8];
68
static TCGv cpu_nip;
69
static TCGv cpu_msr;
70
static TCGv cpu_ctr;
71
static TCGv cpu_lr;
72
static TCGv cpu_xer;
73
static TCGv cpu_reserve;
74
static TCGv_i32 cpu_fpscr;
75
static TCGv_i32 cpu_access_type;
76

    
77
#include "gen-icount.h"
78

    
79
void ppc_translate_init(void)
80
{
81
    int i;
82
    char* p;
83
    size_t cpu_reg_names_size;
84
    static int done_init = 0;
85

    
86
    if (done_init)
87
        return;
88

    
89
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90

    
91
    p = cpu_reg_names;
92
    cpu_reg_names_size = sizeof(cpu_reg_names);
93

    
94
    for (i = 0; i < 8; i++) {
95
        snprintf(p, cpu_reg_names_size, "crf%d", i);
96
        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97
                                            offsetof(CPUState, crf[i]), p);
98
        p += 5;
99
        cpu_reg_names_size -= 5;
100
    }
101

    
102
    for (i = 0; i < 32; i++) {
103
        snprintf(p, cpu_reg_names_size, "r%d", i);
104
        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
105
                                        offsetof(CPUState, gpr[i]), p);
106
        p += (i < 10) ? 3 : 4;
107
        cpu_reg_names_size -= (i < 10) ? 3 : 4;
108
#if !defined(TARGET_PPC64)
109
        snprintf(p, cpu_reg_names_size, "r%dH", i);
110
        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
111
                                             offsetof(CPUState, gprh[i]), p);
112
        p += (i < 10) ? 4 : 5;
113
        cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
#endif
115

    
116
        snprintf(p, cpu_reg_names_size, "fp%d", i);
117
        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118
                                            offsetof(CPUState, fpr[i]), p);
119
        p += (i < 10) ? 4 : 5;
120
        cpu_reg_names_size -= (i < 10) ? 4 : 5;
121

    
122
        snprintf(p, cpu_reg_names_size, "avr%dH", i);
123
#ifdef HOST_WORDS_BIGENDIAN
124
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125
                                             offsetof(CPUState, avr[i].u64[0]), p);
126
#else
127
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128
                                             offsetof(CPUState, avr[i].u64[1]), p);
129
#endif
130
        p += (i < 10) ? 6 : 7;
131
        cpu_reg_names_size -= (i < 10) ? 6 : 7;
132

    
133
        snprintf(p, cpu_reg_names_size, "avr%dL", i);
134
#ifdef HOST_WORDS_BIGENDIAN
135
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136
                                             offsetof(CPUState, avr[i].u64[1]), p);
137
#else
138
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139
                                             offsetof(CPUState, avr[i].u64[0]), p);
140
#endif
141
        p += (i < 10) ? 6 : 7;
142
        cpu_reg_names_size -= (i < 10) ? 6 : 7;
143
    }
144

    
145
    cpu_nip = tcg_global_mem_new(TCG_AREG0,
146
                                 offsetof(CPUState, nip), "nip");
147

    
148
    cpu_msr = tcg_global_mem_new(TCG_AREG0,
149
                                 offsetof(CPUState, msr), "msr");
150

    
151
    cpu_ctr = tcg_global_mem_new(TCG_AREG0,
152
                                 offsetof(CPUState, ctr), "ctr");
153

    
154
    cpu_lr = tcg_global_mem_new(TCG_AREG0,
155
                                offsetof(CPUState, lr), "lr");
156

    
157
    cpu_xer = tcg_global_mem_new(TCG_AREG0,
158
                                 offsetof(CPUState, xer), "xer");
159

    
160
    cpu_reserve = tcg_global_mem_new(TCG_AREG0,
161
                                     offsetof(CPUState, reserve_addr),
162
                                     "reserve_addr");
163

    
164
    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165
                                       offsetof(CPUState, fpscr), "fpscr");
166

    
167
    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168
                                             offsetof(CPUState, access_type), "access_type");
169

    
170
    /* register helpers */
171
#define GEN_HELPER 2
172
#include "helper.h"
173

    
174
    done_init = 1;
175
}
176

    
177
/* internal defines */
178
typedef struct DisasContext {
179
    struct TranslationBlock *tb;
180
    target_ulong nip;
181
    uint32_t opcode;
182
    uint32_t exception;
183
    /* Routine used to access memory */
184
    int mem_idx;
185
    int access_type;
186
    /* Translation flags */
187
    int le_mode;
188
#if defined(TARGET_PPC64)
189
    int sf_mode;
190
#endif
191
    int fpu_enabled;
192
    int altivec_enabled;
193
    int spe_enabled;
194
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
195
    int singlestep_enabled;
196
} DisasContext;
197

    
198
struct opc_handler_t {
199
    /* invalid bits */
200
    uint32_t inval;
201
    /* instruction type */
202
    uint64_t type;
203
    /* handler */
204
    void (*handler)(DisasContext *ctx);
205
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
206
    const char *oname;
207
#endif
208
#if defined(DO_PPC_STATISTICS)
209
    uint64_t count;
210
#endif
211
};
212

    
213
static inline void gen_reset_fpstatus(void)
214
{
215
#ifdef CONFIG_SOFTFLOAT
216
    gen_helper_reset_fpstatus();
217
#endif
218
}
219

    
220
static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
221
{
222
    TCGv_i32 t0 = tcg_temp_new_i32();
223

    
224
    if (set_fprf != 0) {
225
        /* This case might be optimized later */
226
        tcg_gen_movi_i32(t0, 1);
227
        gen_helper_compute_fprf(t0, arg, t0);
228
        if (unlikely(set_rc)) {
229
            tcg_gen_mov_i32(cpu_crf[1], t0);
230
        }
231
        gen_helper_float_check_status();
232
    } else if (unlikely(set_rc)) {
233
        /* We always need to compute fpcc */
234
        tcg_gen_movi_i32(t0, 0);
235
        gen_helper_compute_fprf(t0, arg, t0);
236
        tcg_gen_mov_i32(cpu_crf[1], t0);
237
    }
238

    
239
    tcg_temp_free_i32(t0);
240
}
241

    
242
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
243
{
244
    if (ctx->access_type != access_type) {
245
        tcg_gen_movi_i32(cpu_access_type, access_type);
246
        ctx->access_type = access_type;
247
    }
248
}
249

    
250
static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
251
{
252
#if defined(TARGET_PPC64)
253
    if (ctx->sf_mode)
254
        tcg_gen_movi_tl(cpu_nip, nip);
255
    else
256
#endif
257
        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
258
}
259

    
260
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
261
{
262
    TCGv_i32 t0, t1;
263
    if (ctx->exception == POWERPC_EXCP_NONE) {
264
        gen_update_nip(ctx, ctx->nip);
265
    }
266
    t0 = tcg_const_i32(excp);
267
    t1 = tcg_const_i32(error);
268
    gen_helper_raise_exception_err(t0, t1);
269
    tcg_temp_free_i32(t0);
270
    tcg_temp_free_i32(t1);
271
    ctx->exception = (excp);
272
}
273

    
274
static inline void gen_exception(DisasContext *ctx, uint32_t excp)
275
{
276
    TCGv_i32 t0;
277
    if (ctx->exception == POWERPC_EXCP_NONE) {
278
        gen_update_nip(ctx, ctx->nip);
279
    }
280
    t0 = tcg_const_i32(excp);
281
    gen_helper_raise_exception(t0);
282
    tcg_temp_free_i32(t0);
283
    ctx->exception = (excp);
284
}
285

    
286
static inline void gen_debug_exception(DisasContext *ctx)
287
{
288
    TCGv_i32 t0;
289

    
290
    if (ctx->exception != POWERPC_EXCP_BRANCH)
291
        gen_update_nip(ctx, ctx->nip);
292
    t0 = tcg_const_i32(EXCP_DEBUG);
293
    gen_helper_raise_exception(t0);
294
    tcg_temp_free_i32(t0);
295
}
296

    
297
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
298
{
299
    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
300
}
301

    
302
/* Stop translation */
303
static inline void gen_stop_exception(DisasContext *ctx)
304
{
305
    gen_update_nip(ctx, ctx->nip);
306
    ctx->exception = POWERPC_EXCP_STOP;
307
}
308

    
309
/* No need to update nip here, as execution flow will change */
310
static inline void gen_sync_exception(DisasContext *ctx)
311
{
312
    ctx->exception = POWERPC_EXCP_SYNC;
313
}
314

    
315
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
316
GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
317

    
318
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
319
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
320

    
321
typedef struct opcode_t {
322
    unsigned char opc1, opc2, opc3;
323
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
324
    unsigned char pad[5];
325
#else
326
    unsigned char pad[1];
327
#endif
328
    opc_handler_t handler;
329
    const char *oname;
330
} opcode_t;
331

    
332
/*****************************************************************************/
333
/***                           Instruction decoding                        ***/
334
#define EXTRACT_HELPER(name, shift, nb)                                       \
335
static inline uint32_t name(uint32_t opcode)                                  \
336
{                                                                             \
337
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
338
}
339

    
340
#define EXTRACT_SHELPER(name, shift, nb)                                      \
341
static inline int32_t name(uint32_t opcode)                                   \
342
{                                                                             \
343
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
344
}
345

    
346
/* Opcode part 1 */
347
EXTRACT_HELPER(opc1, 26, 6);
348
/* Opcode part 2 */
349
EXTRACT_HELPER(opc2, 1, 5);
350
/* Opcode part 3 */
351
EXTRACT_HELPER(opc3, 6, 5);
352
/* Update Cr0 flags */
353
EXTRACT_HELPER(Rc, 0, 1);
354
/* Destination */
355
EXTRACT_HELPER(rD, 21, 5);
356
/* Source */
357
EXTRACT_HELPER(rS, 21, 5);
358
/* First operand */
359
EXTRACT_HELPER(rA, 16, 5);
360
/* Second operand */
361
EXTRACT_HELPER(rB, 11, 5);
362
/* Third operand */
363
EXTRACT_HELPER(rC, 6, 5);
364
/***                               Get CRn                                 ***/
365
EXTRACT_HELPER(crfD, 23, 3);
366
EXTRACT_HELPER(crfS, 18, 3);
367
EXTRACT_HELPER(crbD, 21, 5);
368
EXTRACT_HELPER(crbA, 16, 5);
369
EXTRACT_HELPER(crbB, 11, 5);
370
/* SPR / TBL */
371
EXTRACT_HELPER(_SPR, 11, 10);
372
static inline uint32_t SPR(uint32_t opcode)
373
{
374
    uint32_t sprn = _SPR(opcode);
375

    
376
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
377
}
378
/***                              Get constants                            ***/
379
EXTRACT_HELPER(IMM, 12, 8);
380
/* 16 bits signed immediate value */
381
EXTRACT_SHELPER(SIMM, 0, 16);
382
/* 16 bits unsigned immediate value */
383
EXTRACT_HELPER(UIMM, 0, 16);
384
/* 5 bits signed immediate value */
385
EXTRACT_HELPER(SIMM5, 16, 5);
386
/* 5 bits signed immediate value */
387
EXTRACT_HELPER(UIMM5, 16, 5);
388
/* Bit count */
389
EXTRACT_HELPER(NB, 11, 5);
390
/* Shift count */
391
EXTRACT_HELPER(SH, 11, 5);
392
/* Vector shift count */
393
EXTRACT_HELPER(VSH, 6, 4);
394
/* Mask start */
395
EXTRACT_HELPER(MB, 6, 5);
396
/* Mask end */
397
EXTRACT_HELPER(ME, 1, 5);
398
/* Trap operand */
399
EXTRACT_HELPER(TO, 21, 5);
400

    
401
EXTRACT_HELPER(CRM, 12, 8);
402
EXTRACT_HELPER(FM, 17, 8);
403
EXTRACT_HELPER(SR, 16, 4);
404
EXTRACT_HELPER(FPIMM, 12, 4);
405

    
406
/***                            Jump target decoding                       ***/
407
/* Displacement */
408
EXTRACT_SHELPER(d, 0, 16);
409
/* Immediate address */
410
static inline target_ulong LI(uint32_t opcode)
411
{
412
    return (opcode >> 0) & 0x03FFFFFC;
413
}
414

    
415
static inline uint32_t BD(uint32_t opcode)
416
{
417
    return (opcode >> 0) & 0xFFFC;
418
}
419

    
420
EXTRACT_HELPER(BO, 21, 5);
421
EXTRACT_HELPER(BI, 16, 5);
422
/* Absolute/relative address */
423
EXTRACT_HELPER(AA, 1, 1);
424
/* Link */
425
EXTRACT_HELPER(LK, 0, 1);
426

    
427
/* Create a mask between <start> and <end> bits */
428
static inline target_ulong MASK(uint32_t start, uint32_t end)
429
{
430
    target_ulong ret;
431

    
432
#if defined(TARGET_PPC64)
433
    if (likely(start == 0)) {
434
        ret = UINT64_MAX << (63 - end);
435
    } else if (likely(end == 63)) {
436
        ret = UINT64_MAX >> start;
437
    }
438
#else
439
    if (likely(start == 0)) {
440
        ret = UINT32_MAX << (31  - end);
441
    } else if (likely(end == 31)) {
442
        ret = UINT32_MAX >> start;
443
    }
444
#endif
445
    else {
446
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
447
            (((target_ulong)(-1ULL) >> (end)) >> 1);
448
        if (unlikely(start > end))
449
            return ~ret;
450
    }
451

    
452
    return ret;
453
}
454

    
455
/*****************************************************************************/
456
/* PowerPC instructions table                                                */
457

    
458
#if defined(DO_PPC_STATISTICS)
459
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
460
{                                                                             \
461
    .opc1 = op1,                                                              \
462
    .opc2 = op2,                                                              \
463
    .opc3 = op3,                                                              \
464
    .pad  = { 0, },                                                           \
465
    .handler = {                                                              \
466
        .inval   = invl,                                                      \
467
        .type = _typ,                                                         \
468
        .handler = &gen_##name,                                               \
469
        .oname = stringify(name),                                             \
470
    },                                                                        \
471
    .oname = stringify(name),                                                 \
472
}
473
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
474
{                                                                             \
475
    .opc1 = op1,                                                              \
476
    .opc2 = op2,                                                              \
477
    .opc3 = op3,                                                              \
478
    .pad  = { 0, },                                                           \
479
    .handler = {                                                              \
480
        .inval   = invl,                                                      \
481
        .type = _typ,                                                         \
482
        .handler = &gen_##name,                                               \
483
        .oname = onam,                                                        \
484
    },                                                                        \
485
    .oname = onam,                                                            \
486
}
487
#else
488
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
489
{                                                                             \
490
    .opc1 = op1,                                                              \
491
    .opc2 = op2,                                                              \
492
    .opc3 = op3,                                                              \
493
    .pad  = { 0, },                                                           \
494
    .handler = {                                                              \
495
        .inval   = invl,                                                      \
496
        .type = _typ,                                                         \
497
        .handler = &gen_##name,                                               \
498
    },                                                                        \
499
    .oname = stringify(name),                                                 \
500
}
501
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
502
{                                                                             \
503
    .opc1 = op1,                                                              \
504
    .opc2 = op2,                                                              \
505
    .opc3 = op3,                                                              \
506
    .pad  = { 0, },                                                           \
507
    .handler = {                                                              \
508
        .inval   = invl,                                                      \
509
        .type = _typ,                                                         \
510
        .handler = &gen_##name,                                               \
511
    },                                                                        \
512
    .oname = onam,                                                            \
513
}
514
#endif
515

    
516
/* SPR load/store helpers */
517
static inline void gen_load_spr(TCGv t, int reg)
518
{
519
    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
520
}
521

    
522
static inline void gen_store_spr(int reg, TCGv t)
523
{
524
    tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
525
}
526

    
527
/* Invalid instruction */
528
static void gen_invalid(DisasContext *ctx)
529
{
530
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
531
}
532

    
533
static opc_handler_t invalid_handler = {
534
    .inval   = 0xFFFFFFFF,
535
    .type    = PPC_NONE,
536
    .handler = gen_invalid,
537
};
538

    
539
/***                           Integer comparison                          ***/
540

    
541
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
542
{
543
    int l1, l2, l3;
544

    
545
    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
546
    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
547
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
548

    
549
    l1 = gen_new_label();
550
    l2 = gen_new_label();
551
    l3 = gen_new_label();
552
    if (s) {
553
        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
554
        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
555
    } else {
556
        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
557
        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
558
    }
559
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
560
    tcg_gen_br(l3);
561
    gen_set_label(l1);
562
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
563
    tcg_gen_br(l3);
564
    gen_set_label(l2);
565
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
566
    gen_set_label(l3);
567
}
568

    
569
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
570
{
571
    TCGv t0 = tcg_const_local_tl(arg1);
572
    gen_op_cmp(arg0, t0, s, crf);
573
    tcg_temp_free(t0);
574
}
575

    
576
#if defined(TARGET_PPC64)
577
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
578
{
579
    TCGv t0, t1;
580
    t0 = tcg_temp_local_new();
581
    t1 = tcg_temp_local_new();
582
    if (s) {
583
        tcg_gen_ext32s_tl(t0, arg0);
584
        tcg_gen_ext32s_tl(t1, arg1);
585
    } else {
586
        tcg_gen_ext32u_tl(t0, arg0);
587
        tcg_gen_ext32u_tl(t1, arg1);
588
    }
589
    gen_op_cmp(t0, t1, s, crf);
590
    tcg_temp_free(t1);
591
    tcg_temp_free(t0);
592
}
593

    
594
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
595
{
596
    TCGv t0 = tcg_const_local_tl(arg1);
597
    gen_op_cmp32(arg0, t0, s, crf);
598
    tcg_temp_free(t0);
599
}
600
#endif
601

    
602
static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
603
{
604
#if defined(TARGET_PPC64)
605
    if (!(ctx->sf_mode))
606
        gen_op_cmpi32(reg, 0, 1, 0);
607
    else
608
#endif
609
        gen_op_cmpi(reg, 0, 1, 0);
610
}
611

    
612
/* cmp */
613
static void gen_cmp(DisasContext *ctx)
614
{
615
#if defined(TARGET_PPC64)
616
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
617
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
618
                     1, crfD(ctx->opcode));
619
    else
620
#endif
621
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
622
                   1, crfD(ctx->opcode));
623
}
624

    
625
/* cmpi */
626
static void gen_cmpi(DisasContext *ctx)
627
{
628
#if defined(TARGET_PPC64)
629
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
630
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
631
                      1, crfD(ctx->opcode));
632
    else
633
#endif
634
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
635
                    1, crfD(ctx->opcode));
636
}
637

    
638
/* cmpl */
639
static void gen_cmpl(DisasContext *ctx)
640
{
641
#if defined(TARGET_PPC64)
642
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
643
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
644
                     0, crfD(ctx->opcode));
645
    else
646
#endif
647
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
648
                   0, crfD(ctx->opcode));
649
}
650

    
651
/* cmpli */
652
static void gen_cmpli(DisasContext *ctx)
653
{
654
#if defined(TARGET_PPC64)
655
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
656
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
657
                      0, crfD(ctx->opcode));
658
    else
659
#endif
660
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
661
                    0, crfD(ctx->opcode));
662
}
663

    
664
/* isel (PowerPC 2.03 specification) */
665
static void gen_isel(DisasContext *ctx)
666
{
667
    int l1, l2;
668
    uint32_t bi = rC(ctx->opcode);
669
    uint32_t mask;
670
    TCGv_i32 t0;
671

    
672
    l1 = gen_new_label();
673
    l2 = gen_new_label();
674

    
675
    mask = 1 << (3 - (bi & 0x03));
676
    t0 = tcg_temp_new_i32();
677
    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
678
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
679
    if (rA(ctx->opcode) == 0)
680
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
681
    else
682
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
683
    tcg_gen_br(l2);
684
    gen_set_label(l1);
685
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
686
    gen_set_label(l2);
687
    tcg_temp_free_i32(t0);
688
}
689

    
690
/***                           Integer arithmetic                          ***/
691

    
692
static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
693
                                           TCGv arg1, TCGv arg2, int sub)
694
{
695
    int l1;
696
    TCGv t0;
697

    
698
    l1 = gen_new_label();
699
    /* Start with XER OV disabled, the most likely case */
700
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
701
    t0 = tcg_temp_local_new();
702
    tcg_gen_xor_tl(t0, arg0, arg1);
703
#if defined(TARGET_PPC64)
704
    if (!ctx->sf_mode)
705
        tcg_gen_ext32s_tl(t0, t0);
706
#endif
707
    if (sub)
708
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
709
    else
710
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
711
    tcg_gen_xor_tl(t0, arg1, arg2);
712
#if defined(TARGET_PPC64)
713
    if (!ctx->sf_mode)
714
        tcg_gen_ext32s_tl(t0, t0);
715
#endif
716
    if (sub)
717
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
718
    else
719
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
720
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
721
    gen_set_label(l1);
722
    tcg_temp_free(t0);
723
}
724

    
725
static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
726
                                           TCGv arg2, int sub)
727
{
728
    int l1 = gen_new_label();
729

    
730
#if defined(TARGET_PPC64)
731
    if (!(ctx->sf_mode)) {
732
        TCGv t0, t1;
733
        t0 = tcg_temp_new();
734
        t1 = tcg_temp_new();
735

    
736
        tcg_gen_ext32u_tl(t0, arg1);
737
        tcg_gen_ext32u_tl(t1, arg2);
738
        if (sub) {
739
            tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
740
        } else {
741
            tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
742
        }
743
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
744
        gen_set_label(l1);
745
        tcg_temp_free(t0);
746
        tcg_temp_free(t1);
747
    } else
748
#endif
749
    {
750
        if (sub) {
751
            tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
752
        } else {
753
            tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
754
        }
755
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
756
        gen_set_label(l1);
757
    }
758
}
759

    
760
/* Common add function */
761
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
762
                                    TCGv arg2, int add_ca, int compute_ca,
763
                                    int compute_ov)
764
{
765
    TCGv t0, t1;
766

    
767
    if ((!compute_ca && !compute_ov) ||
768
        (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {
769
        t0 = ret;
770
    } else {
771
        t0 = tcg_temp_local_new();
772
    }
773

    
774
    if (add_ca) {
775
        t1 = tcg_temp_local_new();
776
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
777
        tcg_gen_shri_tl(t1, t1, XER_CA);
778
    } else {
779
        TCGV_UNUSED(t1);
780
    }
781

    
782
    if (compute_ca && compute_ov) {
783
        /* Start with XER CA and OV disabled, the most likely case */
784
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
785
    } else if (compute_ca) {
786
        /* Start with XER CA disabled, the most likely case */
787
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
788
    } else if (compute_ov) {
789
        /* Start with XER OV disabled, the most likely case */
790
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
791
    }
792

    
793
    tcg_gen_add_tl(t0, arg1, arg2);
794

    
795
    if (compute_ca) {
796
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
797
    }
798
    if (add_ca) {
799
        tcg_gen_add_tl(t0, t0, t1);
800
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
801
        tcg_temp_free(t1);
802
    }
803
    if (compute_ov) {
804
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
805
    }
806

    
807
    if (unlikely(Rc(ctx->opcode) != 0))
808
        gen_set_Rc0(ctx, t0);
809

    
810
    if (!TCGV_EQUAL(t0, ret)) {
811
        tcg_gen_mov_tl(ret, t0);
812
        tcg_temp_free(t0);
813
    }
814
}
815
/* Add functions with two operands */
816
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
817
static void glue(gen_, name)(DisasContext *ctx)                                       \
818
{                                                                             \
819
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
820
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
821
                     add_ca, compute_ca, compute_ov);                         \
822
}
823
/* Add functions with one operand and one immediate */
824
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
825
                                add_ca, compute_ca, compute_ov)               \
826
static void glue(gen_, name)(DisasContext *ctx)                                       \
827
{                                                                             \
828
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
829
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
830
                     cpu_gpr[rA(ctx->opcode)], t0,                            \
831
                     add_ca, compute_ca, compute_ov);                         \
832
    tcg_temp_free(t0);                                                        \
833
}
834

    
835
/* add  add.  addo  addo. */
836
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
837
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
838
/* addc  addc.  addco  addco. */
839
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
840
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
841
/* adde  adde.  addeo  addeo. */
842
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
843
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
844
/* addme  addme.  addmeo  addmeo.  */
845
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
846
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
847
/* addze  addze.  addzeo  addzeo.*/
848
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
849
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
850
/* addi */
851
static void gen_addi(DisasContext *ctx)
852
{
853
    target_long simm = SIMM(ctx->opcode);
854

    
855
    if (rA(ctx->opcode) == 0) {
856
        /* li case */
857
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
858
    } else {
859
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
860
    }
861
}
862
/* addic  addic.*/
863
static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
864
                                int compute_Rc0)
865
{
866
    target_long simm = SIMM(ctx->opcode);
867

    
868
    /* Start with XER CA and OV disabled, the most likely case */
869
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
870

    
871
    if (likely(simm != 0)) {
872
        TCGv t0 = tcg_temp_local_new();
873
        tcg_gen_addi_tl(t0, arg1, simm);
874
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
875
        tcg_gen_mov_tl(ret, t0);
876
        tcg_temp_free(t0);
877
    } else {
878
        tcg_gen_mov_tl(ret, arg1);
879
    }
880
    if (compute_Rc0) {
881
        gen_set_Rc0(ctx, ret);
882
    }
883
}
884

    
885
static void gen_addic(DisasContext *ctx)
886
{
887
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
888
}
889

    
890
static void gen_addic_(DisasContext *ctx)
891
{
892
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
893
}
894

    
895
/* addis */
896
static void gen_addis(DisasContext *ctx)
897
{
898
    target_long simm = SIMM(ctx->opcode);
899

    
900
    if (rA(ctx->opcode) == 0) {
901
        /* lis case */
902
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
903
    } else {
904
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
905
    }
906
}
907

    
908
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
909
                                     TCGv arg2, int sign, int compute_ov)
910
{
911
    int l1 = gen_new_label();
912
    int l2 = gen_new_label();
913
    TCGv_i32 t0 = tcg_temp_local_new_i32();
914
    TCGv_i32 t1 = tcg_temp_local_new_i32();
915

    
916
    tcg_gen_trunc_tl_i32(t0, arg1);
917
    tcg_gen_trunc_tl_i32(t1, arg2);
918
    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
919
    if (sign) {
920
        int l3 = gen_new_label();
921
        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
922
        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
923
        gen_set_label(l3);
924
        tcg_gen_div_i32(t0, t0, t1);
925
    } else {
926
        tcg_gen_divu_i32(t0, t0, t1);
927
    }
928
    if (compute_ov) {
929
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
930
    }
931
    tcg_gen_br(l2);
932
    gen_set_label(l1);
933
    if (sign) {
934
        tcg_gen_sari_i32(t0, t0, 31);
935
    } else {
936
        tcg_gen_movi_i32(t0, 0);
937
    }
938
    if (compute_ov) {
939
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
940
    }
941
    gen_set_label(l2);
942
    tcg_gen_extu_i32_tl(ret, t0);
943
    tcg_temp_free_i32(t0);
944
    tcg_temp_free_i32(t1);
945
    if (unlikely(Rc(ctx->opcode) != 0))
946
        gen_set_Rc0(ctx, ret);
947
}
948
/* Div functions */
949
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
950
static void glue(gen_, name)(DisasContext *ctx)                                       \
951
{                                                                             \
952
    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
953
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
954
                     sign, compute_ov);                                       \
955
}
956
/* divwu  divwu.  divwuo  divwuo.   */
957
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959
/* divw  divw.  divwo  divwo.   */
960
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962
#if defined(TARGET_PPC64)
963
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964
                                     TCGv arg2, int sign, int compute_ov)
965
{
966
    int l1 = gen_new_label();
967
    int l2 = gen_new_label();
968

    
969
    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970
    if (sign) {
971
        int l3 = gen_new_label();
972
        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973
        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974
        gen_set_label(l3);
975
        tcg_gen_div_i64(ret, arg1, arg2);
976
    } else {
977
        tcg_gen_divu_i64(ret, arg1, arg2);
978
    }
979
    if (compute_ov) {
980
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
981
    }
982
    tcg_gen_br(l2);
983
    gen_set_label(l1);
984
    if (sign) {
985
        tcg_gen_sari_i64(ret, arg1, 63);
986
    } else {
987
        tcg_gen_movi_i64(ret, 0);
988
    }
989
    if (compute_ov) {
990
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
991
    }
992
    gen_set_label(l2);
993
    if (unlikely(Rc(ctx->opcode) != 0))
994
        gen_set_Rc0(ctx, ret);
995
}
996
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
997
static void glue(gen_, name)(DisasContext *ctx)                                       \
998
{                                                                             \
999
    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1000
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1001
                      sign, compute_ov);                                      \
1002
}
1003
/* divwu  divwu.  divwuo  divwuo.   */
1004
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1005
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1006
/* divw  divw.  divwo  divwo.   */
1007
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1008
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1009
#endif
1010

    
1011
/* mulhw  mulhw. */
1012
static void gen_mulhw(DisasContext *ctx)
1013
{
1014
    TCGv_i64 t0, t1;
1015

    
1016
    t0 = tcg_temp_new_i64();
1017
    t1 = tcg_temp_new_i64();
1018
#if defined(TARGET_PPC64)
1019
    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1020
    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1021
    tcg_gen_mul_i64(t0, t0, t1);
1022
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1023
#else
1024
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1025
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1026
    tcg_gen_mul_i64(t0, t0, t1);
1027
    tcg_gen_shri_i64(t0, t0, 32);
1028
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1029
#endif
1030
    tcg_temp_free_i64(t0);
1031
    tcg_temp_free_i64(t1);
1032
    if (unlikely(Rc(ctx->opcode) != 0))
1033
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034
}
1035

    
1036
/* mulhwu  mulhwu.  */
1037
static void gen_mulhwu(DisasContext *ctx)
1038
{
1039
    TCGv_i64 t0, t1;
1040

    
1041
    t0 = tcg_temp_new_i64();
1042
    t1 = tcg_temp_new_i64();
1043
#if defined(TARGET_PPC64)
1044
    tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1045
    tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1046
    tcg_gen_mul_i64(t0, t0, t1);
1047
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1048
#else
1049
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1050
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1051
    tcg_gen_mul_i64(t0, t0, t1);
1052
    tcg_gen_shri_i64(t0, t0, 32);
1053
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1054
#endif
1055
    tcg_temp_free_i64(t0);
1056
    tcg_temp_free_i64(t1);
1057
    if (unlikely(Rc(ctx->opcode) != 0))
1058
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1059
}
1060

    
1061
/* mullw  mullw. */
1062
static void gen_mullw(DisasContext *ctx)
1063
{
1064
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1065
                   cpu_gpr[rB(ctx->opcode)]);
1066
    tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1067
    if (unlikely(Rc(ctx->opcode) != 0))
1068
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1069
}
1070

    
1071
/* mullwo  mullwo. */
1072
static void gen_mullwo(DisasContext *ctx)
1073
{
1074
    int l1;
1075
    TCGv_i64 t0, t1;
1076

    
1077
    t0 = tcg_temp_new_i64();
1078
    t1 = tcg_temp_new_i64();
1079
    l1 = gen_new_label();
1080
    /* Start with XER OV disabled, the most likely case */
1081
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1082
#if defined(TARGET_PPC64)
1083
    tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1084
    tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1085
#else
1086
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1087
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1088
#endif
1089
    tcg_gen_mul_i64(t0, t0, t1);
1090
#if defined(TARGET_PPC64)
1091
    tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1092
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1093
#else
1094
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1095
    tcg_gen_ext32s_i64(t1, t0);
1096
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1097
#endif
1098
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099
    gen_set_label(l1);
1100
    tcg_temp_free_i64(t0);
1101
    tcg_temp_free_i64(t1);
1102
    if (unlikely(Rc(ctx->opcode) != 0))
1103
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1104
}
1105

    
1106
/* mulli */
1107
static void gen_mulli(DisasContext *ctx)
1108
{
1109
    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1110
                    SIMM(ctx->opcode));
1111
}
1112
#if defined(TARGET_PPC64)
1113
#define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
1114
static void glue(gen_, name)(DisasContext *ctx)                                       \
1115
{                                                                             \
1116
    gen_helper_##name (cpu_gpr[rD(ctx->opcode)],                              \
1117
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);   \
1118
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1119
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1120
}
1121
/* mulhd  mulhd. */
1122
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1123
/* mulhdu  mulhdu. */
1124
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1125

    
1126
/* mulld  mulld. */
1127
static void gen_mulld(DisasContext *ctx)
1128
{
1129
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1130
                   cpu_gpr[rB(ctx->opcode)]);
1131
    if (unlikely(Rc(ctx->opcode) != 0))
1132
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1133
}
1134
/* mulldo  mulldo. */
1135
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1136
#endif
1137

    
1138
/* neg neg. nego nego. */
1139
static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1140
                                    int ov_check)
1141
{
1142
    int l1 = gen_new_label();
1143
    int l2 = gen_new_label();
1144
    TCGv t0 = tcg_temp_local_new();
1145
#if defined(TARGET_PPC64)
1146
    if (ctx->sf_mode) {
1147
        tcg_gen_mov_tl(t0, arg1);
1148
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1149
    } else
1150
#endif
1151
    {
1152
        tcg_gen_ext32s_tl(t0, arg1);
1153
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1154
    }
1155
    tcg_gen_neg_tl(ret, arg1);
1156
    if (ov_check) {
1157
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1158
    }
1159
    tcg_gen_br(l2);
1160
    gen_set_label(l1);
1161
    tcg_gen_mov_tl(ret, t0);
1162
    if (ov_check) {
1163
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1164
    }
1165
    gen_set_label(l2);
1166
    tcg_temp_free(t0);
1167
    if (unlikely(Rc(ctx->opcode) != 0))
1168
        gen_set_Rc0(ctx, ret);
1169
}
1170

    
1171
static void gen_neg(DisasContext *ctx)
1172
{
1173
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1174
}
1175

    
1176
static void gen_nego(DisasContext *ctx)
1177
{
1178
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1179
}
1180

    
1181
/* Common subf function */
1182
static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1183
                                     TCGv arg2, int add_ca, int compute_ca,
1184
                                     int compute_ov)
1185
{
1186
    TCGv t0, t1;
1187

    
1188
    if ((!compute_ca && !compute_ov) ||
1189
        (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2)))  {
1190
        t0 = ret;
1191
    } else {
1192
        t0 = tcg_temp_local_new();
1193
    }
1194

    
1195
    if (add_ca) {
1196
        t1 = tcg_temp_local_new();
1197
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1198
        tcg_gen_shri_tl(t1, t1, XER_CA);
1199
    } else {
1200
        TCGV_UNUSED(t1);
1201
    }
1202

    
1203
    if (compute_ca && compute_ov) {
1204
        /* Start with XER CA and OV disabled, the most likely case */
1205
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1206
    } else if (compute_ca) {
1207
        /* Start with XER CA disabled, the most likely case */
1208
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1209
    } else if (compute_ov) {
1210
        /* Start with XER OV disabled, the most likely case */
1211
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1212
    }
1213

    
1214
    if (add_ca) {
1215
        tcg_gen_not_tl(t0, arg1);
1216
        tcg_gen_add_tl(t0, t0, arg2);
1217
        gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1218
        tcg_gen_add_tl(t0, t0, t1);
1219
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
1220
        tcg_temp_free(t1);
1221
    } else {
1222
        tcg_gen_sub_tl(t0, arg2, arg1);
1223
        if (compute_ca) {
1224
            gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1225
        }
1226
    }
1227
    if (compute_ov) {
1228
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1229
    }
1230

    
1231
    if (unlikely(Rc(ctx->opcode) != 0))
1232
        gen_set_Rc0(ctx, t0);
1233

    
1234
    if (!TCGV_EQUAL(t0, ret)) {
1235
        tcg_gen_mov_tl(ret, t0);
1236
        tcg_temp_free(t0);
1237
    }
1238
}
1239
/* Sub functions with Two operands functions */
1240
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1241
static void glue(gen_, name)(DisasContext *ctx)                                       \
1242
{                                                                             \
1243
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1244
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1245
                      add_ca, compute_ca, compute_ov);                        \
1246
}
1247
/* Sub functions with one operand and one immediate */
1248
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1249
                                add_ca, compute_ca, compute_ov)               \
1250
static void glue(gen_, name)(DisasContext *ctx)                                       \
1251
{                                                                             \
1252
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
1253
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1254
                      cpu_gpr[rA(ctx->opcode)], t0,                           \
1255
                      add_ca, compute_ca, compute_ov);                        \
1256
    tcg_temp_free(t0);                                                        \
1257
}
1258
/* subf  subf.  subfo  subfo. */
1259
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1260
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1261
/* subfc  subfc.  subfco  subfco. */
1262
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1263
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1264
/* subfe  subfe.  subfeo  subfo. */
1265
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1266
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1267
/* subfme  subfme.  subfmeo  subfmeo.  */
1268
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1269
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1270
/* subfze  subfze.  subfzeo  subfzeo.*/
1271
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1272
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1273

    
1274
/* subfic */
1275
static void gen_subfic(DisasContext *ctx)
1276
{
1277
    /* Start with XER CA and OV disabled, the most likely case */
1278
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1279
    TCGv t0 = tcg_temp_local_new();
1280
    TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1281
    tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1282
    gen_op_arith_compute_ca(ctx, t0, t1, 1);
1283
    tcg_temp_free(t1);
1284
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1285
    tcg_temp_free(t0);
1286
}
1287

    
1288
/***                            Integer logical                            ***/
1289
#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1290
static void glue(gen_, name)(DisasContext *ctx)                                       \
1291
{                                                                             \
1292
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1293
       cpu_gpr[rB(ctx->opcode)]);                                             \
1294
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1295
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1296
}
1297

    
1298
#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1299
static void glue(gen_, name)(DisasContext *ctx)                                       \
1300
{                                                                             \
1301
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1302
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1303
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1304
}
1305

    
1306
/* and & and. */
1307
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1308
/* andc & andc. */
1309
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1310

    
1311
/* andi. */
1312
static void gen_andi_(DisasContext *ctx)
1313
{
1314
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1315
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1316
}
1317

    
1318
/* andis. */
1319
static void gen_andis_(DisasContext *ctx)
1320
{
1321
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1322
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1323
}
1324

    
1325
/* cntlzw */
1326
static void gen_cntlzw(DisasContext *ctx)
1327
{
1328
    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1329
    if (unlikely(Rc(ctx->opcode) != 0))
1330
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1331
}
1332
/* eqv & eqv. */
1333
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1334
/* extsb & extsb. */
1335
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1336
/* extsh & extsh. */
1337
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1338
/* nand & nand. */
1339
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1340
/* nor & nor. */
1341
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1342

    
1343
/* or & or. */
1344
static void gen_or(DisasContext *ctx)
1345
{
1346
    int rs, ra, rb;
1347

    
1348
    rs = rS(ctx->opcode);
1349
    ra = rA(ctx->opcode);
1350
    rb = rB(ctx->opcode);
1351
    /* Optimisation for mr. ri case */
1352
    if (rs != ra || rs != rb) {
1353
        if (rs != rb)
1354
            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1355
        else
1356
            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1357
        if (unlikely(Rc(ctx->opcode) != 0))
1358
            gen_set_Rc0(ctx, cpu_gpr[ra]);
1359
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1360
        gen_set_Rc0(ctx, cpu_gpr[rs]);
1361
#if defined(TARGET_PPC64)
1362
    } else {
1363
        int prio = 0;
1364

    
1365
        switch (rs) {
1366
        case 1:
1367
            /* Set process priority to low */
1368
            prio = 2;
1369
            break;
1370
        case 6:
1371
            /* Set process priority to medium-low */
1372
            prio = 3;
1373
            break;
1374
        case 2:
1375
            /* Set process priority to normal */
1376
            prio = 4;
1377
            break;
1378
#if !defined(CONFIG_USER_ONLY)
1379
        case 31:
1380
            if (ctx->mem_idx > 0) {
1381
                /* Set process priority to very low */
1382
                prio = 1;
1383
            }
1384
            break;
1385
        case 5:
1386
            if (ctx->mem_idx > 0) {
1387
                /* Set process priority to medium-hight */
1388
                prio = 5;
1389
            }
1390
            break;
1391
        case 3:
1392
            if (ctx->mem_idx > 0) {
1393
                /* Set process priority to high */
1394
                prio = 6;
1395
            }
1396
            break;
1397
        case 7:
1398
            if (ctx->mem_idx > 1) {
1399
                /* Set process priority to very high */
1400
                prio = 7;
1401
            }
1402
            break;
1403
#endif
1404
        default:
1405
            /* nop */
1406
            break;
1407
        }
1408
        if (prio) {
1409
            TCGv t0 = tcg_temp_new();
1410
            gen_load_spr(t0, SPR_PPR);
1411
            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1412
            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1413
            gen_store_spr(SPR_PPR, t0);
1414
            tcg_temp_free(t0);
1415
        }
1416
#endif
1417
    }
1418
}
1419
/* orc & orc. */
1420
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1421

    
1422
/* xor & xor. */
1423
static void gen_xor(DisasContext *ctx)
1424
{
1425
    /* Optimisation for "set to zero" case */
1426
    if (rS(ctx->opcode) != rB(ctx->opcode))
1427
        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1428
    else
1429
        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1430
    if (unlikely(Rc(ctx->opcode) != 0))
1431
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1432
}
1433

    
1434
/* ori */
1435
static void gen_ori(DisasContext *ctx)
1436
{
1437
    target_ulong uimm = UIMM(ctx->opcode);
1438

    
1439
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1440
        /* NOP */
1441
        /* XXX: should handle special NOPs for POWER series */
1442
        return;
1443
    }
1444
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1445
}
1446

    
1447
/* oris */
1448
static void gen_oris(DisasContext *ctx)
1449
{
1450
    target_ulong uimm = UIMM(ctx->opcode);
1451

    
1452
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1453
        /* NOP */
1454
        return;
1455
    }
1456
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1457
}
1458

    
1459
/* xori */
1460
static void gen_xori(DisasContext *ctx)
1461
{
1462
    target_ulong uimm = UIMM(ctx->opcode);
1463

    
1464
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1465
        /* NOP */
1466
        return;
1467
    }
1468
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1469
}
1470

    
1471
/* xoris */
1472
static void gen_xoris(DisasContext *ctx)
1473
{
1474
    target_ulong uimm = UIMM(ctx->opcode);
1475

    
1476
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1477
        /* NOP */
1478
        return;
1479
    }
1480
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1481
}
1482

    
1483
/* popcntb : PowerPC 2.03 specification */
1484
static void gen_popcntb(DisasContext *ctx)
1485
{
1486
    gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1487
}
1488

    
1489
static void gen_popcntw(DisasContext *ctx)
1490
{
1491
    gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1492
}
1493

    
1494
#if defined(TARGET_PPC64)
1495
/* popcntd: PowerPC 2.06 specification */
1496
static void gen_popcntd(DisasContext *ctx)
1497
{
1498
    gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1499
}
1500
#endif
1501

    
1502
#if defined(TARGET_PPC64)
1503
/* extsw & extsw. */
1504
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1505

    
1506
/* cntlzd */
1507
static void gen_cntlzd(DisasContext *ctx)
1508
{
1509
    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1510
    if (unlikely(Rc(ctx->opcode) != 0))
1511
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1512
}
1513
#endif
1514

    
1515
/***                             Integer rotate                            ***/
1516

    
1517
/* rlwimi & rlwimi. */
1518
static void gen_rlwimi(DisasContext *ctx)
1519
{
1520
    uint32_t mb, me, sh;
1521

    
1522
    mb = MB(ctx->opcode);
1523
    me = ME(ctx->opcode);
1524
    sh = SH(ctx->opcode);
1525
    if (likely(sh == 0 && mb == 0 && me == 31)) {
1526
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1527
    } else {
1528
        target_ulong mask;
1529
        TCGv t1;
1530
        TCGv t0 = tcg_temp_new();
1531
#if defined(TARGET_PPC64)
1532
        TCGv_i32 t2 = tcg_temp_new_i32();
1533
        tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1534
        tcg_gen_rotli_i32(t2, t2, sh);
1535
        tcg_gen_extu_i32_i64(t0, t2);
1536
        tcg_temp_free_i32(t2);
1537
#else
1538
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1539
#endif
1540
#if defined(TARGET_PPC64)
1541
        mb += 32;
1542
        me += 32;
1543
#endif
1544
        mask = MASK(mb, me);
1545
        t1 = tcg_temp_new();
1546
        tcg_gen_andi_tl(t0, t0, mask);
1547
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1548
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1549
        tcg_temp_free(t0);
1550
        tcg_temp_free(t1);
1551
    }
1552
    if (unlikely(Rc(ctx->opcode) != 0))
1553
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1554
}
1555

    
1556
/* rlwinm & rlwinm. */
1557
static void gen_rlwinm(DisasContext *ctx)
1558
{
1559
    uint32_t mb, me, sh;
1560

    
1561
    sh = SH(ctx->opcode);
1562
    mb = MB(ctx->opcode);
1563
    me = ME(ctx->opcode);
1564

    
1565
    if (likely(mb == 0 && me == (31 - sh))) {
1566
        if (likely(sh == 0)) {
1567
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568
        } else {
1569
            TCGv t0 = tcg_temp_new();
1570
            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1571
            tcg_gen_shli_tl(t0, t0, sh);
1572
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1573
            tcg_temp_free(t0);
1574
        }
1575
    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1576
        TCGv t0 = tcg_temp_new();
1577
        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1578
        tcg_gen_shri_tl(t0, t0, mb);
1579
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580
        tcg_temp_free(t0);
1581
    } else {
1582
        TCGv t0 = tcg_temp_new();
1583
#if defined(TARGET_PPC64)
1584
        TCGv_i32 t1 = tcg_temp_new_i32();
1585
        tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1586
        tcg_gen_rotli_i32(t1, t1, sh);
1587
        tcg_gen_extu_i32_i64(t0, t1);
1588
        tcg_temp_free_i32(t1);
1589
#else
1590
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1591
#endif
1592
#if defined(TARGET_PPC64)
1593
        mb += 32;
1594
        me += 32;
1595
#endif
1596
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1597
        tcg_temp_free(t0);
1598
    }
1599
    if (unlikely(Rc(ctx->opcode) != 0))
1600
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601
}
1602

    
1603
/* rlwnm & rlwnm. */
1604
static void gen_rlwnm(DisasContext *ctx)
1605
{
1606
    uint32_t mb, me;
1607
    TCGv t0;
1608
#if defined(TARGET_PPC64)
1609
    TCGv_i32 t1, t2;
1610
#endif
1611

    
1612
    mb = MB(ctx->opcode);
1613
    me = ME(ctx->opcode);
1614
    t0 = tcg_temp_new();
1615
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1616
#if defined(TARGET_PPC64)
1617
    t1 = tcg_temp_new_i32();
1618
    t2 = tcg_temp_new_i32();
1619
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1620
    tcg_gen_trunc_i64_i32(t2, t0);
1621
    tcg_gen_rotl_i32(t1, t1, t2);
1622
    tcg_gen_extu_i32_i64(t0, t1);
1623
    tcg_temp_free_i32(t1);
1624
    tcg_temp_free_i32(t2);
1625
#else
1626
    tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1627
#endif
1628
    if (unlikely(mb != 0 || me != 31)) {
1629
#if defined(TARGET_PPC64)
1630
        mb += 32;
1631
        me += 32;
1632
#endif
1633
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1634
    } else {
1635
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636
    }
1637
    tcg_temp_free(t0);
1638
    if (unlikely(Rc(ctx->opcode) != 0))
1639
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640
}
1641

    
1642
#if defined(TARGET_PPC64)
1643
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1644
static void glue(gen_, name##0)(DisasContext *ctx)                            \
1645
{                                                                             \
1646
    gen_##name(ctx, 0);                                                       \
1647
}                                                                             \
1648
                                                                              \
1649
static void glue(gen_, name##1)(DisasContext *ctx)                            \
1650
{                                                                             \
1651
    gen_##name(ctx, 1);                                                       \
1652
}
1653
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1654
static void glue(gen_, name##0)(DisasContext *ctx)                            \
1655
{                                                                             \
1656
    gen_##name(ctx, 0, 0);                                                    \
1657
}                                                                             \
1658
                                                                              \
1659
static void glue(gen_, name##1)(DisasContext *ctx)                            \
1660
{                                                                             \
1661
    gen_##name(ctx, 0, 1);                                                    \
1662
}                                                                             \
1663
                                                                              \
1664
static void glue(gen_, name##2)(DisasContext *ctx)                            \
1665
{                                                                             \
1666
    gen_##name(ctx, 1, 0);                                                    \
1667
}                                                                             \
1668
                                                                              \
1669
static void glue(gen_, name##3)(DisasContext *ctx)                            \
1670
{                                                                             \
1671
    gen_##name(ctx, 1, 1);                                                    \
1672
}
1673

    
1674
static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1675
                              uint32_t sh)
1676
{
1677
    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1678
        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1679
    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1680
        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1681
    } else {
1682
        TCGv t0 = tcg_temp_new();
1683
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1684
        if (likely(mb == 0 && me == 63)) {
1685
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686
        } else {
1687
            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688
        }
1689
        tcg_temp_free(t0);
1690
    }
1691
    if (unlikely(Rc(ctx->opcode) != 0))
1692
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1693
}
1694
/* rldicl - rldicl. */
1695
static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1696
{
1697
    uint32_t sh, mb;
1698

    
1699
    sh = SH(ctx->opcode) | (shn << 5);
1700
    mb = MB(ctx->opcode) | (mbn << 5);
1701
    gen_rldinm(ctx, mb, 63, sh);
1702
}
1703
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1704
/* rldicr - rldicr. */
1705
static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1706
{
1707
    uint32_t sh, me;
1708

    
1709
    sh = SH(ctx->opcode) | (shn << 5);
1710
    me = MB(ctx->opcode) | (men << 5);
1711
    gen_rldinm(ctx, 0, me, sh);
1712
}
1713
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1714
/* rldic - rldic. */
1715
static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1716
{
1717
    uint32_t sh, mb;
1718

    
1719
    sh = SH(ctx->opcode) | (shn << 5);
1720
    mb = MB(ctx->opcode) | (mbn << 5);
1721
    gen_rldinm(ctx, mb, 63 - sh, sh);
1722
}
1723
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1724

    
1725
static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1726
{
1727
    TCGv t0;
1728

    
1729
    mb = MB(ctx->opcode);
1730
    me = ME(ctx->opcode);
1731
    t0 = tcg_temp_new();
1732
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1733
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1734
    if (unlikely(mb != 0 || me != 63)) {
1735
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1736
    } else {
1737
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1738
    }
1739
    tcg_temp_free(t0);
1740
    if (unlikely(Rc(ctx->opcode) != 0))
1741
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1742
}
1743

    
1744
/* rldcl - rldcl. */
1745
static inline void gen_rldcl(DisasContext *ctx, int mbn)
1746
{
1747
    uint32_t mb;
1748

    
1749
    mb = MB(ctx->opcode) | (mbn << 5);
1750
    gen_rldnm(ctx, mb, 63);
1751
}
1752
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1753
/* rldcr - rldcr. */
1754
static inline void gen_rldcr(DisasContext *ctx, int men)
1755
{
1756
    uint32_t me;
1757

    
1758
    me = MB(ctx->opcode) | (men << 5);
1759
    gen_rldnm(ctx, 0, me);
1760
}
1761
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1762
/* rldimi - rldimi. */
1763
static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1764
{
1765
    uint32_t sh, mb, me;
1766

    
1767
    sh = SH(ctx->opcode) | (shn << 5);
1768
    mb = MB(ctx->opcode) | (mbn << 5);
1769
    me = 63 - sh;
1770
    if (unlikely(sh == 0 && mb == 0)) {
1771
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1772
    } else {
1773
        TCGv t0, t1;
1774
        target_ulong mask;
1775

    
1776
        t0 = tcg_temp_new();
1777
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778
        t1 = tcg_temp_new();
1779
        mask = MASK(mb, me);
1780
        tcg_gen_andi_tl(t0, t0, mask);
1781
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1782
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1783
        tcg_temp_free(t0);
1784
        tcg_temp_free(t1);
1785
    }
1786
    if (unlikely(Rc(ctx->opcode) != 0))
1787
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1788
}
1789
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1790
#endif
1791

    
1792
/***                             Integer shift                             ***/
1793

    
1794
/* slw & slw. */
1795
static void gen_slw(DisasContext *ctx)
1796
{
1797
    TCGv t0, t1;
1798

    
1799
    t0 = tcg_temp_new();
1800
    /* AND rS with a mask that is 0 when rB >= 0x20 */
1801
#if defined(TARGET_PPC64)
1802
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1803
    tcg_gen_sari_tl(t0, t0, 0x3f);
1804
#else
1805
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1806
    tcg_gen_sari_tl(t0, t0, 0x1f);
1807
#endif
1808
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1809
    t1 = tcg_temp_new();
1810
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1811
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1812
    tcg_temp_free(t1);
1813
    tcg_temp_free(t0);
1814
    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1815
    if (unlikely(Rc(ctx->opcode) != 0))
1816
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1817
}
1818

    
1819
/* sraw & sraw. */
1820
static void gen_sraw(DisasContext *ctx)
1821
{
1822
    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1823
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1824
    if (unlikely(Rc(ctx->opcode) != 0))
1825
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1826
}
1827

    
1828
/* srawi & srawi. */
1829
static void gen_srawi(DisasContext *ctx)
1830
{
1831
    int sh = SH(ctx->opcode);
1832
    if (sh != 0) {
1833
        int l1, l2;
1834
        TCGv t0;
1835
        l1 = gen_new_label();
1836
        l2 = gen_new_label();
1837
        t0 = tcg_temp_local_new();
1838
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1839
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1840
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1841
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1842
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1843
        tcg_gen_br(l2);
1844
        gen_set_label(l1);
1845
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1846
        gen_set_label(l2);
1847
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1848
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1849
        tcg_temp_free(t0);
1850
    } else {
1851
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1852
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1853
    }
1854
    if (unlikely(Rc(ctx->opcode) != 0))
1855
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1856
}
1857

    
1858
/* srw & srw. */
1859
static void gen_srw(DisasContext *ctx)
1860
{
1861
    TCGv t0, t1;
1862

    
1863
    t0 = tcg_temp_new();
1864
    /* AND rS with a mask that is 0 when rB >= 0x20 */
1865
#if defined(TARGET_PPC64)
1866
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1867
    tcg_gen_sari_tl(t0, t0, 0x3f);
1868
#else
1869
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1870
    tcg_gen_sari_tl(t0, t0, 0x1f);
1871
#endif
1872
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1873
    tcg_gen_ext32u_tl(t0, t0);
1874
    t1 = tcg_temp_new();
1875
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1876
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1877
    tcg_temp_free(t1);
1878
    tcg_temp_free(t0);
1879
    if (unlikely(Rc(ctx->opcode) != 0))
1880
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1881
}
1882

    
1883
#if defined(TARGET_PPC64)
1884
/* sld & sld. */
1885
static void gen_sld(DisasContext *ctx)
1886
{
1887
    TCGv t0, t1;
1888

    
1889
    t0 = tcg_temp_new();
1890
    /* AND rS with a mask that is 0 when rB >= 0x40 */
1891
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1892
    tcg_gen_sari_tl(t0, t0, 0x3f);
1893
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1894
    t1 = tcg_temp_new();
1895
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1896
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1897
    tcg_temp_free(t1);
1898
    tcg_temp_free(t0);
1899
    if (unlikely(Rc(ctx->opcode) != 0))
1900
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901
}
1902

    
1903
/* srad & srad. */
1904
static void gen_srad(DisasContext *ctx)
1905
{
1906
    gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1907
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1908
    if (unlikely(Rc(ctx->opcode) != 0))
1909
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1910
}
1911
/* sradi & sradi. */
1912
static inline void gen_sradi(DisasContext *ctx, int n)
1913
{
1914
    int sh = SH(ctx->opcode) + (n << 5);
1915
    if (sh != 0) {
1916
        int l1, l2;
1917
        TCGv t0;
1918
        l1 = gen_new_label();
1919
        l2 = gen_new_label();
1920
        t0 = tcg_temp_local_new();
1921
        tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1922
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1923
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1924
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1925
        tcg_gen_br(l2);
1926
        gen_set_label(l1);
1927
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1928
        gen_set_label(l2);
1929
        tcg_temp_free(t0);
1930
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1931
    } else {
1932
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1933
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1934
    }
1935
    if (unlikely(Rc(ctx->opcode) != 0))
1936
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1937
}
1938

    
1939
static void gen_sradi0(DisasContext *ctx)
1940
{
1941
    gen_sradi(ctx, 0);
1942
}
1943

    
1944
static void gen_sradi1(DisasContext *ctx)
1945
{
1946
    gen_sradi(ctx, 1);
1947
}
1948

    
1949
/* srd & srd. */
1950
static void gen_srd(DisasContext *ctx)
1951
{
1952
    TCGv t0, t1;
1953

    
1954
    t0 = tcg_temp_new();
1955
    /* AND rS with a mask that is 0 when rB >= 0x40 */
1956
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1957
    tcg_gen_sari_tl(t0, t0, 0x3f);
1958
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959
    t1 = tcg_temp_new();
1960
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1961
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1962
    tcg_temp_free(t1);
1963
    tcg_temp_free(t0);
1964
    if (unlikely(Rc(ctx->opcode) != 0))
1965
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966
}
1967
#endif
1968

    
1969
/***                       Floating-Point arithmetic                       ***/
1970
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1971
static void gen_f##name(DisasContext *ctx)                                    \
1972
{                                                                             \
1973
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1974
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
1975
        return;                                                               \
1976
    }                                                                         \
1977
    /* NIP cannot be restored if the memory exception comes from an helper */ \
1978
    gen_update_nip(ctx, ctx->nip - 4);                                        \
1979
    gen_reset_fpstatus();                                                     \
1980
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
1981
                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
1982
    if (isfloat) {                                                            \
1983
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
1984
    }                                                                         \
1985
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf,                      \
1986
                     Rc(ctx->opcode) != 0);                                   \
1987
}
1988

    
1989
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1990
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1991
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1992

    
1993
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1994
static void gen_f##name(DisasContext *ctx)                                    \
1995
{                                                                             \
1996
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1997
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
1998
        return;                                                               \
1999
    }                                                                         \
2000
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2001
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2002
    gen_reset_fpstatus();                                                     \
2003
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2004
                     cpu_fpr[rB(ctx->opcode)]);                               \
2005
    if (isfloat) {                                                            \
2006
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2007
    }                                                                         \
2008
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2009
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2010
}
2011
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
2012
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2013
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2014

    
2015
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2016
static void gen_f##name(DisasContext *ctx)                                    \
2017
{                                                                             \
2018
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2019
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2020
        return;                                                               \
2021
    }                                                                         \
2022
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2023
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2024
    gen_reset_fpstatus();                                                     \
2025
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2026
                       cpu_fpr[rC(ctx->opcode)]);                             \
2027
    if (isfloat) {                                                            \
2028
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2029
    }                                                                         \
2030
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2031
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2032
}
2033
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
2034
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2035
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2036

    
2037
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2038
static void gen_f##name(DisasContext *ctx)                                    \
2039
{                                                                             \
2040
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2041
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2042
        return;                                                               \
2043
    }                                                                         \
2044
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2045
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2046
    gen_reset_fpstatus();                                                     \
2047
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2048
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2049
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2050
}
2051

    
2052
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2053
static void gen_f##name(DisasContext *ctx)                                    \
2054
{                                                                             \
2055
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2056
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2057
        return;                                                               \
2058
    }                                                                         \
2059
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2060
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2061
    gen_reset_fpstatus();                                                     \
2062
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2063
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2064
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2065
}
2066

    
2067
/* fadd - fadds */
2068
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2069
/* fdiv - fdivs */
2070
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2071
/* fmul - fmuls */
2072
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2073

    
2074
/* fre */
2075
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2076

    
2077
/* fres */
2078
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2079

    
2080
/* frsqrte */
2081
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2082

    
2083
/* frsqrtes */
2084
static void gen_frsqrtes(DisasContext *ctx)
2085
{
2086
    if (unlikely(!ctx->fpu_enabled)) {
2087
        gen_exception(ctx, POWERPC_EXCP_FPU);
2088
        return;
2089
    }
2090
    /* NIP cannot be restored if the memory exception comes from an helper */
2091
    gen_update_nip(ctx, ctx->nip - 4);
2092
    gen_reset_fpstatus();
2093
    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2094
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2095
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2096
}
2097

    
2098
/* fsel */
2099
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2100
/* fsub - fsubs */
2101
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2102
/* Optional: */
2103

    
2104
/* fsqrt */
2105
static void gen_fsqrt(DisasContext *ctx)
2106
{
2107
    if (unlikely(!ctx->fpu_enabled)) {
2108
        gen_exception(ctx, POWERPC_EXCP_FPU);
2109
        return;
2110
    }
2111
    /* NIP cannot be restored if the memory exception comes from an helper */
2112
    gen_update_nip(ctx, ctx->nip - 4);
2113
    gen_reset_fpstatus();
2114
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2115
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2116
}
2117

    
2118
static void gen_fsqrts(DisasContext *ctx)
2119
{
2120
    if (unlikely(!ctx->fpu_enabled)) {
2121
        gen_exception(ctx, POWERPC_EXCP_FPU);
2122
        return;
2123
    }
2124
    /* NIP cannot be restored if the memory exception comes from an helper */
2125
    gen_update_nip(ctx, ctx->nip - 4);
2126
    gen_reset_fpstatus();
2127
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2128
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2129
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2130
}
2131

    
2132
/***                     Floating-Point multiply-and-add                   ***/
2133
/* fmadd - fmadds */
2134
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2135
/* fmsub - fmsubs */
2136
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2137
/* fnmadd - fnmadds */
2138
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2139
/* fnmsub - fnmsubs */
2140
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2141

    
2142
/***                     Floating-Point round & convert                    ***/
2143
/* fctiw */
2144
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2145
/* fctiwz */
2146
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2147
/* frsp */
2148
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2149
#if defined(TARGET_PPC64)
2150
/* fcfid */
2151
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2152
/* fctid */
2153
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2154
/* fctidz */
2155
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2156
#endif
2157

    
2158
/* frin */
2159
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2160
/* friz */
2161
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2162
/* frip */
2163
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2164
/* frim */
2165
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2166

    
2167
/***                         Floating-Point compare                        ***/
2168

    
2169
/* fcmpo */
2170
static void gen_fcmpo(DisasContext *ctx)
2171
{
2172
    TCGv_i32 crf;
2173
    if (unlikely(!ctx->fpu_enabled)) {
2174
        gen_exception(ctx, POWERPC_EXCP_FPU);
2175
        return;
2176
    }
2177
    /* NIP cannot be restored if the memory exception comes from an helper */
2178
    gen_update_nip(ctx, ctx->nip - 4);
2179
    gen_reset_fpstatus();
2180
    crf = tcg_const_i32(crfD(ctx->opcode));
2181
    gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2182
    tcg_temp_free_i32(crf);
2183
    gen_helper_float_check_status();
2184
}
2185

    
2186
/* fcmpu */
2187
static void gen_fcmpu(DisasContext *ctx)
2188
{
2189
    TCGv_i32 crf;
2190
    if (unlikely(!ctx->fpu_enabled)) {
2191
        gen_exception(ctx, POWERPC_EXCP_FPU);
2192
        return;
2193
    }
2194
    /* NIP cannot be restored if the memory exception comes from an helper */
2195
    gen_update_nip(ctx, ctx->nip - 4);
2196
    gen_reset_fpstatus();
2197
    crf = tcg_const_i32(crfD(ctx->opcode));
2198
    gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2199
    tcg_temp_free_i32(crf);
2200
    gen_helper_float_check_status();
2201
}
2202

    
2203
/***                         Floating-point move                           ***/
2204
/* fabs */
2205
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2206
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2207

    
2208
/* fmr  - fmr. */
2209
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2210
static void gen_fmr(DisasContext *ctx)
2211
{
2212
    if (unlikely(!ctx->fpu_enabled)) {
2213
        gen_exception(ctx, POWERPC_EXCP_FPU);
2214
        return;
2215
    }
2216
    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2217
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2218
}
2219

    
2220
/* fnabs */
2221
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2222
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2223
/* fneg */
2224
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2225
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2226

    
2227
/***                  Floating-Point status & ctrl register                ***/
2228

    
2229
/* mcrfs */
2230
static void gen_mcrfs(DisasContext *ctx)
2231
{
2232
    int bfa;
2233

    
2234
    if (unlikely(!ctx->fpu_enabled)) {
2235
        gen_exception(ctx, POWERPC_EXCP_FPU);
2236
        return;
2237
    }
2238
    bfa = 4 * (7 - crfS(ctx->opcode));
2239
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2240
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2241
    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2242
}
2243

    
2244
/* mffs */
2245
static void gen_mffs(DisasContext *ctx)
2246
{
2247
    if (unlikely(!ctx->fpu_enabled)) {
2248
        gen_exception(ctx, POWERPC_EXCP_FPU);
2249
        return;
2250
    }
2251
    gen_reset_fpstatus();
2252
    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2253
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2254
}
2255

    
2256
/* mtfsb0 */
2257
static void gen_mtfsb0(DisasContext *ctx)
2258
{
2259
    uint8_t crb;
2260

    
2261
    if (unlikely(!ctx->fpu_enabled)) {
2262
        gen_exception(ctx, POWERPC_EXCP_FPU);
2263
        return;
2264
    }
2265
    crb = 31 - crbD(ctx->opcode);
2266
    gen_reset_fpstatus();
2267
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2268
        TCGv_i32 t0;
2269
        /* NIP cannot be restored if the memory exception comes from an helper */
2270
        gen_update_nip(ctx, ctx->nip - 4);
2271
        t0 = tcg_const_i32(crb);
2272
        gen_helper_fpscr_clrbit(t0);
2273
        tcg_temp_free_i32(t0);
2274
    }
2275
    if (unlikely(Rc(ctx->opcode) != 0)) {
2276
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2277
    }
2278
}
2279

    
2280
/* mtfsb1 */
2281
static void gen_mtfsb1(DisasContext *ctx)
2282
{
2283
    uint8_t crb;
2284

    
2285
    if (unlikely(!ctx->fpu_enabled)) {
2286
        gen_exception(ctx, POWERPC_EXCP_FPU);
2287
        return;
2288
    }
2289
    crb = 31 - crbD(ctx->opcode);
2290
    gen_reset_fpstatus();
2291
    /* XXX: we pretend we can only do IEEE floating-point computations */
2292
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2293
        TCGv_i32 t0;
2294
        /* NIP cannot be restored if the memory exception comes from an helper */
2295
        gen_update_nip(ctx, ctx->nip - 4);
2296
        t0 = tcg_const_i32(crb);
2297
        gen_helper_fpscr_setbit(t0);
2298
        tcg_temp_free_i32(t0);
2299
    }
2300
    if (unlikely(Rc(ctx->opcode) != 0)) {
2301
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2302
    }
2303
    /* We can raise a differed exception */
2304
    gen_helper_float_check_status();
2305
}
2306

    
2307
/* mtfsf */
2308
static void gen_mtfsf(DisasContext *ctx)
2309
{
2310
    TCGv_i32 t0;
2311
    int L = ctx->opcode & 0x02000000;
2312

    
2313
    if (unlikely(!ctx->fpu_enabled)) {
2314
        gen_exception(ctx, POWERPC_EXCP_FPU);
2315
        return;
2316
    }
2317
    /* NIP cannot be restored if the memory exception comes from an helper */
2318
    gen_update_nip(ctx, ctx->nip - 4);
2319
    gen_reset_fpstatus();
2320
    if (L)
2321
        t0 = tcg_const_i32(0xff);
2322
    else
2323
        t0 = tcg_const_i32(FM(ctx->opcode));
2324
    gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2325
    tcg_temp_free_i32(t0);
2326
    if (unlikely(Rc(ctx->opcode) != 0)) {
2327
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2328
    }
2329
    /* We can raise a differed exception */
2330
    gen_helper_float_check_status();
2331
}
2332

    
2333
/* mtfsfi */
2334
static void gen_mtfsfi(DisasContext *ctx)
2335
{
2336
    int bf, sh;
2337
    TCGv_i64 t0;
2338
    TCGv_i32 t1;
2339

    
2340
    if (unlikely(!ctx->fpu_enabled)) {
2341
        gen_exception(ctx, POWERPC_EXCP_FPU);
2342
        return;
2343
    }
2344
    bf = crbD(ctx->opcode) >> 2;
2345
    sh = 7 - bf;
2346
    /* NIP cannot be restored if the memory exception comes from an helper */
2347
    gen_update_nip(ctx, ctx->nip - 4);
2348
    gen_reset_fpstatus();
2349
    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2350
    t1 = tcg_const_i32(1 << sh);
2351
    gen_helper_store_fpscr(t0, t1);
2352
    tcg_temp_free_i64(t0);
2353
    tcg_temp_free_i32(t1);
2354
    if (unlikely(Rc(ctx->opcode) != 0)) {
2355
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2356
    }
2357
    /* We can raise a differed exception */
2358
    gen_helper_float_check_status();
2359
}
2360

    
2361
/***                           Addressing modes                            ***/
2362
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2363
static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2364
                                      target_long maskl)
2365
{
2366
    target_long simm = SIMM(ctx->opcode);
2367

    
2368
    simm &= ~maskl;
2369
    if (rA(ctx->opcode) == 0) {
2370
#if defined(TARGET_PPC64)
2371
        if (!ctx->sf_mode) {
2372
            tcg_gen_movi_tl(EA, (uint32_t)simm);
2373
        } else
2374
#endif
2375
        tcg_gen_movi_tl(EA, simm);
2376
    } else if (likely(simm != 0)) {
2377
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2378
#if defined(TARGET_PPC64)
2379
        if (!ctx->sf_mode) {
2380
            tcg_gen_ext32u_tl(EA, EA);
2381
        }
2382
#endif
2383
    } else {
2384
#if defined(TARGET_PPC64)
2385
        if (!ctx->sf_mode) {
2386
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2387
        } else
2388
#endif
2389
        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2390
    }
2391
}
2392

    
2393
static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2394
{
2395
    if (rA(ctx->opcode) == 0) {
2396
#if defined(TARGET_PPC64)
2397
        if (!ctx->sf_mode) {
2398
            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2399
        } else
2400
#endif
2401
        tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2402
    } else {
2403
        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2404
#if defined(TARGET_PPC64)
2405
        if (!ctx->sf_mode) {
2406
            tcg_gen_ext32u_tl(EA, EA);
2407
        }
2408
#endif
2409
    }
2410
}
2411

    
2412
static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2413
{
2414
    if (rA(ctx->opcode) == 0) {
2415
        tcg_gen_movi_tl(EA, 0);
2416
    } else {
2417
#if defined(TARGET_PPC64)
2418
        if (!ctx->sf_mode) {
2419
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2420
        } else
2421
#endif
2422
            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2423
    }
2424
}
2425

    
2426
static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2427
                                target_long val)
2428
{
2429
    tcg_gen_addi_tl(ret, arg1, val);
2430
#if defined(TARGET_PPC64)
2431
    if (!ctx->sf_mode) {
2432
        tcg_gen_ext32u_tl(ret, ret);
2433
    }
2434
#endif
2435
}
2436

    
2437
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2438
{
2439
    int l1 = gen_new_label();
2440
    TCGv t0 = tcg_temp_new();
2441
    TCGv_i32 t1, t2;
2442
    /* NIP cannot be restored if the memory exception comes from an helper */
2443
    gen_update_nip(ctx, ctx->nip - 4);
2444
    tcg_gen_andi_tl(t0, EA, mask);
2445
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2446
    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2447
    t2 = tcg_const_i32(0);
2448
    gen_helper_raise_exception_err(t1, t2);
2449
    tcg_temp_free_i32(t1);
2450
    tcg_temp_free_i32(t2);
2451
    gen_set_label(l1);
2452
    tcg_temp_free(t0);
2453
}
2454

    
2455
/***                             Integer load                              ***/
2456
static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2457
{
2458
    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2459
}
2460

    
2461
static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2462
{
2463
    tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2464
}
2465

    
2466
static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2467
{
2468
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2469
    if (unlikely(ctx->le_mode)) {
2470
        tcg_gen_bswap16_tl(arg1, arg1);
2471
    }
2472
}
2473

    
2474
static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2475
{
2476
    if (unlikely(ctx->le_mode)) {
2477
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2478
        tcg_gen_bswap16_tl(arg1, arg1);
2479
        tcg_gen_ext16s_tl(arg1, arg1);
2480
    } else {
2481
        tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2482
    }
2483
}
2484

    
2485
static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2486
{
2487
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2488
    if (unlikely(ctx->le_mode)) {
2489
        tcg_gen_bswap32_tl(arg1, arg1);
2490
    }
2491
}
2492

    
2493
#if defined(TARGET_PPC64)
2494
static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2495
{
2496
    if (unlikely(ctx->le_mode)) {
2497
        tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2498
        tcg_gen_bswap32_tl(arg1, arg1);
2499
        tcg_gen_ext32s_tl(arg1, arg1);
2500
    } else
2501
        tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2502
}
2503
#endif
2504

    
2505
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2506
{
2507
    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2508
    if (unlikely(ctx->le_mode)) {
2509
        tcg_gen_bswap64_i64(arg1, arg1);
2510
    }
2511
}
2512

    
2513
static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2514
{
2515
    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2516
}
2517

    
2518
static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2519
{
2520
    if (unlikely(ctx->le_mode)) {
2521
        TCGv t0 = tcg_temp_new();
2522
        tcg_gen_ext16u_tl(t0, arg1);
2523
        tcg_gen_bswap16_tl(t0, t0);
2524
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2525
        tcg_temp_free(t0);
2526
    } else {
2527
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2528
    }
2529
}
2530

    
2531
static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2532
{
2533
    if (unlikely(ctx->le_mode)) {
2534
        TCGv t0 = tcg_temp_new();
2535
        tcg_gen_ext32u_tl(t0, arg1);
2536
        tcg_gen_bswap32_tl(t0, t0);
2537
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2538
        tcg_temp_free(t0);
2539
    } else {
2540
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2541
    }
2542
}
2543

    
2544
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2545
{
2546
    if (unlikely(ctx->le_mode)) {
2547
        TCGv_i64 t0 = tcg_temp_new_i64();
2548
        tcg_gen_bswap64_i64(t0, arg1);
2549
        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2550
        tcg_temp_free_i64(t0);
2551
    } else
2552
        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2553
}
2554

    
2555
#define GEN_LD(name, ldop, opc, type)                                         \
2556
static void glue(gen_, name)(DisasContext *ctx)                                       \
2557
{                                                                             \
2558
    TCGv EA;                                                                  \
2559
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2560
    EA = tcg_temp_new();                                                      \
2561
    gen_addr_imm_index(ctx, EA, 0);                                           \
2562
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2563
    tcg_temp_free(EA);                                                        \
2564
}
2565

    
2566
#define GEN_LDU(name, ldop, opc, type)                                        \
2567
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
2568
{                                                                             \
2569
    TCGv EA;                                                                  \
2570
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2571
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2572
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2573
        return;                                                               \
2574
    }                                                                         \
2575
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2576
    EA = tcg_temp_new();                                                      \
2577
    if (type == PPC_64B)                                                      \
2578
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2579
    else                                                                      \
2580
        gen_addr_imm_index(ctx, EA, 0);                                       \
2581
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2582
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2583
    tcg_temp_free(EA);                                                        \
2584
}
2585

    
2586
#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2587
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2588
{                                                                             \
2589
    TCGv EA;                                                                  \
2590
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2591
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2592
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2593
        return;                                                               \
2594
    }                                                                         \
2595
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2596
    EA = tcg_temp_new();                                                      \
2597
    gen_addr_reg_index(ctx, EA);                                              \
2598
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2599
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2600
    tcg_temp_free(EA);                                                        \
2601
}
2602

    
2603
#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2604
static void glue(gen_, name##x)(DisasContext *ctx)                            \
2605
{                                                                             \
2606
    TCGv EA;                                                                  \
2607
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2608
    EA = tcg_temp_new();                                                      \
2609
    gen_addr_reg_index(ctx, EA);                                              \
2610
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2611
    tcg_temp_free(EA);                                                        \
2612
}
2613

    
2614
#define GEN_LDS(name, ldop, op, type)                                         \
2615
GEN_LD(name, ldop, op | 0x20, type);                                          \
2616
GEN_LDU(name, ldop, op | 0x21, type);                                         \
2617
GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2618
GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2619

    
2620
/* lbz lbzu lbzux lbzx */
2621
GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2622
/* lha lhau lhaux lhax */
2623
GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2624
/* lhz lhzu lhzux lhzx */
2625
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2626
/* lwz lwzu lwzux lwzx */
2627
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2628
#if defined(TARGET_PPC64)
2629
/* lwaux */
2630
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2631
/* lwax */
2632
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2633
/* ldux */
2634
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2635
/* ldx */
2636
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2637

    
2638
static void gen_ld(DisasContext *ctx)
2639
{
2640
    TCGv EA;
2641
    if (Rc(ctx->opcode)) {
2642
        if (unlikely(rA(ctx->opcode) == 0 ||
2643
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2644
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2645
            return;
2646
        }
2647
    }
2648
    gen_set_access_type(ctx, ACCESS_INT);
2649
    EA = tcg_temp_new();
2650
    gen_addr_imm_index(ctx, EA, 0x03);
2651
    if (ctx->opcode & 0x02) {
2652
        /* lwa (lwau is undefined) */
2653
        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2654
    } else {
2655
        /* ld - ldu */
2656
        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2657
    }
2658
    if (Rc(ctx->opcode))
2659
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2660
    tcg_temp_free(EA);
2661
}
2662

    
2663
/* lq */
2664
static void gen_lq(DisasContext *ctx)
2665
{
2666
#if defined(CONFIG_USER_ONLY)
2667
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2668
#else
2669
    int ra, rd;
2670
    TCGv EA;
2671

    
2672
    /* Restore CPU state */
2673
    if (unlikely(ctx->mem_idx == 0)) {
2674
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2675
        return;
2676
    }
2677
    ra = rA(ctx->opcode);
2678
    rd = rD(ctx->opcode);
2679
    if (unlikely((rd & 1) || rd == ra)) {
2680
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2681
        return;
2682
    }
2683
    if (unlikely(ctx->le_mode)) {
2684
        /* Little-endian mode is not handled */
2685
        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2686
        return;
2687
    }
2688
    gen_set_access_type(ctx, ACCESS_INT);
2689
    EA = tcg_temp_new();
2690
    gen_addr_imm_index(ctx, EA, 0x0F);
2691
    gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2692
    gen_addr_add(ctx, EA, EA, 8);
2693
    gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2694
    tcg_temp_free(EA);
2695
#endif
2696
}
2697
#endif
2698

    
2699
/***                              Integer store                            ***/
2700
#define GEN_ST(name, stop, opc, type)                                         \
2701
static void glue(gen_, name)(DisasContext *ctx)                                       \
2702
{                                                                             \
2703
    TCGv EA;                                                                  \
2704
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2705
    EA = tcg_temp_new();                                                      \
2706
    gen_addr_imm_index(ctx, EA, 0);                                           \
2707
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2708
    tcg_temp_free(EA);                                                        \
2709
}
2710

    
2711
#define GEN_STU(name, stop, opc, type)                                        \
2712
static void glue(gen_, stop##u)(DisasContext *ctx)                                    \
2713
{                                                                             \
2714
    TCGv EA;                                                                  \
2715
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2716
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2717
        return;                                                               \
2718
    }                                                                         \
2719
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2720
    EA = tcg_temp_new();                                                      \
2721
    if (type == PPC_64B)                                                      \
2722
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2723
    else                                                                      \
2724
        gen_addr_imm_index(ctx, EA, 0);                                       \
2725
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2726
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2727
    tcg_temp_free(EA);                                                        \
2728
}
2729

    
2730
#define GEN_STUX(name, stop, opc2, opc3, type)                                \
2731
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2732
{                                                                             \
2733
    TCGv EA;                                                                  \
2734
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2735
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2736
        return;                                                               \
2737
    }                                                                         \
2738
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2739
    EA = tcg_temp_new();                                                      \
2740
    gen_addr_reg_index(ctx, EA);                                              \
2741
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2742
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2743
    tcg_temp_free(EA);                                                        \
2744
}
2745

    
2746
#define GEN_STX(name, stop, opc2, opc3, type)                                 \
2747
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
2748
{                                                                             \
2749
    TCGv EA;                                                                  \
2750
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2751
    EA = tcg_temp_new();                                                      \
2752
    gen_addr_reg_index(ctx, EA);                                              \
2753
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2754
    tcg_temp_free(EA);                                                        \
2755
}
2756

    
2757
#define GEN_STS(name, stop, op, type)                                         \
2758
GEN_ST(name, stop, op | 0x20, type);                                          \
2759
GEN_STU(name, stop, op | 0x21, type);                                         \
2760
GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
2761
GEN_STX(name, stop, 0x17, op | 0x00, type)
2762

    
2763
/* stb stbu stbux stbx */
2764
GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2765
/* sth sthu sthux sthx */
2766
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2767
/* stw stwu stwux stwx */
2768
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2769
#if defined(TARGET_PPC64)
2770
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2771
GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2772

    
2773
static void gen_std(DisasContext *ctx)
2774
{
2775
    int rs;
2776
    TCGv EA;
2777

    
2778
    rs = rS(ctx->opcode);
2779
    if ((ctx->opcode & 0x3) == 0x2) {
2780
#if defined(CONFIG_USER_ONLY)
2781
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2782
#else
2783
        /* stq */
2784
        if (unlikely(ctx->mem_idx == 0)) {
2785
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2786
            return;
2787
        }
2788
        if (unlikely(rs & 1)) {
2789
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2790
            return;
2791
        }
2792
        if (unlikely(ctx->le_mode)) {
2793
            /* Little-endian mode is not handled */
2794
            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2795
            return;
2796
        }
2797
        gen_set_access_type(ctx, ACCESS_INT);
2798
        EA = tcg_temp_new();
2799
        gen_addr_imm_index(ctx, EA, 0x03);
2800
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2801
        gen_addr_add(ctx, EA, EA, 8);
2802
        gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2803
        tcg_temp_free(EA);
2804
#endif
2805
    } else {
2806
        /* std / stdu */
2807
        if (Rc(ctx->opcode)) {
2808
            if (unlikely(rA(ctx->opcode) == 0)) {
2809
                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2810
                return;
2811
            }
2812
        }
2813
        gen_set_access_type(ctx, ACCESS_INT);
2814
        EA = tcg_temp_new();
2815
        gen_addr_imm_index(ctx, EA, 0x03);
2816
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2817
        if (Rc(ctx->opcode))
2818
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2819
        tcg_temp_free(EA);
2820
    }
2821
}
2822
#endif
2823
/***                Integer load and store with byte reverse               ***/
2824
/* lhbrx */
2825
static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2826
{
2827
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2828
    if (likely(!ctx->le_mode)) {
2829
        tcg_gen_bswap16_tl(arg1, arg1);
2830
    }
2831
}
2832
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2833

    
2834
/* lwbrx */
2835
static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2836
{
2837
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2838
    if (likely(!ctx->le_mode)) {
2839
        tcg_gen_bswap32_tl(arg1, arg1);
2840
    }
2841
}
2842
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2843

    
2844
/* sthbrx */
2845
static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2846
{
2847
    if (likely(!ctx->le_mode)) {
2848
        TCGv t0 = tcg_temp_new();
2849
        tcg_gen_ext16u_tl(t0, arg1);
2850
        tcg_gen_bswap16_tl(t0, t0);
2851
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2852
        tcg_temp_free(t0);
2853
    } else {
2854
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2855
    }
2856
}
2857
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2858

    
2859
/* stwbrx */
2860
static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2861
{
2862
    if (likely(!ctx->le_mode)) {
2863
        TCGv t0 = tcg_temp_new();
2864
        tcg_gen_ext32u_tl(t0, arg1);
2865
        tcg_gen_bswap32_tl(t0, t0);
2866
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2867
        tcg_temp_free(t0);
2868
    } else {
2869
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2870
    }
2871
}
2872
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2873

    
2874
/***                    Integer load and store multiple                    ***/
2875

    
2876
/* lmw */
2877
static void gen_lmw(DisasContext *ctx)
2878
{
2879
    TCGv t0;
2880
    TCGv_i32 t1;
2881
    gen_set_access_type(ctx, ACCESS_INT);
2882
    /* NIP cannot be restored if the memory exception comes from an helper */
2883
    gen_update_nip(ctx, ctx->nip - 4);
2884
    t0 = tcg_temp_new();
2885
    t1 = tcg_const_i32(rD(ctx->opcode));
2886
    gen_addr_imm_index(ctx, t0, 0);
2887
    gen_helper_lmw(t0, t1);
2888
    tcg_temp_free(t0);
2889
    tcg_temp_free_i32(t1);
2890
}
2891

    
2892
/* stmw */
2893
static void gen_stmw(DisasContext *ctx)
2894
{
2895
    TCGv t0;
2896
    TCGv_i32 t1;
2897
    gen_set_access_type(ctx, ACCESS_INT);
2898
    /* NIP cannot be restored if the memory exception comes from an helper */
2899
    gen_update_nip(ctx, ctx->nip - 4);
2900
    t0 = tcg_temp_new();
2901
    t1 = tcg_const_i32(rS(ctx->opcode));
2902
    gen_addr_imm_index(ctx, t0, 0);
2903
    gen_helper_stmw(t0, t1);
2904
    tcg_temp_free(t0);
2905
    tcg_temp_free_i32(t1);
2906
}
2907

    
2908
/***                    Integer load and store strings                     ***/
2909

    
2910
/* lswi */
2911
/* PowerPC32 specification says we must generate an exception if
2912
 * rA is in the range of registers to be loaded.
2913
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2914
 * For now, I'll follow the spec...
2915
 */
2916
static void gen_lswi(DisasContext *ctx)
2917
{
2918
    TCGv t0;
2919
    TCGv_i32 t1, t2;
2920
    int nb = NB(ctx->opcode);
2921
    int start = rD(ctx->opcode);
2922
    int ra = rA(ctx->opcode);
2923
    int nr;
2924

    
2925
    if (nb == 0)
2926
        nb = 32;
2927
    nr = nb / 4;
2928
    if (unlikely(((start + nr) > 32  &&
2929
                  start <= ra && (start + nr - 32) > ra) ||
2930
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2931
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2932
        return;
2933
    }
2934
    gen_set_access_type(ctx, ACCESS_INT);
2935
    /* NIP cannot be restored if the memory exception comes from an helper */
2936
    gen_update_nip(ctx, ctx->nip - 4);
2937
    t0 = tcg_temp_new();
2938
    gen_addr_register(ctx, t0);
2939
    t1 = tcg_const_i32(nb);
2940
    t2 = tcg_const_i32(start);
2941
    gen_helper_lsw(t0, t1, t2);
2942
    tcg_temp_free(t0);
2943
    tcg_temp_free_i32(t1);
2944
    tcg_temp_free_i32(t2);
2945
}
2946

    
2947
/* lswx */
2948
static void gen_lswx(DisasContext *ctx)
2949
{
2950
    TCGv t0;
2951
    TCGv_i32 t1, t2, t3;
2952
    gen_set_access_type(ctx, ACCESS_INT);
2953
    /* NIP cannot be restored if the memory exception comes from an helper */
2954
    gen_update_nip(ctx, ctx->nip - 4);
2955
    t0 = tcg_temp_new();
2956
    gen_addr_reg_index(ctx, t0);
2957
    t1 = tcg_const_i32(rD(ctx->opcode));
2958
    t2 = tcg_const_i32(rA(ctx->opcode));
2959
    t3 = tcg_const_i32(rB(ctx->opcode));
2960
    gen_helper_lswx(t0, t1, t2, t3);
2961
    tcg_temp_free(t0);
2962
    tcg_temp_free_i32(t1);
2963
    tcg_temp_free_i32(t2);
2964
    tcg_temp_free_i32(t3);
2965
}
2966

    
2967
/* stswi */
2968
static void gen_stswi(DisasContext *ctx)
2969
{
2970
    TCGv t0;
2971
    TCGv_i32 t1, t2;
2972
    int nb = NB(ctx->opcode);
2973
    gen_set_access_type(ctx, ACCESS_INT);
2974
    /* NIP cannot be restored if the memory exception comes from an helper */
2975
    gen_update_nip(ctx, ctx->nip - 4);
2976
    t0 = tcg_temp_new();
2977
    gen_addr_register(ctx, t0);
2978
    if (nb == 0)
2979
        nb = 32;
2980
    t1 = tcg_const_i32(nb);
2981
    t2 = tcg_const_i32(rS(ctx->opcode));
2982
    gen_helper_stsw(t0, t1, t2);
2983
    tcg_temp_free(t0);
2984
    tcg_temp_free_i32(t1);
2985
    tcg_temp_free_i32(t2);
2986
}
2987

    
2988
/* stswx */
2989
static void gen_stswx(DisasContext *ctx)
2990
{
2991
    TCGv t0;
2992
    TCGv_i32 t1, t2;
2993
    gen_set_access_type(ctx, ACCESS_INT);
2994
    /* NIP cannot be restored if the memory exception comes from an helper */
2995
    gen_update_nip(ctx, ctx->nip - 4);
2996
    t0 = tcg_temp_new();
2997
    gen_addr_reg_index(ctx, t0);
2998
    t1 = tcg_temp_new_i32();
2999
    tcg_gen_trunc_tl_i32(t1, cpu_xer);
3000
    tcg_gen_andi_i32(t1, t1, 0x7F);
3001
    t2 = tcg_const_i32(rS(ctx->opcode));
3002
    gen_helper_stsw(t0, t1, t2);
3003
    tcg_temp_free(t0);
3004
    tcg_temp_free_i32(t1);
3005
    tcg_temp_free_i32(t2);
3006
}
3007

    
3008
/***                        Memory synchronisation                         ***/
3009
/* eieio */
3010
static void gen_eieio(DisasContext *ctx)
3011
{
3012
}
3013

    
3014
/* isync */
3015
static void gen_isync(DisasContext *ctx)
3016
{
3017
    gen_stop_exception(ctx);
3018
}
3019

    
3020
/* lwarx */
3021
static void gen_lwarx(DisasContext *ctx)
3022
{
3023
    TCGv t0;
3024
    TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3025
    gen_set_access_type(ctx, ACCESS_RES);
3026
    t0 = tcg_temp_local_new();
3027
    gen_addr_reg_index(ctx, t0);
3028
    gen_check_align(ctx, t0, 0x03);
3029
    gen_qemu_ld32u(ctx, gpr, t0);
3030
    tcg_gen_mov_tl(cpu_reserve, t0);
3031
    tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3032
    tcg_temp_free(t0);
3033
}
3034

    
3035
#if defined(CONFIG_USER_ONLY)
3036
static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3037
                                   int reg, int size)
3038
{
3039
    TCGv t0 = tcg_temp_new();
3040
    uint32_t save_exception = ctx->exception;
3041

    
3042
    tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3043
    tcg_gen_movi_tl(t0, (size << 5) | reg);
3044
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3045
    tcg_temp_free(t0);
3046
    gen_update_nip(ctx, ctx->nip-4);
3047
    ctx->exception = POWERPC_EXCP_BRANCH;
3048
    gen_exception(ctx, POWERPC_EXCP_STCX);
3049
    ctx->exception = save_exception;
3050
}
3051
#endif
3052

    
3053
/* stwcx. */
3054
static void gen_stwcx_(DisasContext *ctx)
3055
{
3056
    TCGv t0;
3057
    gen_set_access_type(ctx, ACCESS_RES);
3058
    t0 = tcg_temp_local_new();
3059
    gen_addr_reg_index(ctx, t0);
3060
    gen_check_align(ctx, t0, 0x03);
3061
#if defined(CONFIG_USER_ONLY)
3062
    gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3063
#else
3064
    {
3065
        int l1;
3066

    
3067
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3068
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3069
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3070
        l1 = gen_new_label();
3071
        tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3072
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3073
        gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3074
        gen_set_label(l1);
3075
        tcg_gen_movi_tl(cpu_reserve, -1);
3076
    }
3077
#endif
3078
    tcg_temp_free(t0);
3079
}
3080

    
3081
#if defined(TARGET_PPC64)
3082
/* ldarx */
3083
static void gen_ldarx(DisasContext *ctx)
3084
{
3085
    TCGv t0;
3086
    TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3087
    gen_set_access_type(ctx, ACCESS_RES);
3088
    t0 = tcg_temp_local_new();
3089
    gen_addr_reg_index(ctx, t0);
3090
    gen_check_align(ctx, t0, 0x07);
3091
    gen_qemu_ld64(ctx, gpr, t0);
3092
    tcg_gen_mov_tl(cpu_reserve, t0);
3093
    tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3094
    tcg_temp_free(t0);
3095
}
3096

    
3097
/* stdcx. */
3098
static void gen_stdcx_(DisasContext *ctx)
3099
{
3100
    TCGv t0;
3101
    gen_set_access_type(ctx, ACCESS_RES);
3102
    t0 = tcg_temp_local_new();
3103
    gen_addr_reg_index(ctx, t0);
3104
    gen_check_align(ctx, t0, 0x07);
3105
#if defined(CONFIG_USER_ONLY)
3106
    gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3107
#else
3108
    {
3109
        int l1;
3110
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3111
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3112
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3113
        l1 = gen_new_label();
3114
        tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3115
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3116
        gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3117
        gen_set_label(l1);
3118
        tcg_gen_movi_tl(cpu_reserve, -1);
3119
    }
3120
#endif
3121
    tcg_temp_free(t0);
3122
}
3123
#endif /* defined(TARGET_PPC64) */
3124

    
3125
/* sync */
3126
static void gen_sync(DisasContext *ctx)
3127
{
3128
}
3129

    
3130
/* wait */
3131
static void gen_wait(DisasContext *ctx)
3132
{
3133
    TCGv_i32 t0 = tcg_temp_new_i32();
3134
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3135
    tcg_temp_free_i32(t0);
3136
    /* Stop translation, as the CPU is supposed to sleep from now */
3137
    gen_exception_err(ctx, EXCP_HLT, 1);
3138
}
3139

    
3140
/***                         Floating-point load                           ***/
3141
#define GEN_LDF(name, ldop, opc, type)                                        \
3142
static void glue(gen_, name)(DisasContext *ctx)                                       \
3143
{                                                                             \
3144
    TCGv EA;                                                                  \
3145
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3146
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3147
        return;                                                               \
3148
    }                                                                         \
3149
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3150
    EA = tcg_temp_new();                                                      \
3151
    gen_addr_imm_index(ctx, EA, 0);                                           \
3152
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3153
    tcg_temp_free(EA);                                                        \
3154
}
3155

    
3156
#define GEN_LDUF(name, ldop, opc, type)                                       \
3157
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3158
{                                                                             \
3159
    TCGv EA;                                                                  \
3160
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3161
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3162
        return;                                                               \
3163
    }                                                                         \
3164
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3165
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3166
        return;                                                               \
3167
    }                                                                         \
3168
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3169
    EA = tcg_temp_new();                                                      \
3170
    gen_addr_imm_index(ctx, EA, 0);                                           \
3171
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3172
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3173
    tcg_temp_free(EA);                                                        \
3174
}
3175

    
3176
#define GEN_LDUXF(name, ldop, opc, type)                                      \
3177
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3178
{                                                                             \
3179
    TCGv EA;                                                                  \
3180
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3181
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3182
        return;                                                               \
3183
    }                                                                         \
3184
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3185
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3186
        return;                                                               \
3187
    }                                                                         \
3188
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3189
    EA = tcg_temp_new();                                                      \
3190
    gen_addr_reg_index(ctx, EA);                                              \
3191
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3192
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3193
    tcg_temp_free(EA);                                                        \
3194
}
3195

    
3196
#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
3197
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3198
{                                                                             \
3199
    TCGv EA;                                                                  \
3200
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3201
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3202
        return;                                                               \
3203
    }                                                                         \
3204
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3205
    EA = tcg_temp_new();                                                      \
3206
    gen_addr_reg_index(ctx, EA);                                              \
3207
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3208
    tcg_temp_free(EA);                                                        \
3209
}
3210

    
3211
#define GEN_LDFS(name, ldop, op, type)                                        \
3212
GEN_LDF(name, ldop, op | 0x20, type);                                         \
3213
GEN_LDUF(name, ldop, op | 0x21, type);                                        \
3214
GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
3215
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3216

    
3217
static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3218
{
3219
    TCGv t0 = tcg_temp_new();
3220
    TCGv_i32 t1 = tcg_temp_new_i32();
3221
    gen_qemu_ld32u(ctx, t0, arg2);
3222
    tcg_gen_trunc_tl_i32(t1, t0);
3223
    tcg_temp_free(t0);
3224
    gen_helper_float32_to_float64(arg1, t1);
3225
    tcg_temp_free_i32(t1);
3226
}
3227

    
3228
 /* lfd lfdu lfdux lfdx */
3229
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3230
 /* lfs lfsu lfsux lfsx */
3231
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3232

    
3233
/***                         Floating-point store                          ***/
3234
#define GEN_STF(name, stop, opc, type)                                        \
3235
static void glue(gen_, name)(DisasContext *ctx)                                       \
3236
{                                                                             \
3237
    TCGv EA;                                                                  \
3238
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3239
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3240
        return;                                                               \
3241
    }                                                                         \
3242
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3243
    EA = tcg_temp_new();                                                      \
3244
    gen_addr_imm_index(ctx, EA, 0);                                           \
3245
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3246
    tcg_temp_free(EA);                                                        \
3247
}
3248

    
3249
#define GEN_STUF(name, stop, opc, type)                                       \
3250
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3251
{                                                                             \
3252
    TCGv EA;                                                                  \
3253
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3254
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3255
        return;                                                               \
3256
    }                                                                         \
3257
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3258
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3259
        return;                                                               \
3260
    }                                                                         \
3261
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3262
    EA = tcg_temp_new();                                                      \
3263
    gen_addr_imm_index(ctx, EA, 0);                                           \
3264
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3265
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3266
    tcg_temp_free(EA);                                                        \
3267
}
3268

    
3269
#define GEN_STUXF(name, stop, opc, type)                                      \
3270
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3271
{                                                                             \
3272
    TCGv EA;                                                                  \
3273
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3274
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3275
        return;                                                               \
3276
    }                                                                         \
3277
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3278
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3279
        return;                                                               \
3280
    }                                                                         \
3281
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3282
    EA = tcg_temp_new();                                                      \
3283
    gen_addr_reg_index(ctx, EA);                                              \
3284
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3285
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3286
    tcg_temp_free(EA);                                                        \
3287
}
3288

    
3289
#define GEN_STXF(name, stop, opc2, opc3, type)                                \
3290
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3291
{                                                                             \
3292
    TCGv EA;                                                                  \
3293
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3294
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3295
        return;                                                               \
3296
    }                                                                         \
3297
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3298
    EA = tcg_temp_new();                                                      \
3299
    gen_addr_reg_index(ctx, EA);                                              \
3300
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3301
    tcg_temp_free(EA);                                                        \
3302
}
3303

    
3304
#define GEN_STFS(name, stop, op, type)                                        \
3305
GEN_STF(name, stop, op | 0x20, type);                                         \
3306
GEN_STUF(name, stop, op | 0x21, type);                                        \
3307
GEN_STUXF(name, stop, op | 0x01, type);                                       \
3308
GEN_STXF(name, stop, 0x17, op | 0x00, type)
3309

    
3310
static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3311
{
3312
    TCGv_i32 t0 = tcg_temp_new_i32();
3313
    TCGv t1 = tcg_temp_new();
3314
    gen_helper_float64_to_float32(t0, arg1);
3315
    tcg_gen_extu_i32_tl(t1, t0);
3316
    tcg_temp_free_i32(t0);
3317
    gen_qemu_st32(ctx, t1, arg2);
3318
    tcg_temp_free(t1);
3319
}
3320

    
3321
/* stfd stfdu stfdux stfdx */
3322
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3323
/* stfs stfsu stfsux stfsx */
3324
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3325

    
3326
/* Optional: */
3327
static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3328
{
3329
    TCGv t0 = tcg_temp_new();
3330
    tcg_gen_trunc_i64_tl(t0, arg1),
3331
    gen_qemu_st32(ctx, t0, arg2);
3332
    tcg_temp_free(t0);
3333
}
3334
/* stfiwx */
3335
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3336

    
3337
/***                                Branch                                 ***/
3338
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3339
{
3340
    TranslationBlock *tb;
3341
    tb = ctx->tb;
3342
#if defined(TARGET_PPC64)
3343
    if (!ctx->sf_mode)
3344
        dest = (uint32_t) dest;
3345
#endif
3346
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3347
        likely(!ctx->singlestep_enabled)) {
3348
        tcg_gen_goto_tb(n);
3349
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3350
        tcg_gen_exit_tb((long)tb + n);
3351
    } else {
3352
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3353
        if (unlikely(ctx->singlestep_enabled)) {
3354
            if ((ctx->singlestep_enabled &
3355
                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3356
                ctx->exception == POWERPC_EXCP_BRANCH) {
3357
                target_ulong tmp = ctx->nip;
3358
                ctx->nip = dest;
3359
                gen_exception(ctx, POWERPC_EXCP_TRACE);
3360
                ctx->nip = tmp;
3361
            }
3362
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3363
                gen_debug_exception(ctx);
3364
            }
3365
        }
3366
        tcg_gen_exit_tb(0);
3367
    }
3368
}
3369

    
3370
static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3371
{
3372
#if defined(TARGET_PPC64)
3373
    if (ctx->sf_mode == 0)
3374
        tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3375
    else
3376
#endif
3377
        tcg_gen_movi_tl(cpu_lr, nip);
3378
}
3379

    
3380
/* b ba bl bla */
3381
static void gen_b(DisasContext *ctx)
3382
{
3383
    target_ulong li, target;
3384

    
3385
    ctx->exception = POWERPC_EXCP_BRANCH;
3386
    /* sign extend LI */
3387
#if defined(TARGET_PPC64)
3388
    if (ctx->sf_mode)
3389
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3390
    else
3391
#endif
3392
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3393
    if (likely(AA(ctx->opcode) == 0))
3394
        target = ctx->nip + li - 4;
3395
    else
3396
        target = li;
3397
    if (LK(ctx->opcode))
3398
        gen_setlr(ctx, ctx->nip);
3399
    gen_goto_tb(ctx, 0, target);
3400
}
3401

    
3402
#define BCOND_IM  0
3403
#define BCOND_LR  1
3404
#define BCOND_CTR 2
3405

    
3406
static inline void gen_bcond(DisasContext *ctx, int type)
3407
{
3408
    uint32_t bo = BO(ctx->opcode);
3409
    int l1;
3410
    TCGv target;
3411

    
3412
    ctx->exception = POWERPC_EXCP_BRANCH;
3413
    if (type == BCOND_LR || type == BCOND_CTR) {
3414
        target = tcg_temp_local_new();
3415
        if (type == BCOND_CTR)
3416
            tcg_gen_mov_tl(target, cpu_ctr);
3417
        else
3418
            tcg_gen_mov_tl(target, cpu_lr);
3419
    } else {
3420
        TCGV_UNUSED(target);
3421
    }
3422
    if (LK(ctx->opcode))
3423
        gen_setlr(ctx, ctx->nip);
3424
    l1 = gen_new_label();
3425
    if ((bo & 0x4) == 0) {
3426
        /* Decrement and test CTR */
3427
        TCGv temp = tcg_temp_new();
3428
        if (unlikely(type == BCOND_CTR)) {
3429
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3430
            return;
3431
        }
3432
        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3433
#if defined(TARGET_PPC64)
3434
        if (!ctx->sf_mode)
3435
            tcg_gen_ext32u_tl(temp, cpu_ctr);
3436
        else
3437
#endif
3438
            tcg_gen_mov_tl(temp, cpu_ctr);
3439
        if (bo & 0x2) {
3440
            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3441
        } else {
3442
            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3443
        }
3444
        tcg_temp_free(temp);
3445
    }
3446
    if ((bo & 0x10) == 0) {
3447
        /* Test CR */
3448
        uint32_t bi = BI(ctx->opcode);
3449
        uint32_t mask = 1 << (3 - (bi & 0x03));
3450
        TCGv_i32 temp = tcg_temp_new_i32();
3451

    
3452
        if (bo & 0x8) {
3453
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3454
            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3455
        } else {
3456
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3457
            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3458
        }
3459
        tcg_temp_free_i32(temp);
3460
    }
3461
    if (type == BCOND_IM) {
3462
        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3463
        if (likely(AA(ctx->opcode) == 0)) {
3464
            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3465
        } else {
3466
            gen_goto_tb(ctx, 0, li);
3467
        }
3468
        gen_set_label(l1);
3469
        gen_goto_tb(ctx, 1, ctx->nip);
3470
    } else {
3471
#if defined(TARGET_PPC64)
3472
        if (!(ctx->sf_mode))
3473
            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3474
        else
3475
#endif
3476
            tcg_gen_andi_tl(cpu_nip, target, ~3);
3477
        tcg_gen_exit_tb(0);
3478
        gen_set_label(l1);
3479
#if defined(TARGET_PPC64)
3480
        if (!(ctx->sf_mode))
3481
            tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3482
        else
3483
#endif
3484
            tcg_gen_movi_tl(cpu_nip, ctx->nip);
3485
        tcg_gen_exit_tb(0);
3486
    }
3487
}
3488

    
3489
static void gen_bc(DisasContext *ctx)
3490
{
3491
    gen_bcond(ctx, BCOND_IM);
3492
}
3493

    
3494
static void gen_bcctr(DisasContext *ctx)
3495
{
3496
    gen_bcond(ctx, BCOND_CTR);
3497
}
3498

    
3499
static void gen_bclr(DisasContext *ctx)
3500
{
3501
    gen_bcond(ctx, BCOND_LR);
3502
}
3503

    
3504
/***                      Condition register logical                       ***/
3505
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3506
static void glue(gen_, name)(DisasContext *ctx)                                       \
3507
{                                                                             \
3508
    uint8_t bitmask;                                                          \
3509
    int sh;                                                                   \
3510
    TCGv_i32 t0, t1;                                                          \
3511
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3512
    t0 = tcg_temp_new_i32();                                                  \
3513
    if (sh > 0)                                                               \
3514
        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3515
    else if (sh < 0)                                                          \
3516
        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3517
    else                                                                      \
3518
        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
3519
    t1 = tcg_temp_new_i32();                                                  \
3520
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3521
    if (sh > 0)                                                               \
3522
        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3523
    else if (sh < 0)                                                          \
3524
        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3525
    else                                                                      \
3526
        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
3527
    tcg_op(t0, t0, t1);                                                       \
3528
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3529
    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
3530
    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
3531
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
3532
    tcg_temp_free_i32(t0);                                                    \
3533
    tcg_temp_free_i32(t1);                                                    \
3534
}
3535

    
3536
/* crand */
3537
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3538
/* crandc */
3539
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3540
/* creqv */
3541
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3542
/* crnand */
3543
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3544
/* crnor */
3545
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3546
/* cror */
3547
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3548
/* crorc */
3549
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3550
/* crxor */
3551
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3552

    
3553
/* mcrf */
3554
static void gen_mcrf(DisasContext *ctx)
3555
{
3556
    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3557
}
3558

    
3559
/***                           System linkage                              ***/
3560

    
3561
/* rfi (mem_idx only) */
3562
static void gen_rfi(DisasContext *ctx)
3563
{
3564
#if defined(CONFIG_USER_ONLY)
3565
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3566
#else
3567
    /* Restore CPU state */
3568
    if (unlikely(!ctx->mem_idx)) {
3569
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3570
        return;
3571
    }
3572
    gen_helper_rfi();
3573
    gen_sync_exception(ctx);
3574
#endif
3575
}
3576

    
3577
#if defined(TARGET_PPC64)
3578
static void gen_rfid(DisasContext *ctx)
3579
{
3580
#if defined(CONFIG_USER_ONLY)
3581
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3582
#else
3583
    /* Restore CPU state */
3584
    if (unlikely(!ctx->mem_idx)) {
3585
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3586
        return;
3587
    }
3588
    gen_helper_rfid();
3589
    gen_sync_exception(ctx);
3590
#endif
3591
}
3592

    
3593
static void gen_hrfid(DisasContext *ctx)
3594
{
3595
#if defined(CONFIG_USER_ONLY)
3596
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3597
#else
3598
    /* Restore CPU state */
3599
    if (unlikely(ctx->mem_idx <= 1)) {
3600
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3601
        return;
3602
    }
3603
    gen_helper_hrfid();
3604
    gen_sync_exception(ctx);
3605
#endif
3606
}
3607
#endif
3608

    
3609
/* sc */
3610
#if defined(CONFIG_USER_ONLY)
3611
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3612
#else
3613
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3614
#endif
3615
static void gen_sc(DisasContext *ctx)
3616
{
3617
    uint32_t lev;
3618

    
3619
    lev = (ctx->opcode >> 5) & 0x7F;
3620
    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3621
}
3622

    
3623
/***                                Trap                                   ***/
3624

    
3625
/* tw */
3626
static void gen_tw(DisasContext *ctx)
3627
{
3628
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3629
    /* Update the nip since this might generate a trap exception */
3630
    gen_update_nip(ctx, ctx->nip);
3631
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3632
    tcg_temp_free_i32(t0);
3633
}
3634

    
3635
/* twi */
3636
static void gen_twi(DisasContext *ctx)
3637
{
3638
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3639
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3640
    /* Update the nip since this might generate a trap exception */
3641
    gen_update_nip(ctx, ctx->nip);
3642
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3643
    tcg_temp_free(t0);
3644
    tcg_temp_free_i32(t1);
3645
}
3646

    
3647
#if defined(TARGET_PPC64)
3648
/* td */
3649
static void gen_td(DisasContext *ctx)
3650
{
3651
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3652
    /* Update the nip since this might generate a trap exception */
3653
    gen_update_nip(ctx, ctx->nip);
3654
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3655
    tcg_temp_free_i32(t0);
3656
}
3657

    
3658
/* tdi */
3659
static void gen_tdi(DisasContext *ctx)
3660
{
3661
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3662
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3663
    /* Update the nip since this might generate a trap exception */
3664
    gen_update_nip(ctx, ctx->nip);
3665
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3666
    tcg_temp_free(t0);
3667
    tcg_temp_free_i32(t1);
3668
}
3669
#endif
3670

    
3671
/***                          Processor control                            ***/
3672

    
3673
/* mcrxr */
3674
static void gen_mcrxr(DisasContext *ctx)
3675
{
3676
    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3677
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3678
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3679
}
3680

    
3681
/* mfcr mfocrf */
3682
static void gen_mfcr(DisasContext *ctx)
3683
{
3684
    uint32_t crm, crn;
3685

    
3686
    if (likely(ctx->opcode & 0x00100000)) {
3687
        crm = CRM(ctx->opcode);
3688
        if (likely(crm && ((crm & (crm - 1)) == 0))) {
3689
            crn = ctz32 (crm);
3690
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3691
            tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3692
                            cpu_gpr[rD(ctx->opcode)], crn * 4);
3693
        }
3694
    } else {
3695
        TCGv_i32 t0 = tcg_temp_new_i32();
3696
        tcg_gen_mov_i32(t0, cpu_crf[0]);
3697
        tcg_gen_shli_i32(t0, t0, 4);
3698
        tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3699
        tcg_gen_shli_i32(t0, t0, 4);
3700
        tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3701
        tcg_gen_shli_i32(t0, t0, 4);
3702
        tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3703
        tcg_gen_shli_i32(t0, t0, 4);
3704
        tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3705
        tcg_gen_shli_i32(t0, t0, 4);
3706
        tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3707
        tcg_gen_shli_i32(t0, t0, 4);
3708
        tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3709
        tcg_gen_shli_i32(t0, t0, 4);
3710
        tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3711
        tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3712
        tcg_temp_free_i32(t0);
3713
    }
3714
}
3715

    
3716
/* mfmsr */
3717
static void gen_mfmsr(DisasContext *ctx)
3718
{
3719
#if defined(CONFIG_USER_ONLY)
3720
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3721
#else
3722
    if (unlikely(!ctx->mem_idx)) {
3723
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3724
        return;
3725
    }
3726
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3727
#endif
3728
}
3729

    
3730
static void spr_noaccess(void *opaque, int gprn, int sprn)
3731
{
3732
#if 0
3733
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3734
    printf("ERROR: try to access SPR %d !\n", sprn);
3735
#endif
3736
}
3737
#define SPR_NOACCESS (&spr_noaccess)
3738

    
3739
/* mfspr */
3740
static inline void gen_op_mfspr(DisasContext *ctx)
3741
{
3742
    void (*read_cb)(void *opaque, int gprn, int sprn);
3743
    uint32_t sprn = SPR(ctx->opcode);
3744

    
3745
#if !defined(CONFIG_USER_ONLY)
3746
    if (ctx->mem_idx == 2)
3747
        read_cb = ctx->spr_cb[sprn].hea_read;
3748
    else if (ctx->mem_idx)
3749
        read_cb = ctx->spr_cb[sprn].oea_read;
3750
    else
3751
#endif
3752
        read_cb = ctx->spr_cb[sprn].uea_read;
3753
    if (likely(read_cb != NULL)) {
3754
        if (likely(read_cb != SPR_NOACCESS)) {
3755
            (*read_cb)(ctx, rD(ctx->opcode), sprn);
3756
        } else {
3757
            /* Privilege exception */
3758
            /* This is a hack to avoid warnings when running Linux:
3759
             * this OS breaks the PowerPC virtualisation model,
3760
             * allowing userland application to read the PVR
3761
             */
3762
            if (sprn != SPR_PVR) {
3763
                qemu_log("Trying to read privileged spr %d %03x at "
3764
                         TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3765
                printf("Trying to read privileged spr %d %03x at "
3766
                       TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3767
            }
3768
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3769
        }
3770
    } else {
3771
        /* Not defined */
3772
        qemu_log("Trying to read invalid spr %d %03x at "
3773
                    TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3774
        printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3775
               sprn, sprn, ctx->nip);
3776
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3777
    }
3778
}
3779

    
3780
static void gen_mfspr(DisasContext *ctx)
3781
{
3782
    gen_op_mfspr(ctx);
3783
}
3784

    
3785
/* mftb */
3786
static void gen_mftb(DisasContext *ctx)
3787
{
3788
    gen_op_mfspr(ctx);
3789
}
3790

    
3791
/* mtcrf mtocrf*/
3792
static void gen_mtcrf(DisasContext *ctx)
3793
{
3794
    uint32_t crm, crn;
3795

    
3796
    crm = CRM(ctx->opcode);
3797
    if (likely((ctx->opcode & 0x00100000))) {
3798
        if (crm && ((crm & (crm - 1)) == 0)) {
3799
            TCGv_i32 temp = tcg_temp_new_i32();
3800
            crn = ctz32 (crm);
3801
            tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3802
            tcg_gen_shri_i32(temp, temp, crn * 4);
3803
            tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3804
            tcg_temp_free_i32(temp);
3805
        }
3806
    } else {
3807
        TCGv_i32 temp = tcg_temp_new_i32();
3808
        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3809
        for (crn = 0 ; crn < 8 ; crn++) {
3810
            if (crm & (1 << crn)) {
3811
                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3812
                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3813
            }
3814
        }
3815
        tcg_temp_free_i32(temp);
3816
    }
3817
}
3818

    
3819
/* mtmsr */
3820
#if defined(TARGET_PPC64)
3821
static void gen_mtmsrd(DisasContext *ctx)
3822
{
3823
#if defined(CONFIG_USER_ONLY)
3824
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3825
#else
3826
    if (unlikely(!ctx->mem_idx)) {
3827
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3828
        return;
3829
    }
3830
    if (ctx->opcode & 0x00010000) {
3831
        /* Special form that does not need any synchronisation */
3832
        TCGv t0 = tcg_temp_new();
3833
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3834
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3835
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3836
        tcg_temp_free(t0);
3837
    } else {
3838
        /* XXX: we need to update nip before the store
3839
         *      if we enter power saving mode, we will exit the loop
3840
         *      directly from ppc_store_msr
3841
         */
3842
        gen_update_nip(ctx, ctx->nip);
3843
        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3844
        /* Must stop the translation as machine state (may have) changed */
3845
        /* Note that mtmsr is not always defined as context-synchronizing */
3846
        gen_stop_exception(ctx);
3847
    }
3848
#endif
3849
}
3850
#endif
3851

    
3852
static void gen_mtmsr(DisasContext *ctx)
3853
{
3854
#if defined(CONFIG_USER_ONLY)
3855
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3856
#else
3857
    if (unlikely(!ctx->mem_idx)) {
3858
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3859
        return;
3860
    }
3861
    if (ctx->opcode & 0x00010000) {
3862
        /* Special form that does not need any synchronisation */
3863
        TCGv t0 = tcg_temp_new();
3864
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3865
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3866
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3867
        tcg_temp_free(t0);
3868
    } else {
3869
        /* XXX: we need to update nip before the store
3870
         *      if we enter power saving mode, we will exit the loop
3871
         *      directly from ppc_store_msr
3872
         */
3873
        gen_update_nip(ctx, ctx->nip);
3874
#if defined(TARGET_PPC64)
3875
        if (!ctx->sf_mode) {
3876
            TCGv t0 = tcg_temp_new();
3877
            TCGv t1 = tcg_temp_new();
3878
            tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3879
            tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3880
            tcg_gen_or_tl(t0, t0, t1);
3881
            tcg_temp_free(t1);
3882
            gen_helper_store_msr(t0);
3883
            tcg_temp_free(t0);
3884
        } else
3885
#endif
3886
            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3887
        /* Must stop the translation as machine state (may have) changed */
3888
        /* Note that mtmsr is not always defined as context-synchronizing */
3889
        gen_stop_exception(ctx);
3890
    }
3891
#endif
3892
}
3893

    
3894
/* mtspr */
3895
static void gen_mtspr(DisasContext *ctx)
3896
{
3897
    void (*write_cb)(void *opaque, int sprn, int gprn);
3898
    uint32_t sprn = SPR(ctx->opcode);
3899

    
3900
#if !defined(CONFIG_USER_ONLY)
3901
    if (ctx->mem_idx == 2)
3902
        write_cb = ctx->spr_cb[sprn].hea_write;
3903
    else if (ctx->mem_idx)
3904
        write_cb = ctx->spr_cb[sprn].oea_write;
3905
    else
3906
#endif
3907
        write_cb = ctx->spr_cb[sprn].uea_write;
3908
    if (likely(write_cb != NULL)) {
3909
        if (likely(write_cb != SPR_NOACCESS)) {
3910
            (*write_cb)(ctx, sprn, rS(ctx->opcode));
3911
        } else {
3912
            /* Privilege exception */
3913
            qemu_log("Trying to write privileged spr %d %03x at "
3914
                     TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3915
            printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3916
                   "\n", sprn, sprn, ctx->nip);
3917
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3918
        }
3919
    } else {
3920
        /* Not defined */
3921
        qemu_log("Trying to write invalid spr %d %03x at "
3922
                 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3923
        printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3924
               sprn, sprn, ctx->nip);
3925
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3926
    }
3927
}
3928

    
3929
/***                         Cache management                              ***/
3930

    
3931
/* dcbf */
3932
static void gen_dcbf(DisasContext *ctx)
3933
{
3934
    /* XXX: specification says this is treated as a load by the MMU */
3935
    TCGv t0;
3936
    gen_set_access_type(ctx, ACCESS_CACHE);
3937
    t0 = tcg_temp_new();
3938
    gen_addr_reg_index(ctx, t0);
3939
    gen_qemu_ld8u(ctx, t0, t0);
3940
    tcg_temp_free(t0);
3941
}
3942

    
3943
/* dcbi (Supervisor only) */
3944
static void gen_dcbi(DisasContext *ctx)
3945
{
3946
#if defined(CONFIG_USER_ONLY)
3947
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3948
#else
3949
    TCGv EA, val;
3950
    if (unlikely(!ctx->mem_idx)) {
3951
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3952
        return;
3953
    }
3954
    EA = tcg_temp_new();
3955
    gen_set_access_type(ctx, ACCESS_CACHE);
3956
    gen_addr_reg_index(ctx, EA);
3957
    val = tcg_temp_new();
3958
    /* XXX: specification says this should be treated as a store by the MMU */
3959
    gen_qemu_ld8u(ctx, val, EA);
3960
    gen_qemu_st8(ctx, val, EA);
3961
    tcg_temp_free(val);
3962
    tcg_temp_free(EA);
3963
#endif
3964
}
3965

    
3966
/* dcdst */
3967
static void gen_dcbst(DisasContext *ctx)
3968
{
3969
    /* XXX: specification say this is treated as a load by the MMU */
3970
    TCGv t0;
3971
    gen_set_access_type(ctx, ACCESS_CACHE);
3972
    t0 = tcg_temp_new();
3973
    gen_addr_reg_index(ctx, t0);
3974
    gen_qemu_ld8u(ctx, t0, t0);
3975
    tcg_temp_free(t0);
3976
}
3977

    
3978
/* dcbt */
3979
static void gen_dcbt(DisasContext *ctx)
3980
{
3981
    /* interpreted as no-op */
3982
    /* XXX: specification say this is treated as a load by the MMU
3983
     *      but does not generate any exception
3984
     */
3985
}
3986

    
3987
/* dcbtst */
3988
static void gen_dcbtst(DisasContext *ctx)
3989
{
3990
    /* interpreted as no-op */
3991
    /* XXX: specification say this is treated as a load by the MMU
3992
     *      but does not generate any exception
3993
     */
3994
}
3995

    
3996
/* dcbz */
3997
static void gen_dcbz(DisasContext *ctx)
3998
{
3999
    TCGv t0;
4000
    gen_set_access_type(ctx, ACCESS_CACHE);
4001
    /* NIP cannot be restored if the memory exception comes from an helper */
4002
    gen_update_nip(ctx, ctx->nip - 4);
4003
    t0 = tcg_temp_new();
4004
    gen_addr_reg_index(ctx, t0);
4005
    gen_helper_dcbz(t0);
4006
    tcg_temp_free(t0);
4007
}
4008

    
4009
static void gen_dcbz_970(DisasContext *ctx)
4010
{
4011
    TCGv t0;
4012
    gen_set_access_type(ctx, ACCESS_CACHE);
4013
    /* NIP cannot be restored if the memory exception comes from an helper */
4014
    gen_update_nip(ctx, ctx->nip - 4);
4015
    t0 = tcg_temp_new();
4016
    gen_addr_reg_index(ctx, t0);
4017
    if (ctx->opcode & 0x00200000)
4018
        gen_helper_dcbz(t0);
4019
    else
4020
        gen_helper_dcbz_970(t0);
4021
    tcg_temp_free(t0);
4022
}
4023

    
4024
/* dst / dstt */
4025
static void gen_dst(DisasContext *ctx)
4026
{
4027
    if (rA(ctx->opcode) == 0) {
4028
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4029
    } else {
4030
        /* interpreted as no-op */
4031
    }
4032
}
4033

    
4034
/* dstst /dststt */
4035
static void gen_dstst(DisasContext *ctx)
4036
{
4037
    if (rA(ctx->opcode) == 0) {
4038
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4039
    } else {
4040
        /* interpreted as no-op */
4041
    }
4042

    
4043
}
4044

    
4045
/* dss / dssall */
4046
static void gen_dss(DisasContext *ctx)
4047
{
4048
    /* interpreted as no-op */
4049
}
4050

    
4051
/* icbi */
4052
static void gen_icbi(DisasContext *ctx)
4053
{
4054
    TCGv t0;
4055
    gen_set_access_type(ctx, ACCESS_CACHE);
4056
    /* NIP cannot be restored if the memory exception comes from an helper */
4057
    gen_update_nip(ctx, ctx->nip - 4);
4058
    t0 = tcg_temp_new();
4059
    gen_addr_reg_index(ctx, t0);
4060
    gen_helper_icbi(t0);
4061
    tcg_temp_free(t0);
4062
}
4063

    
4064
/* Optional: */
4065
/* dcba */
4066
static void gen_dcba(DisasContext *ctx)
4067
{
4068
    /* interpreted as no-op */
4069
    /* XXX: specification say this is treated as a store by the MMU
4070
     *      but does not generate any exception
4071
     */
4072
}
4073

    
4074
/***                    Segment register manipulation                      ***/
4075
/* Supervisor only: */
4076

    
4077
/* mfsr */
4078
static void gen_mfsr(DisasContext *ctx)
4079
{
4080
#if defined(CONFIG_USER_ONLY)
4081
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4082
#else
4083
    TCGv t0;
4084
    if (unlikely(!ctx->mem_idx)) {
4085
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4086
        return;
4087
    }
4088
    t0 = tcg_const_tl(SR(ctx->opcode));
4089
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4090
    tcg_temp_free(t0);
4091
#endif
4092
}
4093

    
4094
/* mfsrin */
4095
static void gen_mfsrin(DisasContext *ctx)
4096
{
4097
#if defined(CONFIG_USER_ONLY)
4098
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4099
#else
4100
    TCGv t0;
4101
    if (unlikely(!ctx->mem_idx)) {
4102
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4103
        return;
4104
    }
4105
    t0 = tcg_temp_new();
4106
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4107
    tcg_gen_andi_tl(t0, t0, 0xF);
4108
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4109
    tcg_temp_free(t0);
4110
#endif
4111
}
4112

    
4113
/* mtsr */
4114
static void gen_mtsr(DisasContext *ctx)
4115
{
4116
#if defined(CONFIG_USER_ONLY)
4117
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4118
#else
4119
    TCGv t0;
4120
    if (unlikely(!ctx->mem_idx)) {
4121
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4122
        return;
4123
    }
4124
    t0 = tcg_const_tl(SR(ctx->opcode));
4125
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4126
    tcg_temp_free(t0);
4127
#endif
4128
}
4129

    
4130
/* mtsrin */
4131
static void gen_mtsrin(DisasContext *ctx)
4132
{
4133
#if defined(CONFIG_USER_ONLY)
4134
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4135
#else
4136
    TCGv t0;
4137
    if (unlikely(!ctx->mem_idx)) {
4138
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4139
        return;
4140
    }
4141
    t0 = tcg_temp_new();
4142
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4143
    tcg_gen_andi_tl(t0, t0, 0xF);
4144
    gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4145
    tcg_temp_free(t0);
4146
#endif
4147
}
4148

    
4149
#if defined(TARGET_PPC64)
4150
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4151

    
4152
/* mfsr */
4153
static void gen_mfsr_64b(DisasContext *ctx)
4154
{
4155
#if defined(CONFIG_USER_ONLY)
4156
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4157
#else
4158
    TCGv t0;
4159
    if (unlikely(!ctx->mem_idx)) {
4160
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4161
        return;
4162
    }
4163
    t0 = tcg_const_tl(SR(ctx->opcode));
4164
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4165
    tcg_temp_free(t0);
4166
#endif
4167
}
4168

    
4169
/* mfsrin */
4170
static void gen_mfsrin_64b(DisasContext *ctx)
4171
{
4172
#if defined(CONFIG_USER_ONLY)
4173
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4174
#else
4175
    TCGv t0;
4176
    if (unlikely(!ctx->mem_idx)) {
4177
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4178
        return;
4179
    }
4180
    t0 = tcg_temp_new();
4181
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4182
    tcg_gen_andi_tl(t0, t0, 0xF);
4183
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4184
    tcg_temp_free(t0);
4185
#endif
4186
}
4187

    
4188
/* mtsr */
4189
static void gen_mtsr_64b(DisasContext *ctx)
4190
{
4191
#if defined(CONFIG_USER_ONLY)
4192
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4193
#else
4194
    TCGv t0;
4195
    if (unlikely(!ctx->mem_idx)) {
4196
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4197
        return;
4198
    }
4199
    t0 = tcg_const_tl(SR(ctx->opcode));
4200
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4201
    tcg_temp_free(t0);
4202
#endif
4203
}
4204

    
4205
/* mtsrin */
4206
static void gen_mtsrin_64b(DisasContext *ctx)
4207
{
4208
#if defined(CONFIG_USER_ONLY)
4209
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4210
#else
4211
    TCGv t0;
4212
    if (unlikely(!ctx->mem_idx)) {
4213
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4214
        return;
4215
    }
4216
    t0 = tcg_temp_new();
4217
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4218
    tcg_gen_andi_tl(t0, t0, 0xF);
4219
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4220
    tcg_temp_free(t0);
4221
#endif
4222
}
4223

    
4224
/* slbmte */
4225
static void gen_slbmte(DisasContext *ctx)
4226
{
4227
#if defined(CONFIG_USER_ONLY)
4228
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4229
#else
4230
    if (unlikely(!ctx->mem_idx)) {
4231
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232
        return;
4233
    }
4234
    gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4235
#endif
4236
}
4237

    
4238
static void gen_slbmfee(DisasContext *ctx)
4239
{
4240
#if defined(CONFIG_USER_ONLY)
4241
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4242
#else
4243
    if (unlikely(!ctx->mem_idx)) {
4244
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4245
        return;
4246
    }
4247
    gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4248
                             cpu_gpr[rB(ctx->opcode)]);
4249
#endif
4250
}
4251

    
4252
static void gen_slbmfev(DisasContext *ctx)
4253
{
4254
#if defined(CONFIG_USER_ONLY)
4255
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4256
#else
4257
    if (unlikely(!ctx->mem_idx)) {
4258
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259
        return;
4260
    }
4261
    gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4262
                             cpu_gpr[rB(ctx->opcode)]);
4263
#endif
4264
}
4265
#endif /* defined(TARGET_PPC64) */
4266

    
4267
/***                      Lookaside buffer management                      ***/
4268
/* Optional & mem_idx only: */
4269

    
4270
/* tlbia */
4271
static void gen_tlbia(DisasContext *ctx)
4272
{
4273
#if defined(CONFIG_USER_ONLY)
4274
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4275
#else
4276
    if (unlikely(!ctx->mem_idx)) {
4277
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4278
        return;
4279
    }
4280
    gen_helper_tlbia();
4281
#endif
4282
}
4283

    
4284
/* tlbiel */
4285
static void gen_tlbiel(DisasContext *ctx)
4286
{
4287
#if defined(CONFIG_USER_ONLY)
4288
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4289
#else
4290
    if (unlikely(!ctx->mem_idx)) {
4291
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4292
        return;
4293
    }
4294
    gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4295
#endif
4296
}
4297

    
4298
/* tlbie */
4299
static void gen_tlbie(DisasContext *ctx)
4300
{
4301
#if defined(CONFIG_USER_ONLY)
4302
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4303
#else
4304
    if (unlikely(!ctx->mem_idx)) {
4305
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4306
        return;
4307
    }
4308
#if defined(TARGET_PPC64)
4309
    if (!ctx->sf_mode) {
4310
        TCGv t0 = tcg_temp_new();
4311
        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4312
        gen_helper_tlbie(t0);
4313
        tcg_temp_free(t0);
4314
    } else
4315
#endif
4316
        gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4317
#endif
4318
}
4319

    
4320
/* tlbsync */
4321
static void gen_tlbsync(DisasContext *ctx)
4322
{
4323
#if defined(CONFIG_USER_ONLY)
4324
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4325
#else
4326
    if (unlikely(!ctx->mem_idx)) {
4327
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4328
        return;
4329
    }
4330
    /* This has no effect: it should ensure that all previous
4331
     * tlbie have completed
4332
     */
4333
    gen_stop_exception(ctx);
4334
#endif
4335
}
4336

    
4337
#if defined(TARGET_PPC64)
4338
/* slbia */
4339
static void gen_slbia(DisasContext *ctx)
4340
{
4341
#if defined(CONFIG_USER_ONLY)
4342
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343
#else
4344
    if (unlikely(!ctx->mem_idx)) {
4345
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346
        return;
4347
    }
4348
    gen_helper_slbia();
4349
#endif
4350
}
4351

    
4352
/* slbie */
4353
static void gen_slbie(DisasContext *ctx)
4354
{
4355
#if defined(CONFIG_USER_ONLY)
4356
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4357
#else
4358
    if (unlikely(!ctx->mem_idx)) {
4359
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4360
        return;
4361
    }
4362
    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4363
#endif
4364
}
4365
#endif
4366

    
4367
/***                              External control                         ***/
4368
/* Optional: */
4369

    
4370
/* eciwx */
4371
static void gen_eciwx(DisasContext *ctx)
4372
{
4373
    TCGv t0;
4374
    /* Should check EAR[E] ! */
4375
    gen_set_access_type(ctx, ACCESS_EXT);
4376
    t0 = tcg_temp_new();
4377
    gen_addr_reg_index(ctx, t0);
4378
    gen_check_align(ctx, t0, 0x03);
4379
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4380
    tcg_temp_free(t0);
4381
}
4382

    
4383
/* ecowx */
4384
static void gen_ecowx(DisasContext *ctx)
4385
{
4386
    TCGv t0;
4387
    /* Should check EAR[E] ! */
4388
    gen_set_access_type(ctx, ACCESS_EXT);
4389
    t0 = tcg_temp_new();
4390
    gen_addr_reg_index(ctx, t0);
4391
    gen_check_align(ctx, t0, 0x03);
4392
    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4393
    tcg_temp_free(t0);
4394
}
4395

    
4396
/* PowerPC 601 specific instructions */
4397

    
4398
/* abs - abs. */
4399
static void gen_abs(DisasContext *ctx)
4400
{
4401
    int l1 = gen_new_label();
4402
    int l2 = gen_new_label();
4403
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4404
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4405
    tcg_gen_br(l2);
4406
    gen_set_label(l1);
4407
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4408
    gen_set_label(l2);
4409
    if (unlikely(Rc(ctx->opcode) != 0))
4410
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4411
}
4412

    
4413
/* abso - abso. */
4414
static void gen_abso(DisasContext *ctx)
4415
{
4416
    int l1 = gen_new_label();
4417
    int l2 = gen_new_label();
4418
    int l3 = gen_new_label();
4419
    /* Start with XER OV disabled, the most likely case */
4420
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4421
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4422
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4423
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4424
    tcg_gen_br(l2);
4425
    gen_set_label(l1);
4426
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4427
    tcg_gen_br(l3);
4428
    gen_set_label(l2);
4429
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4430
    gen_set_label(l3);
4431
    if (unlikely(Rc(ctx->opcode) != 0))
4432
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4433
}
4434

    
4435
/* clcs */
4436
static void gen_clcs(DisasContext *ctx)
4437
{
4438
    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4439
    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4440
    tcg_temp_free_i32(t0);
4441
    /* Rc=1 sets CR0 to an undefined state */
4442
}
4443

    
4444
/* div - div. */
4445
static void gen_div(DisasContext *ctx)
4446
{
4447
    gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4448
    if (unlikely(Rc(ctx->opcode) != 0))
4449
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4450
}
4451

    
4452
/* divo - divo. */
4453
static void gen_divo(DisasContext *ctx)
4454
{
4455
    gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4456
    if (unlikely(Rc(ctx->opcode) != 0))
4457
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4458
}
4459

    
4460
/* divs - divs. */
4461
static void gen_divs(DisasContext *ctx)
4462
{
4463
    gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4464
    if (unlikely(Rc(ctx->opcode) != 0))
4465
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4466
}
4467

    
4468
/* divso - divso. */
4469
static void gen_divso(DisasContext *ctx)
4470
{
4471
    gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4472
    if (unlikely(Rc(ctx->opcode) != 0))
4473
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4474
}
4475

    
4476
/* doz - doz. */
4477
static void gen_doz(DisasContext *ctx)
4478
{
4479
    int l1 = gen_new_label();
4480
    int l2 = gen_new_label();
4481
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4482
    tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4483
    tcg_gen_br(l2);
4484
    gen_set_label(l1);
4485
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4486
    gen_set_label(l2);
4487
    if (unlikely(Rc(ctx->opcode) != 0))
4488
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489
}
4490

    
4491
/* dozo - dozo. */
4492
static void gen_dozo(DisasContext *ctx)
4493
{
4494
    int l1 = gen_new_label();
4495
    int l2 = gen_new_label();
4496
    TCGv t0 = tcg_temp_new();
4497
    TCGv t1 = tcg_temp_new();
4498
    TCGv t2 = tcg_temp_new();
4499
    /* Start with XER OV disabled, the most likely case */
4500
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4501
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4502
    tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4503
    tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4504
    tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4505
    tcg_gen_andc_tl(t1, t1, t2);
4506
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4507
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4508
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4509
    tcg_gen_br(l2);
4510
    gen_set_label(l1);
4511
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4512
    gen_set_label(l2);
4513
    tcg_temp_free(t0);
4514
    tcg_temp_free(t1);
4515
    tcg_temp_free(t2);
4516
    if (unlikely(Rc(ctx->opcode) != 0))
4517
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4518
}
4519

    
4520
/* dozi */
4521
static void gen_dozi(DisasContext *ctx)
4522
{
4523
    target_long simm = SIMM(ctx->opcode);
4524
    int l1 = gen_new_label();
4525
    int l2 = gen_new_label();
4526
    tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4527
    tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4528
    tcg_gen_br(l2);
4529
    gen_set_label(l1);
4530
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4531
    gen_set_label(l2);
4532
    if (unlikely(Rc(ctx->opcode) != 0))
4533
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4534
}
4535

    
4536
/* lscbx - lscbx. */
4537
static void gen_lscbx(DisasContext *ctx)
4538
{
4539
    TCGv t0 = tcg_temp_new();
4540
    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4541
    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4542
    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4543

    
4544
    gen_addr_reg_index(ctx, t0);
4545
    /* NIP cannot be restored if the memory exception comes from an helper */
4546
    gen_update_nip(ctx, ctx->nip - 4);
4547
    gen_helper_lscbx(t0, t0, t1, t2, t3);
4548
    tcg_temp_free_i32(t1);
4549
    tcg_temp_free_i32(t2);
4550
    tcg_temp_free_i32(t3);
4551
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4552
    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4553
    if (unlikely(Rc(ctx->opcode) != 0))
4554
        gen_set_Rc0(ctx, t0);
4555
    tcg_temp_free(t0);
4556
}
4557

    
4558
/* maskg - maskg. */
4559
static void gen_maskg(DisasContext *ctx)
4560
{
4561
    int l1 = gen_new_label();
4562
    TCGv t0 = tcg_temp_new();
4563
    TCGv t1 = tcg_temp_new();
4564
    TCGv t2 = tcg_temp_new();
4565
    TCGv t3 = tcg_temp_new();
4566
    tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4567
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4568
    tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4569
    tcg_gen_addi_tl(t2, t0, 1);
4570
    tcg_gen_shr_tl(t2, t3, t2);
4571
    tcg_gen_shr_tl(t3, t3, t1);
4572
    tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4573
    tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4574
    tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4575
    gen_set_label(l1);
4576
    tcg_temp_free(t0);
4577
    tcg_temp_free(t1);
4578
    tcg_temp_free(t2);
4579
    tcg_temp_free(t3);
4580
    if (unlikely(Rc(ctx->opcode) != 0))
4581
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4582
}
4583

    
4584
/* maskir - maskir. */
4585
static void gen_maskir(DisasContext *ctx)
4586
{
4587
    TCGv t0 = tcg_temp_new();
4588
    TCGv t1 = tcg_temp_new();
4589
    tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4590
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4591
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4592
    tcg_temp_free(t0);
4593
    tcg_temp_free(t1);
4594
    if (unlikely(Rc(ctx->opcode) != 0))
4595
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4596
}
4597

    
4598
/* mul - mul. */
4599
static void gen_mul(DisasContext *ctx)
4600
{
4601
    TCGv_i64 t0 = tcg_temp_new_i64();
4602
    TCGv_i64 t1 = tcg_temp_new_i64();
4603
    TCGv t2 = tcg_temp_new();
4604
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4605
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4606
    tcg_gen_mul_i64(t0, t0, t1);
4607
    tcg_gen_trunc_i64_tl(t2, t0);
4608
    gen_store_spr(SPR_MQ, t2);
4609
    tcg_gen_shri_i64(t1, t0, 32);
4610
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4611
    tcg_temp_free_i64(t0);
4612
    tcg_temp_free_i64(t1);
4613
    tcg_temp_free(t2);
4614
    if (unlikely(Rc(ctx->opcode) != 0))
4615
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4616
}
4617

    
4618
/* mulo - mulo. */
4619
static void gen_mulo(DisasContext *ctx)
4620
{
4621
    int l1 = gen_new_label();
4622
    TCGv_i64 t0 = tcg_temp_new_i64();
4623
    TCGv_i64 t1 = tcg_temp_new_i64();
4624
    TCGv t2 = tcg_temp_new();
4625
    /* Start with XER OV disabled, the most likely case */
4626
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4627
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4628
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4629
    tcg_gen_mul_i64(t0, t0, t1);
4630
    tcg_gen_trunc_i64_tl(t2, t0);
4631
    gen_store_spr(SPR_MQ, t2);
4632
    tcg_gen_shri_i64(t1, t0, 32);
4633
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4634
    tcg_gen_ext32s_i64(t1, t0);
4635
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4636
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4637
    gen_set_label(l1);
4638
    tcg_temp_free_i64(t0);
4639
    tcg_temp_free_i64(t1);
4640
    tcg_temp_free(t2);
4641
    if (unlikely(Rc(ctx->opcode) != 0))
4642
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4643
}
4644

    
4645
/* nabs - nabs. */
4646
static void gen_nabs(DisasContext *ctx)
4647
{
4648
    int l1 = gen_new_label();
4649
    int l2 = gen_new_label();
4650
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4651
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4652
    tcg_gen_br(l2);
4653
    gen_set_label(l1);
4654
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4655
    gen_set_label(l2);
4656
    if (unlikely(Rc(ctx->opcode) != 0))
4657
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4658
}
4659

    
4660
/* nabso - nabso. */
4661
static void gen_nabso(DisasContext *ctx)
4662
{
4663
    int l1 = gen_new_label();
4664
    int l2 = gen_new_label();
4665
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4666
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4667
    tcg_gen_br(l2);
4668
    gen_set_label(l1);
4669
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4670
    gen_set_label(l2);
4671
    /* nabs never overflows */
4672
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4673
    if (unlikely(Rc(ctx->opcode) != 0))
4674
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4675
}
4676

    
4677
/* rlmi - rlmi. */
4678
static void gen_rlmi(DisasContext *ctx)
4679
{
4680
    uint32_t mb = MB(ctx->opcode);
4681
    uint32_t me = ME(ctx->opcode);
4682
    TCGv t0 = tcg_temp_new();
4683
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4684
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4685
    tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4686
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4687
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4688
    tcg_temp_free(t0);
4689
    if (unlikely(Rc(ctx->opcode) != 0))
4690
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4691
}
4692

    
4693
/* rrib - rrib. */
4694
static void gen_rrib(DisasContext *ctx)
4695
{
4696
    TCGv t0 = tcg_temp_new();
4697
    TCGv t1 = tcg_temp_new();
4698
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4699
    tcg_gen_movi_tl(t1, 0x80000000);
4700
    tcg_gen_shr_tl(t1, t1, t0);
4701
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4702
    tcg_gen_and_tl(t0, t0, t1);
4703
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4704
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4705
    tcg_temp_free(t0);
4706
    tcg_temp_free(t1);
4707
    if (unlikely(Rc(ctx->opcode) != 0))
4708
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4709
}
4710

    
4711
/* sle - sle. */
4712
static void gen_sle(DisasContext *ctx)
4713
{
4714
    TCGv t0 = tcg_temp_new();
4715
    TCGv t1 = tcg_temp_new();
4716
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4717
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4718
    tcg_gen_subfi_tl(t1, 32, t1);
4719
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4720
    tcg_gen_or_tl(t1, t0, t1);
4721
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4722
    gen_store_spr(SPR_MQ, t1);
4723
    tcg_temp_free(t0);
4724
    tcg_temp_free(t1);
4725
    if (unlikely(Rc(ctx->opcode) != 0))
4726
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4727
}
4728

    
4729
/* sleq - sleq. */
4730
static void gen_sleq(DisasContext *ctx)
4731
{
4732
    TCGv t0 = tcg_temp_new();
4733
    TCGv t1 = tcg_temp_new();
4734
    TCGv t2 = tcg_temp_new();
4735
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4736
    tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4737
    tcg_gen_shl_tl(t2, t2, t0);
4738
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4739
    gen_load_spr(t1, SPR_MQ);
4740
    gen_store_spr(SPR_MQ, t0);
4741
    tcg_gen_and_tl(t0, t0, t2);
4742
    tcg_gen_andc_tl(t1, t1, t2);
4743
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4744
    tcg_temp_free(t0);
4745
    tcg_temp_free(t1);
4746
    tcg_temp_free(t2);
4747
    if (unlikely(Rc(ctx->opcode) != 0))
4748
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4749
}
4750

    
4751
/* sliq - sliq. */
4752
static void gen_sliq(DisasContext *ctx)
4753
{
4754
    int sh = SH(ctx->opcode);
4755
    TCGv t0 = tcg_temp_new();
4756
    TCGv t1 = tcg_temp_new();
4757
    tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4758
    tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4759
    tcg_gen_or_tl(t1, t0, t1);
4760
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4761
    gen_store_spr(SPR_MQ, t1);
4762
    tcg_temp_free(t0);
4763
    tcg_temp_free(t1);
4764
    if (unlikely(Rc(ctx->opcode) != 0))
4765
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4766
}
4767

    
4768
/* slliq - slliq. */
4769
static void gen_slliq(DisasContext *ctx)
4770
{
4771
    int sh = SH(ctx->opcode);
4772
    TCGv t0 = tcg_temp_new();
4773
    TCGv t1 = tcg_temp_new();
4774
    tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4775
    gen_load_spr(t1, SPR_MQ);
4776
    gen_store_spr(SPR_MQ, t0);
4777
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
4778
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4779
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4780
    tcg_temp_free(t0);
4781
    tcg_temp_free(t1);
4782
    if (unlikely(Rc(ctx->opcode) != 0))
4783
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4784
}
4785

    
4786
/* sllq - sllq. */
4787
static void gen_sllq(DisasContext *ctx)
4788
{
4789
    int l1 = gen_new_label();
4790
    int l2 = gen_new_label();
4791
    TCGv t0 = tcg_temp_local_new();
4792
    TCGv t1 = tcg_temp_local_new();
4793
    TCGv t2 = tcg_temp_local_new();
4794
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4795
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4796
    tcg_gen_shl_tl(t1, t1, t2);
4797
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4798
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4799
    gen_load_spr(t0, SPR_MQ);
4800
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4801
    tcg_gen_br(l2);
4802
    gen_set_label(l1);
4803
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4804
    gen_load_spr(t2, SPR_MQ);
4805
    tcg_gen_andc_tl(t1, t2, t1);
4806
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4807
    gen_set_label(l2);
4808
    tcg_temp_free(t0);
4809
    tcg_temp_free(t1);
4810
    tcg_temp_free(t2);
4811
    if (unlikely(Rc(ctx->opcode) != 0))
4812
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4813
}
4814

    
4815
/* slq - slq. */
4816
static void gen_slq(DisasContext *ctx)
4817
{
4818
    int l1 = gen_new_label();
4819
    TCGv t0 = tcg_temp_new();
4820
    TCGv t1 = tcg_temp_new();
4821
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4823
    tcg_gen_subfi_tl(t1, 32, t1);
4824
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4825
    tcg_gen_or_tl(t1, t0, t1);
4826
    gen_store_spr(SPR_MQ, t1);
4827
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4828
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4829
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4830
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4831
    gen_set_label(l1);
4832
    tcg_temp_free(t0);
4833
    tcg_temp_free(t1);
4834
    if (unlikely(Rc(ctx->opcode) != 0))
4835
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4836
}
4837

    
4838
/* sraiq - sraiq. */
4839
static void gen_sraiq(DisasContext *ctx)
4840
{
4841
    int sh = SH(ctx->opcode);
4842
    int l1 = gen_new_label();
4843
    TCGv t0 = tcg_temp_new();
4844
    TCGv t1 = tcg_temp_new();
4845
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4846
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4847
    tcg_gen_or_tl(t0, t0, t1);
4848
    gen_store_spr(SPR_MQ, t0);
4849
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4850
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4851
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4852
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4853
    gen_set_label(l1);
4854
    tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4855
    tcg_temp_free(t0);
4856
    tcg_temp_free(t1);
4857
    if (unlikely(Rc(ctx->opcode) != 0))
4858
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4859
}
4860

    
4861
/* sraq - sraq. */
4862
static void gen_sraq(DisasContext *ctx)
4863
{
4864
    int l1 = gen_new_label();
4865
    int l2 = gen_new_label();
4866
    TCGv t0 = tcg_temp_new();
4867
    TCGv t1 = tcg_temp_local_new();
4868
    TCGv t2 = tcg_temp_local_new();
4869
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4870
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4871
    tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4872
    tcg_gen_subfi_tl(t2, 32, t2);
4873
    tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4874
    tcg_gen_or_tl(t0, t0, t2);
4875
    gen_store_spr(SPR_MQ, t0);
4876
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4877
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4878
    tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4879
    tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4880
    gen_set_label(l1);
4881
    tcg_temp_free(t0);
4882
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4883
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4884
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4885
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4886
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4887
    gen_set_label(l2);
4888
    tcg_temp_free(t1);
4889
    tcg_temp_free(t2);
4890
    if (unlikely(Rc(ctx->opcode) != 0))
4891
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4892
}
4893

    
4894
/* sre - sre. */
4895
static void gen_sre(DisasContext *ctx)
4896
{
4897
    TCGv t0 = tcg_temp_new();
4898
    TCGv t1 = tcg_temp_new();
4899
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4900
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4901
    tcg_gen_subfi_tl(t1, 32, t1);
4902
    tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4903
    tcg_gen_or_tl(t1, t0, t1);
4904
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4905
    gen_store_spr(SPR_MQ, t1);
4906
    tcg_temp_free(t0);
4907
    tcg_temp_free(t1);
4908
    if (unlikely(Rc(ctx->opcode) != 0))
4909
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4910
}
4911

    
4912
/* srea - srea. */
4913
static void gen_srea(DisasContext *ctx)
4914
{
4915
    TCGv t0 = tcg_temp_new();
4916
    TCGv t1 = tcg_temp_new();
4917
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4918
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4919
    gen_store_spr(SPR_MQ, t0);
4920
    tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4921
    tcg_temp_free(t0);
4922
    tcg_temp_free(t1);
4923
    if (unlikely(Rc(ctx->opcode) != 0))
4924
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4925
}
4926

    
4927
/* sreq */
4928
static void gen_sreq(DisasContext *ctx)
4929
{
4930
    TCGv t0 = tcg_temp_new();
4931
    TCGv t1 = tcg_temp_new();
4932
    TCGv t2 = tcg_temp_new();
4933
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4934
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4935
    tcg_gen_shr_tl(t1, t1, t0);
4936
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4937
    gen_load_spr(t2, SPR_MQ);
4938
    gen_store_spr(SPR_MQ, t0);
4939
    tcg_gen_and_tl(t0, t0, t1);
4940
    tcg_gen_andc_tl(t2, t2, t1);
4941
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4942
    tcg_temp_free(t0);
4943
    tcg_temp_free(t1);
4944
    tcg_temp_free(t2);
4945
    if (unlikely(Rc(ctx->opcode) != 0))
4946
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4947
}
4948

    
4949
/* sriq */
4950
static void gen_sriq(DisasContext *ctx)
4951
{
4952
    int sh = SH(ctx->opcode);
4953
    TCGv t0 = tcg_temp_new();
4954
    TCGv t1 = tcg_temp_new();
4955
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4956
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4957
    tcg_gen_or_tl(t1, t0, t1);
4958
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4959
    gen_store_spr(SPR_MQ, t1);
4960
    tcg_temp_free(t0);
4961
    tcg_temp_free(t1);
4962
    if (unlikely(Rc(ctx->opcode) != 0))
4963
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4964
}
4965

    
4966
/* srliq */
4967
static void gen_srliq(DisasContext *ctx)
4968
{
4969
    int sh = SH(ctx->opcode);
4970
    TCGv t0 = tcg_temp_new();
4971
    TCGv t1 = tcg_temp_new();
4972
    tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4973
    gen_load_spr(t1, SPR_MQ);
4974
    gen_store_spr(SPR_MQ, t0);
4975
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU >> sh));
4976
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4977
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4978
    tcg_temp_free(t0);
4979
    tcg_temp_free(t1);
4980
    if (unlikely(Rc(ctx->opcode) != 0))
4981
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4982
}
4983

    
4984
/* srlq */
4985
static void gen_srlq(DisasContext *ctx)
4986
{
4987
    int l1 = gen_new_label();
4988
    int l2 = gen_new_label();
4989
    TCGv t0 = tcg_temp_local_new();
4990
    TCGv t1 = tcg_temp_local_new();
4991
    TCGv t2 = tcg_temp_local_new();
4992
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4993
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4994
    tcg_gen_shr_tl(t2, t1, t2);
4995
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4996
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4997
    gen_load_spr(t0, SPR_MQ);
4998
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4999
    tcg_gen_br(l2);
5000
    gen_set_label(l1);
5001
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5002
    tcg_gen_and_tl(t0, t0, t2);
5003
    gen_load_spr(t1, SPR_MQ);
5004
    tcg_gen_andc_tl(t1, t1, t2);
5005
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5006
    gen_set_label(l2);
5007
    tcg_temp_free(t0);
5008
    tcg_temp_free(t1);
5009
    tcg_temp_free(t2);
5010
    if (unlikely(Rc(ctx->opcode) != 0))
5011
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5012
}
5013

    
5014
/* srq */
5015
static void gen_srq(DisasContext *ctx)
5016
{
5017
    int l1 = gen_new_label();
5018
    TCGv t0 = tcg_temp_new();
5019
    TCGv t1 = tcg_temp_new();