Revision eacc3249
| b/target-ppc/helper.c | ||
|---|---|---|
| 601 | 601 |
} |
| 602 | 602 |
|
| 603 | 603 |
#if defined(TARGET_PPC64) |
| 604 |
static inline int slb_is_valid (uint64_t slb64) |
|
| 605 |
{
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|
| 606 |
return slb64 & 0x0000000008000000ULL ? 1 : 0; |
|
| 607 |
} |
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| 608 |
|
|
| 609 |
static inline void slb_invalidate (uint64_t *slb64) |
|
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{
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|
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*slb64 &= ~0x0000000008000000ULL; |
|
| 612 |
} |
|
| 613 |
|
|
| 604 | 614 |
static int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
| 605 | 615 |
target_ulong *vsid, target_ulong *page_mask, int *attr) |
| 606 | 616 |
{
|
| ... | ... | |
| 609 | 619 |
uint64_t tmp64; |
| 610 | 620 |
uint32_t tmp; |
| 611 | 621 |
int n, ret; |
| 612 |
int slb_nr; |
|
| 613 | 622 |
|
| 614 | 623 |
ret = -5; |
| 615 | 624 |
sr_base = env->spr[SPR_ASR]; |
| ... | ... | |
| 620 | 629 |
} |
| 621 | 630 |
#endif |
| 622 | 631 |
mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
| 623 |
slb_nr = env->slb_nr; |
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for (n = 0; n < slb_nr; n++) {
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| 632 |
for (n = 0; n < env->slb_nr; n++) {
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|
| 625 | 633 |
tmp64 = ldq_phys(sr_base); |
| 626 | 634 |
tmp = ldl_phys(sr_base + 8); |
| 627 | 635 |
#if defined(DEBUG_SLB) |
| ... | ... | |
| 630 | 638 |
PRIx32 "\n", __func__, n, sr_base, tmp64, tmp); |
| 631 | 639 |
} |
| 632 | 640 |
#endif |
| 633 |
if (tmp64 & 0x0000000008000000ULL) {
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| 641 |
if (slb_is_valid(tmp64)) {
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|
| 634 | 642 |
/* SLB entry is valid */ |
| 635 | 643 |
switch (tmp64 & 0x0000000006000000ULL) {
|
| 636 | 644 |
case 0x0000000000000000ULL: |
| ... | ... | |
| 651 | 659 |
*vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
| 652 | 660 |
*page_mask = ~mask; |
| 653 | 661 |
*attr = tmp & 0xFF; |
| 654 |
ret = 0;
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ret = n;
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|
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break; |
| 656 | 664 |
} |
| 657 | 665 |
} |
| ... | ... | |
| 661 | 669 |
return ret; |
| 662 | 670 |
} |
| 663 | 671 |
|
| 672 |
void ppc_slb_invalidate_all (CPUPPCState *env) |
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{
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target_phys_addr_t sr_base; |
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uint64_t tmp64; |
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int n, do_invalidate; |
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do_invalidate = 0; |
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sr_base = env->spr[SPR_ASR]; |
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for (n = 0; n < env->slb_nr; n++) {
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| 681 |
tmp64 = ldq_phys(sr_base); |
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if (slb_is_valid(tmp64)) {
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| 683 |
slb_invalidate(&tmp64); |
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stq_phys(sr_base, tmp64); |
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| 685 |
/* XXX: given the fact that segment size is 256 MB or 1TB, |
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| 686 |
* and we still don't have a tlb_flush_mask(env, n, mask) |
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| 687 |
* in Qemu, we just invalidate all TLBs |
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*/ |
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do_invalidate = 1; |
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} |
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sr_base += 12; |
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} |
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if (do_invalidate) |
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tlb_flush(env, 1); |
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} |
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|
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void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) |
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{
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| 699 |
target_phys_addr_t sr_base; |
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target_ulong vsid, page_mask; |
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uint64_t tmp64; |
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int attr; |
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int n; |
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| 704 |
|
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n = slb_lookup(env, T0, &vsid, &page_mask, &attr); |
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if (n >= 0) {
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| 707 |
sr_base = env->spr[SPR_ASR]; |
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sr_base += 12 * n; |
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tmp64 = ldq_phys(sr_base); |
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if (slb_is_valid(tmp64)) {
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| 711 |
slb_invalidate(&tmp64); |
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| 712 |
stq_phys(sr_base, tmp64); |
|
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/* XXX: given the fact that segment size is 256 MB or 1TB, |
|
| 714 |
* and we still don't have a tlb_flush_mask(env, n, mask) |
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| 715 |
* in Qemu, we just invalidate all TLBs |
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| 716 |
*/ |
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| 717 |
tlb_flush(env, 1); |
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| 718 |
} |
|
| 719 |
} |
|
| 720 |
} |
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| 721 |
|
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| 664 | 722 |
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) |
| 665 | 723 |
{
|
| 666 | 724 |
target_phys_addr_t sr_base; |
| ... | ... | |
| 1828 | 1886 |
#endif |
| 1829 | 1887 |
} |
| 1830 | 1888 |
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| 1831 |
#if defined(TARGET_PPC64) |
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| 1832 |
void ppc_slb_invalidate_all (CPUPPCState *env) |
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{
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| 1834 |
/* XXX: TODO */ |
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| 1835 |
tlb_flush(env, 1); |
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| 1836 |
} |
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| 1837 |
|
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| 1838 |
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) |
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| 1839 |
{
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| 1840 |
/* XXX: TODO */ |
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| 1841 |
tlb_flush(env, 1); |
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| 1842 |
} |
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| 1843 |
#endif |
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| 1844 |
|
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| 1845 | 1889 |
/*****************************************************************************/ |
| 1846 | 1890 |
/* Special registers manipulation */ |
| 1847 | 1891 |
#if defined(TARGET_PPC64) |
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