Revision ead9360e target-mips/op_helper.c
b/target-mips/op_helper.c | ||
---|---|---|
160 | 160 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
161 | 161 |
static inline uint64_t get_HILO (void) |
162 | 162 |
{ |
163 |
return (env->HI << 32) | (uint32_t)env->LO;
|
|
163 |
return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
|
|
164 | 164 |
} |
165 | 165 |
|
166 | 166 |
static inline void set_HILO (uint64_t HILO) |
167 | 167 |
{ |
168 |
env->LO = (int32_t)HILO; |
|
169 |
env->HI = (int32_t)(HILO >> 32); |
|
168 |
env->LO[0][env->current_tc] = (int32_t)HILO;
|
|
169 |
env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
|
|
170 | 170 |
} |
171 | 171 |
|
172 | 172 |
void do_mult (void) |
... | ... | |
217 | 217 |
{ |
218 | 218 |
/* 64bit datatypes because we may see overflow/underflow. */ |
219 | 219 |
if (T1 != 0) { |
220 |
env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1); |
|
221 |
env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1); |
|
220 |
env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
|
|
221 |
env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
|
|
222 | 222 |
} |
223 | 223 |
} |
224 | 224 |
#endif |
... | ... | |
228 | 228 |
{ |
229 | 229 |
if (T1 != 0) { |
230 | 230 |
lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
231 |
env->LO = res.quot; |
|
232 |
env->HI = res.rem; |
|
231 |
env->LO[0][env->current_tc] = res.quot;
|
|
232 |
env->HI[0][env->current_tc] = res.rem;
|
|
233 | 233 |
} |
234 | 234 |
} |
235 | 235 |
|
... | ... | |
237 | 237 |
void do_ddivu (void) |
238 | 238 |
{ |
239 | 239 |
if (T1 != 0) { |
240 |
env->LO = T0 / T1; |
|
241 |
env->HI = T0 % T1; |
|
240 |
env->LO[0][env->current_tc] = T0 / T1;
|
|
241 |
env->HI[0][env->current_tc] = T0 % T1;
|
|
242 | 242 |
} |
243 | 243 |
} |
244 | 244 |
#endif |
... | ... | |
316 | 316 |
void fpu_handle_exception(void) |
317 | 317 |
{ |
318 | 318 |
#ifdef CONFIG_SOFTFLOAT |
319 |
int flags = get_float_exception_flags(&env->fp_status); |
|
319 |
int flags = get_float_exception_flags(&env->fpu->fp_status);
|
|
320 | 320 |
unsigned int cpuflags = 0, enable, cause = 0; |
321 | 321 |
|
322 |
enable = GET_FP_ENABLE(env->fcr31); |
|
322 |
enable = GET_FP_ENABLE(env->fpu->fcr31);
|
|
323 | 323 |
|
324 | 324 |
/* determine current flags */ |
325 | 325 |
if (flags & float_flag_invalid) { |
... | ... | |
342 | 342 |
cpuflags |= FP_INEXACT; |
343 | 343 |
cause |= FP_INEXACT & enable; |
344 | 344 |
} |
345 |
SET_FP_FLAGS(env->fcr31, cpuflags); |
|
346 |
SET_FP_CAUSE(env->fcr31, cause); |
|
345 |
SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
|
|
346 |
SET_FP_CAUSE(env->fpu->fcr31, cause);
|
|
347 | 347 |
#else |
348 |
SET_FP_FLAGS(env->fcr31, 0); |
|
349 |
SET_FP_CAUSE(env->fcr31, 0); |
|
348 |
SET_FP_FLAGS(env->fpu->fcr31, 0);
|
|
349 |
SET_FP_CAUSE(env->fpu->fcr31, 0);
|
|
350 | 350 |
#endif |
351 | 351 |
} |
352 | 352 |
|
... | ... | |
355 | 355 |
{ |
356 | 356 |
/* Flush qemu's TLB and discard all shadowed entries. */ |
357 | 357 |
tlb_flush (env, flush_global); |
358 |
env->tlb_in_use = env->nb_tlb;
|
|
358 |
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
|
359 | 359 |
} |
360 | 360 |
|
361 | 361 |
static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
362 | 362 |
{ |
363 | 363 |
/* Discard entries from env->tlb[first] onwards. */ |
364 |
while (env->tlb_in_use > first) { |
|
365 |
r4k_invalidate_tlb(env, --env->tlb_in_use, 0); |
|
364 |
while (env->tlb->tlb_in_use > first) {
|
|
365 |
r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
|
366 | 366 |
} |
367 | 367 |
} |
368 | 368 |
|
... | ... | |
371 | 371 |
r4k_tlb_t *tlb; |
372 | 372 |
|
373 | 373 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
374 |
tlb = &env->mmu.r4k.tlb[idx]; |
|
374 |
tlb = &env->tlb->mmu.r4k.tlb[idx];
|
|
375 | 375 |
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
376 | 376 |
#ifdef TARGET_MIPS64 |
377 | 377 |
tlb->VPN &= env->SEGMask; |
... | ... | |
394 | 394 |
/* Discard cached TLB entries. We could avoid doing this if the |
395 | 395 |
tlbwi is just upgrading access permissions on the current entry; |
396 | 396 |
that might be a further win. */ |
397 |
r4k_mips_tlb_flush_extra (env, env->nb_tlb); |
|
397 |
r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
|
|
398 | 398 |
|
399 |
r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0); |
|
400 |
r4k_fill_tlb(env->CP0_Index % env->nb_tlb); |
|
399 |
r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
|
400 |
r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
|
|
401 | 401 |
} |
402 | 402 |
|
403 | 403 |
void r4k_do_tlbwr (void) |
... | ... | |
418 | 418 |
int i; |
419 | 419 |
|
420 | 420 |
ASID = env->CP0_EntryHi & 0xFF; |
421 |
for (i = 0; i < env->nb_tlb; i++) { |
|
422 |
tlb = &env->mmu.r4k.tlb[i]; |
|
421 |
for (i = 0; i < env->tlb->nb_tlb; i++) {
|
|
422 |
tlb = &env->tlb->mmu.r4k.tlb[i];
|
|
423 | 423 |
/* 1k pages are not supported. */ |
424 | 424 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
425 | 425 |
tag = env->CP0_EntryHi & ~mask; |
... | ... | |
431 | 431 |
break; |
432 | 432 |
} |
433 | 433 |
} |
434 |
if (i == env->nb_tlb) { |
|
434 |
if (i == env->tlb->nb_tlb) {
|
|
435 | 435 |
/* No match. Discard any shadow entries, if any of them match. */ |
436 |
for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
|
|
437 |
tlb = &env->mmu.r4k.tlb[i]; |
|
436 |
for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
|
437 |
tlb = &env->tlb->mmu.r4k.tlb[i];
|
|
438 | 438 |
/* 1k pages are not supported. */ |
439 | 439 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
440 | 440 |
tag = env->CP0_EntryHi & ~mask; |
... | ... | |
456 | 456 |
uint8_t ASID; |
457 | 457 |
|
458 | 458 |
ASID = env->CP0_EntryHi & 0xFF; |
459 |
tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];
|
|
459 |
tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
|
|
460 | 460 |
|
461 | 461 |
/* If this will change the current ASID, flush qemu's TLB. */ |
462 | 462 |
if (ASID != tlb->ASID) |
463 | 463 |
cpu_mips_tlb_flush (env, 1); |
464 | 464 |
|
465 |
r4k_mips_tlb_flush_extra(env, env->nb_tlb); |
|
465 |
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
|
|
466 | 466 |
|
467 | 467 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
468 | 468 |
env->CP0_PageMask = tlb->PageMask; |
... | ... | |
491 | 491 |
void debug_pre_eret (void) |
492 | 492 |
{ |
493 | 493 |
fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
494 |
env->PC, env->CP0_EPC); |
|
494 |
env->PC[env->current_tc], env->CP0_EPC);
|
|
495 | 495 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
496 | 496 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
497 | 497 |
if (env->hflags & MIPS_HFLAG_DM) |
... | ... | |
502 | 502 |
void debug_post_eret (void) |
503 | 503 |
{ |
504 | 504 |
fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
505 |
env->PC, env->CP0_EPC); |
|
505 |
env->PC[env->current_tc], env->CP0_EPC);
|
|
506 | 506 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
507 | 507 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
508 | 508 |
if (env->hflags & MIPS_HFLAG_DM) |
... | ... | |
518 | 518 |
function /= 2; |
519 | 519 |
switch (function) { |
520 | 520 |
case 2: /* TODO: char inbyte(int waitflag); */ |
521 |
if (env->gpr[4] == 0) |
|
522 |
env->gpr[2] = -1; |
|
521 |
if (env->gpr[4][env->current_tc] == 0)
|
|
522 |
env->gpr[2][env->current_tc] = -1;
|
|
523 | 523 |
/* Fall through */ |
524 | 524 |
case 11: /* TODO: char inbyte (void); */ |
525 |
env->gpr[2] = -1; |
|
525 |
env->gpr[2][env->current_tc] = -1;
|
|
526 | 526 |
break; |
527 | 527 |
case 3: |
528 | 528 |
case 12: |
529 |
printf("%c", (char)(env->gpr[4] & 0xFF)); |
|
529 |
printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
|
|
530 | 530 |
break; |
531 | 531 |
case 17: |
532 | 532 |
break; |
533 | 533 |
case 158: |
534 | 534 |
{ |
535 |
unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
|
535 |
unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
|
|
536 | 536 |
printf("%s", fmt); |
537 | 537 |
} |
538 | 538 |
break; |
... | ... | |
613 | 613 |
}; |
614 | 614 |
|
615 | 615 |
#define RESTORE_ROUNDING_MODE \ |
616 |
set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
|
|
616 |
set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
|
617 | 617 |
|
618 |
void do_ctc1 (void)
|
|
618 |
void do_cfc1 (int reg)
|
|
619 | 619 |
{ |
620 |
switch(T1) { |
|
620 |
switch (reg) { |
|
621 |
case 0: |
|
622 |
T0 = (int32_t)env->fpu->fcr0; |
|
623 |
break; |
|
624 |
case 25: |
|
625 |
T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
|
626 |
break; |
|
627 |
case 26: |
|
628 |
T0 = env->fpu->fcr31 & 0x0003f07c; |
|
629 |
break; |
|
630 |
case 28: |
|
631 |
T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
|
632 |
break; |
|
633 |
default: |
|
634 |
T0 = (int32_t)env->fpu->fcr31; |
|
635 |
break; |
|
636 |
} |
|
637 |
} |
|
638 |
|
|
639 |
void do_ctc1 (int reg) |
|
640 |
{ |
|
641 |
switch(reg) { |
|
621 | 642 |
case 25: |
622 | 643 |
if (T0 & 0xffffff00) |
623 | 644 |
return; |
624 |
env->fcr31 = (env->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
|
|
645 |
env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
|
|
625 | 646 |
((T0 & 0x1) << 23); |
626 | 647 |
break; |
627 | 648 |
case 26: |
628 | 649 |
if (T0 & 0x007c0000) |
629 | 650 |
return; |
630 |
env->fcr31 = (env->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
|
|
651 |
env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
|
|
631 | 652 |
break; |
632 | 653 |
case 28: |
633 | 654 |
if (T0 & 0x007c0000) |
634 | 655 |
return; |
635 |
env->fcr31 = (env->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
|
|
656 |
env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
|
|
636 | 657 |
((T0 & 0x4) << 22); |
637 | 658 |
break; |
638 | 659 |
case 31: |
639 | 660 |
if (T0 & 0x007c0000) |
640 | 661 |
return; |
641 |
env->fcr31 = T0; |
|
662 |
env->fpu->fcr31 = T0;
|
|
642 | 663 |
break; |
643 | 664 |
default: |
644 | 665 |
return; |
645 | 666 |
} |
646 | 667 |
/* set rounding mode */ |
647 | 668 |
RESTORE_ROUNDING_MODE; |
648 |
set_float_exception_flags(0, &env->fp_status); |
|
649 |
if ((GET_FP_ENABLE(env->fcr31) | 0x20) & GET_FP_CAUSE(env->fcr31))
|
|
669 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
670 |
if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
|
|
650 | 671 |
do_raise_exception(EXCP_FPE); |
651 | 672 |
} |
652 | 673 |
|
... | ... | |
670 | 691 |
|
671 | 692 |
inline void update_fcr31(void) |
672 | 693 |
{ |
673 |
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fp_status)); |
|
694 |
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
|
674 | 695 |
|
675 |
SET_FP_CAUSE(env->fcr31, tmp); |
|
676 |
if (GET_FP_ENABLE(env->fcr31) & tmp) |
|
696 |
SET_FP_CAUSE(env->fpu->fcr31, tmp);
|
|
697 |
if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
|
677 | 698 |
do_raise_exception(EXCP_FPE); |
678 | 699 |
else |
679 |
UPDATE_FP_FLAGS(env->fcr31, tmp); |
|
700 |
UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
|
|
680 | 701 |
} |
681 | 702 |
|
682 | 703 |
#define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
683 | 704 |
|
684 | 705 |
FLOAT_OP(cvtd, s) |
685 | 706 |
{ |
686 |
set_float_exception_flags(0, &env->fp_status); |
|
687 |
FDT2 = float32_to_float64(FST0, &env->fp_status); |
|
707 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
708 |
FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
|
|
688 | 709 |
update_fcr31(); |
689 | 710 |
} |
690 | 711 |
FLOAT_OP(cvtd, w) |
691 | 712 |
{ |
692 |
set_float_exception_flags(0, &env->fp_status); |
|
693 |
FDT2 = int32_to_float64(WT0, &env->fp_status); |
|
713 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
714 |
FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
|
|
694 | 715 |
update_fcr31(); |
695 | 716 |
} |
696 | 717 |
FLOAT_OP(cvtd, l) |
697 | 718 |
{ |
698 |
set_float_exception_flags(0, &env->fp_status); |
|
699 |
FDT2 = int64_to_float64(DT0, &env->fp_status); |
|
719 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
720 |
FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
|
|
700 | 721 |
update_fcr31(); |
701 | 722 |
} |
702 | 723 |
FLOAT_OP(cvtl, d) |
703 | 724 |
{ |
704 |
set_float_exception_flags(0, &env->fp_status); |
|
705 |
DT2 = float64_to_int64(FDT0, &env->fp_status); |
|
725 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
726 |
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
706 | 727 |
update_fcr31(); |
707 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
728 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
708 | 729 |
DT2 = 0x7fffffffffffffffULL; |
709 | 730 |
} |
710 | 731 |
FLOAT_OP(cvtl, s) |
711 | 732 |
{ |
712 |
set_float_exception_flags(0, &env->fp_status); |
|
713 |
DT2 = float32_to_int64(FST0, &env->fp_status); |
|
733 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
734 |
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
714 | 735 |
update_fcr31(); |
715 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
736 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
716 | 737 |
DT2 = 0x7fffffffffffffffULL; |
717 | 738 |
} |
718 | 739 |
|
719 | 740 |
FLOAT_OP(cvtps, pw) |
720 | 741 |
{ |
721 |
set_float_exception_flags(0, &env->fp_status); |
|
722 |
FST2 = int32_to_float32(WT0, &env->fp_status); |
|
723 |
FSTH2 = int32_to_float32(WTH0, &env->fp_status); |
|
742 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
743 |
FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
|
|
744 |
FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
|
|
724 | 745 |
update_fcr31(); |
725 | 746 |
} |
726 | 747 |
FLOAT_OP(cvtpw, ps) |
727 | 748 |
{ |
728 |
set_float_exception_flags(0, &env->fp_status); |
|
729 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
|
730 |
WTH2 = float32_to_int32(FSTH0, &env->fp_status); |
|
749 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
750 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
751 |
WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
|
|
731 | 752 |
update_fcr31(); |
732 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
753 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
733 | 754 |
WT2 = 0x7fffffff; |
734 | 755 |
} |
735 | 756 |
FLOAT_OP(cvts, d) |
736 | 757 |
{ |
737 |
set_float_exception_flags(0, &env->fp_status); |
|
738 |
FST2 = float64_to_float32(FDT0, &env->fp_status); |
|
758 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
759 |
FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
|
|
739 | 760 |
update_fcr31(); |
740 | 761 |
} |
741 | 762 |
FLOAT_OP(cvts, w) |
742 | 763 |
{ |
743 |
set_float_exception_flags(0, &env->fp_status); |
|
744 |
FST2 = int32_to_float32(WT0, &env->fp_status); |
|
764 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
765 |
FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
|
|
745 | 766 |
update_fcr31(); |
746 | 767 |
} |
747 | 768 |
FLOAT_OP(cvts, l) |
748 | 769 |
{ |
749 |
set_float_exception_flags(0, &env->fp_status); |
|
750 |
FST2 = int64_to_float32(DT0, &env->fp_status); |
|
770 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
771 |
FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
|
|
751 | 772 |
update_fcr31(); |
752 | 773 |
} |
753 | 774 |
FLOAT_OP(cvts, pl) |
754 | 775 |
{ |
755 |
set_float_exception_flags(0, &env->fp_status); |
|
776 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
756 | 777 |
WT2 = WT0; |
757 | 778 |
update_fcr31(); |
758 | 779 |
} |
759 | 780 |
FLOAT_OP(cvts, pu) |
760 | 781 |
{ |
761 |
set_float_exception_flags(0, &env->fp_status); |
|
782 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
762 | 783 |
WT2 = WTH0; |
763 | 784 |
update_fcr31(); |
764 | 785 |
} |
765 | 786 |
FLOAT_OP(cvtw, s) |
766 | 787 |
{ |
767 |
set_float_exception_flags(0, &env->fp_status); |
|
768 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
|
788 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
789 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
769 | 790 |
update_fcr31(); |
770 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
791 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
771 | 792 |
WT2 = 0x7fffffff; |
772 | 793 |
} |
773 | 794 |
FLOAT_OP(cvtw, d) |
774 | 795 |
{ |
775 |
set_float_exception_flags(0, &env->fp_status); |
|
776 |
WT2 = float64_to_int32(FDT0, &env->fp_status); |
|
796 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
797 |
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
777 | 798 |
update_fcr31(); |
778 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
799 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
779 | 800 |
WT2 = 0x7fffffff; |
780 | 801 |
} |
781 | 802 |
|
782 | 803 |
FLOAT_OP(roundl, d) |
783 | 804 |
{ |
784 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
|
785 |
DT2 = float64_to_int64(FDT0, &env->fp_status); |
|
805 |
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
806 |
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
786 | 807 |
RESTORE_ROUNDING_MODE; |
787 | 808 |
update_fcr31(); |
788 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
809 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
789 | 810 |
DT2 = 0x7fffffffffffffffULL; |
790 | 811 |
} |
791 | 812 |
FLOAT_OP(roundl, s) |
792 | 813 |
{ |
793 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
|
794 |
DT2 = float32_to_int64(FST0, &env->fp_status); |
|
814 |
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
815 |
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
795 | 816 |
RESTORE_ROUNDING_MODE; |
796 | 817 |
update_fcr31(); |
797 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
818 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
798 | 819 |
DT2 = 0x7fffffffffffffffULL; |
799 | 820 |
} |
800 | 821 |
FLOAT_OP(roundw, d) |
801 | 822 |
{ |
802 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
|
803 |
WT2 = float64_to_int32(FDT0, &env->fp_status); |
|
823 |
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
824 |
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
804 | 825 |
RESTORE_ROUNDING_MODE; |
805 | 826 |
update_fcr31(); |
806 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
827 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
807 | 828 |
WT2 = 0x7fffffff; |
808 | 829 |
} |
809 | 830 |
FLOAT_OP(roundw, s) |
810 | 831 |
{ |
811 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
|
812 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
|
832 |
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
833 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
813 | 834 |
RESTORE_ROUNDING_MODE; |
814 | 835 |
update_fcr31(); |
815 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
836 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
816 | 837 |
WT2 = 0x7fffffff; |
817 | 838 |
} |
818 | 839 |
|
819 | 840 |
FLOAT_OP(truncl, d) |
820 | 841 |
{ |
821 |
DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status); |
|
842 |
DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
|
|
822 | 843 |
update_fcr31(); |
823 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
844 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
824 | 845 |
DT2 = 0x7fffffffffffffffULL; |
825 | 846 |
} |
826 | 847 |
FLOAT_OP(truncl, s) |
827 | 848 |
{ |
828 |
DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status); |
|
849 |
DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
|
|
829 | 850 |
update_fcr31(); |
830 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
851 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
831 | 852 |
DT2 = 0x7fffffffffffffffULL; |
832 | 853 |
} |
833 | 854 |
FLOAT_OP(truncw, d) |
834 | 855 |
{ |
835 |
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
|
856 |
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
|
|
836 | 857 |
update_fcr31(); |
837 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
858 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
838 | 859 |
WT2 = 0x7fffffff; |
839 | 860 |
} |
840 | 861 |
FLOAT_OP(truncw, s) |
841 | 862 |
{ |
842 |
WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
|
863 |
WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
|
|
843 | 864 |
update_fcr31(); |
844 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
865 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
845 | 866 |
WT2 = 0x7fffffff; |
846 | 867 |
} |
847 | 868 |
|
848 | 869 |
FLOAT_OP(ceill, d) |
849 | 870 |
{ |
850 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
|
851 |
DT2 = float64_to_int64(FDT0, &env->fp_status); |
|
871 |
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
872 |
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
852 | 873 |
RESTORE_ROUNDING_MODE; |
853 | 874 |
update_fcr31(); |
854 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
875 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
855 | 876 |
DT2 = 0x7fffffffffffffffULL; |
856 | 877 |
} |
857 | 878 |
FLOAT_OP(ceill, s) |
858 | 879 |
{ |
859 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
|
860 |
DT2 = float32_to_int64(FST0, &env->fp_status); |
|
880 |
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
881 |
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
861 | 882 |
RESTORE_ROUNDING_MODE; |
862 | 883 |
update_fcr31(); |
863 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
884 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
864 | 885 |
DT2 = 0x7fffffffffffffffULL; |
865 | 886 |
} |
866 | 887 |
FLOAT_OP(ceilw, d) |
867 | 888 |
{ |
868 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
|
869 |
WT2 = float64_to_int32(FDT0, &env->fp_status); |
|
889 |
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
890 |
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
870 | 891 |
RESTORE_ROUNDING_MODE; |
871 | 892 |
update_fcr31(); |
872 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
893 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
873 | 894 |
WT2 = 0x7fffffff; |
874 | 895 |
} |
875 | 896 |
FLOAT_OP(ceilw, s) |
876 | 897 |
{ |
877 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
|
878 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
|
898 |
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
899 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
879 | 900 |
RESTORE_ROUNDING_MODE; |
880 | 901 |
update_fcr31(); |
881 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
902 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
882 | 903 |
WT2 = 0x7fffffff; |
883 | 904 |
} |
884 | 905 |
|
885 | 906 |
FLOAT_OP(floorl, d) |
886 | 907 |
{ |
887 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
|
888 |
DT2 = float64_to_int64(FDT0, &env->fp_status); |
|
908 |
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
909 |
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
889 | 910 |
RESTORE_ROUNDING_MODE; |
890 | 911 |
update_fcr31(); |
891 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
912 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
892 | 913 |
DT2 = 0x7fffffffffffffffULL; |
893 | 914 |
} |
894 | 915 |
FLOAT_OP(floorl, s) |
895 | 916 |
{ |
896 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
|
897 |
DT2 = float32_to_int64(FST0, &env->fp_status); |
|
917 |
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
918 |
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
898 | 919 |
RESTORE_ROUNDING_MODE; |
899 | 920 |
update_fcr31(); |
900 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
921 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
901 | 922 |
DT2 = 0x7fffffffffffffffULL; |
902 | 923 |
} |
903 | 924 |
FLOAT_OP(floorw, d) |
904 | 925 |
{ |
905 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
|
906 |
WT2 = float64_to_int32(FDT0, &env->fp_status); |
|
926 |
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
927 |
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
907 | 928 |
RESTORE_ROUNDING_MODE; |
908 | 929 |
update_fcr31(); |
909 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
930 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
910 | 931 |
WT2 = 0x7fffffff; |
911 | 932 |
} |
912 | 933 |
FLOAT_OP(floorw, s) |
913 | 934 |
{ |
914 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
|
915 |
WT2 = float32_to_int32(FST0, &env->fp_status); |
|
935 |
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
936 |
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
916 | 937 |
RESTORE_ROUNDING_MODE; |
917 | 938 |
update_fcr31(); |
918 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
939 |
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
919 | 940 |
WT2 = 0x7fffffff; |
920 | 941 |
} |
921 | 942 |
|
922 | 943 |
/* MIPS specific unary operations */ |
923 | 944 |
FLOAT_OP(recip, d) |
924 | 945 |
{ |
925 |
set_float_exception_flags(0, &env->fp_status); |
|
926 |
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fp_status); |
|
946 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
947 |
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
|
|
927 | 948 |
update_fcr31(); |
928 | 949 |
} |
929 | 950 |
FLOAT_OP(recip, s) |
930 | 951 |
{ |
931 |
set_float_exception_flags(0, &env->fp_status); |
|
932 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status); |
|
952 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
953 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
933 | 954 |
update_fcr31(); |
934 | 955 |
} |
935 | 956 |
|
936 | 957 |
FLOAT_OP(rsqrt, d) |
937 | 958 |
{ |
938 |
set_float_exception_flags(0, &env->fp_status); |
|
939 |
FDT2 = float64_sqrt(FDT0, &env->fp_status); |
|
940 |
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fp_status); |
|
959 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
960 |
FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
|
|
961 |
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
|
|
941 | 962 |
update_fcr31(); |
942 | 963 |
} |
943 | 964 |
FLOAT_OP(rsqrt, s) |
944 | 965 |
{ |
945 |
set_float_exception_flags(0, &env->fp_status); |
|
946 |
FST2 = float32_sqrt(FST0, &env->fp_status); |
|
947 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status); |
|
966 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
967 |
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
968 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
948 | 969 |
update_fcr31(); |
949 | 970 |
} |
950 | 971 |
|
951 | 972 |
FLOAT_OP(recip1, d) |
952 | 973 |
{ |
953 |
set_float_exception_flags(0, &env->fp_status); |
|
954 |
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fp_status); |
|
974 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
975 |
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
|
|
955 | 976 |
update_fcr31(); |
956 | 977 |
} |
957 | 978 |
FLOAT_OP(recip1, s) |
958 | 979 |
{ |
959 |
set_float_exception_flags(0, &env->fp_status); |
|
960 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status); |
|
980 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
981 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
961 | 982 |
update_fcr31(); |
962 | 983 |
} |
963 | 984 |
FLOAT_OP(recip1, ps) |
964 | 985 |
{ |
965 |
set_float_exception_flags(0, &env->fp_status); |
|
966 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status); |
|
967 |
FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fp_status); |
|
986 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
987 |
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
988 |
FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
|
|
968 | 989 |
update_fcr31(); |
969 | 990 |
} |
970 | 991 |
|
971 | 992 |
FLOAT_OP(rsqrt1, d) |
972 | 993 |
{ |
973 |
set_float_exception_flags(0, &env->fp_status); |
|
974 |
FDT2 = float64_sqrt(FDT0, &env->fp_status); |
|
975 |
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fp_status); |
|
994 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
995 |
FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
|
|
996 |
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
|
|
976 | 997 |
update_fcr31(); |
977 | 998 |
} |
978 | 999 |
FLOAT_OP(rsqrt1, s) |
979 | 1000 |
{ |
980 |
set_float_exception_flags(0, &env->fp_status); |
|
981 |
FST2 = float32_sqrt(FST0, &env->fp_status); |
|
982 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status); |
|
1001 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1002 |
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
1003 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
983 | 1004 |
update_fcr31(); |
984 | 1005 |
} |
985 | 1006 |
FLOAT_OP(rsqrt1, ps) |
986 | 1007 |
{ |
987 |
set_float_exception_flags(0, &env->fp_status); |
|
988 |
FST2 = float32_sqrt(FST0, &env->fp_status); |
|
989 |
FSTH2 = float32_sqrt(FSTH0, &env->fp_status); |
|
990 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status); |
|
991 |
FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fp_status); |
|
1008 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1009 |
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
1010 |
FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
|
|
1011 |
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
1012 |
FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
|
|
992 | 1013 |
update_fcr31(); |
993 | 1014 |
} |
994 | 1015 |
|
... | ... | |
996 | 1017 |
#define FLOAT_BINOP(name) \ |
997 | 1018 |
FLOAT_OP(name, d) \ |
998 | 1019 |
{ \ |
999 |
set_float_exception_flags(0, &env->fp_status); \ |
|
1000 |
FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ |
|
1001 |
update_fcr31(); \ |
|
1002 |
if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) \ |
|
1003 |
FDT2 = 0x7ff7ffffffffffffULL; \ |
|
1004 |
else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
|
1005 |
if ((env->fcr31 & 0x3) == 0) \ |
|
1006 |
FDT2 &= FLOAT_SIGN64; \ |
|
1020 |
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
1021 |
FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
|
|
1022 |
update_fcr31(); \
|
|
1023 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
|
1024 |
FDT2 = 0x7ff7ffffffffffffULL; \
|
|
1025 |
else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
|
|
1026 |
if ((env->fpu->fcr31 & 0x3) == 0) \
|
|
1027 |
FDT2 &= FLOAT_SIGN64; \
|
|
1007 | 1028 |
} \ |
1008 | 1029 |
} \ |
1009 | 1030 |
FLOAT_OP(name, s) \ |
1010 | 1031 |
{ \ |
1011 |
set_float_exception_flags(0, &env->fp_status); \ |
|
1012 |
FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
|
1013 |
update_fcr31(); \ |
|
1014 |
if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) \ |
|
1015 |
FST2 = 0x7fbfffff; \ |
|
1016 |
else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
|
1017 |
if ((env->fcr31 & 0x3) == 0) \ |
|
1018 |
FST2 &= FLOAT_SIGN32; \ |
|
1032 |
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
1033 |
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
|
|
1034 |
update_fcr31(); \
|
|
1035 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
|
1036 |
FST2 = 0x7fbfffff; \
|
|
1037 |
else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
|
|
1038 |
if ((env->fpu->fcr31 & 0x3) == 0) \
|
|
1039 |
FST2 &= FLOAT_SIGN32; \
|
|
1019 | 1040 |
} \ |
1020 | 1041 |
} \ |
1021 | 1042 |
FLOAT_OP(name, ps) \ |
1022 | 1043 |
{ \ |
1023 |
set_float_exception_flags(0, &env->fp_status); \ |
|
1024 |
FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
|
1025 |
FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \ |
|
1044 |
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
1045 |
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
|
|
1046 |
FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
|
|
1026 | 1047 |
update_fcr31(); \ |
1027 |
if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) { \ |
|
1028 |
FST2 = 0x7fbfffff; \ |
|
1029 |
FSTH2 = 0x7fbfffff; \ |
|
1030 |
} else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) { \ |
|
1031 |
if ((env->fcr31 & 0x3) == 0) { \ |
|
1032 |
FST2 &= FLOAT_SIGN32; \ |
|
1033 |
FSTH2 &= FLOAT_SIGN32; \ |
|
1048 |
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
|
1049 |
FST2 = 0x7fbfffff; \
|
|
1050 |
FSTH2 = 0x7fbfffff; \
|
|
1051 |
} else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
|
|
1052 |
if ((env->fpu->fcr31 & 0x3) == 0) { \
|
|
1053 |
FST2 &= FLOAT_SIGN32; \
|
|
1054 |
FSTH2 &= FLOAT_SIGN32; \
|
|
1034 | 1055 |
} \ |
1035 | 1056 |
} \ |
1036 | 1057 |
} |
... | ... | |
1043 | 1064 |
/* MIPS specific binary operations */ |
1044 | 1065 |
FLOAT_OP(recip2, d) |
1045 | 1066 |
{ |
1046 |
set_float_exception_flags(0, &env->fp_status); |
|
1047 |
FDT2 = float64_mul(FDT0, FDT2, &env->fp_status); |
|
1048 |
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fp_status) ^ FLOAT_SIGN64; |
|
1067 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1068 |
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
|
|
1069 |
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
|
|
1049 | 1070 |
update_fcr31(); |
1050 | 1071 |
} |
1051 | 1072 |
FLOAT_OP(recip2, s) |
1052 | 1073 |
{ |
1053 |
set_float_exception_flags(0, &env->fp_status); |
|
1054 |
FST2 = float32_mul(FST0, FST2, &env->fp_status); |
|
1055 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1074 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1075 |
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
1076 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1056 | 1077 |
update_fcr31(); |
1057 | 1078 |
} |
1058 | 1079 |
FLOAT_OP(recip2, ps) |
1059 | 1080 |
{ |
1060 |
set_float_exception_flags(0, &env->fp_status); |
|
1061 |
FST2 = float32_mul(FST0, FST2, &env->fp_status); |
|
1062 |
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fp_status); |
|
1063 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1064 |
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1081 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1082 |
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
1083 |
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
|
|
1084 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1085 |
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1065 | 1086 |
update_fcr31(); |
1066 | 1087 |
} |
1067 | 1088 |
|
1068 | 1089 |
FLOAT_OP(rsqrt2, d) |
1069 | 1090 |
{ |
1070 |
set_float_exception_flags(0, &env->fp_status); |
|
1071 |
FDT2 = float64_mul(FDT0, FDT2, &env->fp_status); |
|
1072 |
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fp_status); |
|
1073 |
FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fp_status) ^ FLOAT_SIGN64; |
|
1091 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1092 |
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
|
|
1093 |
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
|
|
1094 |
FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
|
|
1074 | 1095 |
update_fcr31(); |
1075 | 1096 |
} |
1076 | 1097 |
FLOAT_OP(rsqrt2, s) |
1077 | 1098 |
{ |
1078 |
set_float_exception_flags(0, &env->fp_status); |
|
1079 |
FST2 = float32_mul(FST0, FST2, &env->fp_status); |
|
1080 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status); |
|
1081 |
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1099 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1100 |
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
1101 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
1102 |
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1082 | 1103 |
update_fcr31(); |
1083 | 1104 |
} |
1084 | 1105 |
FLOAT_OP(rsqrt2, ps) |
1085 | 1106 |
{ |
1086 |
set_float_exception_flags(0, &env->fp_status); |
|
1087 |
FST2 = float32_mul(FST0, FST2, &env->fp_status); |
|
1088 |
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fp_status); |
|
1089 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status); |
|
1090 |
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fp_status); |
|
1091 |
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1092 |
FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32; |
|
1107 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1108 |
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
1109 |
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
|
|
1110 |
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
1111 |
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
1112 |
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1113 |
FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
1093 | 1114 |
update_fcr31(); |
1094 | 1115 |
} |
1095 | 1116 |
|
1096 | 1117 |
FLOAT_OP(addr, ps) |
1097 | 1118 |
{ |
1098 |
set_float_exception_flags(0, &env->fp_status); |
|
1099 |
FST2 = float32_add (FST0, FSTH0, &env->fp_status); |
|
1100 |
FSTH2 = float32_add (FST1, FSTH1, &env->fp_status); |
|
1119 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1120 |
FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
|
|
1121 |
FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
|
|
1101 | 1122 |
update_fcr31(); |
1102 | 1123 |
} |
1103 | 1124 |
|
1104 | 1125 |
FLOAT_OP(mulr, ps) |
1105 | 1126 |
{ |
1106 |
set_float_exception_flags(0, &env->fp_status); |
|
1107 |
FST2 = float32_mul (FST0, FSTH0, &env->fp_status); |
|
1108 |
FSTH2 = float32_mul (FST1, FSTH1, &env->fp_status); |
|
1127 |
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
1128 |
FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
|
|
1129 |
FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
|
|
1109 | 1130 |
update_fcr31(); |
1110 | 1131 |
} |
1111 | 1132 |
|
... | ... | |
1116 | 1137 |
int c = cond; \ |
1117 | 1138 |
update_fcr31(); \ |
1118 | 1139 |
if (c) \ |
1119 |
SET_FP_COND(cc, env); \
|
|
1140 |
SET_FP_COND(cc, env->fpu); \
|
|
1120 | 1141 |
else \ |
1121 |
CLEAR_FP_COND(cc, env); \
|
|
1142 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1122 | 1143 |
} \ |
1123 | 1144 |
void do_cmpabs_d_ ## op (long cc) \ |
1124 | 1145 |
{ \ |
... | ... | |
1128 | 1149 |
c = cond; \ |
1129 | 1150 |
update_fcr31(); \ |
1130 | 1151 |
if (c) \ |
1131 |
SET_FP_COND(cc, env); \
|
|
1152 |
SET_FP_COND(cc, env->fpu); \
|
|
1132 | 1153 |
else \ |
1133 |
CLEAR_FP_COND(cc, env); \
|
|
1154 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1134 | 1155 |
} |
1135 | 1156 |
|
1136 | 1157 |
int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
... | ... | |
1149 | 1170 |
|
1150 | 1171 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1151 | 1172 |
* but float*_is_unordered() is still called. */ |
1152 |
FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fp_status), 0)) |
|
1153 |
FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)) |
|
1154 |
FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
|
1155 |
FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
|
1156 |
FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
|
1157 |
FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
|
1158 |
FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
|
1159 |
FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
|
1173 |
FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
|
|
1174 |
FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
|
1175 |
FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
1176 |
FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
1177 |
FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
1178 |
FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
1179 |
FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
1180 |
FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
1160 | 1181 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1161 | 1182 |
* but float*_is_unordered() is still called. */ |
1162 |
FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fp_status), 0)) |
|
1163 |
FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fp_status)) |
|
1164 |
FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
|
|
1165 |
FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
|
1166 |
FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
|
|
1167 |
FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
|
1168 |
FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
|
|
1169 |
FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
|
1183 |
FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
|
|
1184 |
FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
|
1185 |
FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
1186 |
FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
1187 |
FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
1188 |
FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
1189 |
FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
1190 |
FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
1170 | 1191 |
|
1171 | 1192 |
#define FOP_COND_S(op, cond) \ |
1172 | 1193 |
void do_cmp_s_ ## op (long cc) \ |
... | ... | |
1174 | 1195 |
int c = cond; \ |
1175 | 1196 |
update_fcr31(); \ |
1176 | 1197 |
if (c) \ |
1177 |
SET_FP_COND(cc, env); \
|
|
1198 |
SET_FP_COND(cc, env->fpu); \
|
|
1178 | 1199 |
else \ |
1179 |
CLEAR_FP_COND(cc, env); \
|
|
1200 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1180 | 1201 |
} \ |
1181 | 1202 |
void do_cmpabs_s_ ## op (long cc) \ |
1182 | 1203 |
{ \ |
... | ... | |
1186 | 1207 |
c = cond; \ |
1187 | 1208 |
update_fcr31(); \ |
1188 | 1209 |
if (c) \ |
1189 |
SET_FP_COND(cc, env); \
|
|
1210 |
SET_FP_COND(cc, env->fpu); \
|
|
1190 | 1211 |
else \ |
1191 |
CLEAR_FP_COND(cc, env); \
|
|
1212 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1192 | 1213 |
} |
1193 | 1214 |
|
1194 | 1215 |
flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) |
... | ... | |
1207 | 1228 |
|
1208 | 1229 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1209 | 1230 |
* but float*_is_unordered() is still called. */ |
1210 |
FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0)) |
|
1211 |
FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fp_status)) |
|
1212 |
FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
|
1213 |
FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
|
1214 |
FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
|
1215 |
FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
|
1216 |
FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
|
1217 |
FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
|
1231 |
FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
|
|
1232 |
FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
|
1233 |
FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
1234 |
FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
1235 |
FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
1236 |
FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
1237 |
FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
1238 |
FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
1218 | 1239 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1219 | 1240 |
* but float*_is_unordered() is still called. */ |
1220 |
FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0)) |
|
1221 |
FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status)) |
|
1222 |
FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
|
|
1223 |
FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
|
1224 |
FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
|
|
1225 |
FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
|
1226 |
FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
|
|
1227 |
FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
|
1241 |
FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
|
|
1242 |
FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
|
1243 |
FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
1244 |
FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
1245 |
FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
1246 |
FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
1247 |
FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
1248 |
FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
1228 | 1249 |
|
1229 | 1250 |
#define FOP_COND_PS(op, condl, condh) \ |
1230 | 1251 |
void do_cmp_ps_ ## op (long cc) \ |
... | ... | |
1233 | 1254 |
int ch = condh; \ |
1234 | 1255 |
update_fcr31(); \ |
1235 | 1256 |
if (cl) \ |
1236 |
SET_FP_COND(cc, env); \
|
|
1257 |
SET_FP_COND(cc, env->fpu); \
|
|
1237 | 1258 |
else \ |
1238 |
CLEAR_FP_COND(cc, env); \
|
|
1259 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1239 | 1260 |
if (ch) \ |
1240 |
SET_FP_COND(cc + 1, env); \
|
|
1261 |
SET_FP_COND(cc + 1, env->fpu); \
|
|
1241 | 1262 |
else \ |
1242 |
CLEAR_FP_COND(cc + 1, env); \
|
|
1263 |
CLEAR_FP_COND(cc + 1, env->fpu); \
|
|
1243 | 1264 |
} \ |
1244 | 1265 |
void do_cmpabs_ps_ ## op (long cc) \ |
1245 | 1266 |
{ \ |
... | ... | |
1252 | 1273 |
ch = condh; \ |
1253 | 1274 |
update_fcr31(); \ |
1254 | 1275 |
if (cl) \ |
1255 |
SET_FP_COND(cc, env); \
|
|
1276 |
SET_FP_COND(cc, env->fpu); \
|
|
1256 | 1277 |
else \ |
1257 |
CLEAR_FP_COND(cc, env); \
|
|
1278 |
CLEAR_FP_COND(cc, env->fpu); \
|
|
1258 | 1279 |
if (ch) \ |
1259 |
SET_FP_COND(cc + 1, env); \
|
|
1280 |
SET_FP_COND(cc + 1, env->fpu); \
|
|
1260 | 1281 |
else \ |
1261 |
CLEAR_FP_COND(cc + 1, env); \
|
|
1282 |
CLEAR_FP_COND(cc + 1, env->fpu); \
|
|
1262 | 1283 |
} |
1263 | 1284 |
|
1264 | 1285 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1265 | 1286 |
* but float*_is_unordered() is still called. */ |
1266 |
FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0), |
|
1267 |
(float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status), 0)) |
|
1268 |
FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fp_status), |
|
1269 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)) |
|
1270 |
FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status),
|
|
1271 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
|
|
1272 |
FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status),
|
|
1273 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status))
|
|
1274 |
FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status),
|
|
1275 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
|
|
1276 |
FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status),
|
|
1277 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status))
|
|
1278 |
FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status),
|
|
1279 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
|
|
1280 |
FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status),
|
|
1281 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status))
|
|
1287 |
FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
|
|
1288 |
(float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
|
|
1289 |
FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
|
1290 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
|
1291 |
FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
1292 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1293 |
FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
1294 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1295 |
FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
1296 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1297 |
FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
1298 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1299 |
FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
1300 |
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1301 |
FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
1302 |
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
1282 | 1303 |
/* NOTE: the comma operator will make "cond" to eval to false, |
1283 | 1304 |
* but float*_is_unordered() is still called. */ |
1284 |
FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0), |
|
1285 |
(float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status), 0)) |
|
1286 |
FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status), |
|
1287 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)) |
|
1288 |
FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status), |
|
1289 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status)) |
|
1290 |
FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status), |
|
1291 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_eq(FSTH0, FSTH1, &env->fp_status)) |
|
1292 |
FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status), |
|
1293 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status)) |
|
1294 |
FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status), |
|
1295 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_lt(FSTH0, FSTH1, &env->fp_status)) |
|
1296 |
FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status), |
|
1297 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status)) |
|
1298 |
FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status), |
|
1299 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) || float32_le(FSTH0, FSTH1, &env->fp_status)) |
|
1305 |
FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
|
1306 |
(float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
|
1307 |
FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), |
|
1308 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status)) |
|
1309 |
FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status), |
|
1310 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status)) |
|
1311 |
FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status), |
|
1312 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status)) |
|
1313 |
FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status), |
|
1314 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status)) |
|
1315 |
FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status), |
|
1316 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status)) |
|
1317 |
FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status), |
|
1318 |
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |
|
1319 |
FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status), |
|
1320 |
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |
Also available in: Unified diff