Revision ead9360e target-mips/translate_init.c
b/target-mips/translate_init.c | ||
---|---|---|
43 | 43 |
|
44 | 44 |
/* No config4, no DSP ASE, no large physaddr, |
45 | 45 |
no external interrupt controller, no vectored interupts, |
46 |
no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
|
|
46 |
no 1kb pages, no SmartMIPS ASE, no trace logic */ |
|
47 | 47 |
#define MIPS_CONFIG3 \ |
48 | 48 |
((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
49 | 49 |
(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
50 |
(0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
|
|
50 |
(0 << CP0C3_SM) | (0 << CP0C3_TL)) |
|
51 | 51 |
|
52 | 52 |
/* Define a implementation number of 1. |
53 | 53 |
Define a major version 1, minor version 0. */ |
... | ... | |
65 | 65 |
int32_t CP0_Config7; |
66 | 66 |
int32_t SYNCI_Step; |
67 | 67 |
int32_t CCRes; |
68 |
int32_t Status_rw_bitmask; |
|
68 |
int32_t CP0_Status_rw_bitmask; |
|
69 |
int32_t CP0_TCStatus_rw_bitmask; |
|
70 |
int32_t CP0_SRSCtl; |
|
69 | 71 |
int32_t CP1_fcr0; |
70 | 72 |
int32_t SEGBITS; |
73 |
int32_t CP0_SRSConf0_rw_bitmask; |
|
74 |
int32_t CP0_SRSConf0; |
|
75 |
int32_t CP0_SRSConf1_rw_bitmask; |
|
76 |
int32_t CP0_SRSConf1; |
|
77 |
int32_t CP0_SRSConf2_rw_bitmask; |
|
78 |
int32_t CP0_SRSConf2; |
|
79 |
int32_t CP0_SRSConf3_rw_bitmask; |
|
80 |
int32_t CP0_SRSConf3; |
|
81 |
int32_t CP0_SRSConf4_rw_bitmask; |
|
82 |
int32_t CP0_SRSConf4; |
|
71 | 83 |
}; |
72 | 84 |
|
73 | 85 |
/*****************************************************************************/ |
... | ... | |
85 | 97 |
.CP0_Config3 = MIPS_CONFIG3, |
86 | 98 |
.SYNCI_Step = 32, |
87 | 99 |
.CCRes = 2, |
88 |
.Status_rw_bitmask = 0x3278FF17,
|
|
100 |
.CP0_Status_rw_bitmask = 0x1278FF17,
|
|
89 | 101 |
}, |
90 | 102 |
{ |
91 | 103 |
.name = "4KEcR1", |
... | ... | |
98 | 110 |
.CP0_Config3 = MIPS_CONFIG3, |
99 | 111 |
.SYNCI_Step = 32, |
100 | 112 |
.CCRes = 2, |
101 |
.Status_rw_bitmask = 0x3278FF17,
|
|
113 |
.CP0_Status_rw_bitmask = 0x1278FF17,
|
|
102 | 114 |
}, |
103 | 115 |
{ |
104 | 116 |
.name = "4KEc", |
... | ... | |
108 | 120 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
109 | 121 |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
110 | 122 |
.CP0_Config2 = MIPS_CONFIG2, |
111 |
.CP0_Config3 = MIPS_CONFIG3, |
|
123 |
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
|
|
112 | 124 |
.SYNCI_Step = 32, |
113 | 125 |
.CCRes = 2, |
114 |
.Status_rw_bitmask = 0x3278FF17,
|
|
126 |
.CP0_Status_rw_bitmask = 0x1278FF17,
|
|
115 | 127 |
}, |
116 | 128 |
{ |
117 | 129 |
.name = "24Kc", |
... | ... | |
121 | 133 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
122 | 134 |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
123 | 135 |
.CP0_Config2 = MIPS_CONFIG2, |
124 |
.CP0_Config3 = MIPS_CONFIG3, |
|
136 |
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
|
|
125 | 137 |
.SYNCI_Step = 32, |
126 | 138 |
.CCRes = 2, |
127 |
.Status_rw_bitmask = 0x3278FF17, |
|
139 |
/* No DSP implemented. */ |
|
140 |
.CP0_Status_rw_bitmask = 0x1278FF17, |
|
128 | 141 |
}, |
129 | 142 |
{ |
130 | 143 |
.name = "24Kf", |
... | ... | |
134 | 147 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
135 | 148 |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
136 | 149 |
.CP0_Config2 = MIPS_CONFIG2, |
137 |
.CP0_Config3 = MIPS_CONFIG3, |
|
150 |
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
|
|
138 | 151 |
.SYNCI_Step = 32, |
139 | 152 |
.CCRes = 2, |
140 |
.Status_rw_bitmask = 0x3678FF17, |
|
153 |
/* No DSP implemented. */ |
|
154 |
.CP0_Status_rw_bitmask = 0x3678FF17, |
|
141 | 155 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
142 | 156 |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
143 | 157 |
}, |
158 |
{ |
|
159 |
.name = "34Kf", |
|
160 |
.CP0_PRid = 0x00019500, |
|
161 |
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), |
|
162 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
|
163 |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
|
164 |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
|
165 |
.CP0_Config2 = MIPS_CONFIG2, |
|
166 |
.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
|
167 |
.SYNCI_Step = 32, |
|
168 |
.CCRes = 2, |
|
169 |
/* No DSP implemented. */ |
|
170 |
.CP0_Status_rw_bitmask = 0x3678FF17, |
|
171 |
/* No DSP implemented. */ |
|
172 |
.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
|
173 |
(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
|
174 |
(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
|
175 |
(1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
|
176 |
(0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
|
177 |
(0xff << CP0TCSt_TASID), |
|
178 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
|
179 |
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
|
180 |
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
|
181 |
.CP0_SRSConf0_rw_bitmask = 0x3fffffff, |
|
182 |
.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
|
183 |
(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
|
184 |
.CP0_SRSConf1_rw_bitmask = 0x3fffffff, |
|
185 |
.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
|
186 |
(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
|
187 |
.CP0_SRSConf2_rw_bitmask = 0x3fffffff, |
|
188 |
.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
|
189 |
(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
|
190 |
.CP0_SRSConf3_rw_bitmask = 0x3fffffff, |
|
191 |
.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
|
192 |
(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
|
193 |
.CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
|
194 |
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
|
195 |
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
|
196 |
}, |
|
144 | 197 |
#ifdef TARGET_MIPS64 |
145 | 198 |
{ |
146 | 199 |
.name = "R4000", |
... | ... | |
153 | 206 |
.CP0_Config3 = MIPS_CONFIG3, |
154 | 207 |
.SYNCI_Step = 16, |
155 | 208 |
.CCRes = 2, |
156 |
.Status_rw_bitmask = 0x3678FFFF, |
|
209 |
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
|
157 | 210 |
/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ |
158 | 211 |
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
159 | 212 |
.SEGBITS = 40, |
... | ... | |
170 | 223 |
.CP0_Config3 = MIPS_CONFIG3, |
171 | 224 |
.SYNCI_Step = 32, |
172 | 225 |
.CCRes = 2, |
173 |
.Status_rw_bitmask = 0x32F8FFFF, |
|
226 |
.CP0_Status_rw_bitmask = 0x32F8FFFF,
|
|
174 | 227 |
.SEGBITS = 42, |
175 | 228 |
}, |
176 | 229 |
{ |
... | ... | |
185 | 238 |
.CP0_Config3 = MIPS_CONFIG3, |
186 | 239 |
.SYNCI_Step = 32, |
187 | 240 |
.CCRes = 2, |
188 |
.Status_rw_bitmask = 0x36F8FFFF, |
|
241 |
.CP0_Status_rw_bitmask = 0x36F8FFFF,
|
|
189 | 242 |
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
190 | 243 |
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
191 | 244 |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
... | ... | |
205 | 258 |
.CP0_Config3 = MIPS_CONFIG3, |
206 | 259 |
.SYNCI_Step = 32, |
207 | 260 |
.CCRes = 2, |
208 |
.Status_rw_bitmask = 0x36FBFFFF, |
|
261 |
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
|
209 | 262 |
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
210 | 263 |
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
211 | 264 |
(1 << FCR0_D) | (1 << FCR0_S) | |
... | ... | |
245 | 298 |
#ifndef CONFIG_USER_ONLY |
246 | 299 |
static void no_mmu_init (CPUMIPSState *env, mips_def_t *def) |
247 | 300 |
{ |
248 |
env->nb_tlb = 1; |
|
249 |
env->map_address = &no_mmu_map_address; |
|
301 |
env->tlb->nb_tlb = 1;
|
|
302 |
env->tlb->map_address = &no_mmu_map_address;
|
|
250 | 303 |
} |
251 | 304 |
|
252 | 305 |
static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def) |
253 | 306 |
{ |
254 |
env->nb_tlb = 1; |
|
255 |
env->map_address = &fixed_mmu_map_address; |
|
307 |
env->tlb->nb_tlb = 1;
|
|
308 |
env->tlb->map_address = &fixed_mmu_map_address;
|
|
256 | 309 |
} |
257 | 310 |
|
258 | 311 |
static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def) |
259 | 312 |
{ |
260 |
env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
|
261 |
env->map_address = &r4k_map_address; |
|
262 |
env->do_tlbwi = r4k_do_tlbwi; |
|
263 |
env->do_tlbwr = r4k_do_tlbwr; |
|
264 |
env->do_tlbp = r4k_do_tlbp; |
|
265 |
env->do_tlbr = r4k_do_tlbr; |
|
313 |
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
|
314 |
env->tlb->map_address = &r4k_map_address; |
|
315 |
env->tlb->do_tlbwi = r4k_do_tlbwi; |
|
316 |
env->tlb->do_tlbwr = r4k_do_tlbwr; |
|
317 |
env->tlb->do_tlbp = r4k_do_tlbp; |
|
318 |
env->tlb->do_tlbr = r4k_do_tlbr; |
|
319 |
} |
|
320 |
|
|
321 |
static void mmu_init (CPUMIPSState *env, mips_def_t *def) |
|
322 |
{ |
|
323 |
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); |
|
324 |
|
|
325 |
/* There are more full-featured MMU variants in older MIPS CPUs, |
|
326 |
R3000, R6000 and R8000 come to mind. If we ever support them, |
|
327 |
this check will need to look up a different place than those |
|
328 |
newfangled config registers. */ |
|
329 |
switch ((env->CP0_Config0 >> CP0C0_MT) & 3) { |
|
330 |
case 0: |
|
331 |
no_mmu_init(env, def); |
|
332 |
break; |
|
333 |
case 1: |
|
334 |
r4k_mmu_init(env, def); |
|
335 |
break; |
|
336 |
case 3: |
|
337 |
fixed_mmu_init(env, def); |
|
338 |
break; |
|
339 |
default: |
|
340 |
cpu_abort(env, "MMU type not supported\n"); |
|
341 |
} |
|
342 |
env->CP0_Random = env->tlb->nb_tlb - 1; |
|
343 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
|
266 | 344 |
} |
267 | 345 |
#endif /* CONFIG_USER_ONLY */ |
268 | 346 |
|
347 |
static void fpu_init (CPUMIPSState *env, mips_def_t *def) |
|
348 |
{ |
|
349 |
env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext)); |
|
350 |
|
|
351 |
env->fpu->fcr0 = def->CP1_fcr0; |
|
352 |
#ifdef CONFIG_USER_ONLY |
|
353 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
354 |
env->hflags |= MIPS_HFLAG_FPU; |
|
355 |
if (env->fpu->fcr0 & (1 << FCR0_F64)) |
|
356 |
env->hflags |= MIPS_HFLAG_F64; |
|
357 |
#endif |
|
358 |
} |
|
359 |
|
|
360 |
static void mvp_init (CPUMIPSState *env, mips_def_t *def) |
|
361 |
{ |
|
362 |
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); |
|
363 |
|
|
364 |
/* MVPConf1 implemented, TLB sharable, no gating storage support, |
|
365 |
programmable cache partitioning implemented, number of allocatable |
|
366 |
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs |
|
367 |
implemented, 5 TCs implemented. */ |
|
368 |
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
|
369 |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
|
370 |
(env->tlb->nb_tlb << CP0MVPC0_PTLBE) | |
|
371 |
// TODO: actually do 2 VPEs. |
|
372 |
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
|
373 |
// (0x04 << CP0MVPC0_PTC); |
|
374 |
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
|
375 |
(0x04 << CP0MVPC0_PTC); |
|
376 |
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
|
377 |
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
|
378 |
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
|
379 |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
|
380 |
(0x1 << CP0MVPC1_PCP1); |
|
381 |
} |
|
382 |
|
|
269 | 383 |
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) |
270 | 384 |
{ |
271 | 385 |
if (!def) |
... | ... | |
285 | 399 |
env->CP0_Config7 = def->CP0_Config7; |
286 | 400 |
env->SYNCI_Step = def->SYNCI_Step; |
287 | 401 |
env->CCRes = def->CCRes; |
288 |
env->Status_rw_bitmask = def->Status_rw_bitmask; |
|
289 |
env->fcr0 = def->CP1_fcr0; |
|
402 |
env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask; |
|
403 |
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |
|
404 |
env->CP0_SRSCtl = def->CP0_SRSCtl; |
|
290 | 405 |
#ifdef TARGET_MIPS64 |
291 | 406 |
if ((env->CP0_Config0 & (0x3 << CP0C0_AT))) |
292 | 407 |
{ |
... | ... | |
298 | 413 |
env->SEGMask = 0xFFFFFFFF; |
299 | 414 |
} |
300 | 415 |
#endif |
301 |
#ifdef CONFIG_USER_ONLY |
|
302 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
303 |
env->hflags |= MIPS_HFLAG_FPU; |
|
304 |
if (env->fcr0 & (1 << FCR0_F64)) |
|
305 |
env->hflags |= MIPS_HFLAG_F64; |
|
306 |
#else |
|
307 |
/* There are more full-featured MMU variants in older MIPS CPUs, |
|
308 |
R3000, R6000 and R8000 come to mind. If we ever support them, |
|
309 |
this check will need to look up a different place than those |
|
310 |
newfangled config registers. */ |
|
311 |
switch ((env->CP0_Config0 >> CP0C0_MT) & 3) { |
|
312 |
case 0: |
|
313 |
no_mmu_init(env, def); |
|
314 |
break; |
|
315 |
case 1: |
|
316 |
r4k_mmu_init(env, def); |
|
317 |
break; |
|
318 |
case 3: |
|
319 |
fixed_mmu_init(env, def); |
|
320 |
break; |
|
321 |
default: |
|
322 |
cpu_abort(env, "MMU type not supported\n"); |
|
323 |
} |
|
324 |
env->CP0_Random = env->nb_tlb - 1; |
|
325 |
env->tlb_in_use = env->nb_tlb; |
|
326 |
#endif /* CONFIG_USER_ONLY */ |
|
416 |
env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask; |
|
417 |
env->CP0_SRSConf0 = def->CP0_SRSConf0; |
|
418 |
env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask; |
|
419 |
env->CP0_SRSConf1 = def->CP0_SRSConf1; |
|
420 |
env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask; |
|
421 |
env->CP0_SRSConf2 = def->CP0_SRSConf2; |
|
422 |
env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask; |
|
423 |
env->CP0_SRSConf3 = def->CP0_SRSConf3; |
|
424 |
env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |
|
425 |
env->CP0_SRSConf4 = def->CP0_SRSConf4; |
|
426 |
|
|
427 |
#ifndef CONFIG_USER_ONLY |
|
428 |
mmu_init(env, def); |
|
429 |
#endif |
|
430 |
fpu_init(env, def); |
|
431 |
mvp_init(env, def); |
|
327 | 432 |
return 0; |
328 | 433 |
} |
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