Revision ebda377f
b/target-i386/cpu.h | ||
---|---|---|
685 | 685 |
|
686 | 686 |
uint64_t tsc; |
687 | 687 |
|
688 |
uint64_t pat; |
|
689 |
|
|
690 | 688 |
uint64_t mcg_status; |
691 | 689 |
|
692 | 690 |
/* exception/interrupt handling */ |
... | ... | |
707 | 705 |
|
708 | 706 |
CPU_COMMON |
709 | 707 |
|
708 |
uint64_t pat; |
|
709 |
|
|
710 | 710 |
/* processor features (e.g. for CPUID insn) */ |
711 | 711 |
uint32_t cpuid_level; |
712 | 712 |
uint32_t cpuid_vendor1; |
b/target-i386/cpuid.c | ||
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847 | 847 |
env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16); |
848 | 848 |
env->cpuid_version |= def->stepping; |
849 | 849 |
env->cpuid_features = def->features; |
850 |
env->pat = 0x0007040600070406ULL; |
|
851 | 850 |
env->cpuid_ext_features = def->ext_features; |
852 | 851 |
env->cpuid_ext2_features = def->ext2_features; |
853 | 852 |
env->cpuid_ext3_features = def->ext3_features; |
b/target-i386/helper.c | ||
---|---|---|
99 | 99 |
|
100 | 100 |
env->mxcsr = 0x1f80; |
101 | 101 |
|
102 |
env->pat = 0x0007040600070406ULL; |
|
103 |
|
|
102 | 104 |
memset(env->dr, 0, sizeof(env->dr)); |
103 | 105 |
env->dr[6] = DR6_FIXED_1; |
104 | 106 |
env->dr[7] = DR7_FIXED_1; |
... | ... | |
1280 | 1282 |
void do_cpu_init(CPUState *env) |
1281 | 1283 |
{ |
1282 | 1284 |
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI; |
1285 |
uint64_t pat = env->pat; |
|
1286 |
|
|
1283 | 1287 |
cpu_reset(env); |
1284 | 1288 |
env->interrupt_request = sipi; |
1289 |
env->pat = pat; |
|
1285 | 1290 |
apic_init_reset(env->apic_state); |
1286 | 1291 |
env->halted = !cpu_is_bsp(env); |
1287 | 1292 |
} |
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