root / hw / sparc / sun4m.c @ ec0503b4
History | View | Annotate | Download (44.6 kB)
1 |
/*
|
---|---|
2 |
* QEMU Sun4m & Sun4d & Sun4c System Emulator
|
3 |
*
|
4 |
* Copyright (c) 2003-2005 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw/sysbus.h" |
25 |
#include "qemu/timer.h" |
26 |
#include "hw/sparc/sun4m.h" |
27 |
#include "hw/timer/m48t59.h" |
28 |
#include "hw/sparc/sparc32_dma.h" |
29 |
#include "hw/block/fdc.h" |
30 |
#include "sysemu/sysemu.h" |
31 |
#include "net/net.h" |
32 |
#include "hw/boards.h" |
33 |
#include "hw/nvram/openbios_firmware_abi.h" |
34 |
#include "hw/scsi/esp.h" |
35 |
#include "hw/i386/pc.h" |
36 |
#include "hw/isa/isa.h" |
37 |
#include "hw/nvram/fw_cfg.h" |
38 |
#include "hw/char/escc.h" |
39 |
#include "hw/empty_slot.h" |
40 |
#include "hw/loader.h" |
41 |
#include "elf.h" |
42 |
#include "sysemu/blockdev.h" |
43 |
#include "trace.h" |
44 |
|
45 |
/*
|
46 |
* Sun4m architecture was used in the following machines:
|
47 |
*
|
48 |
* SPARCserver 6xxMP/xx
|
49 |
* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
|
50 |
* SPARCclassic X (4/10)
|
51 |
* SPARCstation LX/ZX (4/30)
|
52 |
* SPARCstation Voyager
|
53 |
* SPARCstation 10/xx, SPARCserver 10/xx
|
54 |
* SPARCstation 5, SPARCserver 5
|
55 |
* SPARCstation 20/xx, SPARCserver 20
|
56 |
* SPARCstation 4
|
57 |
*
|
58 |
* See for example: http://www.sunhelp.org/faq/sunref1.html
|
59 |
*/
|
60 |
|
61 |
#define KERNEL_LOAD_ADDR 0x00004000 |
62 |
#define CMDLINE_ADDR 0x007ff000 |
63 |
#define INITRD_LOAD_ADDR 0x00800000 |
64 |
#define PROM_SIZE_MAX (1024 * 1024) |
65 |
#define PROM_VADDR 0xffd00000 |
66 |
#define PROM_FILENAME "openbios-sparc32" |
67 |
#define CFG_ADDR 0xd00000510ULL |
68 |
#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
69 |
|
70 |
#define MAX_CPUS 16 |
71 |
#define MAX_PILS 16 |
72 |
#define MAX_VSIMMS 4 |
73 |
|
74 |
#define ESCC_CLOCK 4915200 |
75 |
|
76 |
struct sun4m_hwdef {
|
77 |
hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
78 |
hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; |
79 |
hwaddr serial_base, fd_base; |
80 |
hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; |
81 |
hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
82 |
hwaddr bpp_base, dbri_base, sx_base; |
83 |
struct {
|
84 |
hwaddr reg_base, vram_base; |
85 |
} vsimm[MAX_VSIMMS]; |
86 |
hwaddr ecc_base; |
87 |
uint64_t max_mem; |
88 |
const char * const default_cpu_model; |
89 |
uint32_t ecc_version; |
90 |
uint32_t iommu_version; |
91 |
uint16_t machine_id; |
92 |
uint8_t nvram_machine_id; |
93 |
}; |
94 |
|
95 |
int DMA_get_channel_mode (int nchan) |
96 |
{ |
97 |
return 0; |
98 |
} |
99 |
int DMA_read_memory (int nchan, void *buf, int pos, int size) |
100 |
{ |
101 |
return 0; |
102 |
} |
103 |
int DMA_write_memory (int nchan, void *buf, int pos, int size) |
104 |
{ |
105 |
return 0; |
106 |
} |
107 |
void DMA_hold_DREQ (int nchan) {} |
108 |
void DMA_release_DREQ (int nchan) {} |
109 |
void DMA_schedule(int nchan) {} |
110 |
|
111 |
void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
112 |
{ |
113 |
} |
114 |
|
115 |
void DMA_register_channel (int nchan, |
116 |
DMA_transfer_handler transfer_handler, |
117 |
void *opaque)
|
118 |
{ |
119 |
} |
120 |
|
121 |
static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
122 |
{ |
123 |
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
124 |
return 0; |
125 |
} |
126 |
|
127 |
static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
128 |
const char *cmdline, const char *boot_devices, |
129 |
ram_addr_t RAM_size, uint32_t kernel_size, |
130 |
int width, int height, int depth, |
131 |
int nvram_machine_id, const char *arch) |
132 |
{ |
133 |
unsigned int i; |
134 |
uint32_t start, end; |
135 |
uint8_t image[0x1ff0];
|
136 |
struct OpenBIOS_nvpart_v1 *part_header;
|
137 |
|
138 |
memset(image, '\0', sizeof(image)); |
139 |
|
140 |
start = 0;
|
141 |
|
142 |
// OpenBIOS nvram variables
|
143 |
// Variable partition
|
144 |
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
145 |
part_header->signature = OPENBIOS_PART_SYSTEM; |
146 |
pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
147 |
|
148 |
end = start + sizeof(struct OpenBIOS_nvpart_v1); |
149 |
for (i = 0; i < nb_prom_envs; i++) |
150 |
end = OpenBIOS_set_var(image, end, prom_envs[i]); |
151 |
|
152 |
// End marker
|
153 |
image[end++] = '\0';
|
154 |
|
155 |
end = start + ((end - start + 15) & ~15); |
156 |
OpenBIOS_finish_partition(part_header, end - start); |
157 |
|
158 |
// free partition
|
159 |
start = end; |
160 |
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
161 |
part_header->signature = OPENBIOS_PART_FREE; |
162 |
pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
163 |
|
164 |
end = 0x1fd0;
|
165 |
OpenBIOS_finish_partition(part_header, end - start); |
166 |
|
167 |
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
168 |
nvram_machine_id); |
169 |
|
170 |
for (i = 0; i < sizeof(image); i++) |
171 |
m48t59_write(nvram, i, image[i]); |
172 |
} |
173 |
|
174 |
static DeviceState *slavio_intctl;
|
175 |
|
176 |
void sun4m_pic_info(Monitor *mon, const QDict *qdict) |
177 |
{ |
178 |
if (slavio_intctl)
|
179 |
slavio_pic_info(mon, slavio_intctl); |
180 |
} |
181 |
|
182 |
void sun4m_irq_info(Monitor *mon, const QDict *qdict) |
183 |
{ |
184 |
if (slavio_intctl)
|
185 |
slavio_irq_info(mon, slavio_intctl); |
186 |
} |
187 |
|
188 |
void cpu_check_irqs(CPUSPARCState *env)
|
189 |
{ |
190 |
CPUState *cs; |
191 |
|
192 |
if (env->pil_in && (env->interrupt_index == 0 || |
193 |
(env->interrupt_index & ~15) == TT_EXTINT)) {
|
194 |
unsigned int i; |
195 |
|
196 |
for (i = 15; i > 0; i--) { |
197 |
if (env->pil_in & (1 << i)) { |
198 |
int old_interrupt = env->interrupt_index;
|
199 |
|
200 |
env->interrupt_index = TT_EXTINT | i; |
201 |
if (old_interrupt != env->interrupt_index) {
|
202 |
cs = CPU(sparc_env_get_cpu(env)); |
203 |
trace_sun4m_cpu_interrupt(i); |
204 |
cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
205 |
} |
206 |
break;
|
207 |
} |
208 |
} |
209 |
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
210 |
cs = CPU(sparc_env_get_cpu(env)); |
211 |
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
|
212 |
env->interrupt_index = 0;
|
213 |
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
214 |
} |
215 |
} |
216 |
|
217 |
static void cpu_kick_irq(SPARCCPU *cpu) |
218 |
{ |
219 |
CPUSPARCState *env = &cpu->env; |
220 |
CPUState *cs = CPU(cpu); |
221 |
|
222 |
cs->halted = 0;
|
223 |
cpu_check_irqs(env); |
224 |
qemu_cpu_kick(cs); |
225 |
} |
226 |
|
227 |
static void cpu_set_irq(void *opaque, int irq, int level) |
228 |
{ |
229 |
SPARCCPU *cpu = opaque; |
230 |
CPUSPARCState *env = &cpu->env; |
231 |
|
232 |
if (level) {
|
233 |
trace_sun4m_cpu_set_irq_raise(irq); |
234 |
env->pil_in |= 1 << irq;
|
235 |
cpu_kick_irq(cpu); |
236 |
} else {
|
237 |
trace_sun4m_cpu_set_irq_lower(irq); |
238 |
env->pil_in &= ~(1 << irq);
|
239 |
cpu_check_irqs(env); |
240 |
} |
241 |
} |
242 |
|
243 |
static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
244 |
{ |
245 |
} |
246 |
|
247 |
static void main_cpu_reset(void *opaque) |
248 |
{ |
249 |
SPARCCPU *cpu = opaque; |
250 |
CPUState *cs = CPU(cpu); |
251 |
|
252 |
cpu_reset(cs); |
253 |
cs->halted = 0;
|
254 |
} |
255 |
|
256 |
static void secondary_cpu_reset(void *opaque) |
257 |
{ |
258 |
SPARCCPU *cpu = opaque; |
259 |
CPUState *cs = CPU(cpu); |
260 |
|
261 |
cpu_reset(cs); |
262 |
cs->halted = 1;
|
263 |
} |
264 |
|
265 |
static void cpu_halt_signal(void *opaque, int irq, int level) |
266 |
{ |
267 |
if (level && cpu_single_env) {
|
268 |
cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)), |
269 |
CPU_INTERRUPT_HALT); |
270 |
} |
271 |
} |
272 |
|
273 |
static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
274 |
{ |
275 |
return addr - 0xf0000000ULL; |
276 |
} |
277 |
|
278 |
static unsigned long sun4m_load_kernel(const char *kernel_filename, |
279 |
const char *initrd_filename, |
280 |
ram_addr_t RAM_size) |
281 |
{ |
282 |
int linux_boot;
|
283 |
unsigned int i; |
284 |
long initrd_size, kernel_size;
|
285 |
uint8_t *ptr; |
286 |
|
287 |
linux_boot = (kernel_filename != NULL);
|
288 |
|
289 |
kernel_size = 0;
|
290 |
if (linux_boot) {
|
291 |
int bswap_needed;
|
292 |
|
293 |
#ifdef BSWAP_NEEDED
|
294 |
bswap_needed = 1;
|
295 |
#else
|
296 |
bswap_needed = 0;
|
297 |
#endif
|
298 |
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
299 |
NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
300 |
if (kernel_size < 0) |
301 |
kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
302 |
RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
303 |
TARGET_PAGE_SIZE); |
304 |
if (kernel_size < 0) |
305 |
kernel_size = load_image_targphys(kernel_filename, |
306 |
KERNEL_LOAD_ADDR, |
307 |
RAM_size - KERNEL_LOAD_ADDR); |
308 |
if (kernel_size < 0) { |
309 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
310 |
kernel_filename); |
311 |
exit(1);
|
312 |
} |
313 |
|
314 |
/* load initrd */
|
315 |
initrd_size = 0;
|
316 |
if (initrd_filename) {
|
317 |
initrd_size = load_image_targphys(initrd_filename, |
318 |
INITRD_LOAD_ADDR, |
319 |
RAM_size - INITRD_LOAD_ADDR); |
320 |
if (initrd_size < 0) { |
321 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
322 |
initrd_filename); |
323 |
exit(1);
|
324 |
} |
325 |
} |
326 |
if (initrd_size > 0) { |
327 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
328 |
ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
329 |
if (ldl_p(ptr) == 0x48647253) { // HdrS |
330 |
stl_p(ptr + 16, INITRD_LOAD_ADDR);
|
331 |
stl_p(ptr + 20, initrd_size);
|
332 |
break;
|
333 |
} |
334 |
} |
335 |
} |
336 |
} |
337 |
return kernel_size;
|
338 |
} |
339 |
|
340 |
static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
341 |
{ |
342 |
DeviceState *dev; |
343 |
SysBusDevice *s; |
344 |
|
345 |
dev = qdev_create(NULL, "iommu"); |
346 |
qdev_prop_set_uint32(dev, "version", version);
|
347 |
qdev_init_nofail(dev); |
348 |
s = SYS_BUS_DEVICE(dev); |
349 |
sysbus_connect_irq(s, 0, irq);
|
350 |
sysbus_mmio_map(s, 0, addr);
|
351 |
|
352 |
return s;
|
353 |
} |
354 |
|
355 |
static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, |
356 |
void *iommu, qemu_irq *dev_irq, int is_ledma) |
357 |
{ |
358 |
DeviceState *dev; |
359 |
SysBusDevice *s; |
360 |
|
361 |
dev = qdev_create(NULL, "sparc32_dma"); |
362 |
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
363 |
qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
|
364 |
qdev_init_nofail(dev); |
365 |
s = SYS_BUS_DEVICE(dev); |
366 |
sysbus_connect_irq(s, 0, parent_irq);
|
367 |
*dev_irq = qdev_get_gpio_in(dev, 0);
|
368 |
sysbus_mmio_map(s, 0, daddr);
|
369 |
|
370 |
return s;
|
371 |
} |
372 |
|
373 |
static void lance_init(NICInfo *nd, hwaddr leaddr, |
374 |
void *dma_opaque, qemu_irq irq)
|
375 |
{ |
376 |
DeviceState *dev; |
377 |
SysBusDevice *s; |
378 |
qemu_irq reset; |
379 |
|
380 |
qemu_check_nic_model(&nd_table[0], "lance"); |
381 |
|
382 |
dev = qdev_create(NULL, "lance"); |
383 |
qdev_set_nic_properties(dev, nd); |
384 |
qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
385 |
qdev_init_nofail(dev); |
386 |
s = SYS_BUS_DEVICE(dev); |
387 |
sysbus_mmio_map(s, 0, leaddr);
|
388 |
sysbus_connect_irq(s, 0, irq);
|
389 |
reset = qdev_get_gpio_in(dev, 0);
|
390 |
qdev_connect_gpio_out(dma_opaque, 0, reset);
|
391 |
} |
392 |
|
393 |
static DeviceState *slavio_intctl_init(hwaddr addr,
|
394 |
hwaddr addrg, |
395 |
qemu_irq **parent_irq) |
396 |
{ |
397 |
DeviceState *dev; |
398 |
SysBusDevice *s; |
399 |
unsigned int i, j; |
400 |
|
401 |
dev = qdev_create(NULL, "slavio_intctl"); |
402 |
qdev_init_nofail(dev); |
403 |
|
404 |
s = SYS_BUS_DEVICE(dev); |
405 |
|
406 |
for (i = 0; i < MAX_CPUS; i++) { |
407 |
for (j = 0; j < MAX_PILS; j++) { |
408 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
409 |
} |
410 |
} |
411 |
sysbus_mmio_map(s, 0, addrg);
|
412 |
for (i = 0; i < MAX_CPUS; i++) { |
413 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
414 |
} |
415 |
|
416 |
return dev;
|
417 |
} |
418 |
|
419 |
#define SYS_TIMER_OFFSET 0x10000ULL |
420 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
421 |
|
422 |
static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
423 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
424 |
{ |
425 |
DeviceState *dev; |
426 |
SysBusDevice *s; |
427 |
unsigned int i; |
428 |
|
429 |
dev = qdev_create(NULL, "slavio_timer"); |
430 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
431 |
qdev_init_nofail(dev); |
432 |
s = SYS_BUS_DEVICE(dev); |
433 |
sysbus_connect_irq(s, 0, master_irq);
|
434 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
435 |
|
436 |
for (i = 0; i < MAX_CPUS; i++) { |
437 |
sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
|
438 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
439 |
} |
440 |
} |
441 |
|
442 |
static qemu_irq slavio_system_powerdown;
|
443 |
|
444 |
static void slavio_powerdown_req(Notifier *n, void *opaque) |
445 |
{ |
446 |
qemu_irq_raise(slavio_system_powerdown); |
447 |
} |
448 |
|
449 |
static Notifier slavio_system_powerdown_notifier = {
|
450 |
.notify = slavio_powerdown_req |
451 |
}; |
452 |
|
453 |
#define MISC_LEDS 0x01600000 |
454 |
#define MISC_CFG 0x01800000 |
455 |
#define MISC_DIAG 0x01a00000 |
456 |
#define MISC_MDM 0x01b00000 |
457 |
#define MISC_SYS 0x01f00000 |
458 |
|
459 |
static void slavio_misc_init(hwaddr base, |
460 |
hwaddr aux1_base, |
461 |
hwaddr aux2_base, qemu_irq irq, |
462 |
qemu_irq fdc_tc) |
463 |
{ |
464 |
DeviceState *dev; |
465 |
SysBusDevice *s; |
466 |
|
467 |
dev = qdev_create(NULL, "slavio_misc"); |
468 |
qdev_init_nofail(dev); |
469 |
s = SYS_BUS_DEVICE(dev); |
470 |
if (base) {
|
471 |
/* 8 bit registers */
|
472 |
/* Slavio control */
|
473 |
sysbus_mmio_map(s, 0, base + MISC_CFG);
|
474 |
/* Diagnostics */
|
475 |
sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
476 |
/* Modem control */
|
477 |
sysbus_mmio_map(s, 2, base + MISC_MDM);
|
478 |
/* 16 bit registers */
|
479 |
/* ss600mp diag LEDs */
|
480 |
sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
481 |
/* 32 bit registers */
|
482 |
/* System control */
|
483 |
sysbus_mmio_map(s, 4, base + MISC_SYS);
|
484 |
} |
485 |
if (aux1_base) {
|
486 |
/* AUX 1 (Misc System Functions) */
|
487 |
sysbus_mmio_map(s, 5, aux1_base);
|
488 |
} |
489 |
if (aux2_base) {
|
490 |
/* AUX 2 (Software Powerdown Control) */
|
491 |
sysbus_mmio_map(s, 6, aux2_base);
|
492 |
} |
493 |
sysbus_connect_irq(s, 0, irq);
|
494 |
sysbus_connect_irq(s, 1, fdc_tc);
|
495 |
slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
|
496 |
qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); |
497 |
} |
498 |
|
499 |
static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
500 |
{ |
501 |
DeviceState *dev; |
502 |
SysBusDevice *s; |
503 |
|
504 |
dev = qdev_create(NULL, "eccmemctl"); |
505 |
qdev_prop_set_uint32(dev, "version", version);
|
506 |
qdev_init_nofail(dev); |
507 |
s = SYS_BUS_DEVICE(dev); |
508 |
sysbus_connect_irq(s, 0, irq);
|
509 |
sysbus_mmio_map(s, 0, base);
|
510 |
if (version == 0) { // SS-600MP only |
511 |
sysbus_mmio_map(s, 1, base + 0x1000); |
512 |
} |
513 |
} |
514 |
|
515 |
static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
516 |
{ |
517 |
DeviceState *dev; |
518 |
SysBusDevice *s; |
519 |
|
520 |
dev = qdev_create(NULL, "apc"); |
521 |
qdev_init_nofail(dev); |
522 |
s = SYS_BUS_DEVICE(dev); |
523 |
/* Power management (APC) XXX: not a Slavio device */
|
524 |
sysbus_mmio_map(s, 0, power_base);
|
525 |
sysbus_connect_irq(s, 0, cpu_halt);
|
526 |
} |
527 |
|
528 |
static void tcx_init(hwaddr addr, int vram_size, int width, |
529 |
int height, int depth) |
530 |
{ |
531 |
DeviceState *dev; |
532 |
SysBusDevice *s; |
533 |
|
534 |
dev = qdev_create(NULL, "SUNW,tcx"); |
535 |
qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
536 |
qdev_prop_set_uint16(dev, "width", width);
|
537 |
qdev_prop_set_uint16(dev, "height", height);
|
538 |
qdev_prop_set_uint16(dev, "depth", depth);
|
539 |
qdev_init_nofail(dev); |
540 |
s = SYS_BUS_DEVICE(dev); |
541 |
/* 8-bit plane */
|
542 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
543 |
/* DAC */
|
544 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
545 |
/* TEC (dummy) */
|
546 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
547 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
548 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
549 |
if (depth == 24) { |
550 |
/* 24-bit plane */
|
551 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
552 |
/* Control plane */
|
553 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
554 |
} else {
|
555 |
/* THC 8 bit (dummy) */
|
556 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
557 |
} |
558 |
} |
559 |
|
560 |
/* NCR89C100/MACIO Internal ID register */
|
561 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
562 |
|
563 |
static void idreg_init(hwaddr addr) |
564 |
{ |
565 |
DeviceState *dev; |
566 |
SysBusDevice *s; |
567 |
|
568 |
dev = qdev_create(NULL, "macio_idreg"); |
569 |
qdev_init_nofail(dev); |
570 |
s = SYS_BUS_DEVICE(dev); |
571 |
|
572 |
sysbus_mmio_map(s, 0, addr);
|
573 |
cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
574 |
} |
575 |
|
576 |
typedef struct IDRegState { |
577 |
SysBusDevice busdev; |
578 |
MemoryRegion mem; |
579 |
} IDRegState; |
580 |
|
581 |
static int idreg_init1(SysBusDevice *dev) |
582 |
{ |
583 |
IDRegState *s = FROM_SYSBUS(IDRegState, dev); |
584 |
|
585 |
memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data)); |
586 |
vmstate_register_ram_global(&s->mem); |
587 |
memory_region_set_readonly(&s->mem, true);
|
588 |
sysbus_init_mmio(dev, &s->mem); |
589 |
return 0; |
590 |
} |
591 |
|
592 |
static void idreg_class_init(ObjectClass *klass, void *data) |
593 |
{ |
594 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
595 |
|
596 |
k->init = idreg_init1; |
597 |
} |
598 |
|
599 |
static const TypeInfo idreg_info = { |
600 |
.name = "macio_idreg",
|
601 |
.parent = TYPE_SYS_BUS_DEVICE, |
602 |
.instance_size = sizeof(IDRegState),
|
603 |
.class_init = idreg_class_init, |
604 |
}; |
605 |
|
606 |
typedef struct AFXState { |
607 |
SysBusDevice busdev; |
608 |
MemoryRegion mem; |
609 |
} AFXState; |
610 |
|
611 |
/* SS-5 TCX AFX register */
|
612 |
static void afx_init(hwaddr addr) |
613 |
{ |
614 |
DeviceState *dev; |
615 |
SysBusDevice *s; |
616 |
|
617 |
dev = qdev_create(NULL, "tcx_afx"); |
618 |
qdev_init_nofail(dev); |
619 |
s = SYS_BUS_DEVICE(dev); |
620 |
|
621 |
sysbus_mmio_map(s, 0, addr);
|
622 |
} |
623 |
|
624 |
static int afx_init1(SysBusDevice *dev) |
625 |
{ |
626 |
AFXState *s = FROM_SYSBUS(AFXState, dev); |
627 |
|
628 |
memory_region_init_ram(&s->mem, "sun4m.afx", 4); |
629 |
vmstate_register_ram_global(&s->mem); |
630 |
sysbus_init_mmio(dev, &s->mem); |
631 |
return 0; |
632 |
} |
633 |
|
634 |
static void afx_class_init(ObjectClass *klass, void *data) |
635 |
{ |
636 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
637 |
|
638 |
k->init = afx_init1; |
639 |
} |
640 |
|
641 |
static const TypeInfo afx_info = { |
642 |
.name = "tcx_afx",
|
643 |
.parent = TYPE_SYS_BUS_DEVICE, |
644 |
.instance_size = sizeof(AFXState),
|
645 |
.class_init = afx_class_init, |
646 |
}; |
647 |
|
648 |
typedef struct PROMState { |
649 |
SysBusDevice busdev; |
650 |
MemoryRegion prom; |
651 |
} PROMState; |
652 |
|
653 |
/* Boot PROM (OpenBIOS) */
|
654 |
static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
655 |
{ |
656 |
hwaddr *base_addr = (hwaddr *)opaque; |
657 |
return addr + *base_addr - PROM_VADDR;
|
658 |
} |
659 |
|
660 |
static void prom_init(hwaddr addr, const char *bios_name) |
661 |
{ |
662 |
DeviceState *dev; |
663 |
SysBusDevice *s; |
664 |
char *filename;
|
665 |
int ret;
|
666 |
|
667 |
dev = qdev_create(NULL, "openprom"); |
668 |
qdev_init_nofail(dev); |
669 |
s = SYS_BUS_DEVICE(dev); |
670 |
|
671 |
sysbus_mmio_map(s, 0, addr);
|
672 |
|
673 |
/* load boot prom */
|
674 |
if (bios_name == NULL) { |
675 |
bios_name = PROM_FILENAME; |
676 |
} |
677 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
678 |
if (filename) {
|
679 |
ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
680 |
NULL, NULL, 1, ELF_MACHINE, 0); |
681 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
682 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
683 |
} |
684 |
g_free(filename); |
685 |
} else {
|
686 |
ret = -1;
|
687 |
} |
688 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
689 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
690 |
exit(1);
|
691 |
} |
692 |
} |
693 |
|
694 |
static int prom_init1(SysBusDevice *dev) |
695 |
{ |
696 |
PROMState *s = FROM_SYSBUS(PROMState, dev); |
697 |
|
698 |
memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
|
699 |
vmstate_register_ram_global(&s->prom); |
700 |
memory_region_set_readonly(&s->prom, true);
|
701 |
sysbus_init_mmio(dev, &s->prom); |
702 |
return 0; |
703 |
} |
704 |
|
705 |
static Property prom_properties[] = {
|
706 |
{/* end of property list */},
|
707 |
}; |
708 |
|
709 |
static void prom_class_init(ObjectClass *klass, void *data) |
710 |
{ |
711 |
DeviceClass *dc = DEVICE_CLASS(klass); |
712 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
713 |
|
714 |
k->init = prom_init1; |
715 |
dc->props = prom_properties; |
716 |
} |
717 |
|
718 |
static const TypeInfo prom_info = { |
719 |
.name = "openprom",
|
720 |
.parent = TYPE_SYS_BUS_DEVICE, |
721 |
.instance_size = sizeof(PROMState),
|
722 |
.class_init = prom_class_init, |
723 |
}; |
724 |
|
725 |
typedef struct RamDevice |
726 |
{ |
727 |
SysBusDevice busdev; |
728 |
MemoryRegion ram; |
729 |
uint64_t size; |
730 |
} RamDevice; |
731 |
|
732 |
/* System RAM */
|
733 |
static int ram_init1(SysBusDevice *dev) |
734 |
{ |
735 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
736 |
|
737 |
memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
|
738 |
vmstate_register_ram_global(&d->ram); |
739 |
sysbus_init_mmio(dev, &d->ram); |
740 |
return 0; |
741 |
} |
742 |
|
743 |
static void ram_init(hwaddr addr, ram_addr_t RAM_size, |
744 |
uint64_t max_mem) |
745 |
{ |
746 |
DeviceState *dev; |
747 |
SysBusDevice *s; |
748 |
RamDevice *d; |
749 |
|
750 |
/* allocate RAM */
|
751 |
if ((uint64_t)RAM_size > max_mem) {
|
752 |
fprintf(stderr, |
753 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
754 |
(unsigned int)(RAM_size / (1024 * 1024)), |
755 |
(unsigned int)(max_mem / (1024 * 1024))); |
756 |
exit(1);
|
757 |
} |
758 |
dev = qdev_create(NULL, "memory"); |
759 |
s = SYS_BUS_DEVICE(dev); |
760 |
|
761 |
d = FROM_SYSBUS(RamDevice, s); |
762 |
d->size = RAM_size; |
763 |
qdev_init_nofail(dev); |
764 |
|
765 |
sysbus_mmio_map(s, 0, addr);
|
766 |
} |
767 |
|
768 |
static Property ram_properties[] = {
|
769 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
770 |
DEFINE_PROP_END_OF_LIST(), |
771 |
}; |
772 |
|
773 |
static void ram_class_init(ObjectClass *klass, void *data) |
774 |
{ |
775 |
DeviceClass *dc = DEVICE_CLASS(klass); |
776 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
777 |
|
778 |
k->init = ram_init1; |
779 |
dc->props = ram_properties; |
780 |
} |
781 |
|
782 |
static const TypeInfo ram_info = { |
783 |
.name = "memory",
|
784 |
.parent = TYPE_SYS_BUS_DEVICE, |
785 |
.instance_size = sizeof(RamDevice),
|
786 |
.class_init = ram_class_init, |
787 |
}; |
788 |
|
789 |
static void cpu_devinit(const char *cpu_model, unsigned int id, |
790 |
uint64_t prom_addr, qemu_irq **cpu_irqs) |
791 |
{ |
792 |
CPUState *cs; |
793 |
SPARCCPU *cpu; |
794 |
CPUSPARCState *env; |
795 |
|
796 |
cpu = cpu_sparc_init(cpu_model); |
797 |
if (cpu == NULL) { |
798 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
799 |
exit(1);
|
800 |
} |
801 |
env = &cpu->env; |
802 |
|
803 |
cpu_sparc_set_id(env, id); |
804 |
if (id == 0) { |
805 |
qemu_register_reset(main_cpu_reset, cpu); |
806 |
} else {
|
807 |
qemu_register_reset(secondary_cpu_reset, cpu); |
808 |
cs = CPU(cpu); |
809 |
cs->halted = 1;
|
810 |
} |
811 |
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
812 |
env->prom_addr = prom_addr; |
813 |
} |
814 |
|
815 |
static void dummy_fdc_tc(void *opaque, int irq, int level) |
816 |
{ |
817 |
} |
818 |
|
819 |
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
820 |
const char *boot_device, |
821 |
const char *kernel_filename, |
822 |
const char *kernel_cmdline, |
823 |
const char *initrd_filename, const char *cpu_model) |
824 |
{ |
825 |
unsigned int i; |
826 |
void *iommu, *espdma, *ledma, *nvram;
|
827 |
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
828 |
espdma_irq, ledma_irq; |
829 |
qemu_irq esp_reset, dma_enable; |
830 |
qemu_irq fdc_tc; |
831 |
qemu_irq *cpu_halt; |
832 |
unsigned long kernel_size; |
833 |
DriveInfo *fd[MAX_FD]; |
834 |
void *fw_cfg;
|
835 |
unsigned int num_vsimms; |
836 |
|
837 |
/* init CPUs */
|
838 |
if (!cpu_model)
|
839 |
cpu_model = hwdef->default_cpu_model; |
840 |
|
841 |
for(i = 0; i < smp_cpus; i++) { |
842 |
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
843 |
} |
844 |
|
845 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
846 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
847 |
|
848 |
|
849 |
/* set up devices */
|
850 |
ram_init(0, RAM_size, hwdef->max_mem);
|
851 |
/* models without ECC don't trap when missing ram is accessed */
|
852 |
if (!hwdef->ecc_base) {
|
853 |
empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); |
854 |
} |
855 |
|
856 |
prom_init(hwdef->slavio_base, bios_name); |
857 |
|
858 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
859 |
hwdef->intctl_base + 0x10000ULL,
|
860 |
cpu_irqs); |
861 |
|
862 |
for (i = 0; i < 32; i++) { |
863 |
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
864 |
} |
865 |
for (i = 0; i < MAX_CPUS; i++) { |
866 |
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
867 |
} |
868 |
|
869 |
if (hwdef->idreg_base) {
|
870 |
idreg_init(hwdef->idreg_base); |
871 |
} |
872 |
|
873 |
if (hwdef->afx_base) {
|
874 |
afx_init(hwdef->afx_base); |
875 |
} |
876 |
|
877 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
878 |
slavio_irq[30]);
|
879 |
|
880 |
if (hwdef->iommu_pad_base) {
|
881 |
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
882 |
Software shouldn't use aliased addresses, neither should it crash
|
883 |
when does. Using empty_slot instead of aliasing can help with
|
884 |
debugging such accesses */
|
885 |
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); |
886 |
} |
887 |
|
888 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
889 |
iommu, &espdma_irq, 0);
|
890 |
|
891 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
892 |
slavio_irq[16], iommu, &ledma_irq, 1); |
893 |
|
894 |
if (graphic_depth != 8 && graphic_depth != 24) { |
895 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
896 |
exit (1);
|
897 |
} |
898 |
num_vsimms = 0;
|
899 |
if (num_vsimms == 0) { |
900 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
901 |
graphic_depth); |
902 |
} |
903 |
|
904 |
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
905 |
/* vsimm registers probed by OBP */
|
906 |
if (hwdef->vsimm[i].reg_base) {
|
907 |
empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
|
908 |
} |
909 |
} |
910 |
|
911 |
if (hwdef->sx_base) {
|
912 |
empty_slot_init(hwdef->sx_base, 0x2000);
|
913 |
} |
914 |
|
915 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
916 |
|
917 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
918 |
|
919 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
920 |
|
921 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
922 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
923 |
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
|
924 |
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
|
925 |
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
926 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
927 |
|
928 |
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
929 |
if (hwdef->apc_base) {
|
930 |
apc_init(hwdef->apc_base, cpu_halt[0]);
|
931 |
} |
932 |
|
933 |
if (hwdef->fd_base) {
|
934 |
/* there is zero or one floppy drive */
|
935 |
memset(fd, 0, sizeof(fd)); |
936 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
937 |
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
938 |
&fdc_tc); |
939 |
} else {
|
940 |
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); |
941 |
} |
942 |
|
943 |
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
944 |
slavio_irq[30], fdc_tc);
|
945 |
|
946 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
947 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
948 |
exit(1);
|
949 |
} |
950 |
|
951 |
esp_init(hwdef->esp_base, 2,
|
952 |
espdma_memory_read, espdma_memory_write, |
953 |
espdma, espdma_irq, &esp_reset, &dma_enable); |
954 |
|
955 |
qdev_connect_gpio_out(espdma, 0, esp_reset);
|
956 |
qdev_connect_gpio_out(espdma, 1, dma_enable);
|
957 |
|
958 |
if (hwdef->cs_base) {
|
959 |
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
960 |
slavio_irq[5]);
|
961 |
} |
962 |
|
963 |
if (hwdef->dbri_base) {
|
964 |
/* ISDN chip with attached CS4215 audio codec */
|
965 |
/* prom space */
|
966 |
empty_slot_init(hwdef->dbri_base+0x1000, 0x30); |
967 |
/* reg space */
|
968 |
empty_slot_init(hwdef->dbri_base+0x10000, 0x100); |
969 |
} |
970 |
|
971 |
if (hwdef->bpp_base) {
|
972 |
/* parallel port */
|
973 |
empty_slot_init(hwdef->bpp_base, 0x20);
|
974 |
} |
975 |
|
976 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
977 |
RAM_size); |
978 |
|
979 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
980 |
boot_device, RAM_size, kernel_size, graphic_width, |
981 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
982 |
"Sun4m");
|
983 |
|
984 |
if (hwdef->ecc_base)
|
985 |
ecc_init(hwdef->ecc_base, slavio_irq[28],
|
986 |
hwdef->ecc_version); |
987 |
|
988 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
989 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
990 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
991 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
992 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
993 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
994 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
995 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
996 |
if (kernel_cmdline) {
|
997 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
998 |
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
999 |
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
1000 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
1001 |
strlen(kernel_cmdline) + 1);
|
1002 |
} else {
|
1003 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1004 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
1005 |
} |
1006 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1007 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1008 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1009 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1010 |
} |
1011 |
|
1012 |
enum {
|
1013 |
ss5_id = 32,
|
1014 |
vger_id, |
1015 |
lx_id, |
1016 |
ss4_id, |
1017 |
scls_id, |
1018 |
sbook_id, |
1019 |
ss10_id = 64,
|
1020 |
ss20_id, |
1021 |
ss600mp_id, |
1022 |
}; |
1023 |
|
1024 |
static const struct sun4m_hwdef sun4m_hwdefs[] = { |
1025 |
/* SS-5 */
|
1026 |
{ |
1027 |
.iommu_base = 0x10000000,
|
1028 |
.iommu_pad_base = 0x10004000,
|
1029 |
.iommu_pad_len = 0x0fffb000,
|
1030 |
.tcx_base = 0x50000000,
|
1031 |
.cs_base = 0x6c000000,
|
1032 |
.slavio_base = 0x70000000,
|
1033 |
.ms_kb_base = 0x71000000,
|
1034 |
.serial_base = 0x71100000,
|
1035 |
.nvram_base = 0x71200000,
|
1036 |
.fd_base = 0x71400000,
|
1037 |
.counter_base = 0x71d00000,
|
1038 |
.intctl_base = 0x71e00000,
|
1039 |
.idreg_base = 0x78000000,
|
1040 |
.dma_base = 0x78400000,
|
1041 |
.esp_base = 0x78800000,
|
1042 |
.le_base = 0x78c00000,
|
1043 |
.apc_base = 0x6a000000,
|
1044 |
.afx_base = 0x6e000000,
|
1045 |
.aux1_base = 0x71900000,
|
1046 |
.aux2_base = 0x71910000,
|
1047 |
.nvram_machine_id = 0x80,
|
1048 |
.machine_id = ss5_id, |
1049 |
.iommu_version = 0x05000000,
|
1050 |
.max_mem = 0x10000000,
|
1051 |
.default_cpu_model = "Fujitsu MB86904",
|
1052 |
}, |
1053 |
/* SS-10 */
|
1054 |
{ |
1055 |
.iommu_base = 0xfe0000000ULL,
|
1056 |
.tcx_base = 0xe20000000ULL,
|
1057 |
.slavio_base = 0xff0000000ULL,
|
1058 |
.ms_kb_base = 0xff1000000ULL,
|
1059 |
.serial_base = 0xff1100000ULL,
|
1060 |
.nvram_base = 0xff1200000ULL,
|
1061 |
.fd_base = 0xff1700000ULL,
|
1062 |
.counter_base = 0xff1300000ULL,
|
1063 |
.intctl_base = 0xff1400000ULL,
|
1064 |
.idreg_base = 0xef0000000ULL,
|
1065 |
.dma_base = 0xef0400000ULL,
|
1066 |
.esp_base = 0xef0800000ULL,
|
1067 |
.le_base = 0xef0c00000ULL,
|
1068 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1069 |
.aux1_base = 0xff1800000ULL,
|
1070 |
.aux2_base = 0xff1a01000ULL,
|
1071 |
.ecc_base = 0xf00000000ULL,
|
1072 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
1073 |
.nvram_machine_id = 0x72,
|
1074 |
.machine_id = ss10_id, |
1075 |
.iommu_version = 0x03000000,
|
1076 |
.max_mem = 0xf00000000ULL,
|
1077 |
.default_cpu_model = "TI SuperSparc II",
|
1078 |
}, |
1079 |
/* SS-600MP */
|
1080 |
{ |
1081 |
.iommu_base = 0xfe0000000ULL,
|
1082 |
.tcx_base = 0xe20000000ULL,
|
1083 |
.slavio_base = 0xff0000000ULL,
|
1084 |
.ms_kb_base = 0xff1000000ULL,
|
1085 |
.serial_base = 0xff1100000ULL,
|
1086 |
.nvram_base = 0xff1200000ULL,
|
1087 |
.counter_base = 0xff1300000ULL,
|
1088 |
.intctl_base = 0xff1400000ULL,
|
1089 |
.dma_base = 0xef0081000ULL,
|
1090 |
.esp_base = 0xef0080000ULL,
|
1091 |
.le_base = 0xef0060000ULL,
|
1092 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1093 |
.aux1_base = 0xff1800000ULL,
|
1094 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
1095 |
.ecc_base = 0xf00000000ULL,
|
1096 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
1097 |
.nvram_machine_id = 0x71,
|
1098 |
.machine_id = ss600mp_id, |
1099 |
.iommu_version = 0x01000000,
|
1100 |
.max_mem = 0xf00000000ULL,
|
1101 |
.default_cpu_model = "TI SuperSparc II",
|
1102 |
}, |
1103 |
/* SS-20 */
|
1104 |
{ |
1105 |
.iommu_base = 0xfe0000000ULL,
|
1106 |
.tcx_base = 0xe20000000ULL,
|
1107 |
.slavio_base = 0xff0000000ULL,
|
1108 |
.ms_kb_base = 0xff1000000ULL,
|
1109 |
.serial_base = 0xff1100000ULL,
|
1110 |
.nvram_base = 0xff1200000ULL,
|
1111 |
.fd_base = 0xff1700000ULL,
|
1112 |
.counter_base = 0xff1300000ULL,
|
1113 |
.intctl_base = 0xff1400000ULL,
|
1114 |
.idreg_base = 0xef0000000ULL,
|
1115 |
.dma_base = 0xef0400000ULL,
|
1116 |
.esp_base = 0xef0800000ULL,
|
1117 |
.le_base = 0xef0c00000ULL,
|
1118 |
.bpp_base = 0xef4800000ULL,
|
1119 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1120 |
.aux1_base = 0xff1800000ULL,
|
1121 |
.aux2_base = 0xff1a01000ULL,
|
1122 |
.dbri_base = 0xee0000000ULL,
|
1123 |
.sx_base = 0xf80000000ULL,
|
1124 |
.vsimm = { |
1125 |
{ |
1126 |
.reg_base = 0x9c000000ULL,
|
1127 |
.vram_base = 0xfc000000ULL
|
1128 |
}, { |
1129 |
.reg_base = 0x90000000ULL,
|
1130 |
.vram_base = 0xf0000000ULL
|
1131 |
}, { |
1132 |
.reg_base = 0x94000000ULL
|
1133 |
}, { |
1134 |
.reg_base = 0x98000000ULL
|
1135 |
} |
1136 |
}, |
1137 |
.ecc_base = 0xf00000000ULL,
|
1138 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
1139 |
.nvram_machine_id = 0x72,
|
1140 |
.machine_id = ss20_id, |
1141 |
.iommu_version = 0x13000000,
|
1142 |
.max_mem = 0xf00000000ULL,
|
1143 |
.default_cpu_model = "TI SuperSparc II",
|
1144 |
}, |
1145 |
/* Voyager */
|
1146 |
{ |
1147 |
.iommu_base = 0x10000000,
|
1148 |
.tcx_base = 0x50000000,
|
1149 |
.slavio_base = 0x70000000,
|
1150 |
.ms_kb_base = 0x71000000,
|
1151 |
.serial_base = 0x71100000,
|
1152 |
.nvram_base = 0x71200000,
|
1153 |
.fd_base = 0x71400000,
|
1154 |
.counter_base = 0x71d00000,
|
1155 |
.intctl_base = 0x71e00000,
|
1156 |
.idreg_base = 0x78000000,
|
1157 |
.dma_base = 0x78400000,
|
1158 |
.esp_base = 0x78800000,
|
1159 |
.le_base = 0x78c00000,
|
1160 |
.apc_base = 0x71300000, // pmc |
1161 |
.aux1_base = 0x71900000,
|
1162 |
.aux2_base = 0x71910000,
|
1163 |
.nvram_machine_id = 0x80,
|
1164 |
.machine_id = vger_id, |
1165 |
.iommu_version = 0x05000000,
|
1166 |
.max_mem = 0x10000000,
|
1167 |
.default_cpu_model = "Fujitsu MB86904",
|
1168 |
}, |
1169 |
/* LX */
|
1170 |
{ |
1171 |
.iommu_base = 0x10000000,
|
1172 |
.iommu_pad_base = 0x10004000,
|
1173 |
.iommu_pad_len = 0x0fffb000,
|
1174 |
.tcx_base = 0x50000000,
|
1175 |
.slavio_base = 0x70000000,
|
1176 |
.ms_kb_base = 0x71000000,
|
1177 |
.serial_base = 0x71100000,
|
1178 |
.nvram_base = 0x71200000,
|
1179 |
.fd_base = 0x71400000,
|
1180 |
.counter_base = 0x71d00000,
|
1181 |
.intctl_base = 0x71e00000,
|
1182 |
.idreg_base = 0x78000000,
|
1183 |
.dma_base = 0x78400000,
|
1184 |
.esp_base = 0x78800000,
|
1185 |
.le_base = 0x78c00000,
|
1186 |
.aux1_base = 0x71900000,
|
1187 |
.aux2_base = 0x71910000,
|
1188 |
.nvram_machine_id = 0x80,
|
1189 |
.machine_id = lx_id, |
1190 |
.iommu_version = 0x04000000,
|
1191 |
.max_mem = 0x10000000,
|
1192 |
.default_cpu_model = "TI MicroSparc I",
|
1193 |
}, |
1194 |
/* SS-4 */
|
1195 |
{ |
1196 |
.iommu_base = 0x10000000,
|
1197 |
.tcx_base = 0x50000000,
|
1198 |
.cs_base = 0x6c000000,
|
1199 |
.slavio_base = 0x70000000,
|
1200 |
.ms_kb_base = 0x71000000,
|
1201 |
.serial_base = 0x71100000,
|
1202 |
.nvram_base = 0x71200000,
|
1203 |
.fd_base = 0x71400000,
|
1204 |
.counter_base = 0x71d00000,
|
1205 |
.intctl_base = 0x71e00000,
|
1206 |
.idreg_base = 0x78000000,
|
1207 |
.dma_base = 0x78400000,
|
1208 |
.esp_base = 0x78800000,
|
1209 |
.le_base = 0x78c00000,
|
1210 |
.apc_base = 0x6a000000,
|
1211 |
.aux1_base = 0x71900000,
|
1212 |
.aux2_base = 0x71910000,
|
1213 |
.nvram_machine_id = 0x80,
|
1214 |
.machine_id = ss4_id, |
1215 |
.iommu_version = 0x05000000,
|
1216 |
.max_mem = 0x10000000,
|
1217 |
.default_cpu_model = "Fujitsu MB86904",
|
1218 |
}, |
1219 |
/* SPARCClassic */
|
1220 |
{ |
1221 |
.iommu_base = 0x10000000,
|
1222 |
.tcx_base = 0x50000000,
|
1223 |
.slavio_base = 0x70000000,
|
1224 |
.ms_kb_base = 0x71000000,
|
1225 |
.serial_base = 0x71100000,
|
1226 |
.nvram_base = 0x71200000,
|
1227 |
.fd_base = 0x71400000,
|
1228 |
.counter_base = 0x71d00000,
|
1229 |
.intctl_base = 0x71e00000,
|
1230 |
.idreg_base = 0x78000000,
|
1231 |
.dma_base = 0x78400000,
|
1232 |
.esp_base = 0x78800000,
|
1233 |
.le_base = 0x78c00000,
|
1234 |
.apc_base = 0x6a000000,
|
1235 |
.aux1_base = 0x71900000,
|
1236 |
.aux2_base = 0x71910000,
|
1237 |
.nvram_machine_id = 0x80,
|
1238 |
.machine_id = scls_id, |
1239 |
.iommu_version = 0x05000000,
|
1240 |
.max_mem = 0x10000000,
|
1241 |
.default_cpu_model = "TI MicroSparc I",
|
1242 |
}, |
1243 |
/* SPARCbook */
|
1244 |
{ |
1245 |
.iommu_base = 0x10000000,
|
1246 |
.tcx_base = 0x50000000, // XXX |
1247 |
.slavio_base = 0x70000000,
|
1248 |
.ms_kb_base = 0x71000000,
|
1249 |
.serial_base = 0x71100000,
|
1250 |
.nvram_base = 0x71200000,
|
1251 |
.fd_base = 0x71400000,
|
1252 |
.counter_base = 0x71d00000,
|
1253 |
.intctl_base = 0x71e00000,
|
1254 |
.idreg_base = 0x78000000,
|
1255 |
.dma_base = 0x78400000,
|
1256 |
.esp_base = 0x78800000,
|
1257 |
.le_base = 0x78c00000,
|
1258 |
.apc_base = 0x6a000000,
|
1259 |
.aux1_base = 0x71900000,
|
1260 |
.aux2_base = 0x71910000,
|
1261 |
.nvram_machine_id = 0x80,
|
1262 |
.machine_id = sbook_id, |
1263 |
.iommu_version = 0x05000000,
|
1264 |
.max_mem = 0x10000000,
|
1265 |
.default_cpu_model = "TI MicroSparc I",
|
1266 |
}, |
1267 |
}; |
1268 |
|
1269 |
/* SPARCstation 5 hardware initialisation */
|
1270 |
static void ss5_init(QEMUMachineInitArgs *args) |
1271 |
{ |
1272 |
ram_addr_t RAM_size = args->ram_size; |
1273 |
const char *cpu_model = args->cpu_model; |
1274 |
const char *kernel_filename = args->kernel_filename; |
1275 |
const char *kernel_cmdline = args->kernel_cmdline; |
1276 |
const char *initrd_filename = args->initrd_filename; |
1277 |
const char *boot_device = args->boot_device; |
1278 |
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1279 |
kernel_cmdline, initrd_filename, cpu_model); |
1280 |
} |
1281 |
|
1282 |
/* SPARCstation 10 hardware initialisation */
|
1283 |
static void ss10_init(QEMUMachineInitArgs *args) |
1284 |
{ |
1285 |
ram_addr_t RAM_size = args->ram_size; |
1286 |
const char *cpu_model = args->cpu_model; |
1287 |
const char *kernel_filename = args->kernel_filename; |
1288 |
const char *kernel_cmdline = args->kernel_cmdline; |
1289 |
const char *initrd_filename = args->initrd_filename; |
1290 |
const char *boot_device = args->boot_device; |
1291 |
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1292 |
kernel_cmdline, initrd_filename, cpu_model); |
1293 |
} |
1294 |
|
1295 |
/* SPARCserver 600MP hardware initialisation */
|
1296 |
static void ss600mp_init(QEMUMachineInitArgs *args) |
1297 |
{ |
1298 |
ram_addr_t RAM_size = args->ram_size; |
1299 |
const char *cpu_model = args->cpu_model; |
1300 |
const char *kernel_filename = args->kernel_filename; |
1301 |
const char *kernel_cmdline = args->kernel_cmdline; |
1302 |
const char *initrd_filename = args->initrd_filename; |
1303 |
const char *boot_device = args->boot_device; |
1304 |
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1305 |
kernel_cmdline, initrd_filename, cpu_model); |
1306 |
} |
1307 |
|
1308 |
/* SPARCstation 20 hardware initialisation */
|
1309 |
static void ss20_init(QEMUMachineInitArgs *args) |
1310 |
{ |
1311 |
ram_addr_t RAM_size = args->ram_size; |
1312 |
const char *cpu_model = args->cpu_model; |
1313 |
const char *kernel_filename = args->kernel_filename; |
1314 |
const char *kernel_cmdline = args->kernel_cmdline; |
1315 |
const char *initrd_filename = args->initrd_filename; |
1316 |
const char *boot_device = args->boot_device; |
1317 |
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1318 |
kernel_cmdline, initrd_filename, cpu_model); |
1319 |
} |
1320 |
|
1321 |
/* SPARCstation Voyager hardware initialisation */
|
1322 |
static void vger_init(QEMUMachineInitArgs *args) |
1323 |
{ |
1324 |
ram_addr_t RAM_size = args->ram_size; |
1325 |
const char *cpu_model = args->cpu_model; |
1326 |
const char *kernel_filename = args->kernel_filename; |
1327 |
const char *kernel_cmdline = args->kernel_cmdline; |
1328 |
const char *initrd_filename = args->initrd_filename; |
1329 |
const char *boot_device = args->boot_device; |
1330 |
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1331 |
kernel_cmdline, initrd_filename, cpu_model); |
1332 |
} |
1333 |
|
1334 |
/* SPARCstation LX hardware initialisation */
|
1335 |
static void ss_lx_init(QEMUMachineInitArgs *args) |
1336 |
{ |
1337 |
ram_addr_t RAM_size = args->ram_size; |
1338 |
const char *cpu_model = args->cpu_model; |
1339 |
const char *kernel_filename = args->kernel_filename; |
1340 |
const char *kernel_cmdline = args->kernel_cmdline; |
1341 |
const char *initrd_filename = args->initrd_filename; |
1342 |
const char *boot_device = args->boot_device; |
1343 |
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1344 |
kernel_cmdline, initrd_filename, cpu_model); |
1345 |
} |
1346 |
|
1347 |
/* SPARCstation 4 hardware initialisation */
|
1348 |
static void ss4_init(QEMUMachineInitArgs *args) |
1349 |
{ |
1350 |
ram_addr_t RAM_size = args->ram_size; |
1351 |
const char *cpu_model = args->cpu_model; |
1352 |
const char *kernel_filename = args->kernel_filename; |
1353 |
const char *kernel_cmdline = args->kernel_cmdline; |
1354 |
const char *initrd_filename = args->initrd_filename; |
1355 |
const char *boot_device = args->boot_device; |
1356 |
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1357 |
kernel_cmdline, initrd_filename, cpu_model); |
1358 |
} |
1359 |
|
1360 |
/* SPARCClassic hardware initialisation */
|
1361 |
static void scls_init(QEMUMachineInitArgs *args) |
1362 |
{ |
1363 |
ram_addr_t RAM_size = args->ram_size; |
1364 |
const char *cpu_model = args->cpu_model; |
1365 |
const char *kernel_filename = args->kernel_filename; |
1366 |
const char *kernel_cmdline = args->kernel_cmdline; |
1367 |
const char *initrd_filename = args->initrd_filename; |
1368 |
const char *boot_device = args->boot_device; |
1369 |
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1370 |
kernel_cmdline, initrd_filename, cpu_model); |
1371 |
} |
1372 |
|
1373 |
/* SPARCbook hardware initialisation */
|
1374 |
static void sbook_init(QEMUMachineInitArgs *args) |
1375 |
{ |
1376 |
ram_addr_t RAM_size = args->ram_size; |
1377 |
const char *cpu_model = args->cpu_model; |
1378 |
const char *kernel_filename = args->kernel_filename; |
1379 |
const char *kernel_cmdline = args->kernel_cmdline; |
1380 |
const char *initrd_filename = args->initrd_filename; |
1381 |
const char *boot_device = args->boot_device; |
1382 |
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1383 |
kernel_cmdline, initrd_filename, cpu_model); |
1384 |
} |
1385 |
|
1386 |
static QEMUMachine ss5_machine = {
|
1387 |
.name = "SS-5",
|
1388 |
.desc = "Sun4m platform, SPARCstation 5",
|
1389 |
.init = ss5_init, |
1390 |
.block_default_type = IF_SCSI, |
1391 |
.is_default = 1,
|
1392 |
DEFAULT_MACHINE_OPTIONS, |
1393 |
}; |
1394 |
|
1395 |
static QEMUMachine ss10_machine = {
|
1396 |
.name = "SS-10",
|
1397 |
.desc = "Sun4m platform, SPARCstation 10",
|
1398 |
.init = ss10_init, |
1399 |
.block_default_type = IF_SCSI, |
1400 |
.max_cpus = 4,
|
1401 |
DEFAULT_MACHINE_OPTIONS, |
1402 |
}; |
1403 |
|
1404 |
static QEMUMachine ss600mp_machine = {
|
1405 |
.name = "SS-600MP",
|
1406 |
.desc = "Sun4m platform, SPARCserver 600MP",
|
1407 |
.init = ss600mp_init, |
1408 |
.block_default_type = IF_SCSI, |
1409 |
.max_cpus = 4,
|
1410 |
DEFAULT_MACHINE_OPTIONS, |
1411 |
}; |
1412 |
|
1413 |
static QEMUMachine ss20_machine = {
|
1414 |
.name = "SS-20",
|
1415 |
.desc = "Sun4m platform, SPARCstation 20",
|
1416 |
.init = ss20_init, |
1417 |
.block_default_type = IF_SCSI, |
1418 |
.max_cpus = 4,
|
1419 |
DEFAULT_MACHINE_OPTIONS, |
1420 |
}; |
1421 |
|
1422 |
static QEMUMachine voyager_machine = {
|
1423 |
.name = "Voyager",
|
1424 |
.desc = "Sun4m platform, SPARCstation Voyager",
|
1425 |
.init = vger_init, |
1426 |
.block_default_type = IF_SCSI, |
1427 |
DEFAULT_MACHINE_OPTIONS, |
1428 |
}; |
1429 |
|
1430 |
static QEMUMachine ss_lx_machine = {
|
1431 |
.name = "LX",
|
1432 |
.desc = "Sun4m platform, SPARCstation LX",
|
1433 |
.init = ss_lx_init, |
1434 |
.block_default_type = IF_SCSI, |
1435 |
DEFAULT_MACHINE_OPTIONS, |
1436 |
}; |
1437 |
|
1438 |
static QEMUMachine ss4_machine = {
|
1439 |
.name = "SS-4",
|
1440 |
.desc = "Sun4m platform, SPARCstation 4",
|
1441 |
.init = ss4_init, |
1442 |
.block_default_type = IF_SCSI, |
1443 |
DEFAULT_MACHINE_OPTIONS, |
1444 |
}; |
1445 |
|
1446 |
static QEMUMachine scls_machine = {
|
1447 |
.name = "SPARCClassic",
|
1448 |
.desc = "Sun4m platform, SPARCClassic",
|
1449 |
.init = scls_init, |
1450 |
.block_default_type = IF_SCSI, |
1451 |
DEFAULT_MACHINE_OPTIONS, |
1452 |
}; |
1453 |
|
1454 |
static QEMUMachine sbook_machine = {
|
1455 |
.name = "SPARCbook",
|
1456 |
.desc = "Sun4m platform, SPARCbook",
|
1457 |
.init = sbook_init, |
1458 |
.block_default_type = IF_SCSI, |
1459 |
DEFAULT_MACHINE_OPTIONS, |
1460 |
}; |
1461 |
|
1462 |
static void sun4m_register_types(void) |
1463 |
{ |
1464 |
type_register_static(&idreg_info); |
1465 |
type_register_static(&afx_info); |
1466 |
type_register_static(&prom_info); |
1467 |
type_register_static(&ram_info); |
1468 |
} |
1469 |
|
1470 |
static void sun4m_machine_init(void) |
1471 |
{ |
1472 |
qemu_register_machine(&ss5_machine); |
1473 |
qemu_register_machine(&ss10_machine); |
1474 |
qemu_register_machine(&ss600mp_machine); |
1475 |
qemu_register_machine(&ss20_machine); |
1476 |
qemu_register_machine(&voyager_machine); |
1477 |
qemu_register_machine(&ss_lx_machine); |
1478 |
qemu_register_machine(&ss4_machine); |
1479 |
qemu_register_machine(&scls_machine); |
1480 |
qemu_register_machine(&sbook_machine); |
1481 |
} |
1482 |
|
1483 |
type_init(sun4m_register_types) |
1484 |
machine_init(sun4m_machine_init); |