root / target-ppc / translate.c @ ec1ac72d
History | View | Annotate | Download (229.3 kB)
1 | 79aceca5 | bellard | /*
|
---|---|---|---|
2 | 3fc6c082 | bellard | * PowerPC emulation for qemu: main translation routines.
|
3 | 5fafdf24 | ths | *
|
4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
|
5 | 79aceca5 | bellard | *
|
6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
|
9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 79aceca5 | bellard | *
|
11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 79aceca5 | bellard | * Lesser General Public License for more details.
|
15 | 79aceca5 | bellard | *
|
16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
|
18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 79aceca5 | bellard | */
|
20 | c6a1c22b | bellard | #include <stdarg.h> |
21 | c6a1c22b | bellard | #include <stdlib.h> |
22 | c6a1c22b | bellard | #include <stdio.h> |
23 | c6a1c22b | bellard | #include <string.h> |
24 | c6a1c22b | bellard | #include <inttypes.h> |
25 | c6a1c22b | bellard | |
26 | 79aceca5 | bellard | #include "cpu.h" |
27 | c6a1c22b | bellard | #include "exec-all.h" |
28 | 79aceca5 | bellard | #include "disas.h" |
29 | f10dc08e | aurel32 | #include "helper.h" |
30 | 57fec1fe | bellard | #include "tcg-op.h" |
31 | ca10f867 | aurel32 | #include "qemu-common.h" |
32 | 79aceca5 | bellard | |
33 | 8cbcb4fa | aurel32 | #define CPU_SINGLE_STEP 0x1 |
34 | 8cbcb4fa | aurel32 | #define CPU_BRANCH_STEP 0x2 |
35 | 8cbcb4fa | aurel32 | #define GDBSTUB_SINGLE_STEP 0x4 |
36 | 8cbcb4fa | aurel32 | |
37 | a750fc0b | j_mayer | /* Include definitions for instructions classes and implementations flags */
|
38 | 79aceca5 | bellard | //#define DO_SINGLE_STEP
|
39 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
|
40 | a496775f | j_mayer | //#define DEBUG_MEMORY_ACCESSES
|
41 | 76a66253 | j_mayer | //#define DO_PPC_STATISTICS
|
42 | 7c58044c | j_mayer | //#define OPTIMIZE_FPRF_UPDATE
|
43 | 79aceca5 | bellard | |
44 | a750fc0b | j_mayer | /*****************************************************************************/
|
45 | a750fc0b | j_mayer | /* Code translation helpers */
|
46 | c53be334 | bellard | |
47 | f78fb44e | aurel32 | /* global register indexes */
|
48 | f78fb44e | aurel32 | static TCGv cpu_env;
|
49 | 1d542695 | aurel32 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
50 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
|
51 | 1d542695 | aurel32 | + 10*4 + 22*5 /* SPE GPRh */ |
52 | f78fb44e | aurel32 | #endif
|
53 | a5e26afa | aurel32 | + 10*4 + 22*5 /* FPR */ |
54 | 1d542695 | aurel32 | + 2*(10*6 + 22*7) /* AVRh, AVRl */]; |
55 | f78fb44e | aurel32 | static TCGv cpu_gpr[32]; |
56 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
|
57 | f78fb44e | aurel32 | static TCGv cpu_gprh[32]; |
58 | f78fb44e | aurel32 | #endif
|
59 | a5e26afa | aurel32 | static TCGv cpu_fpr[32]; |
60 | 1d542695 | aurel32 | static TCGv cpu_avrh[32], cpu_avrl[32]; |
61 | f78fb44e | aurel32 | |
62 | f78fb44e | aurel32 | /* dyngen register indexes */
|
63 | f78fb44e | aurel32 | static TCGv cpu_T[3]; |
64 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
65 | f78fb44e | aurel32 | #define cpu_T64 cpu_T
|
66 | f78fb44e | aurel32 | #else
|
67 | f78fb44e | aurel32 | static TCGv cpu_T64[3]; |
68 | f78fb44e | aurel32 | #endif
|
69 | a5e26afa | aurel32 | static TCGv cpu_FT[3]; |
70 | 1d542695 | aurel32 | static TCGv cpu_AVRh[3], cpu_AVRl[3]; |
71 | 2e70f6ef | pbrook | |
72 | 2e70f6ef | pbrook | #include "gen-icount.h" |
73 | 2e70f6ef | pbrook | |
74 | 2e70f6ef | pbrook | void ppc_translate_init(void) |
75 | 2e70f6ef | pbrook | { |
76 | f78fb44e | aurel32 | int i;
|
77 | f78fb44e | aurel32 | char* p;
|
78 | b2437bf2 | pbrook | static int done_init = 0; |
79 | f78fb44e | aurel32 | |
80 | 2e70f6ef | pbrook | if (done_init)
|
81 | 2e70f6ef | pbrook | return;
|
82 | f78fb44e | aurel32 | |
83 | 2e70f6ef | pbrook | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
84 | 1c73fe5b | aurel32 | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
85 | 1c73fe5b | aurel32 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
|
86 | 1c73fe5b | aurel32 | TCG_AREG0, offsetof(CPUState, t0), "T0");
|
87 | 1c73fe5b | aurel32 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
|
88 | 1c73fe5b | aurel32 | TCG_AREG0, offsetof(CPUState, t1), "T1");
|
89 | 1c73fe5b | aurel32 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
|
90 | 1c73fe5b | aurel32 | TCG_AREG0, offsetof(CPUState, t2), "T2");
|
91 | 1c73fe5b | aurel32 | #else
|
92 | 1c73fe5b | aurel32 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
93 | 1c73fe5b | aurel32 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
94 | 1c73fe5b | aurel32 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
95 | 1c73fe5b | aurel32 | #endif
|
96 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
|
97 | f78fb44e | aurel32 | cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
|
98 | bd7d9a6d | aurel32 | TCG_AREG0, offsetof(CPUState, t0_64), |
99 | f78fb44e | aurel32 | "T0_64");
|
100 | f78fb44e | aurel32 | cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
|
101 | bd7d9a6d | aurel32 | TCG_AREG0, offsetof(CPUState, t1_64), |
102 | f78fb44e | aurel32 | "T1_64");
|
103 | f78fb44e | aurel32 | cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
|
104 | bd7d9a6d | aurel32 | TCG_AREG0, offsetof(CPUState, t2_64), |
105 | f78fb44e | aurel32 | "T2_64");
|
106 | f78fb44e | aurel32 | #endif
|
107 | a5e26afa | aurel32 | |
108 | a5e26afa | aurel32 | cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
109 | a5e26afa | aurel32 | offsetof(CPUState, ft0), "FT0");
|
110 | a5e26afa | aurel32 | cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
111 | a5e26afa | aurel32 | offsetof(CPUState, ft1), "FT1");
|
112 | a5e26afa | aurel32 | cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
113 | a5e26afa | aurel32 | offsetof(CPUState, ft2), "FT2");
|
114 | a5e26afa | aurel32 | |
115 | 1d542695 | aurel32 | cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
116 | 1d542695 | aurel32 | offsetof(CPUState, avr0.u64[0]), "AVR0H"); |
117 | 1d542695 | aurel32 | cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
118 | 1d542695 | aurel32 | offsetof(CPUState, avr0.u64[1]), "AVR0L"); |
119 | 1d542695 | aurel32 | cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
120 | 1d542695 | aurel32 | offsetof(CPUState, avr1.u64[0]), "AVR1H"); |
121 | 1d542695 | aurel32 | cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
122 | 1d542695 | aurel32 | offsetof(CPUState, avr1.u64[1]), "AVR1L"); |
123 | 1d542695 | aurel32 | cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
124 | 1d542695 | aurel32 | offsetof(CPUState, avr2.u64[0]), "AVR2H"); |
125 | 1d542695 | aurel32 | cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
|
126 | 1d542695 | aurel32 | offsetof(CPUState, avr2.u64[1]), "AVR2L"); |
127 | 1d542695 | aurel32 | |
128 | f78fb44e | aurel32 | p = cpu_reg_names; |
129 | f78fb44e | aurel32 | for (i = 0; i < 32; i++) { |
130 | f78fb44e | aurel32 | sprintf(p, "r%d", i);
|
131 | f78fb44e | aurel32 | cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
132 | f78fb44e | aurel32 | offsetof(CPUState, gpr[i]), p); |
133 | f78fb44e | aurel32 | p += (i < 10) ? 3 : 4; |
134 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
|
135 | f78fb44e | aurel32 | sprintf(p, "r%dH", i);
|
136 | f78fb44e | aurel32 | cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
137 | f78fb44e | aurel32 | offsetof(CPUState, gprh[i]), p); |
138 | f78fb44e | aurel32 | p += (i < 10) ? 4 : 5; |
139 | f78fb44e | aurel32 | #endif
|
140 | 1d542695 | aurel32 | |
141 | a5e26afa | aurel32 | sprintf(p, "fp%d", i);
|
142 | a5e26afa | aurel32 | cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
143 | a5e26afa | aurel32 | offsetof(CPUState, fpr[i]), p); |
144 | ec1ac72d | aurel32 | p += (i < 10) ? 4 : 5; |
145 | a5e26afa | aurel32 | |
146 | 1d542695 | aurel32 | sprintf(p, "avr%dH", i);
|
147 | 1d542695 | aurel32 | cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
148 | 1d542695 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
|
149 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
150 | ec1ac72d | aurel32 | |
151 | 1d542695 | aurel32 | sprintf(p, "avr%dL", i);
|
152 | 1d542695 | aurel32 | cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
153 | 1d542695 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
|
154 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
155 | f78fb44e | aurel32 | } |
156 | f10dc08e | aurel32 | |
157 | f10dc08e | aurel32 | /* register helpers */
|
158 | f10dc08e | aurel32 | #undef DEF_HELPER
|
159 | f10dc08e | aurel32 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
160 | f10dc08e | aurel32 | #include "helper.h" |
161 | f10dc08e | aurel32 | |
162 | 2e70f6ef | pbrook | done_init = 1;
|
163 | 2e70f6ef | pbrook | } |
164 | 2e70f6ef | pbrook | |
165 | 7c58044c | j_mayer | #if defined(OPTIMIZE_FPRF_UPDATE)
|
166 | 7c58044c | j_mayer | static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
|
167 | 7c58044c | j_mayer | static uint16_t **gen_fprf_ptr;
|
168 | 7c58044c | j_mayer | #endif
|
169 | 79aceca5 | bellard | |
170 | d9bce9d9 | j_mayer | #define GEN8(func, NAME) \
|
171 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [8] = { \ |
172 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
173 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
174 | 9a64fbe4 | bellard | }; \ |
175 | b068d6a7 | j_mayer | static always_inline void func (int n) \ |
176 | 9a64fbe4 | bellard | { \ |
177 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
178 | 9a64fbe4 | bellard | } |
179 | 9a64fbe4 | bellard | |
180 | 9a64fbe4 | bellard | #define GEN16(func, NAME) \
|
181 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [16] = { \ |
182 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
183 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
184 | 9a64fbe4 | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
185 | 9a64fbe4 | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
186 | 9a64fbe4 | bellard | }; \ |
187 | b068d6a7 | j_mayer | static always_inline void func (int n) \ |
188 | 9a64fbe4 | bellard | { \ |
189 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
190 | 28b6751f | bellard | } |
191 | 28b6751f | bellard | |
192 | d9bce9d9 | j_mayer | #define GEN32(func, NAME) \
|
193 | 9a64fbe4 | bellard | static GenOpFunc *NAME ## _table [32] = { \ |
194 | 9a64fbe4 | bellard | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
195 | 9a64fbe4 | bellard | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
196 | 9a64fbe4 | bellard | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
197 | 9a64fbe4 | bellard | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
198 | 9a64fbe4 | bellard | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
199 | 9a64fbe4 | bellard | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
200 | 9a64fbe4 | bellard | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
201 | 9a64fbe4 | bellard | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
202 | 9a64fbe4 | bellard | }; \ |
203 | b068d6a7 | j_mayer | static always_inline void func (int n) \ |
204 | 9a64fbe4 | bellard | { \ |
205 | 9a64fbe4 | bellard | NAME ## _table[n](); \ |
206 | 9a64fbe4 | bellard | } |
207 | 9a64fbe4 | bellard | |
208 | 9a64fbe4 | bellard | /* Condition register moves */
|
209 | 9a64fbe4 | bellard | GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf); |
210 | 9a64fbe4 | bellard | GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf); |
211 | 9a64fbe4 | bellard | GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); |
212 | fc0d441e | j_mayer | #if 0 // Unused
|
213 | 9a64fbe4 | bellard | GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
|
214 | fc0d441e | j_mayer | #endif
|
215 | 28b6751f | bellard | |
216 | 79aceca5 | bellard | /* internal defines */
|
217 | 79aceca5 | bellard | typedef struct DisasContext { |
218 | 79aceca5 | bellard | struct TranslationBlock *tb;
|
219 | 0fa85d43 | bellard | target_ulong nip; |
220 | 79aceca5 | bellard | uint32_t opcode; |
221 | 9a64fbe4 | bellard | uint32_t exception; |
222 | 3cc62370 | bellard | /* Routine used to access memory */
|
223 | 3cc62370 | bellard | int mem_idx;
|
224 | 3cc62370 | bellard | /* Translation flags */
|
225 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
|
226 | 79aceca5 | bellard | int supervisor;
|
227 | 9a64fbe4 | bellard | #endif
|
228 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
229 | d9bce9d9 | j_mayer | int sf_mode;
|
230 | d9bce9d9 | j_mayer | #endif
|
231 | 3cc62370 | bellard | int fpu_enabled;
|
232 | a9d9eb8f | j_mayer | int altivec_enabled;
|
233 | 0487d6a8 | j_mayer | int spe_enabled;
|
234 | 3fc6c082 | bellard | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
|
235 | ea4e754f | bellard | int singlestep_enabled;
|
236 | d63001d1 | j_mayer | int dcache_line_size;
|
237 | 79aceca5 | bellard | } DisasContext; |
238 | 79aceca5 | bellard | |
239 | 3fc6c082 | bellard | struct opc_handler_t {
|
240 | 79aceca5 | bellard | /* invalid bits */
|
241 | 79aceca5 | bellard | uint32_t inval; |
242 | 9a64fbe4 | bellard | /* instruction type */
|
243 | 0487d6a8 | j_mayer | uint64_t type; |
244 | 79aceca5 | bellard | /* handler */
|
245 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
|
246 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
|
247 | 76a66253 | j_mayer | const unsigned char *oname; |
248 | a750fc0b | j_mayer | #endif
|
249 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS)
|
250 | 76a66253 | j_mayer | uint64_t count; |
251 | 76a66253 | j_mayer | #endif
|
252 | 3fc6c082 | bellard | }; |
253 | 79aceca5 | bellard | |
254 | b068d6a7 | j_mayer | static always_inline void gen_set_Rc0 (DisasContext *ctx) |
255 | 76a66253 | j_mayer | { |
256 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
257 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
258 | d9bce9d9 | j_mayer | gen_op_cmpi_64(0);
|
259 | d9bce9d9 | j_mayer | else
|
260 | d9bce9d9 | j_mayer | #endif
|
261 | d9bce9d9 | j_mayer | gen_op_cmpi(0);
|
262 | 76a66253 | j_mayer | gen_op_set_Rc0(); |
263 | 76a66253 | j_mayer | } |
264 | 76a66253 | j_mayer | |
265 | 7c58044c | j_mayer | static always_inline void gen_reset_fpstatus (void) |
266 | 7c58044c | j_mayer | { |
267 | 7c58044c | j_mayer | #ifdef CONFIG_SOFTFLOAT
|
268 | 7c58044c | j_mayer | gen_op_reset_fpstatus(); |
269 | 7c58044c | j_mayer | #endif
|
270 | 7c58044c | j_mayer | } |
271 | 7c58044c | j_mayer | |
272 | 7c58044c | j_mayer | static always_inline void gen_compute_fprf (int set_fprf, int set_rc) |
273 | 7c58044c | j_mayer | { |
274 | 7c58044c | j_mayer | if (set_fprf != 0) { |
275 | 7c58044c | j_mayer | /* This case might be optimized later */
|
276 | 7c58044c | j_mayer | #if defined(OPTIMIZE_FPRF_UPDATE)
|
277 | 7c58044c | j_mayer | *gen_fprf_ptr++ = gen_opc_ptr; |
278 | 7c58044c | j_mayer | #endif
|
279 | 7c58044c | j_mayer | gen_op_compute_fprf(1);
|
280 | 7c58044c | j_mayer | if (unlikely(set_rc))
|
281 | 7c58044c | j_mayer | gen_op_store_T0_crf(1);
|
282 | 7c58044c | j_mayer | gen_op_float_check_status(); |
283 | 7c58044c | j_mayer | } else if (unlikely(set_rc)) { |
284 | 7c58044c | j_mayer | /* We always need to compute fpcc */
|
285 | 7c58044c | j_mayer | gen_op_compute_fprf(0);
|
286 | 7c58044c | j_mayer | gen_op_store_T0_crf(1);
|
287 | 7c58044c | j_mayer | if (set_fprf)
|
288 | 7c58044c | j_mayer | gen_op_float_check_status(); |
289 | 7c58044c | j_mayer | } |
290 | 7c58044c | j_mayer | } |
291 | 7c58044c | j_mayer | |
292 | 7c58044c | j_mayer | static always_inline void gen_optimize_fprf (void) |
293 | 7c58044c | j_mayer | { |
294 | 7c58044c | j_mayer | #if defined(OPTIMIZE_FPRF_UPDATE)
|
295 | 7c58044c | j_mayer | uint16_t **ptr; |
296 | 7c58044c | j_mayer | |
297 | 7c58044c | j_mayer | for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++) |
298 | 7c58044c | j_mayer | *ptr = INDEX_op_nop1; |
299 | 7c58044c | j_mayer | gen_fprf_ptr = gen_fprf_buf; |
300 | 7c58044c | j_mayer | #endif
|
301 | 7c58044c | j_mayer | } |
302 | 7c58044c | j_mayer | |
303 | b068d6a7 | j_mayer | static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) |
304 | d9bce9d9 | j_mayer | { |
305 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
306 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
307 | 6676f424 | aurel32 | gen_op_update_nip_64(nip >> 32, nip);
|
308 | d9bce9d9 | j_mayer | else
|
309 | d9bce9d9 | j_mayer | #endif
|
310 | 6676f424 | aurel32 | gen_op_update_nip(nip); |
311 | d9bce9d9 | j_mayer | } |
312 | d9bce9d9 | j_mayer | |
313 | e1833e1f | j_mayer | #define GEN_EXCP(ctx, excp, error) \
|
314 | 79aceca5 | bellard | do { \
|
315 | e1833e1f | j_mayer | if ((ctx)->exception == POWERPC_EXCP_NONE) { \
|
316 | d9bce9d9 | j_mayer | gen_update_nip(ctx, (ctx)->nip); \ |
317 | 9fddaa0c | bellard | } \ |
318 | 9fddaa0c | bellard | gen_op_raise_exception_err((excp), (error)); \ |
319 | 9fddaa0c | bellard | ctx->exception = (excp); \ |
320 | 79aceca5 | bellard | } while (0) |
321 | 79aceca5 | bellard | |
322 | e1833e1f | j_mayer | #define GEN_EXCP_INVAL(ctx) \
|
323 | e1833e1f | j_mayer | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
324 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL) |
325 | 9fddaa0c | bellard | |
326 | e1833e1f | j_mayer | #define GEN_EXCP_PRIVOPC(ctx) \
|
327 | e1833e1f | j_mayer | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
328 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC) |
329 | 9a64fbe4 | bellard | |
330 | e1833e1f | j_mayer | #define GEN_EXCP_PRIVREG(ctx) \
|
331 | e1833e1f | j_mayer | GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \ |
332 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG) |
333 | e1833e1f | j_mayer | |
334 | e1833e1f | j_mayer | #define GEN_EXCP_NO_FP(ctx) \
|
335 | e1833e1f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
|
336 | e1833e1f | j_mayer | |
337 | e1833e1f | j_mayer | #define GEN_EXCP_NO_AP(ctx) \
|
338 | e1833e1f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
|
339 | 9a64fbe4 | bellard | |
340 | a9d9eb8f | j_mayer | #define GEN_EXCP_NO_VR(ctx) \
|
341 | a9d9eb8f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
|
342 | a9d9eb8f | j_mayer | |
343 | f24e5695 | bellard | /* Stop translation */
|
344 | b068d6a7 | j_mayer | static always_inline void GEN_STOP (DisasContext *ctx) |
345 | 3fc6c082 | bellard | { |
346 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
347 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
348 | 3fc6c082 | bellard | } |
349 | 3fc6c082 | bellard | |
350 | f24e5695 | bellard | /* No need to update nip here, as execution flow will change */
|
351 | b068d6a7 | j_mayer | static always_inline void GEN_SYNC (DisasContext *ctx) |
352 | 2be0071f | bellard | { |
353 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_SYNC; |
354 | 2be0071f | bellard | } |
355 | 2be0071f | bellard | |
356 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
|
357 | 79aceca5 | bellard | static void gen_##name (DisasContext *ctx); \ |
358 | 79aceca5 | bellard | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
359 | 79aceca5 | bellard | static void gen_##name (DisasContext *ctx) |
360 | 79aceca5 | bellard | |
361 | c7697e1f | j_mayer | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
|
362 | c7697e1f | j_mayer | static void gen_##name (DisasContext *ctx); \ |
363 | c7697e1f | j_mayer | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \ |
364 | c7697e1f | j_mayer | static void gen_##name (DisasContext *ctx) |
365 | c7697e1f | j_mayer | |
366 | 79aceca5 | bellard | typedef struct opcode_t { |
367 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
368 | 1235fc06 | ths | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
369 | 18fba28c | bellard | unsigned char pad[5]; |
370 | 18fba28c | bellard | #else
|
371 | 18fba28c | bellard | unsigned char pad[1]; |
372 | 18fba28c | bellard | #endif
|
373 | 79aceca5 | bellard | opc_handler_t handler; |
374 | 3fc6c082 | bellard | const unsigned char *oname; |
375 | 79aceca5 | bellard | } opcode_t; |
376 | 79aceca5 | bellard | |
377 | a750fc0b | j_mayer | /*****************************************************************************/
|
378 | 79aceca5 | bellard | /*** Instruction decoding ***/
|
379 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
|
380 | b068d6a7 | j_mayer | static always_inline uint32_t name (uint32_t opcode) \
|
381 | 79aceca5 | bellard | { \ |
382 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
383 | 79aceca5 | bellard | } |
384 | 79aceca5 | bellard | |
385 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
|
386 | b068d6a7 | j_mayer | static always_inline int32_t name (uint32_t opcode) \
|
387 | 79aceca5 | bellard | { \ |
388 | 18fba28c | bellard | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
389 | 79aceca5 | bellard | } |
390 | 79aceca5 | bellard | |
391 | 79aceca5 | bellard | /* Opcode part 1 */
|
392 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
393 | 79aceca5 | bellard | /* Opcode part 2 */
|
394 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
395 | 79aceca5 | bellard | /* Opcode part 3 */
|
396 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
397 | 79aceca5 | bellard | /* Update Cr0 flags */
|
398 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
399 | 79aceca5 | bellard | /* Destination */
|
400 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
401 | 79aceca5 | bellard | /* Source */
|
402 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
403 | 79aceca5 | bellard | /* First operand */
|
404 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
405 | 79aceca5 | bellard | /* Second operand */
|
406 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
407 | 79aceca5 | bellard | /* Third operand */
|
408 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
409 | 79aceca5 | bellard | /*** Get CRn ***/
|
410 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
411 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
412 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
413 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
414 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
415 | 79aceca5 | bellard | /* SPR / TBL */
|
416 | 3fc6c082 | bellard | EXTRACT_HELPER(_SPR, 11, 10); |
417 | b068d6a7 | j_mayer | static always_inline uint32_t SPR (uint32_t opcode)
|
418 | 3fc6c082 | bellard | { |
419 | 3fc6c082 | bellard | uint32_t sprn = _SPR(opcode); |
420 | 3fc6c082 | bellard | |
421 | 3fc6c082 | bellard | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
422 | 3fc6c082 | bellard | } |
423 | 79aceca5 | bellard | /*** Get constants ***/
|
424 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
425 | 79aceca5 | bellard | /* 16 bits signed immediate value */
|
426 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
427 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
|
428 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
429 | 79aceca5 | bellard | /* Bit count */
|
430 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
431 | 79aceca5 | bellard | /* Shift count */
|
432 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
433 | 79aceca5 | bellard | /* Mask start */
|
434 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
435 | 79aceca5 | bellard | /* Mask end */
|
436 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
437 | fb0eaffc | bellard | /* Trap operand */
|
438 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
439 | 79aceca5 | bellard | |
440 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
441 | 79aceca5 | bellard | EXTRACT_HELPER(FM, 17, 8); |
442 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
443 | e4bb997e | aurel32 | EXTRACT_HELPER(FPIMM, 12, 4); |
444 | fb0eaffc | bellard | |
445 | 79aceca5 | bellard | /*** Jump target decoding ***/
|
446 | 79aceca5 | bellard | /* Displacement */
|
447 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
448 | 79aceca5 | bellard | /* Immediate address */
|
449 | b068d6a7 | j_mayer | static always_inline target_ulong LI (uint32_t opcode)
|
450 | 79aceca5 | bellard | { |
451 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
452 | 79aceca5 | bellard | } |
453 | 79aceca5 | bellard | |
454 | b068d6a7 | j_mayer | static always_inline uint32_t BD (uint32_t opcode)
|
455 | 79aceca5 | bellard | { |
456 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
457 | 79aceca5 | bellard | } |
458 | 79aceca5 | bellard | |
459 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
460 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
461 | 79aceca5 | bellard | /* Absolute/relative address */
|
462 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
463 | 79aceca5 | bellard | /* Link */
|
464 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
465 | 79aceca5 | bellard | |
466 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
|
467 | b068d6a7 | j_mayer | static always_inline target_ulong MASK (uint32_t start, uint32_t end)
|
468 | 79aceca5 | bellard | { |
469 | 76a66253 | j_mayer | target_ulong ret; |
470 | 79aceca5 | bellard | |
471 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
472 | 76a66253 | j_mayer | if (likely(start == 0)) { |
473 | 6f2d8978 | j_mayer | ret = UINT64_MAX << (63 - end);
|
474 | 76a66253 | j_mayer | } else if (likely(end == 63)) { |
475 | 6f2d8978 | j_mayer | ret = UINT64_MAX >> start; |
476 | 76a66253 | j_mayer | } |
477 | 76a66253 | j_mayer | #else
|
478 | 76a66253 | j_mayer | if (likely(start == 0)) { |
479 | 6f2d8978 | j_mayer | ret = UINT32_MAX << (31 - end);
|
480 | 76a66253 | j_mayer | } else if (likely(end == 31)) { |
481 | 6f2d8978 | j_mayer | ret = UINT32_MAX >> start; |
482 | 76a66253 | j_mayer | } |
483 | 76a66253 | j_mayer | #endif
|
484 | 76a66253 | j_mayer | else {
|
485 | 76a66253 | j_mayer | ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
486 | 76a66253 | j_mayer | (((target_ulong)(-1ULL) >> (end)) >> 1); |
487 | 76a66253 | j_mayer | if (unlikely(start > end))
|
488 | 76a66253 | j_mayer | return ~ret;
|
489 | 76a66253 | j_mayer | } |
490 | 79aceca5 | bellard | |
491 | 79aceca5 | bellard | return ret;
|
492 | 79aceca5 | bellard | } |
493 | 79aceca5 | bellard | |
494 | a750fc0b | j_mayer | /*****************************************************************************/
|
495 | a750fc0b | j_mayer | /* PowerPC Instructions types definitions */
|
496 | a750fc0b | j_mayer | enum {
|
497 | 1b413d55 | j_mayer | PPC_NONE = 0x0000000000000000ULL,
|
498 | 12de9a39 | j_mayer | /* PowerPC base instructions set */
|
499 | 1b413d55 | j_mayer | PPC_INSNS_BASE = 0x0000000000000001ULL,
|
500 | 1b413d55 | j_mayer | /* integer operations instructions */
|
501 | a750fc0b | j_mayer | #define PPC_INTEGER PPC_INSNS_BASE
|
502 | 1b413d55 | j_mayer | /* flow control instructions */
|
503 | a750fc0b | j_mayer | #define PPC_FLOW PPC_INSNS_BASE
|
504 | 1b413d55 | j_mayer | /* virtual memory instructions */
|
505 | a750fc0b | j_mayer | #define PPC_MEM PPC_INSNS_BASE
|
506 | 1b413d55 | j_mayer | /* ld/st with reservation instructions */
|
507 | a750fc0b | j_mayer | #define PPC_RES PPC_INSNS_BASE
|
508 | 1b413d55 | j_mayer | /* spr/msr access instructions */
|
509 | a750fc0b | j_mayer | #define PPC_MISC PPC_INSNS_BASE
|
510 | 1b413d55 | j_mayer | /* Deprecated instruction sets */
|
511 | 1b413d55 | j_mayer | /* Original POWER instruction set */
|
512 | f610349f | j_mayer | PPC_POWER = 0x0000000000000002ULL,
|
513 | 1b413d55 | j_mayer | /* POWER2 instruction set extension */
|
514 | f610349f | j_mayer | PPC_POWER2 = 0x0000000000000004ULL,
|
515 | 1b413d55 | j_mayer | /* Power RTC support */
|
516 | f610349f | j_mayer | PPC_POWER_RTC = 0x0000000000000008ULL,
|
517 | 1b413d55 | j_mayer | /* Power-to-PowerPC bridge (601) */
|
518 | f610349f | j_mayer | PPC_POWER_BR = 0x0000000000000010ULL,
|
519 | 1b413d55 | j_mayer | /* 64 bits PowerPC instruction set */
|
520 | f610349f | j_mayer | PPC_64B = 0x0000000000000020ULL,
|
521 | 1b413d55 | j_mayer | /* New 64 bits extensions (PowerPC 2.0x) */
|
522 | f610349f | j_mayer | PPC_64BX = 0x0000000000000040ULL,
|
523 | 1b413d55 | j_mayer | /* 64 bits hypervisor extensions */
|
524 | f610349f | j_mayer | PPC_64H = 0x0000000000000080ULL,
|
525 | 1b413d55 | j_mayer | /* New wait instruction (PowerPC 2.0x) */
|
526 | f610349f | j_mayer | PPC_WAIT = 0x0000000000000100ULL,
|
527 | 1b413d55 | j_mayer | /* Time base mftb instruction */
|
528 | f610349f | j_mayer | PPC_MFTB = 0x0000000000000200ULL,
|
529 | 1b413d55 | j_mayer | |
530 | 1b413d55 | j_mayer | /* Fixed-point unit extensions */
|
531 | 1b413d55 | j_mayer | /* PowerPC 602 specific */
|
532 | f610349f | j_mayer | PPC_602_SPEC = 0x0000000000000400ULL,
|
533 | 05332d70 | j_mayer | /* isel instruction */
|
534 | 05332d70 | j_mayer | PPC_ISEL = 0x0000000000000800ULL,
|
535 | 05332d70 | j_mayer | /* popcntb instruction */
|
536 | 05332d70 | j_mayer | PPC_POPCNTB = 0x0000000000001000ULL,
|
537 | 05332d70 | j_mayer | /* string load / store */
|
538 | 05332d70 | j_mayer | PPC_STRING = 0x0000000000002000ULL,
|
539 | 1b413d55 | j_mayer | |
540 | 1b413d55 | j_mayer | /* Floating-point unit extensions */
|
541 | 1b413d55 | j_mayer | /* Optional floating point instructions */
|
542 | 1b413d55 | j_mayer | PPC_FLOAT = 0x0000000000010000ULL,
|
543 | 1b413d55 | j_mayer | /* New floating-point extensions (PowerPC 2.0x) */
|
544 | 1b413d55 | j_mayer | PPC_FLOAT_EXT = 0x0000000000020000ULL,
|
545 | 1b413d55 | j_mayer | PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
|
546 | 1b413d55 | j_mayer | PPC_FLOAT_FRES = 0x0000000000080000ULL,
|
547 | 1b413d55 | j_mayer | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
|
548 | 1b413d55 | j_mayer | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
|
549 | 1b413d55 | j_mayer | PPC_FLOAT_FSEL = 0x0000000000400000ULL,
|
550 | 1b413d55 | j_mayer | PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
|
551 | 1b413d55 | j_mayer | |
552 | 1b413d55 | j_mayer | /* Vector/SIMD extensions */
|
553 | 1b413d55 | j_mayer | /* Altivec support */
|
554 | 1b413d55 | j_mayer | PPC_ALTIVEC = 0x0000000001000000ULL,
|
555 | 1b413d55 | j_mayer | /* PowerPC 2.03 SPE extension */
|
556 | 05332d70 | j_mayer | PPC_SPE = 0x0000000002000000ULL,
|
557 | 1b413d55 | j_mayer | /* PowerPC 2.03 SPE floating-point extension */
|
558 | 05332d70 | j_mayer | PPC_SPEFPU = 0x0000000004000000ULL,
|
559 | 1b413d55 | j_mayer | |
560 | 12de9a39 | j_mayer | /* Optional memory control instructions */
|
561 | 1b413d55 | j_mayer | PPC_MEM_TLBIA = 0x0000000010000000ULL,
|
562 | 1b413d55 | j_mayer | PPC_MEM_TLBIE = 0x0000000020000000ULL,
|
563 | 1b413d55 | j_mayer | PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
|
564 | 1b413d55 | j_mayer | /* sync instruction */
|
565 | 1b413d55 | j_mayer | PPC_MEM_SYNC = 0x0000000080000000ULL,
|
566 | 1b413d55 | j_mayer | /* eieio instruction */
|
567 | 1b413d55 | j_mayer | PPC_MEM_EIEIO = 0x0000000100000000ULL,
|
568 | 1b413d55 | j_mayer | |
569 | 1b413d55 | j_mayer | /* Cache control instructions */
|
570 | c8623f2e | j_mayer | PPC_CACHE = 0x0000000200000000ULL,
|
571 | 1b413d55 | j_mayer | /* icbi instruction */
|
572 | 05332d70 | j_mayer | PPC_CACHE_ICBI = 0x0000000400000000ULL,
|
573 | 1b413d55 | j_mayer | /* dcbz instruction with fixed cache line size */
|
574 | 05332d70 | j_mayer | PPC_CACHE_DCBZ = 0x0000000800000000ULL,
|
575 | 1b413d55 | j_mayer | /* dcbz instruction with tunable cache line size */
|
576 | 05332d70 | j_mayer | PPC_CACHE_DCBZT = 0x0000001000000000ULL,
|
577 | 1b413d55 | j_mayer | /* dcba instruction */
|
578 | 05332d70 | j_mayer | PPC_CACHE_DCBA = 0x0000002000000000ULL,
|
579 | 05332d70 | j_mayer | /* Freescale cache locking instructions */
|
580 | 05332d70 | j_mayer | PPC_CACHE_LOCK = 0x0000004000000000ULL,
|
581 | 1b413d55 | j_mayer | |
582 | 1b413d55 | j_mayer | /* MMU related extensions */
|
583 | 1b413d55 | j_mayer | /* external control instructions */
|
584 | 05332d70 | j_mayer | PPC_EXTERN = 0x0000010000000000ULL,
|
585 | 1b413d55 | j_mayer | /* segment register access instructions */
|
586 | 05332d70 | j_mayer | PPC_SEGMENT = 0x0000020000000000ULL,
|
587 | 1b413d55 | j_mayer | /* PowerPC 6xx TLB management instructions */
|
588 | 05332d70 | j_mayer | PPC_6xx_TLB = 0x0000040000000000ULL,
|
589 | 1b413d55 | j_mayer | /* PowerPC 74xx TLB management instructions */
|
590 | 05332d70 | j_mayer | PPC_74xx_TLB = 0x0000080000000000ULL,
|
591 | 1b413d55 | j_mayer | /* PowerPC 40x TLB management instructions */
|
592 | 05332d70 | j_mayer | PPC_40x_TLB = 0x0000100000000000ULL,
|
593 | 1b413d55 | j_mayer | /* segment register access instructions for PowerPC 64 "bridge" */
|
594 | 05332d70 | j_mayer | PPC_SEGMENT_64B = 0x0000200000000000ULL,
|
595 | 1b413d55 | j_mayer | /* SLB management */
|
596 | 05332d70 | j_mayer | PPC_SLBI = 0x0000400000000000ULL,
|
597 | 1b413d55 | j_mayer | |
598 | 12de9a39 | j_mayer | /* Embedded PowerPC dedicated instructions */
|
599 | 05332d70 | j_mayer | PPC_WRTEE = 0x0001000000000000ULL,
|
600 | 12de9a39 | j_mayer | /* PowerPC 40x exception model */
|
601 | 05332d70 | j_mayer | PPC_40x_EXCP = 0x0002000000000000ULL,
|
602 | 12de9a39 | j_mayer | /* PowerPC 405 Mac instructions */
|
603 | 05332d70 | j_mayer | PPC_405_MAC = 0x0004000000000000ULL,
|
604 | 12de9a39 | j_mayer | /* PowerPC 440 specific instructions */
|
605 | 05332d70 | j_mayer | PPC_440_SPEC = 0x0008000000000000ULL,
|
606 | 12de9a39 | j_mayer | /* BookE (embedded) PowerPC specification */
|
607 | 05332d70 | j_mayer | PPC_BOOKE = 0x0010000000000000ULL,
|
608 | 05332d70 | j_mayer | /* mfapidi instruction */
|
609 | 05332d70 | j_mayer | PPC_MFAPIDI = 0x0020000000000000ULL,
|
610 | 05332d70 | j_mayer | /* tlbiva instruction */
|
611 | 05332d70 | j_mayer | PPC_TLBIVA = 0x0040000000000000ULL,
|
612 | 05332d70 | j_mayer | /* tlbivax instruction */
|
613 | 05332d70 | j_mayer | PPC_TLBIVAX = 0x0080000000000000ULL,
|
614 | 12de9a39 | j_mayer | /* PowerPC 4xx dedicated instructions */
|
615 | 05332d70 | j_mayer | PPC_4xx_COMMON = 0x0100000000000000ULL,
|
616 | 12de9a39 | j_mayer | /* PowerPC 40x ibct instructions */
|
617 | 05332d70 | j_mayer | PPC_40x_ICBT = 0x0200000000000000ULL,
|
618 | 12de9a39 | j_mayer | /* rfmci is not implemented in all BookE PowerPC */
|
619 | 05332d70 | j_mayer | PPC_RFMCI = 0x0400000000000000ULL,
|
620 | 05332d70 | j_mayer | /* rfdi instruction */
|
621 | 05332d70 | j_mayer | PPC_RFDI = 0x0800000000000000ULL,
|
622 | 05332d70 | j_mayer | /* DCR accesses */
|
623 | 05332d70 | j_mayer | PPC_DCR = 0x1000000000000000ULL,
|
624 | 05332d70 | j_mayer | /* DCR extended accesse */
|
625 | 05332d70 | j_mayer | PPC_DCRX = 0x2000000000000000ULL,
|
626 | 12de9a39 | j_mayer | /* user-mode DCR access, implemented in PowerPC 460 */
|
627 | 05332d70 | j_mayer | PPC_DCRUX = 0x4000000000000000ULL,
|
628 | a750fc0b | j_mayer | }; |
629 | a750fc0b | j_mayer | |
630 | a750fc0b | j_mayer | /*****************************************************************************/
|
631 | a750fc0b | j_mayer | /* PowerPC instructions table */
|
632 | 3fc6c082 | bellard | #if HOST_LONG_BITS == 64 |
633 | 3fc6c082 | bellard | #define OPC_ALIGN 8 |
634 | 3fc6c082 | bellard | #else
|
635 | 3fc6c082 | bellard | #define OPC_ALIGN 4 |
636 | 3fc6c082 | bellard | #endif
|
637 | 1b039c09 | bellard | #if defined(__APPLE__)
|
638 | d9bce9d9 | j_mayer | #define OPCODES_SECTION \
|
639 | 3fc6c082 | bellard | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
|
640 | 933dc6eb | bellard | #else
|
641 | d9bce9d9 | j_mayer | #define OPCODES_SECTION \
|
642 | 3fc6c082 | bellard | __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
|
643 | 933dc6eb | bellard | #endif
|
644 | 933dc6eb | bellard | |
645 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
646 | 79aceca5 | bellard | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
647 | 18fba28c | bellard | OPCODES_SECTION opcode_t opc_##name = { \ |
648 | 79aceca5 | bellard | .opc1 = op1, \ |
649 | 79aceca5 | bellard | .opc2 = op2, \ |
650 | 79aceca5 | bellard | .opc3 = op3, \ |
651 | 18fba28c | bellard | .pad = { 0, }, \
|
652 | 79aceca5 | bellard | .handler = { \ |
653 | 79aceca5 | bellard | .inval = invl, \ |
654 | 9a64fbe4 | bellard | .type = _typ, \ |
655 | 79aceca5 | bellard | .handler = &gen_##name, \ |
656 | 76a66253 | j_mayer | .oname = stringify(name), \ |
657 | 79aceca5 | bellard | }, \ |
658 | 3fc6c082 | bellard | .oname = stringify(name), \ |
659 | 79aceca5 | bellard | } |
660 | c7697e1f | j_mayer | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
661 | c7697e1f | j_mayer | OPCODES_SECTION opcode_t opc_##name = { \ |
662 | c7697e1f | j_mayer | .opc1 = op1, \ |
663 | c7697e1f | j_mayer | .opc2 = op2, \ |
664 | c7697e1f | j_mayer | .opc3 = op3, \ |
665 | c7697e1f | j_mayer | .pad = { 0, }, \
|
666 | c7697e1f | j_mayer | .handler = { \ |
667 | c7697e1f | j_mayer | .inval = invl, \ |
668 | c7697e1f | j_mayer | .type = _typ, \ |
669 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
670 | c7697e1f | j_mayer | .oname = onam, \ |
671 | c7697e1f | j_mayer | }, \ |
672 | c7697e1f | j_mayer | .oname = onam, \ |
673 | c7697e1f | j_mayer | } |
674 | 76a66253 | j_mayer | #else
|
675 | 76a66253 | j_mayer | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
676 | 76a66253 | j_mayer | OPCODES_SECTION opcode_t opc_##name = { \ |
677 | 76a66253 | j_mayer | .opc1 = op1, \ |
678 | 76a66253 | j_mayer | .opc2 = op2, \ |
679 | 76a66253 | j_mayer | .opc3 = op3, \ |
680 | 76a66253 | j_mayer | .pad = { 0, }, \
|
681 | 76a66253 | j_mayer | .handler = { \ |
682 | 76a66253 | j_mayer | .inval = invl, \ |
683 | 76a66253 | j_mayer | .type = _typ, \ |
684 | 76a66253 | j_mayer | .handler = &gen_##name, \ |
685 | 76a66253 | j_mayer | }, \ |
686 | 76a66253 | j_mayer | .oname = stringify(name), \ |
687 | 76a66253 | j_mayer | } |
688 | c7697e1f | j_mayer | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
689 | c7697e1f | j_mayer | OPCODES_SECTION opcode_t opc_##name = { \ |
690 | c7697e1f | j_mayer | .opc1 = op1, \ |
691 | c7697e1f | j_mayer | .opc2 = op2, \ |
692 | c7697e1f | j_mayer | .opc3 = op3, \ |
693 | c7697e1f | j_mayer | .pad = { 0, }, \
|
694 | c7697e1f | j_mayer | .handler = { \ |
695 | c7697e1f | j_mayer | .inval = invl, \ |
696 | c7697e1f | j_mayer | .type = _typ, \ |
697 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
698 | c7697e1f | j_mayer | }, \ |
699 | c7697e1f | j_mayer | .oname = onam, \ |
700 | c7697e1f | j_mayer | } |
701 | 76a66253 | j_mayer | #endif
|
702 | 79aceca5 | bellard | |
703 | 79aceca5 | bellard | #define GEN_OPCODE_MARK(name) \
|
704 | 18fba28c | bellard | OPCODES_SECTION opcode_t opc_##name = { \ |
705 | 79aceca5 | bellard | .opc1 = 0xFF, \
|
706 | 79aceca5 | bellard | .opc2 = 0xFF, \
|
707 | 79aceca5 | bellard | .opc3 = 0xFF, \
|
708 | 18fba28c | bellard | .pad = { 0, }, \
|
709 | 79aceca5 | bellard | .handler = { \ |
710 | 79aceca5 | bellard | .inval = 0x00000000, \
|
711 | 9a64fbe4 | bellard | .type = 0x00, \
|
712 | 79aceca5 | bellard | .handler = NULL, \
|
713 | 79aceca5 | bellard | }, \ |
714 | 3fc6c082 | bellard | .oname = stringify(name), \ |
715 | 79aceca5 | bellard | } |
716 | 79aceca5 | bellard | |
717 | 79aceca5 | bellard | /* Start opcode list */
|
718 | 79aceca5 | bellard | GEN_OPCODE_MARK(start); |
719 | 79aceca5 | bellard | |
720 | 79aceca5 | bellard | /* Invalid instruction */
|
721 | 9a64fbe4 | bellard | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
722 | 9a64fbe4 | bellard | { |
723 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
724 | 9a64fbe4 | bellard | } |
725 | 9a64fbe4 | bellard | |
726 | 79aceca5 | bellard | static opc_handler_t invalid_handler = {
|
727 | 79aceca5 | bellard | .inval = 0xFFFFFFFF,
|
728 | 9a64fbe4 | bellard | .type = PPC_NONE, |
729 | 79aceca5 | bellard | .handler = gen_invalid, |
730 | 79aceca5 | bellard | }; |
731 | 79aceca5 | bellard | |
732 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
733 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
|
734 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
735 | 79aceca5 | bellard | { \ |
736 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
737 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
738 | 79aceca5 | bellard | gen_op_##name(); \ |
739 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
740 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
741 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
742 | 79aceca5 | bellard | } |
743 | 79aceca5 | bellard | |
744 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
|
745 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
746 | 79aceca5 | bellard | { \ |
747 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
748 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
749 | 79aceca5 | bellard | gen_op_##name(); \ |
750 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
751 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
752 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
753 | 79aceca5 | bellard | } |
754 | 79aceca5 | bellard | |
755 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
|
756 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
757 | 79aceca5 | bellard | { \ |
758 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
759 | 79aceca5 | bellard | gen_op_##name(); \ |
760 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
761 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
762 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
763 | 79aceca5 | bellard | } |
764 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
|
765 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
766 | 79aceca5 | bellard | { \ |
767 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
768 | 79aceca5 | bellard | gen_op_##name(); \ |
769 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
770 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
771 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
772 | 79aceca5 | bellard | } |
773 | 79aceca5 | bellard | |
774 | 79aceca5 | bellard | /* Two operands arithmetic functions */
|
775 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
|
776 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
|
777 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
778 | d9bce9d9 | j_mayer | |
779 | d9bce9d9 | j_mayer | /* Two operands arithmetic functions with no overflow allowed */
|
780 | d9bce9d9 | j_mayer | #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
|
781 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
|
782 | d9bce9d9 | j_mayer | |
783 | d9bce9d9 | j_mayer | /* One operand arithmetic functions */
|
784 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
|
785 | d9bce9d9 | j_mayer | __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ |
786 | d9bce9d9 | j_mayer | __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) |
787 | d9bce9d9 | j_mayer | |
788 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
789 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
|
790 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
791 | d9bce9d9 | j_mayer | { \ |
792 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
793 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
794 | d9bce9d9 | j_mayer | if (ctx->sf_mode) \
|
795 | d9bce9d9 | j_mayer | gen_op_##name##_64(); \ |
796 | d9bce9d9 | j_mayer | else \
|
797 | d9bce9d9 | j_mayer | gen_op_##name(); \ |
798 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
799 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
800 | d9bce9d9 | j_mayer | gen_set_Rc0(ctx); \ |
801 | d9bce9d9 | j_mayer | } |
802 | d9bce9d9 | j_mayer | |
803 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
|
804 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
805 | d9bce9d9 | j_mayer | { \ |
806 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
807 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
808 | d9bce9d9 | j_mayer | if (ctx->sf_mode) \
|
809 | d9bce9d9 | j_mayer | gen_op_##name##_64(); \ |
810 | d9bce9d9 | j_mayer | else \
|
811 | d9bce9d9 | j_mayer | gen_op_##name(); \ |
812 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
813 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
814 | d9bce9d9 | j_mayer | gen_set_Rc0(ctx); \ |
815 | d9bce9d9 | j_mayer | } |
816 | d9bce9d9 | j_mayer | |
817 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
|
818 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
819 | d9bce9d9 | j_mayer | { \ |
820 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
821 | d9bce9d9 | j_mayer | if (ctx->sf_mode) \
|
822 | d9bce9d9 | j_mayer | gen_op_##name##_64(); \ |
823 | d9bce9d9 | j_mayer | else \
|
824 | d9bce9d9 | j_mayer | gen_op_##name(); \ |
825 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
826 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
827 | d9bce9d9 | j_mayer | gen_set_Rc0(ctx); \ |
828 | d9bce9d9 | j_mayer | } |
829 | d9bce9d9 | j_mayer | #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
|
830 | d9bce9d9 | j_mayer | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
|
831 | d9bce9d9 | j_mayer | { \ |
832 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
833 | d9bce9d9 | j_mayer | if (ctx->sf_mode) \
|
834 | d9bce9d9 | j_mayer | gen_op_##name##_64(); \ |
835 | d9bce9d9 | j_mayer | else \
|
836 | d9bce9d9 | j_mayer | gen_op_##name(); \ |
837 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
|
838 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
839 | d9bce9d9 | j_mayer | gen_set_Rc0(ctx); \ |
840 | d9bce9d9 | j_mayer | } |
841 | d9bce9d9 | j_mayer | |
842 | d9bce9d9 | j_mayer | /* Two operands arithmetic functions */
|
843 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
|
844 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
|
845 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type) |
846 | 79aceca5 | bellard | |
847 | 79aceca5 | bellard | /* Two operands arithmetic functions with no overflow allowed */
|
848 | d9bce9d9 | j_mayer | #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
|
849 | d9bce9d9 | j_mayer | __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
|
850 | 79aceca5 | bellard | |
851 | 79aceca5 | bellard | /* One operand arithmetic functions */
|
852 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
|
853 | d9bce9d9 | j_mayer | __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ |
854 | d9bce9d9 | j_mayer | __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) |
855 | d9bce9d9 | j_mayer | #else
|
856 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
|
857 | d9bce9d9 | j_mayer | #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
|
858 | d9bce9d9 | j_mayer | #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
|
859 | d9bce9d9 | j_mayer | #endif
|
860 | 79aceca5 | bellard | |
861 | 79aceca5 | bellard | /* add add. addo addo. */
|
862 | b068d6a7 | j_mayer | static always_inline void gen_op_addo (void) |
863 | d9bce9d9 | j_mayer | { |
864 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
865 | d9bce9d9 | j_mayer | gen_op_add(); |
866 | d9bce9d9 | j_mayer | gen_op_check_addo(); |
867 | d9bce9d9 | j_mayer | } |
868 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
869 | d9bce9d9 | j_mayer | #define gen_op_add_64 gen_op_add
|
870 | b068d6a7 | j_mayer | static always_inline void gen_op_addo_64 (void) |
871 | d9bce9d9 | j_mayer | { |
872 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
873 | d9bce9d9 | j_mayer | gen_op_add(); |
874 | d9bce9d9 | j_mayer | gen_op_check_addo_64(); |
875 | d9bce9d9 | j_mayer | } |
876 | d9bce9d9 | j_mayer | #endif
|
877 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); |
878 | 79aceca5 | bellard | /* addc addc. addco addco. */
|
879 | b068d6a7 | j_mayer | static always_inline void gen_op_addc (void) |
880 | d9bce9d9 | j_mayer | { |
881 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
882 | d9bce9d9 | j_mayer | gen_op_add(); |
883 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
884 | d9bce9d9 | j_mayer | } |
885 | b068d6a7 | j_mayer | static always_inline void gen_op_addco (void) |
886 | d9bce9d9 | j_mayer | { |
887 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
888 | d9bce9d9 | j_mayer | gen_op_add(); |
889 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
890 | d9bce9d9 | j_mayer | gen_op_check_addo(); |
891 | d9bce9d9 | j_mayer | } |
892 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
893 | b068d6a7 | j_mayer | static always_inline void gen_op_addc_64 (void) |
894 | d9bce9d9 | j_mayer | { |
895 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
896 | d9bce9d9 | j_mayer | gen_op_add(); |
897 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
898 | d9bce9d9 | j_mayer | } |
899 | b068d6a7 | j_mayer | static always_inline void gen_op_addco_64 (void) |
900 | d9bce9d9 | j_mayer | { |
901 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
902 | d9bce9d9 | j_mayer | gen_op_add(); |
903 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
904 | d9bce9d9 | j_mayer | gen_op_check_addo_64(); |
905 | d9bce9d9 | j_mayer | } |
906 | d9bce9d9 | j_mayer | #endif
|
907 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER); |
908 | 79aceca5 | bellard | /* adde adde. addeo addeo. */
|
909 | b068d6a7 | j_mayer | static always_inline void gen_op_addeo (void) |
910 | d9bce9d9 | j_mayer | { |
911 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
912 | d9bce9d9 | j_mayer | gen_op_adde(); |
913 | d9bce9d9 | j_mayer | gen_op_check_addo(); |
914 | d9bce9d9 | j_mayer | } |
915 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
916 | b068d6a7 | j_mayer | static always_inline void gen_op_addeo_64 (void) |
917 | d9bce9d9 | j_mayer | { |
918 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
919 | d9bce9d9 | j_mayer | gen_op_adde_64(); |
920 | d9bce9d9 | j_mayer | gen_op_check_addo_64(); |
921 | d9bce9d9 | j_mayer | } |
922 | d9bce9d9 | j_mayer | #endif
|
923 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER); |
924 | 79aceca5 | bellard | /* addme addme. addmeo addmeo. */
|
925 | b068d6a7 | j_mayer | static always_inline void gen_op_addme (void) |
926 | d9bce9d9 | j_mayer | { |
927 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
928 | d9bce9d9 | j_mayer | gen_op_add_me(); |
929 | d9bce9d9 | j_mayer | } |
930 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
931 | b068d6a7 | j_mayer | static always_inline void gen_op_addme_64 (void) |
932 | d9bce9d9 | j_mayer | { |
933 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
934 | d9bce9d9 | j_mayer | gen_op_add_me_64(); |
935 | d9bce9d9 | j_mayer | } |
936 | d9bce9d9 | j_mayer | #endif
|
937 | d9bce9d9 | j_mayer | GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER); |
938 | 79aceca5 | bellard | /* addze addze. addzeo addzeo. */
|
939 | b068d6a7 | j_mayer | static always_inline void gen_op_addze (void) |
940 | d9bce9d9 | j_mayer | { |
941 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
942 | d9bce9d9 | j_mayer | gen_op_add_ze(); |
943 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
944 | d9bce9d9 | j_mayer | } |
945 | b068d6a7 | j_mayer | static always_inline void gen_op_addzeo (void) |
946 | d9bce9d9 | j_mayer | { |
947 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
948 | d9bce9d9 | j_mayer | gen_op_add_ze(); |
949 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
950 | d9bce9d9 | j_mayer | gen_op_check_addo(); |
951 | d9bce9d9 | j_mayer | } |
952 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
953 | b068d6a7 | j_mayer | static always_inline void gen_op_addze_64 (void) |
954 | d9bce9d9 | j_mayer | { |
955 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
956 | d9bce9d9 | j_mayer | gen_op_add_ze(); |
957 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
958 | d9bce9d9 | j_mayer | } |
959 | b068d6a7 | j_mayer | static always_inline void gen_op_addzeo_64 (void) |
960 | d9bce9d9 | j_mayer | { |
961 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
962 | d9bce9d9 | j_mayer | gen_op_add_ze(); |
963 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
964 | d9bce9d9 | j_mayer | gen_op_check_addo_64(); |
965 | d9bce9d9 | j_mayer | } |
966 | d9bce9d9 | j_mayer | #endif
|
967 | d9bce9d9 | j_mayer | GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER); |
968 | 79aceca5 | bellard | /* divw divw. divwo divwo. */
|
969 | d9bce9d9 | j_mayer | GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER); |
970 | 79aceca5 | bellard | /* divwu divwu. divwuo divwuo. */
|
971 | d9bce9d9 | j_mayer | GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER); |
972 | 79aceca5 | bellard | /* mulhw mulhw. */
|
973 | d9bce9d9 | j_mayer | GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER); |
974 | 79aceca5 | bellard | /* mulhwu mulhwu. */
|
975 | d9bce9d9 | j_mayer | GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER); |
976 | 79aceca5 | bellard | /* mullw mullw. mullwo mullwo. */
|
977 | d9bce9d9 | j_mayer | GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER); |
978 | 79aceca5 | bellard | /* neg neg. nego nego. */
|
979 | d9bce9d9 | j_mayer | GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); |
980 | 79aceca5 | bellard | /* subf subf. subfo subfo. */
|
981 | b068d6a7 | j_mayer | static always_inline void gen_op_subfo (void) |
982 | d9bce9d9 | j_mayer | { |
983 | f0413473 | aurel32 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
984 | d9bce9d9 | j_mayer | gen_op_subf(); |
985 | c3e10c7b | j_mayer | gen_op_check_addo(); |
986 | d9bce9d9 | j_mayer | } |
987 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
988 | d9bce9d9 | j_mayer | #define gen_op_subf_64 gen_op_subf
|
989 | b068d6a7 | j_mayer | static always_inline void gen_op_subfo_64 (void) |
990 | d9bce9d9 | j_mayer | { |
991 | f0413473 | aurel32 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
992 | d9bce9d9 | j_mayer | gen_op_subf(); |
993 | c3e10c7b | j_mayer | gen_op_check_addo_64(); |
994 | d9bce9d9 | j_mayer | } |
995 | d9bce9d9 | j_mayer | #endif
|
996 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER); |
997 | 79aceca5 | bellard | /* subfc subfc. subfco subfco. */
|
998 | b068d6a7 | j_mayer | static always_inline void gen_op_subfc (void) |
999 | d9bce9d9 | j_mayer | { |
1000 | d9bce9d9 | j_mayer | gen_op_subf(); |
1001 | d9bce9d9 | j_mayer | gen_op_check_subfc(); |
1002 | d9bce9d9 | j_mayer | } |
1003 | b068d6a7 | j_mayer | static always_inline void gen_op_subfco (void) |
1004 | d9bce9d9 | j_mayer | { |
1005 | f0413473 | aurel32 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
1006 | d9bce9d9 | j_mayer | gen_op_subf(); |
1007 | d9bce9d9 | j_mayer | gen_op_check_subfc(); |
1008 | c3e10c7b | j_mayer | gen_op_check_addo(); |
1009 | d9bce9d9 | j_mayer | } |
1010 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1011 | b068d6a7 | j_mayer | static always_inline void gen_op_subfc_64 (void) |
1012 | d9bce9d9 | j_mayer | { |
1013 | d9bce9d9 | j_mayer | gen_op_subf(); |
1014 | d9bce9d9 | j_mayer | gen_op_check_subfc_64(); |
1015 | d9bce9d9 | j_mayer | } |
1016 | b068d6a7 | j_mayer | static always_inline void gen_op_subfco_64 (void) |
1017 | d9bce9d9 | j_mayer | { |
1018 | f0413473 | aurel32 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
1019 | d9bce9d9 | j_mayer | gen_op_subf(); |
1020 | d9bce9d9 | j_mayer | gen_op_check_subfc_64(); |
1021 | c3e10c7b | j_mayer | gen_op_check_addo_64(); |
1022 | d9bce9d9 | j_mayer | } |
1023 | d9bce9d9 | j_mayer | #endif
|
1024 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER); |
1025 | 79aceca5 | bellard | /* subfe subfe. subfeo subfeo. */
|
1026 | b068d6a7 | j_mayer | static always_inline void gen_op_subfeo (void) |
1027 | d9bce9d9 | j_mayer | { |
1028 | f0413473 | aurel32 | tcg_gen_not_tl(cpu_T[2], cpu_T[0]); |
1029 | d9bce9d9 | j_mayer | gen_op_subfe(); |
1030 | c3e10c7b | j_mayer | gen_op_check_addo(); |
1031 | d9bce9d9 | j_mayer | } |
1032 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1033 | d9bce9d9 | j_mayer | #define gen_op_subfe_64 gen_op_subfe
|
1034 | b068d6a7 | j_mayer | static always_inline void gen_op_subfeo_64 (void) |
1035 | d9bce9d9 | j_mayer | { |
1036 | f0413473 | aurel32 | tcg_gen_not_i64(cpu_T[2], cpu_T[0]); |
1037 | d9bce9d9 | j_mayer | gen_op_subfe_64(); |
1038 | c3e10c7b | j_mayer | gen_op_check_addo_64(); |
1039 | d9bce9d9 | j_mayer | } |
1040 | d9bce9d9 | j_mayer | #endif
|
1041 | d9bce9d9 | j_mayer | GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER); |
1042 | 79aceca5 | bellard | /* subfme subfme. subfmeo subfmeo. */
|
1043 | d9bce9d9 | j_mayer | GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER); |
1044 | 79aceca5 | bellard | /* subfze subfze. subfzeo subfzeo. */
|
1045 | d9bce9d9 | j_mayer | GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER); |
1046 | 79aceca5 | bellard | /* addi */
|
1047 | 79aceca5 | bellard | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1048 | 79aceca5 | bellard | { |
1049 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
1050 | 79aceca5 | bellard | |
1051 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1052 | 76a66253 | j_mayer | /* li case */
|
1053 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[0], simm);
|
1054 | 79aceca5 | bellard | } else {
|
1055 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1056 | 76a66253 | j_mayer | if (likely(simm != 0)) |
1057 | 76a66253 | j_mayer | gen_op_addi(simm); |
1058 | 79aceca5 | bellard | } |
1059 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1060 | 79aceca5 | bellard | } |
1061 | 79aceca5 | bellard | /* addic */
|
1062 | 79aceca5 | bellard | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1063 | 79aceca5 | bellard | { |
1064 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
1065 | 76a66253 | j_mayer | |
1066 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1067 | d9bce9d9 | j_mayer | if (likely(simm != 0)) { |
1068 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
1069 | d9bce9d9 | j_mayer | gen_op_addi(simm); |
1070 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1071 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1072 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
1073 | d9bce9d9 | j_mayer | else
|
1074 | d9bce9d9 | j_mayer | #endif
|
1075 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
1076 | e864cabd | j_mayer | } else {
|
1077 | e864cabd | j_mayer | gen_op_clear_xer_ca(); |
1078 | d9bce9d9 | j_mayer | } |
1079 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1080 | 79aceca5 | bellard | } |
1081 | 79aceca5 | bellard | /* addic. */
|
1082 | c7697e1f | j_mayer | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1083 | 79aceca5 | bellard | { |
1084 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
1085 | 76a66253 | j_mayer | |
1086 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1087 | d9bce9d9 | j_mayer | if (likely(simm != 0)) { |
1088 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); |
1089 | d9bce9d9 | j_mayer | gen_op_addi(simm); |
1090 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1091 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1092 | d9bce9d9 | j_mayer | gen_op_check_addc_64(); |
1093 | d9bce9d9 | j_mayer | else
|
1094 | d9bce9d9 | j_mayer | #endif
|
1095 | d9bce9d9 | j_mayer | gen_op_check_addc(); |
1096 | 966439a6 | j_mayer | } else {
|
1097 | 966439a6 | j_mayer | gen_op_clear_xer_ca(); |
1098 | d9bce9d9 | j_mayer | } |
1099 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1100 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1101 | 79aceca5 | bellard | } |
1102 | 79aceca5 | bellard | /* addis */
|
1103 | 79aceca5 | bellard | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1104 | 79aceca5 | bellard | { |
1105 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
1106 | 79aceca5 | bellard | |
1107 | 79aceca5 | bellard | if (rA(ctx->opcode) == 0) { |
1108 | 76a66253 | j_mayer | /* lis case */
|
1109 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[0], simm << 16); |
1110 | 79aceca5 | bellard | } else {
|
1111 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1112 | 76a66253 | j_mayer | if (likely(simm != 0)) |
1113 | 76a66253 | j_mayer | gen_op_addi(simm << 16);
|
1114 | 79aceca5 | bellard | } |
1115 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1116 | 79aceca5 | bellard | } |
1117 | 79aceca5 | bellard | /* mulli */
|
1118 | 79aceca5 | bellard | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1119 | 79aceca5 | bellard | { |
1120 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1121 | 79aceca5 | bellard | gen_op_mulli(SIMM(ctx->opcode)); |
1122 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1123 | 79aceca5 | bellard | } |
1124 | 79aceca5 | bellard | /* subfic */
|
1125 | 79aceca5 | bellard | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1126 | 79aceca5 | bellard | { |
1127 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1128 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1129 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1130 | d9bce9d9 | j_mayer | gen_op_subfic_64(SIMM(ctx->opcode)); |
1131 | d9bce9d9 | j_mayer | else
|
1132 | d9bce9d9 | j_mayer | #endif
|
1133 | d9bce9d9 | j_mayer | gen_op_subfic(SIMM(ctx->opcode)); |
1134 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1135 | 79aceca5 | bellard | } |
1136 | 79aceca5 | bellard | |
1137 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1138 | d9bce9d9 | j_mayer | /* mulhd mulhd. */
|
1139 | a750fc0b | j_mayer | GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B); |
1140 | d9bce9d9 | j_mayer | /* mulhdu mulhdu. */
|
1141 | a750fc0b | j_mayer | GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B); |
1142 | d9bce9d9 | j_mayer | /* mulld mulld. mulldo mulldo. */
|
1143 | a750fc0b | j_mayer | GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B); |
1144 | d9bce9d9 | j_mayer | /* divd divd. divdo divdo. */
|
1145 | a750fc0b | j_mayer | GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B); |
1146 | d9bce9d9 | j_mayer | /* divdu divdu. divduo divduo. */
|
1147 | a750fc0b | j_mayer | GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); |
1148 | d9bce9d9 | j_mayer | #endif
|
1149 | d9bce9d9 | j_mayer | |
1150 | 79aceca5 | bellard | /*** Integer comparison ***/
|
1151 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1152 | d9bce9d9 | j_mayer | #define GEN_CMP(name, opc, type) \
|
1153 | d9bce9d9 | j_mayer | GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ |
1154 | d9bce9d9 | j_mayer | { \ |
1155 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
1156 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1157 | e3878283 | j_mayer | if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \ |
1158 | d9bce9d9 | j_mayer | gen_op_##name##_64(); \ |
1159 | d9bce9d9 | j_mayer | else \
|
1160 | d9bce9d9 | j_mayer | gen_op_##name(); \ |
1161 | d9bce9d9 | j_mayer | gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
1162 | d9bce9d9 | j_mayer | } |
1163 | d9bce9d9 | j_mayer | #else
|
1164 | d9bce9d9 | j_mayer | #define GEN_CMP(name, opc, type) \
|
1165 | d9bce9d9 | j_mayer | GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ |
1166 | 79aceca5 | bellard | { \ |
1167 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
|
1168 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1169 | 79aceca5 | bellard | gen_op_##name(); \ |
1170 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
1171 | 79aceca5 | bellard | } |
1172 | d9bce9d9 | j_mayer | #endif
|
1173 | 79aceca5 | bellard | |
1174 | 79aceca5 | bellard | /* cmp */
|
1175 | d9bce9d9 | j_mayer | GEN_CMP(cmp, 0x00, PPC_INTEGER);
|
1176 | 79aceca5 | bellard | /* cmpi */
|
1177 | 79aceca5 | bellard | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
1178 | 79aceca5 | bellard | { |
1179 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1180 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1181 | e3878283 | j_mayer | if (ctx->sf_mode && (ctx->opcode & 0x00200000)) |
1182 | d9bce9d9 | j_mayer | gen_op_cmpi_64(SIMM(ctx->opcode)); |
1183 | d9bce9d9 | j_mayer | else
|
1184 | d9bce9d9 | j_mayer | #endif
|
1185 | d9bce9d9 | j_mayer | gen_op_cmpi(SIMM(ctx->opcode)); |
1186 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1187 | 79aceca5 | bellard | } |
1188 | 79aceca5 | bellard | /* cmpl */
|
1189 | d9bce9d9 | j_mayer | GEN_CMP(cmpl, 0x01, PPC_INTEGER);
|
1190 | 79aceca5 | bellard | /* cmpli */
|
1191 | 79aceca5 | bellard | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
1192 | 79aceca5 | bellard | { |
1193 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1194 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1195 | e3878283 | j_mayer | if (ctx->sf_mode && (ctx->opcode & 0x00200000)) |
1196 | d9bce9d9 | j_mayer | gen_op_cmpli_64(UIMM(ctx->opcode)); |
1197 | d9bce9d9 | j_mayer | else
|
1198 | d9bce9d9 | j_mayer | #endif
|
1199 | d9bce9d9 | j_mayer | gen_op_cmpli(UIMM(ctx->opcode)); |
1200 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1201 | 79aceca5 | bellard | } |
1202 | 79aceca5 | bellard | |
1203 | d9bce9d9 | j_mayer | /* isel (PowerPC 2.03 specification) */
|
1204 | fd501a05 | aurel32 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) |
1205 | d9bce9d9 | j_mayer | { |
1206 | d9bce9d9 | j_mayer | uint32_t bi = rC(ctx->opcode); |
1207 | d9bce9d9 | j_mayer | uint32_t mask; |
1208 | d9bce9d9 | j_mayer | |
1209 | d9bce9d9 | j_mayer | if (rA(ctx->opcode) == 0) { |
1210 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[0], 0); |
1211 | d9bce9d9 | j_mayer | } else {
|
1212 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1213 | d9bce9d9 | j_mayer | } |
1214 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
1215 | d9bce9d9 | j_mayer | mask = 1 << (3 - (bi & 0x03)); |
1216 | d9bce9d9 | j_mayer | gen_op_load_crf_T0(bi >> 2);
|
1217 | d9bce9d9 | j_mayer | gen_op_test_true(mask); |
1218 | d9bce9d9 | j_mayer | gen_op_isel(); |
1219 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
1220 | d9bce9d9 | j_mayer | } |
1221 | d9bce9d9 | j_mayer | |
1222 | 79aceca5 | bellard | /*** Integer logical ***/
|
1223 | d9bce9d9 | j_mayer | #define __GEN_LOGICAL2(name, opc2, opc3, type) \
|
1224 | d9bce9d9 | j_mayer | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \ |
1225 | 79aceca5 | bellard | { \ |
1226 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
|
1227 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
|
1228 | 79aceca5 | bellard | gen_op_##name(); \ |
1229 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
1230 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1231 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
1232 | 79aceca5 | bellard | } |
1233 | d9bce9d9 | j_mayer | #define GEN_LOGICAL2(name, opc, type) \
|
1234 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(name, 0x1C, opc, type)
|
1235 | 79aceca5 | bellard | |
1236 | d9bce9d9 | j_mayer | #define GEN_LOGICAL1(name, opc, type) \
|
1237 | d9bce9d9 | j_mayer | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ |
1238 | 79aceca5 | bellard | { \ |
1239 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
|
1240 | 79aceca5 | bellard | gen_op_##name(); \ |
1241 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
1242 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1243 | 76a66253 | j_mayer | gen_set_Rc0(ctx); \ |
1244 | 79aceca5 | bellard | } |
1245 | 79aceca5 | bellard | |
1246 | 79aceca5 | bellard | /* and & and. */
|
1247 | d9bce9d9 | j_mayer | GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
|
1248 | 79aceca5 | bellard | /* andc & andc. */
|
1249 | d9bce9d9 | j_mayer | GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
|
1250 | 79aceca5 | bellard | /* andi. */
|
1251 | c7697e1f | j_mayer | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1252 | 79aceca5 | bellard | { |
1253 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1254 | 76a66253 | j_mayer | gen_op_andi_T0(UIMM(ctx->opcode)); |
1255 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1256 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1257 | 79aceca5 | bellard | } |
1258 | 79aceca5 | bellard | /* andis. */
|
1259 | c7697e1f | j_mayer | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1260 | 79aceca5 | bellard | { |
1261 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1262 | 76a66253 | j_mayer | gen_op_andi_T0(UIMM(ctx->opcode) << 16);
|
1263 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1264 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1265 | 79aceca5 | bellard | } |
1266 | 79aceca5 | bellard | |
1267 | 79aceca5 | bellard | /* cntlzw */
|
1268 | d9bce9d9 | j_mayer | GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
|
1269 | 79aceca5 | bellard | /* eqv & eqv. */
|
1270 | d9bce9d9 | j_mayer | GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
|
1271 | 79aceca5 | bellard | /* extsb & extsb. */
|
1272 | d9bce9d9 | j_mayer | GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
|
1273 | 79aceca5 | bellard | /* extsh & extsh. */
|
1274 | d9bce9d9 | j_mayer | GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
|
1275 | 79aceca5 | bellard | /* nand & nand. */
|
1276 | d9bce9d9 | j_mayer | GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
|
1277 | 79aceca5 | bellard | /* nor & nor. */
|
1278 | d9bce9d9 | j_mayer | GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
|
1279 | 9a64fbe4 | bellard | |
1280 | 79aceca5 | bellard | /* or & or. */
|
1281 | 9a64fbe4 | bellard | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
1282 | 9a64fbe4 | bellard | { |
1283 | 76a66253 | j_mayer | int rs, ra, rb;
|
1284 | 76a66253 | j_mayer | |
1285 | 76a66253 | j_mayer | rs = rS(ctx->opcode); |
1286 | 76a66253 | j_mayer | ra = rA(ctx->opcode); |
1287 | 76a66253 | j_mayer | rb = rB(ctx->opcode); |
1288 | 76a66253 | j_mayer | /* Optimisation for mr. ri case */
|
1289 | 76a66253 | j_mayer | if (rs != ra || rs != rb) {
|
1290 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
|
1291 | 76a66253 | j_mayer | if (rs != rb) {
|
1292 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
|
1293 | 76a66253 | j_mayer | gen_op_or(); |
1294 | 76a66253 | j_mayer | } |
1295 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
1296 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1297 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1298 | 76a66253 | j_mayer | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1299 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
|
1300 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1301 | c80f84e3 | j_mayer | #if defined(TARGET_PPC64)
|
1302 | c80f84e3 | j_mayer | } else {
|
1303 | c80f84e3 | j_mayer | switch (rs) {
|
1304 | c80f84e3 | j_mayer | case 1: |
1305 | c80f84e3 | j_mayer | /* Set process priority to low */
|
1306 | c80f84e3 | j_mayer | gen_op_store_pri(2);
|
1307 | c80f84e3 | j_mayer | break;
|
1308 | c80f84e3 | j_mayer | case 6: |
1309 | c80f84e3 | j_mayer | /* Set process priority to medium-low */
|
1310 | c80f84e3 | j_mayer | gen_op_store_pri(3);
|
1311 | c80f84e3 | j_mayer | break;
|
1312 | c80f84e3 | j_mayer | case 2: |
1313 | c80f84e3 | j_mayer | /* Set process priority to normal */
|
1314 | c80f84e3 | j_mayer | gen_op_store_pri(4);
|
1315 | c80f84e3 | j_mayer | break;
|
1316 | be147d08 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
1317 | be147d08 | j_mayer | case 31: |
1318 | be147d08 | j_mayer | if (ctx->supervisor > 0) { |
1319 | be147d08 | j_mayer | /* Set process priority to very low */
|
1320 | be147d08 | j_mayer | gen_op_store_pri(1);
|
1321 | be147d08 | j_mayer | } |
1322 | be147d08 | j_mayer | break;
|
1323 | be147d08 | j_mayer | case 5: |
1324 | be147d08 | j_mayer | if (ctx->supervisor > 0) { |
1325 | be147d08 | j_mayer | /* Set process priority to medium-hight */
|
1326 | be147d08 | j_mayer | gen_op_store_pri(5);
|
1327 | be147d08 | j_mayer | } |
1328 | be147d08 | j_mayer | break;
|
1329 | be147d08 | j_mayer | case 3: |
1330 | be147d08 | j_mayer | if (ctx->supervisor > 0) { |
1331 | be147d08 | j_mayer | /* Set process priority to high */
|
1332 | be147d08 | j_mayer | gen_op_store_pri(6);
|
1333 | be147d08 | j_mayer | } |
1334 | be147d08 | j_mayer | break;
|
1335 | be147d08 | j_mayer | case 7: |
1336 | be147d08 | j_mayer | if (ctx->supervisor > 1) { |
1337 | be147d08 | j_mayer | /* Set process priority to very high */
|
1338 | be147d08 | j_mayer | gen_op_store_pri(7);
|
1339 | be147d08 | j_mayer | } |
1340 | be147d08 | j_mayer | break;
|
1341 | be147d08 | j_mayer | #endif
|
1342 | c80f84e3 | j_mayer | default:
|
1343 | c80f84e3 | j_mayer | /* nop */
|
1344 | c80f84e3 | j_mayer | break;
|
1345 | c80f84e3 | j_mayer | } |
1346 | c80f84e3 | j_mayer | #endif
|
1347 | 9a64fbe4 | bellard | } |
1348 | 9a64fbe4 | bellard | } |
1349 | 9a64fbe4 | bellard | |
1350 | 79aceca5 | bellard | /* orc & orc. */
|
1351 | d9bce9d9 | j_mayer | GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
|
1352 | 79aceca5 | bellard | /* xor & xor. */
|
1353 | 9a64fbe4 | bellard | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
1354 | 9a64fbe4 | bellard | { |
1355 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1356 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
1357 | 9a64fbe4 | bellard | if (rS(ctx->opcode) != rB(ctx->opcode)) {
|
1358 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1359 | 9a64fbe4 | bellard | gen_op_xor(); |
1360 | 9a64fbe4 | bellard | } else {
|
1361 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[0], 0); |
1362 | 9a64fbe4 | bellard | } |
1363 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1364 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1365 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1366 | 9a64fbe4 | bellard | } |
1367 | 79aceca5 | bellard | /* ori */
|
1368 | 79aceca5 | bellard | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1369 | 79aceca5 | bellard | { |
1370 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1371 | 79aceca5 | bellard | |
1372 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1373 | 9a64fbe4 | bellard | /* NOP */
|
1374 | 76a66253 | j_mayer | /* XXX: should handle special NOPs for POWER series */
|
1375 | 9a64fbe4 | bellard | return;
|
1376 | 76a66253 | j_mayer | } |
1377 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1378 | 76a66253 | j_mayer | if (likely(uimm != 0)) |
1379 | 79aceca5 | bellard | gen_op_ori(uimm); |
1380 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1381 | 79aceca5 | bellard | } |
1382 | 79aceca5 | bellard | /* oris */
|
1383 | 79aceca5 | bellard | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1384 | 79aceca5 | bellard | { |
1385 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1386 | 79aceca5 | bellard | |
1387 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1388 | 9a64fbe4 | bellard | /* NOP */
|
1389 | 9a64fbe4 | bellard | return;
|
1390 | 76a66253 | j_mayer | } |
1391 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1392 | 76a66253 | j_mayer | if (likely(uimm != 0)) |
1393 | 79aceca5 | bellard | gen_op_ori(uimm << 16);
|
1394 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1395 | 79aceca5 | bellard | } |
1396 | 79aceca5 | bellard | /* xori */
|
1397 | 79aceca5 | bellard | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1398 | 79aceca5 | bellard | { |
1399 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1400 | 9a64fbe4 | bellard | |
1401 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1402 | 9a64fbe4 | bellard | /* NOP */
|
1403 | 9a64fbe4 | bellard | return;
|
1404 | 9a64fbe4 | bellard | } |
1405 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1406 | 76a66253 | j_mayer | if (likely(uimm != 0)) |
1407 | 76a66253 | j_mayer | gen_op_xori(uimm); |
1408 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1409 | 79aceca5 | bellard | } |
1410 | 79aceca5 | bellard | |
1411 | 79aceca5 | bellard | /* xoris */
|
1412 | 79aceca5 | bellard | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1413 | 79aceca5 | bellard | { |
1414 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1415 | 9a64fbe4 | bellard | |
1416 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1417 | 9a64fbe4 | bellard | /* NOP */
|
1418 | 9a64fbe4 | bellard | return;
|
1419 | 9a64fbe4 | bellard | } |
1420 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1421 | 76a66253 | j_mayer | if (likely(uimm != 0)) |
1422 | 76a66253 | j_mayer | gen_op_xori(uimm << 16);
|
1423 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1424 | 79aceca5 | bellard | } |
1425 | 79aceca5 | bellard | |
1426 | d9bce9d9 | j_mayer | /* popcntb : PowerPC 2.03 specification */
|
1427 | 05332d70 | j_mayer | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) |
1428 | d9bce9d9 | j_mayer | { |
1429 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1430 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1431 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1432 | 6676f424 | aurel32 | gen_op_popcntb_64(); |
1433 | d9bce9d9 | j_mayer | else
|
1434 | d9bce9d9 | j_mayer | #endif
|
1435 | 6676f424 | aurel32 | gen_op_popcntb(); |
1436 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1437 | d9bce9d9 | j_mayer | } |
1438 | d9bce9d9 | j_mayer | |
1439 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1440 | d9bce9d9 | j_mayer | /* extsw & extsw. */
|
1441 | d9bce9d9 | j_mayer | GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
|
1442 | d9bce9d9 | j_mayer | /* cntlzd */
|
1443 | d9bce9d9 | j_mayer | GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
|
1444 | d9bce9d9 | j_mayer | #endif
|
1445 | d9bce9d9 | j_mayer | |
1446 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1447 | 79aceca5 | bellard | /* rlwimi & rlwimi. */
|
1448 | 79aceca5 | bellard | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1449 | 79aceca5 | bellard | { |
1450 | 76a66253 | j_mayer | target_ulong mask; |
1451 | 76a66253 | j_mayer | uint32_t mb, me, sh; |
1452 | 79aceca5 | bellard | |
1453 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1454 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1455 | 76a66253 | j_mayer | sh = SH(ctx->opcode); |
1456 | 76a66253 | j_mayer | if (likely(sh == 0)) { |
1457 | 76a66253 | j_mayer | if (likely(mb == 0 && me == 31)) { |
1458 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1459 | 76a66253 | j_mayer | goto do_store;
|
1460 | 76a66253 | j_mayer | } else if (likely(mb == 31 && me == 0)) { |
1461 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
1462 | 76a66253 | j_mayer | goto do_store;
|
1463 | 76a66253 | j_mayer | } |
1464 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1465 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1466 | 76a66253 | j_mayer | goto do_mask;
|
1467 | 76a66253 | j_mayer | } |
1468 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1469 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1470 | 76a66253 | j_mayer | gen_op_rotli32_T0(SH(ctx->opcode)); |
1471 | 76a66253 | j_mayer | do_mask:
|
1472 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1473 | 76a66253 | j_mayer | mb += 32;
|
1474 | 76a66253 | j_mayer | me += 32;
|
1475 | 76a66253 | j_mayer | #endif
|
1476 | 76a66253 | j_mayer | mask = MASK(mb, me); |
1477 | 76a66253 | j_mayer | gen_op_andi_T0(mask); |
1478 | 76a66253 | j_mayer | gen_op_andi_T1(~mask); |
1479 | 76a66253 | j_mayer | gen_op_or(); |
1480 | 76a66253 | j_mayer | do_store:
|
1481 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1482 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1483 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1484 | 79aceca5 | bellard | } |
1485 | 79aceca5 | bellard | /* rlwinm & rlwinm. */
|
1486 | 79aceca5 | bellard | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1487 | 79aceca5 | bellard | { |
1488 | 79aceca5 | bellard | uint32_t mb, me, sh; |
1489 | 3b46e624 | ths | |
1490 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
1491 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1492 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1493 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1494 | 76a66253 | j_mayer | if (likely(sh == 0)) { |
1495 | 76a66253 | j_mayer | goto do_mask;
|
1496 | 76a66253 | j_mayer | } |
1497 | 76a66253 | j_mayer | if (likely(mb == 0)) { |
1498 | 76a66253 | j_mayer | if (likely(me == 31)) { |
1499 | 76a66253 | j_mayer | gen_op_rotli32_T0(sh); |
1500 | 76a66253 | j_mayer | goto do_store;
|
1501 | 76a66253 | j_mayer | } else if (likely(me == (31 - sh))) { |
1502 | 76a66253 | j_mayer | gen_op_sli_T0(sh); |
1503 | 76a66253 | j_mayer | goto do_store;
|
1504 | 79aceca5 | bellard | } |
1505 | 76a66253 | j_mayer | } else if (likely(me == 31)) { |
1506 | 76a66253 | j_mayer | if (likely(sh == (32 - mb))) { |
1507 | 76a66253 | j_mayer | gen_op_srli_T0(mb); |
1508 | 76a66253 | j_mayer | goto do_store;
|
1509 | 79aceca5 | bellard | } |
1510 | 79aceca5 | bellard | } |
1511 | 76a66253 | j_mayer | gen_op_rotli32_T0(sh); |
1512 | 76a66253 | j_mayer | do_mask:
|
1513 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1514 | 76a66253 | j_mayer | mb += 32;
|
1515 | 76a66253 | j_mayer | me += 32;
|
1516 | 76a66253 | j_mayer | #endif
|
1517 | 76a66253 | j_mayer | gen_op_andi_T0(MASK(mb, me)); |
1518 | 76a66253 | j_mayer | do_store:
|
1519 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1520 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1521 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1522 | 79aceca5 | bellard | } |
1523 | 79aceca5 | bellard | /* rlwnm & rlwnm. */
|
1524 | 79aceca5 | bellard | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
1525 | 79aceca5 | bellard | { |
1526 | 79aceca5 | bellard | uint32_t mb, me; |
1527 | 79aceca5 | bellard | |
1528 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1529 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1530 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1531 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1532 | 76a66253 | j_mayer | gen_op_rotl32_T0_T1(); |
1533 | 76a66253 | j_mayer | if (unlikely(mb != 0 || me != 31)) { |
1534 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1535 | 76a66253 | j_mayer | mb += 32;
|
1536 | 76a66253 | j_mayer | me += 32;
|
1537 | 76a66253 | j_mayer | #endif
|
1538 | 76a66253 | j_mayer | gen_op_andi_T0(MASK(mb, me)); |
1539 | 79aceca5 | bellard | } |
1540 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1541 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1542 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1543 | 79aceca5 | bellard | } |
1544 | 79aceca5 | bellard | |
1545 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1546 | d9bce9d9 | j_mayer | #define GEN_PPC64_R2(name, opc1, opc2) \
|
1547 | c7697e1f | j_mayer | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
1548 | d9bce9d9 | j_mayer | { \ |
1549 | d9bce9d9 | j_mayer | gen_##name(ctx, 0); \ |
1550 | d9bce9d9 | j_mayer | } \ |
1551 | c7697e1f | j_mayer | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
1552 | c7697e1f | j_mayer | PPC_64B) \ |
1553 | d9bce9d9 | j_mayer | { \ |
1554 | d9bce9d9 | j_mayer | gen_##name(ctx, 1); \ |
1555 | d9bce9d9 | j_mayer | } |
1556 | d9bce9d9 | j_mayer | #define GEN_PPC64_R4(name, opc1, opc2) \
|
1557 | c7697e1f | j_mayer | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \ |
1558 | d9bce9d9 | j_mayer | { \ |
1559 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 0); \ |
1560 | d9bce9d9 | j_mayer | } \ |
1561 | c7697e1f | j_mayer | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
1562 | c7697e1f | j_mayer | PPC_64B) \ |
1563 | d9bce9d9 | j_mayer | { \ |
1564 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 1); \ |
1565 | d9bce9d9 | j_mayer | } \ |
1566 | c7697e1f | j_mayer | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
1567 | c7697e1f | j_mayer | PPC_64B) \ |
1568 | d9bce9d9 | j_mayer | { \ |
1569 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 0); \ |
1570 | d9bce9d9 | j_mayer | } \ |
1571 | c7697e1f | j_mayer | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
1572 | c7697e1f | j_mayer | PPC_64B) \ |
1573 | d9bce9d9 | j_mayer | { \ |
1574 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 1); \ |
1575 | d9bce9d9 | j_mayer | } |
1576 | 51789c41 | j_mayer | |
1577 | b068d6a7 | j_mayer | static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask) |
1578 | 40d0591e | j_mayer | { |
1579 | 40d0591e | j_mayer | if (mask >> 32) |
1580 | 40d0591e | j_mayer | gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF); |
1581 | 40d0591e | j_mayer | else
|
1582 | 40d0591e | j_mayer | gen_op_andi_T0(mask); |
1583 | 40d0591e | j_mayer | } |
1584 | 40d0591e | j_mayer | |
1585 | b068d6a7 | j_mayer | static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask) |
1586 | 40d0591e | j_mayer | { |
1587 | 40d0591e | j_mayer | if (mask >> 32) |
1588 | 40d0591e | j_mayer | gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF); |
1589 | 40d0591e | j_mayer | else
|
1590 | 40d0591e | j_mayer | gen_op_andi_T1(mask); |
1591 | 40d0591e | j_mayer | } |
1592 | 40d0591e | j_mayer | |
1593 | b068d6a7 | j_mayer | static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, |
1594 | b068d6a7 | j_mayer | uint32_t me, uint32_t sh) |
1595 | 51789c41 | j_mayer | { |
1596 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1597 | 51789c41 | j_mayer | if (likely(sh == 0)) { |
1598 | 51789c41 | j_mayer | goto do_mask;
|
1599 | 51789c41 | j_mayer | } |
1600 | 51789c41 | j_mayer | if (likely(mb == 0)) { |
1601 | 51789c41 | j_mayer | if (likely(me == 63)) { |
1602 | 40d0591e | j_mayer | gen_op_rotli64_T0(sh); |
1603 | 51789c41 | j_mayer | goto do_store;
|
1604 | 51789c41 | j_mayer | } else if (likely(me == (63 - sh))) { |
1605 | 51789c41 | j_mayer | gen_op_sli_T0(sh); |
1606 | 51789c41 | j_mayer | goto do_store;
|
1607 | 51789c41 | j_mayer | } |
1608 | 51789c41 | j_mayer | } else if (likely(me == 63)) { |
1609 | 51789c41 | j_mayer | if (likely(sh == (64 - mb))) { |
1610 | 40d0591e | j_mayer | gen_op_srli_T0_64(mb); |
1611 | 51789c41 | j_mayer | goto do_store;
|
1612 | 51789c41 | j_mayer | } |
1613 | 51789c41 | j_mayer | } |
1614 | 51789c41 | j_mayer | gen_op_rotli64_T0(sh); |
1615 | 51789c41 | j_mayer | do_mask:
|
1616 | 40d0591e | j_mayer | gen_andi_T0_64(ctx, MASK(mb, me)); |
1617 | 51789c41 | j_mayer | do_store:
|
1618 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1619 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1620 | 51789c41 | j_mayer | gen_set_Rc0(ctx); |
1621 | 51789c41 | j_mayer | } |
1622 | d9bce9d9 | j_mayer | /* rldicl - rldicl. */
|
1623 | b068d6a7 | j_mayer | static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) |
1624 | d9bce9d9 | j_mayer | { |
1625 | 51789c41 | j_mayer | uint32_t sh, mb; |
1626 | d9bce9d9 | j_mayer | |
1627 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1628 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1629 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63, sh);
|
1630 | d9bce9d9 | j_mayer | } |
1631 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1632 | d9bce9d9 | j_mayer | /* rldicr - rldicr. */
|
1633 | b068d6a7 | j_mayer | static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) |
1634 | d9bce9d9 | j_mayer | { |
1635 | 51789c41 | j_mayer | uint32_t sh, me; |
1636 | d9bce9d9 | j_mayer | |
1637 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1638 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1639 | 51789c41 | j_mayer | gen_rldinm(ctx, 0, me, sh);
|
1640 | d9bce9d9 | j_mayer | } |
1641 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1642 | d9bce9d9 | j_mayer | /* rldic - rldic. */
|
1643 | b068d6a7 | j_mayer | static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) |
1644 | d9bce9d9 | j_mayer | { |
1645 | 51789c41 | j_mayer | uint32_t sh, mb; |
1646 | d9bce9d9 | j_mayer | |
1647 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1648 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1649 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63 - sh, sh);
|
1650 | 51789c41 | j_mayer | } |
1651 | 51789c41 | j_mayer | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1652 | 51789c41 | j_mayer | |
1653 | b068d6a7 | j_mayer | static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
1654 | b068d6a7 | j_mayer | uint32_t me) |
1655 | 51789c41 | j_mayer | { |
1656 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1657 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
1658 | 51789c41 | j_mayer | gen_op_rotl64_T0_T1(); |
1659 | 51789c41 | j_mayer | if (unlikely(mb != 0 || me != 63)) { |
1660 | 40d0591e | j_mayer | gen_andi_T0_64(ctx, MASK(mb, me)); |
1661 | 51789c41 | j_mayer | } |
1662 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1663 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1664 | 51789c41 | j_mayer | gen_set_Rc0(ctx); |
1665 | d9bce9d9 | j_mayer | } |
1666 | 51789c41 | j_mayer | |
1667 | d9bce9d9 | j_mayer | /* rldcl - rldcl. */
|
1668 | b068d6a7 | j_mayer | static always_inline void gen_rldcl (DisasContext *ctx, int mbn) |
1669 | d9bce9d9 | j_mayer | { |
1670 | 51789c41 | j_mayer | uint32_t mb; |
1671 | d9bce9d9 | j_mayer | |
1672 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1673 | 51789c41 | j_mayer | gen_rldnm(ctx, mb, 63);
|
1674 | d9bce9d9 | j_mayer | } |
1675 | 36081602 | j_mayer | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1676 | d9bce9d9 | j_mayer | /* rldcr - rldcr. */
|
1677 | b068d6a7 | j_mayer | static always_inline void gen_rldcr (DisasContext *ctx, int men) |
1678 | d9bce9d9 | j_mayer | { |
1679 | 51789c41 | j_mayer | uint32_t me; |
1680 | d9bce9d9 | j_mayer | |
1681 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1682 | 51789c41 | j_mayer | gen_rldnm(ctx, 0, me);
|
1683 | d9bce9d9 | j_mayer | } |
1684 | 36081602 | j_mayer | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1685 | d9bce9d9 | j_mayer | /* rldimi - rldimi. */
|
1686 | b068d6a7 | j_mayer | static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) |
1687 | d9bce9d9 | j_mayer | { |
1688 | 51789c41 | j_mayer | uint64_t mask; |
1689 | 271a916e | j_mayer | uint32_t sh, mb, me; |
1690 | d9bce9d9 | j_mayer | |
1691 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1692 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1693 | 271a916e | j_mayer | me = 63 - sh;
|
1694 | 51789c41 | j_mayer | if (likely(sh == 0)) { |
1695 | 51789c41 | j_mayer | if (likely(mb == 0)) { |
1696 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1697 | 51789c41 | j_mayer | goto do_store;
|
1698 | 51789c41 | j_mayer | } |
1699 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1700 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1701 | 51789c41 | j_mayer | goto do_mask;
|
1702 | 51789c41 | j_mayer | } |
1703 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1704 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
1705 | 40d0591e | j_mayer | gen_op_rotli64_T0(sh); |
1706 | 51789c41 | j_mayer | do_mask:
|
1707 | 271a916e | j_mayer | mask = MASK(mb, me); |
1708 | 40d0591e | j_mayer | gen_andi_T0_64(ctx, mask); |
1709 | 40d0591e | j_mayer | gen_andi_T1_64(ctx, ~mask); |
1710 | 51789c41 | j_mayer | gen_op_or(); |
1711 | 51789c41 | j_mayer | do_store:
|
1712 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1713 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1714 | 51789c41 | j_mayer | gen_set_Rc0(ctx); |
1715 | d9bce9d9 | j_mayer | } |
1716 | 36081602 | j_mayer | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1717 | d9bce9d9 | j_mayer | #endif
|
1718 | d9bce9d9 | j_mayer | |
1719 | 79aceca5 | bellard | /*** Integer shift ***/
|
1720 | 79aceca5 | bellard | /* slw & slw. */
|
1721 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER); |
1722 | 79aceca5 | bellard | /* sraw & sraw. */
|
1723 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); |
1724 | 79aceca5 | bellard | /* srawi & srawi. */
|
1725 | 79aceca5 | bellard | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
1726 | 79aceca5 | bellard | { |
1727 | d9bce9d9 | j_mayer | int mb, me;
|
1728 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1729 | d9bce9d9 | j_mayer | if (SH(ctx->opcode) != 0) { |
1730 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
1731 | d9bce9d9 | j_mayer | mb = 32 - SH(ctx->opcode);
|
1732 | d9bce9d9 | j_mayer | me = 31;
|
1733 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1734 | d9bce9d9 | j_mayer | mb += 32;
|
1735 | d9bce9d9 | j_mayer | me += 32;
|
1736 | d9bce9d9 | j_mayer | #endif
|
1737 | d9bce9d9 | j_mayer | gen_op_srawi(SH(ctx->opcode), MASK(mb, me)); |
1738 | d9bce9d9 | j_mayer | } |
1739 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1740 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1741 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
1742 | 79aceca5 | bellard | } |
1743 | 79aceca5 | bellard | /* srw & srw. */
|
1744 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER); |
1745 | d9bce9d9 | j_mayer | |
1746 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1747 | d9bce9d9 | j_mayer | /* sld & sld. */
|
1748 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B); |
1749 | d9bce9d9 | j_mayer | /* srad & srad. */
|
1750 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B); |
1751 | d9bce9d9 | j_mayer | /* sradi & sradi. */
|
1752 | b068d6a7 | j_mayer | static always_inline void gen_sradi (DisasContext *ctx, int n) |
1753 | d9bce9d9 | j_mayer | { |
1754 | d9bce9d9 | j_mayer | uint64_t mask; |
1755 | d9bce9d9 | j_mayer | int sh, mb, me;
|
1756 | d9bce9d9 | j_mayer | |
1757 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
1758 | d9bce9d9 | j_mayer | sh = SH(ctx->opcode) + (n << 5);
|
1759 | d9bce9d9 | j_mayer | if (sh != 0) { |
1760 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
1761 | d9bce9d9 | j_mayer | mb = 64 - SH(ctx->opcode);
|
1762 | d9bce9d9 | j_mayer | me = 63;
|
1763 | d9bce9d9 | j_mayer | mask = MASK(mb, me); |
1764 | d9bce9d9 | j_mayer | gen_op_sradi(sh, mask >> 32, mask);
|
1765 | d9bce9d9 | j_mayer | } |
1766 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
1767 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1768 | d9bce9d9 | j_mayer | gen_set_Rc0(ctx); |
1769 | d9bce9d9 | j_mayer | } |
1770 | c7697e1f | j_mayer | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B) |
1771 | d9bce9d9 | j_mayer | { |
1772 | d9bce9d9 | j_mayer | gen_sradi(ctx, 0);
|
1773 | d9bce9d9 | j_mayer | } |
1774 | c7697e1f | j_mayer | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B) |
1775 | d9bce9d9 | j_mayer | { |
1776 | d9bce9d9 | j_mayer | gen_sradi(ctx, 1);
|
1777 | d9bce9d9 | j_mayer | } |
1778 | d9bce9d9 | j_mayer | /* srd & srd. */
|
1779 | d9bce9d9 | j_mayer | __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B); |
1780 | d9bce9d9 | j_mayer | #endif
|
1781 | 79aceca5 | bellard | |
1782 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1783 | 7c58044c | j_mayer | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
1784 | a750fc0b | j_mayer | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ |
1785 | 9a64fbe4 | bellard | { \ |
1786 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1787 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
1788 | 3cc62370 | bellard | return; \
|
1789 | 3cc62370 | bellard | } \ |
1790 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1791 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
1792 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
|
1793 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1794 | 4ecc3190 | bellard | gen_op_f##op(); \ |
1795 | 4ecc3190 | bellard | if (isfloat) { \
|
1796 | 4ecc3190 | bellard | gen_op_frsp(); \ |
1797 | 4ecc3190 | bellard | } \ |
1798 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1799 | 7c58044c | j_mayer | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1800 | 9a64fbe4 | bellard | } |
1801 | 9a64fbe4 | bellard | |
1802 | 7c58044c | j_mayer | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
1803 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
1804 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
1805 | 9a64fbe4 | bellard | |
1806 | 7c58044c | j_mayer | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1807 | 7c58044c | j_mayer | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
1808 | 9a64fbe4 | bellard | { \ |
1809 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1810 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
1811 | 3cc62370 | bellard | return; \
|
1812 | 3cc62370 | bellard | } \ |
1813 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1814 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
|
1815 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1816 | 4ecc3190 | bellard | gen_op_f##op(); \ |
1817 | 4ecc3190 | bellard | if (isfloat) { \
|
1818 | 4ecc3190 | bellard | gen_op_frsp(); \ |
1819 | 4ecc3190 | bellard | } \ |
1820 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1821 | 7c58044c | j_mayer | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1822 | 9a64fbe4 | bellard | } |
1823 | 7c58044c | j_mayer | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
1824 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
1825 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
1826 | 9a64fbe4 | bellard | |
1827 | 7c58044c | j_mayer | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1828 | 7c58044c | j_mayer | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ |
1829 | 9a64fbe4 | bellard | { \ |
1830 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1831 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
1832 | 3cc62370 | bellard | return; \
|
1833 | 3cc62370 | bellard | } \ |
1834 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
|
1835 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
|
1836 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1837 | 4ecc3190 | bellard | gen_op_f##op(); \ |
1838 | 4ecc3190 | bellard | if (isfloat) { \
|
1839 | 4ecc3190 | bellard | gen_op_frsp(); \ |
1840 | 4ecc3190 | bellard | } \ |
1841 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1842 | 7c58044c | j_mayer | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1843 | 9a64fbe4 | bellard | } |
1844 | 7c58044c | j_mayer | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
1845 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
1846 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
1847 | 9a64fbe4 | bellard | |
1848 | 7c58044c | j_mayer | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
1849 | a750fc0b | j_mayer | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ |
1850 | 9a64fbe4 | bellard | { \ |
1851 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1852 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
1853 | 3cc62370 | bellard | return; \
|
1854 | 3cc62370 | bellard | } \ |
1855 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
1856 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1857 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
1858 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1859 | 7c58044c | j_mayer | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1860 | 79aceca5 | bellard | } |
1861 | 79aceca5 | bellard | |
1862 | 7c58044c | j_mayer | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
1863 | a750fc0b | j_mayer | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ |
1864 | 9a64fbe4 | bellard | { \ |
1865 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1866 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
1867 | 3cc62370 | bellard | return; \
|
1868 | 3cc62370 | bellard | } \ |
1869 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
|
1870 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1871 | 9a64fbe4 | bellard | gen_op_f##name(); \ |
1872 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
1873 | 7c58044c | j_mayer | gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
|
1874 | 79aceca5 | bellard | } |
1875 | 79aceca5 | bellard | |
1876 | 9a64fbe4 | bellard | /* fadd - fadds */
|
1877 | 7c58044c | j_mayer | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
1878 | 4ecc3190 | bellard | /* fdiv - fdivs */
|
1879 | 7c58044c | j_mayer | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
1880 | 4ecc3190 | bellard | /* fmul - fmuls */
|
1881 | 7c58044c | j_mayer | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
1882 | 79aceca5 | bellard | |
1883 | d7e4b87e | j_mayer | /* fre */
|
1884 | 7c58044c | j_mayer | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
1885 | d7e4b87e | j_mayer | |
1886 | a750fc0b | j_mayer | /* fres */
|
1887 | 7c58044c | j_mayer | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
1888 | 79aceca5 | bellard | |
1889 | a750fc0b | j_mayer | /* frsqrte */
|
1890 | 7c58044c | j_mayer | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
1891 | 7c58044c | j_mayer | |
1892 | 7c58044c | j_mayer | /* frsqrtes */
|
1893 | 7c58044c | j_mayer | static always_inline void gen_op_frsqrtes (void) |
1894 | 7c58044c | j_mayer | { |
1895 | 7c58044c | j_mayer | gen_op_frsqrte(); |
1896 | 7c58044c | j_mayer | gen_op_frsp(); |
1897 | 7c58044c | j_mayer | } |
1898 | 1b413d55 | j_mayer | GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES); |
1899 | 79aceca5 | bellard | |
1900 | a750fc0b | j_mayer | /* fsel */
|
1901 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
1902 | 4ecc3190 | bellard | /* fsub - fsubs */
|
1903 | 7c58044c | j_mayer | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
1904 | 79aceca5 | bellard | /* Optional: */
|
1905 | 79aceca5 | bellard | /* fsqrt */
|
1906 | a750fc0b | j_mayer | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
1907 | c7d344af | bellard | { |
1908 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
1909 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
1910 | c7d344af | bellard | return;
|
1911 | c7d344af | bellard | } |
1912 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
1913 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
1914 | c7d344af | bellard | gen_op_fsqrt(); |
1915 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
1916 | 7c58044c | j_mayer | gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
1917 | c7d344af | bellard | } |
1918 | 79aceca5 | bellard | |
1919 | a750fc0b | j_mayer | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) |
1920 | 79aceca5 | bellard | { |
1921 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
1922 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
1923 | 3cc62370 | bellard | return;
|
1924 | 3cc62370 | bellard | } |
1925 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
1926 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
1927 | 4ecc3190 | bellard | gen_op_fsqrt(); |
1928 | 4ecc3190 | bellard | gen_op_frsp(); |
1929 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
1930 | 7c58044c | j_mayer | gen_compute_fprf(1, Rc(ctx->opcode) != 0); |
1931 | 79aceca5 | bellard | } |
1932 | 79aceca5 | bellard | |
1933 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
1934 | 4ecc3190 | bellard | /* fmadd - fmadds */
|
1935 | 7c58044c | j_mayer | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
1936 | 4ecc3190 | bellard | /* fmsub - fmsubs */
|
1937 | 7c58044c | j_mayer | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
1938 | 4ecc3190 | bellard | /* fnmadd - fnmadds */
|
1939 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
1940 | 4ecc3190 | bellard | /* fnmsub - fnmsubs */
|
1941 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
1942 | 79aceca5 | bellard | |
1943 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
1944 | 79aceca5 | bellard | /* fctiw */
|
1945 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
1946 | 79aceca5 | bellard | /* fctiwz */
|
1947 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
1948 | 79aceca5 | bellard | /* frsp */
|
1949 | 7c58044c | j_mayer | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
1950 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
1951 | 426613db | j_mayer | /* fcfid */
|
1952 | 7c58044c | j_mayer | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
1953 | 426613db | j_mayer | /* fctid */
|
1954 | 7c58044c | j_mayer | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
1955 | 426613db | j_mayer | /* fctidz */
|
1956 | 7c58044c | j_mayer | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
1957 | 426613db | j_mayer | #endif
|
1958 | 79aceca5 | bellard | |
1959 | d7e4b87e | j_mayer | /* frin */
|
1960 | 7c58044c | j_mayer | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
1961 | d7e4b87e | j_mayer | /* friz */
|
1962 | 7c58044c | j_mayer | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
1963 | d7e4b87e | j_mayer | /* frip */
|
1964 | 7c58044c | j_mayer | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
1965 | d7e4b87e | j_mayer | /* frim */
|
1966 | 7c58044c | j_mayer | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
1967 | d7e4b87e | j_mayer | |
1968 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
1969 | 79aceca5 | bellard | /* fcmpo */
|
1970 | 76a66253 | j_mayer | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
1971 | 79aceca5 | bellard | { |
1972 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
1973 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
1974 | 3cc62370 | bellard | return;
|
1975 | 3cc62370 | bellard | } |
1976 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
1977 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
1978 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
1979 | 9a64fbe4 | bellard | gen_op_fcmpo(); |
1980 | 9a64fbe4 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1981 | 7c58044c | j_mayer | gen_op_float_check_status(); |
1982 | 79aceca5 | bellard | } |
1983 | 79aceca5 | bellard | |
1984 | 79aceca5 | bellard | /* fcmpu */
|
1985 | 76a66253 | j_mayer | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
1986 | 79aceca5 | bellard | { |
1987 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
1988 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
1989 | 3cc62370 | bellard | return;
|
1990 | 3cc62370 | bellard | } |
1991 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
|
1992 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
|
1993 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
1994 | 9a64fbe4 | bellard | gen_op_fcmpu(); |
1995 | 9a64fbe4 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
1996 | 7c58044c | j_mayer | gen_op_float_check_status(); |
1997 | 79aceca5 | bellard | } |
1998 | 79aceca5 | bellard | |
1999 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
2000 | 9a64fbe4 | bellard | /* fabs */
|
2001 | 7c58044c | j_mayer | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
2002 | 7c58044c | j_mayer | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
2003 | 9a64fbe4 | bellard | |
2004 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
2005 | 7c58044c | j_mayer | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
2006 | 9a64fbe4 | bellard | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
2007 | 9a64fbe4 | bellard | { |
2008 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2009 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2010 | 3cc62370 | bellard | return;
|
2011 | 3cc62370 | bellard | } |
2012 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
2013 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
2014 | 7c58044c | j_mayer | gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
2015 | 9a64fbe4 | bellard | } |
2016 | 9a64fbe4 | bellard | |
2017 | 9a64fbe4 | bellard | /* fnabs */
|
2018 | 7c58044c | j_mayer | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
2019 | 7c58044c | j_mayer | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
2020 | 9a64fbe4 | bellard | /* fneg */
|
2021 | 7c58044c | j_mayer | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
2022 | 7c58044c | j_mayer | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
2023 | 9a64fbe4 | bellard | |
2024 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
2025 | 79aceca5 | bellard | /* mcrfs */
|
2026 | 79aceca5 | bellard | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
2027 | 79aceca5 | bellard | { |
2028 | 7c58044c | j_mayer | int bfa;
|
2029 | 7c58044c | j_mayer | |
2030 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2031 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2032 | 3cc62370 | bellard | return;
|
2033 | 3cc62370 | bellard | } |
2034 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2035 | 7c58044c | j_mayer | bfa = 4 * (7 - crfS(ctx->opcode)); |
2036 | 7c58044c | j_mayer | gen_op_load_fpscr_T0(bfa); |
2037 | fb0eaffc | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
2038 | 7c58044c | j_mayer | gen_op_fpscr_resetbit(~(0xF << bfa));
|
2039 | 79aceca5 | bellard | } |
2040 | 79aceca5 | bellard | |
2041 | 79aceca5 | bellard | /* mffs */
|
2042 | 79aceca5 | bellard | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
2043 | 79aceca5 | bellard | { |
2044 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2045 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2046 | 3cc62370 | bellard | return;
|
2047 | 3cc62370 | bellard | } |
2048 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2049 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2050 | 7c58044c | j_mayer | gen_op_load_fpscr_FT0(); |
2051 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
2052 | 7c58044c | j_mayer | gen_compute_fprf(0, Rc(ctx->opcode) != 0); |
2053 | 79aceca5 | bellard | } |
2054 | 79aceca5 | bellard | |
2055 | 79aceca5 | bellard | /* mtfsb0 */
|
2056 | 79aceca5 | bellard | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
2057 | 79aceca5 | bellard | { |
2058 | fb0eaffc | bellard | uint8_t crb; |
2059 | 3b46e624 | ths | |
2060 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2061 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2062 | 3cc62370 | bellard | return;
|
2063 | 3cc62370 | bellard | } |
2064 | 7c58044c | j_mayer | crb = 32 - (crbD(ctx->opcode) >> 2); |
2065 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2066 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2067 | 7c58044c | j_mayer | if (likely(crb != 30 && crb != 29)) |
2068 | 7c58044c | j_mayer | gen_op_fpscr_resetbit(~(1 << crb));
|
2069 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2070 | 7c58044c | j_mayer | gen_op_load_fpcc(); |
2071 | 7c58044c | j_mayer | gen_op_set_Rc0(); |
2072 | 7c58044c | j_mayer | } |
2073 | 79aceca5 | bellard | } |
2074 | 79aceca5 | bellard | |
2075 | 79aceca5 | bellard | /* mtfsb1 */
|
2076 | 79aceca5 | bellard | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
2077 | 79aceca5 | bellard | { |
2078 | fb0eaffc | bellard | uint8_t crb; |
2079 | 3b46e624 | ths | |
2080 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2081 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2082 | 3cc62370 | bellard | return;
|
2083 | 3cc62370 | bellard | } |
2084 | 7c58044c | j_mayer | crb = 32 - (crbD(ctx->opcode) >> 2); |
2085 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2086 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2087 | 7c58044c | j_mayer | /* XXX: we pretend we can only do IEEE floating-point computations */
|
2088 | 7c58044c | j_mayer | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
|
2089 | 7c58044c | j_mayer | gen_op_fpscr_setbit(crb); |
2090 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2091 | 7c58044c | j_mayer | gen_op_load_fpcc(); |
2092 | 7c58044c | j_mayer | gen_op_set_Rc0(); |
2093 | 7c58044c | j_mayer | } |
2094 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2095 | 7c58044c | j_mayer | gen_op_float_check_status(); |
2096 | 79aceca5 | bellard | } |
2097 | 79aceca5 | bellard | |
2098 | 79aceca5 | bellard | /* mtfsf */
|
2099 | 79aceca5 | bellard | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
2100 | 79aceca5 | bellard | { |
2101 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2102 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2103 | 3cc62370 | bellard | return;
|
2104 | 3cc62370 | bellard | } |
2105 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2106 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
|
2107 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2108 | 28b6751f | bellard | gen_op_store_fpscr(FM(ctx->opcode)); |
2109 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2110 | 7c58044c | j_mayer | gen_op_load_fpcc(); |
2111 | 7c58044c | j_mayer | gen_op_set_Rc0(); |
2112 | 7c58044c | j_mayer | } |
2113 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2114 | 7c58044c | j_mayer | gen_op_float_check_status(); |
2115 | 79aceca5 | bellard | } |
2116 | 79aceca5 | bellard | |
2117 | 79aceca5 | bellard | /* mtfsfi */
|
2118 | 79aceca5 | bellard | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
2119 | 79aceca5 | bellard | { |
2120 | 7c58044c | j_mayer | int bf, sh;
|
2121 | 7c58044c | j_mayer | |
2122 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2123 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); |
2124 | 3cc62370 | bellard | return;
|
2125 | 3cc62370 | bellard | } |
2126 | 7c58044c | j_mayer | bf = crbD(ctx->opcode) >> 2;
|
2127 | 7c58044c | j_mayer | sh = 7 - bf;
|
2128 | 7c58044c | j_mayer | gen_optimize_fprf(); |
2129 | 7c58044c | j_mayer | gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
|
2130 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2131 | 7c58044c | j_mayer | gen_op_store_fpscr(1 << sh);
|
2132 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2133 | 7c58044c | j_mayer | gen_op_load_fpcc(); |
2134 | 7c58044c | j_mayer | gen_op_set_Rc0(); |
2135 | 7c58044c | j_mayer | } |
2136 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2137 | 7c58044c | j_mayer | gen_op_float_check_status(); |
2138 | 79aceca5 | bellard | } |
2139 | 79aceca5 | bellard | |
2140 | 76a66253 | j_mayer | /*** Addressing modes ***/
|
2141 | 76a66253 | j_mayer | /* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2142 | b068d6a7 | j_mayer | static always_inline void gen_addr_imm_index (DisasContext *ctx, |
2143 | b068d6a7 | j_mayer | target_long maskl) |
2144 | 76a66253 | j_mayer | { |
2145 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
2146 | 76a66253 | j_mayer | |
2147 | be147d08 | j_mayer | simm &= ~maskl; |
2148 | 76a66253 | j_mayer | if (rA(ctx->opcode) == 0) { |
2149 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[0], simm);
|
2150 | 76a66253 | j_mayer | } else {
|
2151 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2152 | 76a66253 | j_mayer | if (likely(simm != 0)) |
2153 | 76a66253 | j_mayer | gen_op_addi(simm); |
2154 | 76a66253 | j_mayer | } |
2155 | a496775f | j_mayer | #ifdef DEBUG_MEMORY_ACCESSES
|
2156 | 6676f424 | aurel32 | gen_op_print_mem_EA(); |
2157 | a496775f | j_mayer | #endif
|
2158 | 76a66253 | j_mayer | } |
2159 | 76a66253 | j_mayer | |
2160 | b068d6a7 | j_mayer | static always_inline void gen_addr_reg_index (DisasContext *ctx) |
2161 | 76a66253 | j_mayer | { |
2162 | 76a66253 | j_mayer | if (rA(ctx->opcode) == 0) { |
2163 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
2164 | 76a66253 | j_mayer | } else {
|
2165 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2166 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
2167 | 76a66253 | j_mayer | gen_op_add(); |
2168 | 76a66253 | j_mayer | } |
2169 | a496775f | j_mayer | #ifdef DEBUG_MEMORY_ACCESSES
|
2170 | 6676f424 | aurel32 | gen_op_print_mem_EA(); |
2171 | a496775f | j_mayer | #endif
|
2172 | 76a66253 | j_mayer | } |
2173 | 76a66253 | j_mayer | |
2174 | b068d6a7 | j_mayer | static always_inline void gen_addr_register (DisasContext *ctx) |
2175 | 76a66253 | j_mayer | { |
2176 | 76a66253 | j_mayer | if (rA(ctx->opcode) == 0) { |
2177 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[0], 0); |
2178 | 76a66253 | j_mayer | } else {
|
2179 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
2180 | 76a66253 | j_mayer | } |
2181 | a496775f | j_mayer | #ifdef DEBUG_MEMORY_ACCESSES
|
2182 | 6676f424 | aurel32 | gen_op_print_mem_EA(); |
2183 | a496775f | j_mayer | #endif
|
2184 | 76a66253 | j_mayer | } |
2185 | 76a66253 | j_mayer | |
2186 | 7863667f | j_mayer | #if defined(TARGET_PPC64)
|
2187 | 7863667f | j_mayer | #define _GEN_MEM_FUNCS(name, mode) \
|
2188 | 7863667f | j_mayer | &gen_op_##name##_##mode, \ |
2189 | 7863667f | j_mayer | &gen_op_##name##_le_##mode, \ |
2190 | 7863667f | j_mayer | &gen_op_##name##_64_##mode, \ |
2191 | 7863667f | j_mayer | &gen_op_##name##_le_64_##mode |
2192 | 7863667f | j_mayer | #else
|
2193 | 7863667f | j_mayer | #define _GEN_MEM_FUNCS(name, mode) \
|
2194 | 7863667f | j_mayer | &gen_op_##name##_##mode, \ |
2195 | 7863667f | j_mayer | &gen_op_##name##_le_##mode |
2196 | 7863667f | j_mayer | #endif
|
2197 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
2198 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2199 | 7863667f | j_mayer | #define NB_MEM_FUNCS 4 |
2200 | d9bce9d9 | j_mayer | #else
|
2201 | 7863667f | j_mayer | #define NB_MEM_FUNCS 2 |
2202 | d9bce9d9 | j_mayer | #endif
|
2203 | 7863667f | j_mayer | #define GEN_MEM_FUNCS(name) \
|
2204 | 7863667f | j_mayer | _GEN_MEM_FUNCS(name, raw) |
2205 | 9a64fbe4 | bellard | #else
|
2206 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2207 | 7863667f | j_mayer | #define NB_MEM_FUNCS 12 |
2208 | 2857068e | j_mayer | #else
|
2209 | 7863667f | j_mayer | #define NB_MEM_FUNCS 6 |
2210 | 2857068e | j_mayer | #endif
|
2211 | 7863667f | j_mayer | #define GEN_MEM_FUNCS(name) \
|
2212 | 7863667f | j_mayer | _GEN_MEM_FUNCS(name, user), \ |
2213 | 7863667f | j_mayer | _GEN_MEM_FUNCS(name, kernel), \ |
2214 | 7863667f | j_mayer | _GEN_MEM_FUNCS(name, hypv) |
2215 | 7863667f | j_mayer | #endif
|
2216 | 7863667f | j_mayer | |
2217 | 7863667f | j_mayer | /*** Integer load ***/
|
2218 | 7863667f | j_mayer | #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
2219 | 111bfab3 | bellard | /* Byte access routine are endian safe */
|
2220 | 7863667f | j_mayer | #define gen_op_lbz_le_raw gen_op_lbz_raw
|
2221 | 7863667f | j_mayer | #define gen_op_lbz_le_user gen_op_lbz_user
|
2222 | 7863667f | j_mayer | #define gen_op_lbz_le_kernel gen_op_lbz_kernel
|
2223 | 7863667f | j_mayer | #define gen_op_lbz_le_hypv gen_op_lbz_hypv
|
2224 | 7863667f | j_mayer | #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
|
2225 | 2857068e | j_mayer | #define gen_op_lbz_le_64_user gen_op_lbz_64_user
|
2226 | d9bce9d9 | j_mayer | #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
|
2227 | 7863667f | j_mayer | #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
|
2228 | 7863667f | j_mayer | #define gen_op_stb_le_raw gen_op_stb_raw
|
2229 | 7863667f | j_mayer | #define gen_op_stb_le_user gen_op_stb_user
|
2230 | 7863667f | j_mayer | #define gen_op_stb_le_kernel gen_op_stb_kernel
|
2231 | 7863667f | j_mayer | #define gen_op_stb_le_hypv gen_op_stb_hypv
|
2232 | 7863667f | j_mayer | #define gen_op_stb_le_64_raw gen_op_stb_64_raw
|
2233 | 7863667f | j_mayer | #define gen_op_stb_le_64_user gen_op_stb_64_user
|
2234 | 7863667f | j_mayer | #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
|
2235 | 7863667f | j_mayer | #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
|
2236 | d9bce9d9 | j_mayer | #define OP_LD_TABLE(width) \
|
2237 | 7863667f | j_mayer | static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \ |
2238 | 7863667f | j_mayer | GEN_MEM_FUNCS(l##width), \ |
2239 | d9bce9d9 | j_mayer | }; |
2240 | d9bce9d9 | j_mayer | #define OP_ST_TABLE(width) \
|
2241 | 7863667f | j_mayer | static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \ |
2242 | 7863667f | j_mayer | GEN_MEM_FUNCS(st##width), \ |
2243 | d9bce9d9 | j_mayer | }; |
2244 | 9a64fbe4 | bellard | |
2245 | d9bce9d9 | j_mayer | #define GEN_LD(width, opc, type) \
|
2246 | d9bce9d9 | j_mayer | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2247 | 79aceca5 | bellard | { \ |
2248 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2249 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2250 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2251 | 79aceca5 | bellard | } |
2252 | 79aceca5 | bellard | |
2253 | d9bce9d9 | j_mayer | #define GEN_LDU(width, opc, type) \
|
2254 | d9bce9d9 | j_mayer | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2255 | 79aceca5 | bellard | { \ |
2256 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2257 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2258 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2259 | 9fddaa0c | bellard | return; \
|
2260 | 9a64fbe4 | bellard | } \ |
2261 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2262 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x03); \
|
2263 | 9d53c753 | j_mayer | else \
|
2264 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2265 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2266 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2267 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2268 | 79aceca5 | bellard | } |
2269 | 79aceca5 | bellard | |
2270 | d9bce9d9 | j_mayer | #define GEN_LDUX(width, opc2, opc3, type) \
|
2271 | d9bce9d9 | j_mayer | GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
2272 | 79aceca5 | bellard | { \ |
2273 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2274 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2275 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2276 | 9fddaa0c | bellard | return; \
|
2277 | 9a64fbe4 | bellard | } \ |
2278 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2279 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2280 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2281 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2282 | 79aceca5 | bellard | } |
2283 | 79aceca5 | bellard | |
2284 | d9bce9d9 | j_mayer | #define GEN_LDX(width, opc2, opc3, type) \
|
2285 | d9bce9d9 | j_mayer | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2286 | 79aceca5 | bellard | { \ |
2287 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2288 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2289 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \
|
2290 | 79aceca5 | bellard | } |
2291 | 79aceca5 | bellard | |
2292 | d9bce9d9 | j_mayer | #define GEN_LDS(width, op, type) \
|
2293 | 9a64fbe4 | bellard | OP_LD_TABLE(width); \ |
2294 | d9bce9d9 | j_mayer | GEN_LD(width, op | 0x20, type); \
|
2295 | d9bce9d9 | j_mayer | GEN_LDU(width, op | 0x21, type); \
|
2296 | d9bce9d9 | j_mayer | GEN_LDUX(width, 0x17, op | 0x01, type); \ |
2297 | d9bce9d9 | j_mayer | GEN_LDX(width, 0x17, op | 0x00, type) |
2298 | 79aceca5 | bellard | |
2299 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
2300 | d9bce9d9 | j_mayer | GEN_LDS(bz, 0x02, PPC_INTEGER);
|
2301 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
2302 | d9bce9d9 | j_mayer | GEN_LDS(ha, 0x0A, PPC_INTEGER);
|
2303 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
2304 | d9bce9d9 | j_mayer | GEN_LDS(hz, 0x08, PPC_INTEGER);
|
2305 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
2306 | d9bce9d9 | j_mayer | GEN_LDS(wz, 0x00, PPC_INTEGER);
|
2307 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2308 | d9bce9d9 | j_mayer | OP_LD_TABLE(wa); |
2309 | d9bce9d9 | j_mayer | OP_LD_TABLE(d); |
2310 | d9bce9d9 | j_mayer | /* lwaux */
|
2311 | d9bce9d9 | j_mayer | GEN_LDUX(wa, 0x15, 0x0B, PPC_64B); |
2312 | d9bce9d9 | j_mayer | /* lwax */
|
2313 | d9bce9d9 | j_mayer | GEN_LDX(wa, 0x15, 0x0A, PPC_64B); |
2314 | d9bce9d9 | j_mayer | /* ldux */
|
2315 | d9bce9d9 | j_mayer | GEN_LDUX(d, 0x15, 0x01, PPC_64B); |
2316 | d9bce9d9 | j_mayer | /* ldx */
|
2317 | d9bce9d9 | j_mayer | GEN_LDX(d, 0x15, 0x00, PPC_64B); |
2318 | d9bce9d9 | j_mayer | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) |
2319 | d9bce9d9 | j_mayer | { |
2320 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode)) {
|
2321 | d9bce9d9 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || |
2322 | d9bce9d9 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { |
2323 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
2324 | d9bce9d9 | j_mayer | return;
|
2325 | d9bce9d9 | j_mayer | } |
2326 | d9bce9d9 | j_mayer | } |
2327 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x03);
|
2328 | d9bce9d9 | j_mayer | if (ctx->opcode & 0x02) { |
2329 | d9bce9d9 | j_mayer | /* lwa (lwau is undefined) */
|
2330 | d9bce9d9 | j_mayer | op_ldst(lwa); |
2331 | d9bce9d9 | j_mayer | } else {
|
2332 | d9bce9d9 | j_mayer | /* ld - ldu */
|
2333 | d9bce9d9 | j_mayer | op_ldst(ld); |
2334 | d9bce9d9 | j_mayer | } |
2335 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2336 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode))
|
2337 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
2338 | d9bce9d9 | j_mayer | } |
2339 | be147d08 | j_mayer | /* lq */
|
2340 | be147d08 | j_mayer | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) |
2341 | be147d08 | j_mayer | { |
2342 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2343 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
2344 | be147d08 | j_mayer | #else
|
2345 | be147d08 | j_mayer | int ra, rd;
|
2346 | be147d08 | j_mayer | |
2347 | be147d08 | j_mayer | /* Restore CPU state */
|
2348 | be147d08 | j_mayer | if (unlikely(ctx->supervisor == 0)) { |
2349 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
2350 | be147d08 | j_mayer | return;
|
2351 | be147d08 | j_mayer | } |
2352 | be147d08 | j_mayer | ra = rA(ctx->opcode); |
2353 | be147d08 | j_mayer | rd = rD(ctx->opcode); |
2354 | be147d08 | j_mayer | if (unlikely((rd & 1) || rd == ra)) { |
2355 | be147d08 | j_mayer | GEN_EXCP_INVAL(ctx); |
2356 | be147d08 | j_mayer | return;
|
2357 | be147d08 | j_mayer | } |
2358 | be147d08 | j_mayer | if (unlikely(ctx->mem_idx & 1)) { |
2359 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2360 | be147d08 | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2361 | be147d08 | j_mayer | return;
|
2362 | be147d08 | j_mayer | } |
2363 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x0F);
|
2364 | be147d08 | j_mayer | op_ldst(ld); |
2365 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
|
2366 | be147d08 | j_mayer | gen_op_addi(8);
|
2367 | be147d08 | j_mayer | op_ldst(ld); |
2368 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); |
2369 | be147d08 | j_mayer | #endif
|
2370 | be147d08 | j_mayer | } |
2371 | d9bce9d9 | j_mayer | #endif
|
2372 | 79aceca5 | bellard | |
2373 | 79aceca5 | bellard | /*** Integer store ***/
|
2374 | d9bce9d9 | j_mayer | #define GEN_ST(width, opc, type) \
|
2375 | d9bce9d9 | j_mayer | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2376 | 79aceca5 | bellard | { \ |
2377 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2378 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2379 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2380 | 79aceca5 | bellard | } |
2381 | 79aceca5 | bellard | |
2382 | d9bce9d9 | j_mayer | #define GEN_STU(width, opc, type) \
|
2383 | d9bce9d9 | j_mayer | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2384 | 79aceca5 | bellard | { \ |
2385 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2386 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2387 | 9fddaa0c | bellard | return; \
|
2388 | 9a64fbe4 | bellard | } \ |
2389 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2390 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x03); \
|
2391 | 9d53c753 | j_mayer | else \
|
2392 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2393 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2394 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2395 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2396 | 79aceca5 | bellard | } |
2397 | 79aceca5 | bellard | |
2398 | d9bce9d9 | j_mayer | #define GEN_STUX(width, opc2, opc3, type) \
|
2399 | d9bce9d9 | j_mayer | GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ |
2400 | 79aceca5 | bellard | { \ |
2401 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2402 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2403 | 9fddaa0c | bellard | return; \
|
2404 | 9a64fbe4 | bellard | } \ |
2405 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2406 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2407 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2408 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2409 | 79aceca5 | bellard | } |
2410 | 79aceca5 | bellard | |
2411 | d9bce9d9 | j_mayer | #define GEN_STX(width, opc2, opc3, type) \
|
2412 | d9bce9d9 | j_mayer | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2413 | 79aceca5 | bellard | { \ |
2414 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2415 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \
|
2416 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2417 | 79aceca5 | bellard | } |
2418 | 79aceca5 | bellard | |
2419 | d9bce9d9 | j_mayer | #define GEN_STS(width, op, type) \
|
2420 | 9a64fbe4 | bellard | OP_ST_TABLE(width); \ |
2421 | d9bce9d9 | j_mayer | GEN_ST(width, op | 0x20, type); \
|
2422 | d9bce9d9 | j_mayer | GEN_STU(width, op | 0x21, type); \
|
2423 | d9bce9d9 | j_mayer | GEN_STUX(width, 0x17, op | 0x01, type); \ |
2424 | d9bce9d9 | j_mayer | GEN_STX(width, 0x17, op | 0x00, type) |
2425 | 79aceca5 | bellard | |
2426 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
2427 | d9bce9d9 | j_mayer | GEN_STS(b, 0x06, PPC_INTEGER);
|
2428 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
2429 | d9bce9d9 | j_mayer | GEN_STS(h, 0x0C, PPC_INTEGER);
|
2430 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
2431 | d9bce9d9 | j_mayer | GEN_STS(w, 0x04, PPC_INTEGER);
|
2432 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2433 | d9bce9d9 | j_mayer | OP_ST_TABLE(d); |
2434 | 426613db | j_mayer | GEN_STUX(d, 0x15, 0x05, PPC_64B); |
2435 | 426613db | j_mayer | GEN_STX(d, 0x15, 0x04, PPC_64B); |
2436 | be147d08 | j_mayer | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) |
2437 | d9bce9d9 | j_mayer | { |
2438 | be147d08 | j_mayer | int rs;
|
2439 | be147d08 | j_mayer | |
2440 | be147d08 | j_mayer | rs = rS(ctx->opcode); |
2441 | be147d08 | j_mayer | if ((ctx->opcode & 0x3) == 0x2) { |
2442 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2443 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
2444 | be147d08 | j_mayer | #else
|
2445 | be147d08 | j_mayer | /* stq */
|
2446 | be147d08 | j_mayer | if (unlikely(ctx->supervisor == 0)) { |
2447 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
2448 | be147d08 | j_mayer | return;
|
2449 | be147d08 | j_mayer | } |
2450 | be147d08 | j_mayer | if (unlikely(rs & 1)) { |
2451 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
2452 | d9bce9d9 | j_mayer | return;
|
2453 | d9bce9d9 | j_mayer | } |
2454 | be147d08 | j_mayer | if (unlikely(ctx->mem_idx & 1)) { |
2455 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2456 | be147d08 | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2457 | be147d08 | j_mayer | return;
|
2458 | be147d08 | j_mayer | } |
2459 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x03);
|
2460 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
|
2461 | be147d08 | j_mayer | op_ldst(std); |
2462 | be147d08 | j_mayer | gen_op_addi(8);
|
2463 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); |
2464 | be147d08 | j_mayer | op_ldst(std); |
2465 | be147d08 | j_mayer | #endif
|
2466 | be147d08 | j_mayer | } else {
|
2467 | be147d08 | j_mayer | /* std / stdu */
|
2468 | be147d08 | j_mayer | if (Rc(ctx->opcode)) {
|
2469 | be147d08 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { |
2470 | be147d08 | j_mayer | GEN_EXCP_INVAL(ctx); |
2471 | be147d08 | j_mayer | return;
|
2472 | be147d08 | j_mayer | } |
2473 | be147d08 | j_mayer | } |
2474 | be147d08 | j_mayer | gen_addr_imm_index(ctx, 0x03);
|
2475 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
|
2476 | be147d08 | j_mayer | op_ldst(std); |
2477 | be147d08 | j_mayer | if (Rc(ctx->opcode))
|
2478 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
2479 | d9bce9d9 | j_mayer | } |
2480 | d9bce9d9 | j_mayer | } |
2481 | d9bce9d9 | j_mayer | #endif
|
2482 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
2483 | 79aceca5 | bellard | /* lhbrx */
|
2484 | 9a64fbe4 | bellard | OP_LD_TABLE(hbr); |
2485 | d9bce9d9 | j_mayer | GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER); |
2486 | 79aceca5 | bellard | /* lwbrx */
|
2487 | 9a64fbe4 | bellard | OP_LD_TABLE(wbr); |
2488 | d9bce9d9 | j_mayer | GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER); |
2489 | 79aceca5 | bellard | /* sthbrx */
|
2490 | 9a64fbe4 | bellard | OP_ST_TABLE(hbr); |
2491 | d9bce9d9 | j_mayer | GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER); |
2492 | 79aceca5 | bellard | /* stwbrx */
|
2493 | 9a64fbe4 | bellard | OP_ST_TABLE(wbr); |
2494 | d9bce9d9 | j_mayer | GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER); |
2495 | 79aceca5 | bellard | |
2496 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
2497 | 111bfab3 | bellard | #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
2498 | 7863667f | j_mayer | static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
|
2499 | 7863667f | j_mayer | GEN_MEM_FUNCS(lmw), |
2500 | d9bce9d9 | j_mayer | }; |
2501 | 7863667f | j_mayer | static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
|
2502 | 7863667f | j_mayer | GEN_MEM_FUNCS(stmw), |
2503 | d9bce9d9 | j_mayer | }; |
2504 | 9a64fbe4 | bellard | |
2505 | 79aceca5 | bellard | /* lmw */
|
2506 | 79aceca5 | bellard | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
2507 | 79aceca5 | bellard | { |
2508 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2509 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2510 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
2511 | 9a64fbe4 | bellard | op_ldstm(lmw, rD(ctx->opcode)); |
2512 | 79aceca5 | bellard | } |
2513 | 79aceca5 | bellard | |
2514 | 79aceca5 | bellard | /* stmw */
|
2515 | 79aceca5 | bellard | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
2516 | 79aceca5 | bellard | { |
2517 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2518 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2519 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
2520 | 9a64fbe4 | bellard | op_ldstm(stmw, rS(ctx->opcode)); |
2521 | 79aceca5 | bellard | } |
2522 | 79aceca5 | bellard | |
2523 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
2524 | 9a64fbe4 | bellard | #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
2525 | 9a64fbe4 | bellard | #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
2526 | e7c24003 | j_mayer | /* string load & stores are by definition endian-safe */
|
2527 | e7c24003 | j_mayer | #define gen_op_lswi_le_raw gen_op_lswi_raw
|
2528 | e7c24003 | j_mayer | #define gen_op_lswi_le_user gen_op_lswi_user
|
2529 | e7c24003 | j_mayer | #define gen_op_lswi_le_kernel gen_op_lswi_kernel
|
2530 | e7c24003 | j_mayer | #define gen_op_lswi_le_hypv gen_op_lswi_hypv
|
2531 | e7c24003 | j_mayer | #define gen_op_lswi_le_64_raw gen_op_lswi_raw
|
2532 | e7c24003 | j_mayer | #define gen_op_lswi_le_64_user gen_op_lswi_user
|
2533 | e7c24003 | j_mayer | #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
|
2534 | e7c24003 | j_mayer | #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
|
2535 | 7863667f | j_mayer | static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
|
2536 | 7863667f | j_mayer | GEN_MEM_FUNCS(lswi), |
2537 | d9bce9d9 | j_mayer | }; |
2538 | e7c24003 | j_mayer | #define gen_op_lswx_le_raw gen_op_lswx_raw
|
2539 | e7c24003 | j_mayer | #define gen_op_lswx_le_user gen_op_lswx_user
|
2540 | e7c24003 | j_mayer | #define gen_op_lswx_le_kernel gen_op_lswx_kernel
|
2541 | e7c24003 | j_mayer | #define gen_op_lswx_le_hypv gen_op_lswx_hypv
|
2542 | e7c24003 | j_mayer | #define gen_op_lswx_le_64_raw gen_op_lswx_raw
|
2543 | e7c24003 | j_mayer | #define gen_op_lswx_le_64_user gen_op_lswx_user
|
2544 | e7c24003 | j_mayer | #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
|
2545 | e7c24003 | j_mayer | #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
|
2546 | 7863667f | j_mayer | static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
|
2547 | 7863667f | j_mayer | GEN_MEM_FUNCS(lswx), |
2548 | d9bce9d9 | j_mayer | }; |
2549 | e7c24003 | j_mayer | #define gen_op_stsw_le_raw gen_op_stsw_raw
|
2550 | e7c24003 | j_mayer | #define gen_op_stsw_le_user gen_op_stsw_user
|
2551 | e7c24003 | j_mayer | #define gen_op_stsw_le_kernel gen_op_stsw_kernel
|
2552 | e7c24003 | j_mayer | #define gen_op_stsw_le_hypv gen_op_stsw_hypv
|
2553 | e7c24003 | j_mayer | #define gen_op_stsw_le_64_raw gen_op_stsw_raw
|
2554 | e7c24003 | j_mayer | #define gen_op_stsw_le_64_user gen_op_stsw_user
|
2555 | e7c24003 | j_mayer | #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
|
2556 | e7c24003 | j_mayer | #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
|
2557 | 7863667f | j_mayer | static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
|
2558 | 7863667f | j_mayer | GEN_MEM_FUNCS(stsw), |
2559 | 9a64fbe4 | bellard | }; |
2560 | 9a64fbe4 | bellard | |
2561 | 79aceca5 | bellard | /* lswi */
|
2562 | 3fc6c082 | bellard | /* PowerPC32 specification says we must generate an exception if
|
2563 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
2564 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
2565 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
2566 | 9a64fbe4 | bellard | */
|
2567 | 05332d70 | j_mayer | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) |
2568 | 79aceca5 | bellard | { |
2569 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
2570 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
2571 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
2572 | 79aceca5 | bellard | int nr;
|
2573 | 79aceca5 | bellard | |
2574 | 79aceca5 | bellard | if (nb == 0) |
2575 | 79aceca5 | bellard | nb = 32;
|
2576 | 79aceca5 | bellard | nr = nb / 4;
|
2577 | 76a66253 | j_mayer | if (unlikely(((start + nr) > 32 && |
2578 | 76a66253 | j_mayer | start <= ra && (start + nr - 32) > ra) ||
|
2579 | 76a66253 | j_mayer | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
2580 | e1833e1f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
2581 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); |
2582 | 9fddaa0c | bellard | return;
|
2583 | 297d8e62 | bellard | } |
2584 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2585 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2586 | 76a66253 | j_mayer | gen_addr_register(ctx); |
2587 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], nb);
|
2588 | 9a64fbe4 | bellard | op_ldsts(lswi, start); |
2589 | 79aceca5 | bellard | } |
2590 | 79aceca5 | bellard | |
2591 | 79aceca5 | bellard | /* lswx */
|
2592 | 05332d70 | j_mayer | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) |
2593 | 79aceca5 | bellard | { |
2594 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
2595 | 9a64fbe4 | bellard | int rb = rB(ctx->opcode);
|
2596 | 9a64fbe4 | bellard | |
2597 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2598 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2599 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
2600 | 9a64fbe4 | bellard | if (ra == 0) { |
2601 | 9a64fbe4 | bellard | ra = rb; |
2602 | 79aceca5 | bellard | } |
2603 | 9a64fbe4 | bellard | gen_op_load_xer_bc(); |
2604 | 9a64fbe4 | bellard | op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
2605 | 79aceca5 | bellard | } |
2606 | 79aceca5 | bellard | |
2607 | 79aceca5 | bellard | /* stswi */
|
2608 | 05332d70 | j_mayer | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) |
2609 | 79aceca5 | bellard | { |
2610 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
2611 | 4b3686fa | bellard | |
2612 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2613 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2614 | 76a66253 | j_mayer | gen_addr_register(ctx); |
2615 | 4b3686fa | bellard | if (nb == 0) |
2616 | 4b3686fa | bellard | nb = 32;
|
2617 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], nb);
|
2618 | 9a64fbe4 | bellard | op_ldsts(stsw, rS(ctx->opcode)); |
2619 | 79aceca5 | bellard | } |
2620 | 79aceca5 | bellard | |
2621 | 79aceca5 | bellard | /* stswx */
|
2622 | 05332d70 | j_mayer | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING) |
2623 | 79aceca5 | bellard | { |
2624 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2625 | 5fafdf24 | ths | gen_update_nip(ctx, ctx->nip - 4);
|
2626 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
2627 | 76a66253 | j_mayer | gen_op_load_xer_bc(); |
2628 | 9a64fbe4 | bellard | op_ldsts(stsw, rS(ctx->opcode)); |
2629 | 79aceca5 | bellard | } |
2630 | 79aceca5 | bellard | |
2631 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
2632 | 79aceca5 | bellard | /* eieio */
|
2633 | 0db1b20e | j_mayer | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO) |
2634 | 79aceca5 | bellard | { |
2635 | 79aceca5 | bellard | } |
2636 | 79aceca5 | bellard | |
2637 | 79aceca5 | bellard | /* isync */
|
2638 | 0db1b20e | j_mayer | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) |
2639 | 79aceca5 | bellard | { |
2640 | e1833e1f | j_mayer | GEN_STOP(ctx); |
2641 | 79aceca5 | bellard | } |
2642 | 79aceca5 | bellard | |
2643 | 111bfab3 | bellard | #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
|
2644 | 111bfab3 | bellard | #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
|
2645 | 7863667f | j_mayer | static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
|
2646 | 7863667f | j_mayer | GEN_MEM_FUNCS(lwarx), |
2647 | 111bfab3 | bellard | }; |
2648 | 7863667f | j_mayer | static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
|
2649 | 7863667f | j_mayer | GEN_MEM_FUNCS(stwcx), |
2650 | 985a19d6 | bellard | }; |
2651 | 9a64fbe4 | bellard | |
2652 | 111bfab3 | bellard | /* lwarx */
|
2653 | 76a66253 | j_mayer | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) |
2654 | 79aceca5 | bellard | { |
2655 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2656 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2657 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
2658 | 985a19d6 | bellard | op_lwarx(); |
2659 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2660 | 79aceca5 | bellard | } |
2661 | 79aceca5 | bellard | |
2662 | 79aceca5 | bellard | /* stwcx. */
|
2663 | c7697e1f | j_mayer | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
2664 | 79aceca5 | bellard | { |
2665 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2666 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2667 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
2668 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
2669 | 9a64fbe4 | bellard | op_stwcx(); |
2670 | 79aceca5 | bellard | } |
2671 | 79aceca5 | bellard | |
2672 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
2673 | 426613db | j_mayer | #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
|
2674 | 426613db | j_mayer | #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
|
2675 | 7863667f | j_mayer | static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
|
2676 | 7863667f | j_mayer | GEN_MEM_FUNCS(ldarx), |
2677 | 426613db | j_mayer | }; |
2678 | 7863667f | j_mayer | static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
|
2679 | 7863667f | j_mayer | GEN_MEM_FUNCS(stdcx), |
2680 | 426613db | j_mayer | }; |
2681 | 426613db | j_mayer | |
2682 | 426613db | j_mayer | /* ldarx */
|
2683 | a750fc0b | j_mayer | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) |
2684 | 426613db | j_mayer | { |
2685 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2686 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2687 | 426613db | j_mayer | gen_addr_reg_index(ctx); |
2688 | 426613db | j_mayer | op_ldarx(); |
2689 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
|
2690 | 426613db | j_mayer | } |
2691 | 426613db | j_mayer | |
2692 | 426613db | j_mayer | /* stdcx. */
|
2693 | c7697e1f | j_mayer | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) |
2694 | 426613db | j_mayer | { |
2695 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2696 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2697 | 426613db | j_mayer | gen_addr_reg_index(ctx); |
2698 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
2699 | 426613db | j_mayer | op_stdcx(); |
2700 | 426613db | j_mayer | } |
2701 | 426613db | j_mayer | #endif /* defined(TARGET_PPC64) */ |
2702 | 426613db | j_mayer | |
2703 | 79aceca5 | bellard | /* sync */
|
2704 | a902d886 | j_mayer | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC) |
2705 | 79aceca5 | bellard | { |
2706 | 79aceca5 | bellard | } |
2707 | 79aceca5 | bellard | |
2708 | 0db1b20e | j_mayer | /* wait */
|
2709 | 0db1b20e | j_mayer | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT) |
2710 | 0db1b20e | j_mayer | { |
2711 | 0db1b20e | j_mayer | /* Stop translation, as the CPU is supposed to sleep from now */
|
2712 | be147d08 | j_mayer | gen_op_wait(); |
2713 | be147d08 | j_mayer | GEN_EXCP(ctx, EXCP_HLT, 1);
|
2714 | 0db1b20e | j_mayer | } |
2715 | 0db1b20e | j_mayer | |
2716 | 79aceca5 | bellard | /*** Floating-point load ***/
|
2717 | 477023a6 | j_mayer | #define GEN_LDF(width, opc, type) \
|
2718 | 477023a6 | j_mayer | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2719 | 79aceca5 | bellard | { \ |
2720 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2721 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2722 | 4ecc3190 | bellard | return; \
|
2723 | 4ecc3190 | bellard | } \ |
2724 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2725 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2726 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2727 | 79aceca5 | bellard | } |
2728 | 79aceca5 | bellard | |
2729 | 477023a6 | j_mayer | #define GEN_LDUF(width, opc, type) \
|
2730 | 477023a6 | j_mayer | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2731 | 79aceca5 | bellard | { \ |
2732 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2733 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2734 | 4ecc3190 | bellard | return; \
|
2735 | 4ecc3190 | bellard | } \ |
2736 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2737 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2738 | 9fddaa0c | bellard | return; \
|
2739 | 9a64fbe4 | bellard | } \ |
2740 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2741 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2742 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2743 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2744 | 79aceca5 | bellard | } |
2745 | 79aceca5 | bellard | |
2746 | 477023a6 | j_mayer | #define GEN_LDUXF(width, opc, type) \
|
2747 | 477023a6 | j_mayer | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
2748 | 79aceca5 | bellard | { \ |
2749 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2750 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2751 | 4ecc3190 | bellard | return; \
|
2752 | 4ecc3190 | bellard | } \ |
2753 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2754 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2755 | 9fddaa0c | bellard | return; \
|
2756 | 9a64fbe4 | bellard | } \ |
2757 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2758 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2759 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2760 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2761 | 79aceca5 | bellard | } |
2762 | 79aceca5 | bellard | |
2763 | 477023a6 | j_mayer | #define GEN_LDXF(width, opc2, opc3, type) \
|
2764 | 477023a6 | j_mayer | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2765 | 79aceca5 | bellard | { \ |
2766 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2767 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2768 | 4ecc3190 | bellard | return; \
|
2769 | 4ecc3190 | bellard | } \ |
2770 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2771 | 9a64fbe4 | bellard | op_ldst(l##width); \ |
2772 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
|
2773 | 79aceca5 | bellard | } |
2774 | 79aceca5 | bellard | |
2775 | 477023a6 | j_mayer | #define GEN_LDFS(width, op, type) \
|
2776 | 9a64fbe4 | bellard | OP_LD_TABLE(width); \ |
2777 | 477023a6 | j_mayer | GEN_LDF(width, op | 0x20, type); \
|
2778 | 477023a6 | j_mayer | GEN_LDUF(width, op | 0x21, type); \
|
2779 | 477023a6 | j_mayer | GEN_LDUXF(width, op | 0x01, type); \
|
2780 | 477023a6 | j_mayer | GEN_LDXF(width, 0x17, op | 0x00, type) |
2781 | 79aceca5 | bellard | |
2782 | 79aceca5 | bellard | /* lfd lfdu lfdux lfdx */
|
2783 | 477023a6 | j_mayer | GEN_LDFS(fd, 0x12, PPC_FLOAT);
|
2784 | 79aceca5 | bellard | /* lfs lfsu lfsux lfsx */
|
2785 | 477023a6 | j_mayer | GEN_LDFS(fs, 0x10, PPC_FLOAT);
|
2786 | 79aceca5 | bellard | |
2787 | 79aceca5 | bellard | /*** Floating-point store ***/
|
2788 | 477023a6 | j_mayer | #define GEN_STF(width, opc, type) \
|
2789 | 477023a6 | j_mayer | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2790 | 79aceca5 | bellard | { \ |
2791 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2792 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2793 | 4ecc3190 | bellard | return; \
|
2794 | 4ecc3190 | bellard | } \ |
2795 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2796 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2797 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2798 | 79aceca5 | bellard | } |
2799 | 79aceca5 | bellard | |
2800 | 477023a6 | j_mayer | #define GEN_STUF(width, opc, type) \
|
2801 | 477023a6 | j_mayer | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ |
2802 | 79aceca5 | bellard | { \ |
2803 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2804 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2805 | 4ecc3190 | bellard | return; \
|
2806 | 4ecc3190 | bellard | } \ |
2807 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2808 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2809 | 9fddaa0c | bellard | return; \
|
2810 | 9a64fbe4 | bellard | } \ |
2811 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0); \
|
2812 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2813 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2814 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2815 | 79aceca5 | bellard | } |
2816 | 79aceca5 | bellard | |
2817 | 477023a6 | j_mayer | #define GEN_STUXF(width, opc, type) \
|
2818 | 477023a6 | j_mayer | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ |
2819 | 79aceca5 | bellard | { \ |
2820 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2821 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2822 | 4ecc3190 | bellard | return; \
|
2823 | 4ecc3190 | bellard | } \ |
2824 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2825 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); \ |
2826 | 9fddaa0c | bellard | return; \
|
2827 | 9a64fbe4 | bellard | } \ |
2828 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2829 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2830 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2831 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
|
2832 | 79aceca5 | bellard | } |
2833 | 79aceca5 | bellard | |
2834 | 477023a6 | j_mayer | #define GEN_STXF(width, opc2, opc3, type) \
|
2835 | 477023a6 | j_mayer | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ |
2836 | 79aceca5 | bellard | { \ |
2837 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2838 | e1833e1f | j_mayer | GEN_EXCP_NO_FP(ctx); \ |
2839 | 4ecc3190 | bellard | return; \
|
2840 | 4ecc3190 | bellard | } \ |
2841 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); \ |
2842 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
|
2843 | 9a64fbe4 | bellard | op_ldst(st##width); \ |
2844 | 79aceca5 | bellard | } |
2845 | 79aceca5 | bellard | |
2846 | 477023a6 | j_mayer | #define GEN_STFS(width, op, type) \
|
2847 | 9a64fbe4 | bellard | OP_ST_TABLE(width); \ |
2848 | 477023a6 | j_mayer | GEN_STF(width, op | 0x20, type); \
|
2849 | 477023a6 | j_mayer | GEN_STUF(width, op | 0x21, type); \
|
2850 | 477023a6 | j_mayer | GEN_STUXF(width, op | 0x01, type); \
|
2851 | 477023a6 | j_mayer | GEN_STXF(width, 0x17, op | 0x00, type) |
2852 | 79aceca5 | bellard | |
2853 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
2854 | 477023a6 | j_mayer | GEN_STFS(fd, 0x16, PPC_FLOAT);
|
2855 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
2856 | 477023a6 | j_mayer | GEN_STFS(fs, 0x14, PPC_FLOAT);
|
2857 | 79aceca5 | bellard | |
2858 | 79aceca5 | bellard | /* Optional: */
|
2859 | 79aceca5 | bellard | /* stfiwx */
|
2860 | 5b8105fa | j_mayer | OP_ST_TABLE(fiw); |
2861 | 5b8105fa | j_mayer | GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
2862 | 79aceca5 | bellard | |
2863 | 79aceca5 | bellard | /*** Branch ***/
|
2864 | b068d6a7 | j_mayer | static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
2865 | b068d6a7 | j_mayer | target_ulong dest) |
2866 | c1942362 | bellard | { |
2867 | c1942362 | bellard | TranslationBlock *tb; |
2868 | c1942362 | bellard | tb = ctx->tb; |
2869 | 57fec1fe | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
2870 | 8cbcb4fa | aurel32 | likely(!ctx->singlestep_enabled)) { |
2871 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
2872 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[1], dest);
|
2873 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2874 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
2875 | d9bce9d9 | j_mayer | gen_op_b_T1_64(); |
2876 | d9bce9d9 | j_mayer | else
|
2877 | d9bce9d9 | j_mayer | #endif
|
2878 | d9bce9d9 | j_mayer | gen_op_b_T1(); |
2879 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + n);
|
2880 | c1942362 | bellard | } else {
|
2881 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[1], dest);
|
2882 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2883 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
2884 | d9bce9d9 | j_mayer | gen_op_b_T1_64(); |
2885 | d9bce9d9 | j_mayer | else
|
2886 | d9bce9d9 | j_mayer | #endif
|
2887 | d9bce9d9 | j_mayer | gen_op_b_T1(); |
2888 | 8cbcb4fa | aurel32 | if (unlikely(ctx->singlestep_enabled)) {
|
2889 | 8cbcb4fa | aurel32 | if ((ctx->singlestep_enabled &
|
2890 | 8cbcb4fa | aurel32 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
2891 | 8cbcb4fa | aurel32 | ctx->exception == POWERPC_EXCP_BRANCH) { |
2892 | 8cbcb4fa | aurel32 | target_ulong tmp = ctx->nip; |
2893 | 8cbcb4fa | aurel32 | ctx->nip = dest; |
2894 | 8cbcb4fa | aurel32 | GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
|
2895 | 8cbcb4fa | aurel32 | ctx->nip = tmp; |
2896 | 8cbcb4fa | aurel32 | } |
2897 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
2898 | 8cbcb4fa | aurel32 | gen_update_nip(ctx, dest); |
2899 | 8cbcb4fa | aurel32 | gen_op_debug(); |
2900 | 8cbcb4fa | aurel32 | } |
2901 | 8cbcb4fa | aurel32 | } |
2902 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2903 | c1942362 | bellard | } |
2904 | c53be334 | bellard | } |
2905 | c53be334 | bellard | |
2906 | b068d6a7 | j_mayer | static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) |
2907 | e1833e1f | j_mayer | { |
2908 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
2909 | e1833e1f | j_mayer | if (ctx->sf_mode != 0 && (nip >> 32)) |
2910 | e1833e1f | j_mayer | gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
|
2911 | e1833e1f | j_mayer | else
|
2912 | e1833e1f | j_mayer | #endif
|
2913 | e1833e1f | j_mayer | gen_op_setlr(ctx->nip); |
2914 | e1833e1f | j_mayer | } |
2915 | e1833e1f | j_mayer | |
2916 | 79aceca5 | bellard | /* b ba bl bla */
|
2917 | 79aceca5 | bellard | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
2918 | 79aceca5 | bellard | { |
2919 | 76a66253 | j_mayer | target_ulong li, target; |
2920 | 38a64f9d | bellard | |
2921 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
2922 | 38a64f9d | bellard | /* sign extend LI */
|
2923 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
2924 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
2925 | d9bce9d9 | j_mayer | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
2926 | d9bce9d9 | j_mayer | else
|
2927 | 76a66253 | j_mayer | #endif
|
2928 | d9bce9d9 | j_mayer | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
2929 | 76a66253 | j_mayer | if (likely(AA(ctx->opcode) == 0)) |
2930 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
2931 | 79aceca5 | bellard | else
|
2932 | 9a64fbe4 | bellard | target = li; |
2933 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2934 | e1833e1f | j_mayer | if (!ctx->sf_mode)
|
2935 | e1833e1f | j_mayer | target = (uint32_t)target; |
2936 | d9bce9d9 | j_mayer | #endif
|
2937 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
2938 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
2939 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
2940 | 79aceca5 | bellard | } |
2941 | 79aceca5 | bellard | |
2942 | e98a6e40 | bellard | #define BCOND_IM 0 |
2943 | e98a6e40 | bellard | #define BCOND_LR 1 |
2944 | e98a6e40 | bellard | #define BCOND_CTR 2 |
2945 | e98a6e40 | bellard | |
2946 | b068d6a7 | j_mayer | static always_inline void gen_bcond (DisasContext *ctx, int type) |
2947 | d9bce9d9 | j_mayer | { |
2948 | 76a66253 | j_mayer | target_ulong target = 0;
|
2949 | 76a66253 | j_mayer | target_ulong li; |
2950 | d9bce9d9 | j_mayer | uint32_t bo = BO(ctx->opcode); |
2951 | d9bce9d9 | j_mayer | uint32_t bi = BI(ctx->opcode); |
2952 | d9bce9d9 | j_mayer | uint32_t mask; |
2953 | e98a6e40 | bellard | |
2954 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
2955 | e98a6e40 | bellard | if ((bo & 0x4) == 0) |
2956 | d9bce9d9 | j_mayer | gen_op_dec_ctr(); |
2957 | e98a6e40 | bellard | switch(type) {
|
2958 | e98a6e40 | bellard | case BCOND_IM:
|
2959 | 76a66253 | j_mayer | li = (target_long)((int16_t)(BD(ctx->opcode))); |
2960 | 76a66253 | j_mayer | if (likely(AA(ctx->opcode) == 0)) { |
2961 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
2962 | e98a6e40 | bellard | } else {
|
2963 | e98a6e40 | bellard | target = li; |
2964 | e98a6e40 | bellard | } |
2965 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
2966 | e1833e1f | j_mayer | if (!ctx->sf_mode)
|
2967 | e1833e1f | j_mayer | target = (uint32_t)target; |
2968 | e1833e1f | j_mayer | #endif
|
2969 | e98a6e40 | bellard | break;
|
2970 | e98a6e40 | bellard | case BCOND_CTR:
|
2971 | e98a6e40 | bellard | gen_op_movl_T1_ctr(); |
2972 | e98a6e40 | bellard | break;
|
2973 | e98a6e40 | bellard | default:
|
2974 | e98a6e40 | bellard | case BCOND_LR:
|
2975 | e98a6e40 | bellard | gen_op_movl_T1_lr(); |
2976 | e98a6e40 | bellard | break;
|
2977 | e98a6e40 | bellard | } |
2978 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
2979 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
2980 | e98a6e40 | bellard | if (bo & 0x10) { |
2981 | d9bce9d9 | j_mayer | /* No CR condition */
|
2982 | d9bce9d9 | j_mayer | switch (bo & 0x6) { |
2983 | d9bce9d9 | j_mayer | case 0: |
2984 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2985 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
2986 | d9bce9d9 | j_mayer | gen_op_test_ctr_64(); |
2987 | d9bce9d9 | j_mayer | else
|
2988 | d9bce9d9 | j_mayer | #endif
|
2989 | d9bce9d9 | j_mayer | gen_op_test_ctr(); |
2990 | d9bce9d9 | j_mayer | break;
|
2991 | d9bce9d9 | j_mayer | case 2: |
2992 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2993 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
2994 | d9bce9d9 | j_mayer | gen_op_test_ctrz_64(); |
2995 | d9bce9d9 | j_mayer | else
|
2996 | d9bce9d9 | j_mayer | #endif
|
2997 | d9bce9d9 | j_mayer | gen_op_test_ctrz(); |
2998 | e98a6e40 | bellard | break;
|
2999 | e98a6e40 | bellard | default:
|
3000 | d9bce9d9 | j_mayer | case 4: |
3001 | d9bce9d9 | j_mayer | case 6: |
3002 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3003 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3004 | 8cbcb4fa | aurel32 | return;
|
3005 | e98a6e40 | bellard | } else {
|
3006 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3007 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3008 | d9bce9d9 | j_mayer | gen_op_b_T1_64(); |
3009 | d9bce9d9 | j_mayer | else
|
3010 | d9bce9d9 | j_mayer | #endif
|
3011 | d9bce9d9 | j_mayer | gen_op_b_T1(); |
3012 | 056b05f8 | j_mayer | goto no_test;
|
3013 | e98a6e40 | bellard | } |
3014 | 056b05f8 | j_mayer | break;
|
3015 | e98a6e40 | bellard | } |
3016 | d9bce9d9 | j_mayer | } else {
|
3017 | d9bce9d9 | j_mayer | mask = 1 << (3 - (bi & 0x03)); |
3018 | d9bce9d9 | j_mayer | gen_op_load_crf_T0(bi >> 2);
|
3019 | d9bce9d9 | j_mayer | if (bo & 0x8) { |
3020 | d9bce9d9 | j_mayer | switch (bo & 0x6) { |
3021 | d9bce9d9 | j_mayer | case 0: |
3022 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3023 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3024 | d9bce9d9 | j_mayer | gen_op_test_ctr_true_64(mask); |
3025 | d9bce9d9 | j_mayer | else
|
3026 | d9bce9d9 | j_mayer | #endif
|
3027 | d9bce9d9 | j_mayer | gen_op_test_ctr_true(mask); |
3028 | d9bce9d9 | j_mayer | break;
|
3029 | d9bce9d9 | j_mayer | case 2: |
3030 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3031 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3032 | d9bce9d9 | j_mayer | gen_op_test_ctrz_true_64(mask); |
3033 | d9bce9d9 | j_mayer | else
|
3034 | d9bce9d9 | j_mayer | #endif
|
3035 | d9bce9d9 | j_mayer | gen_op_test_ctrz_true(mask); |
3036 | d9bce9d9 | j_mayer | break;
|
3037 | d9bce9d9 | j_mayer | default:
|
3038 | d9bce9d9 | j_mayer | case 4: |
3039 | d9bce9d9 | j_mayer | case 6: |
3040 | e98a6e40 | bellard | gen_op_test_true(mask); |
3041 | d9bce9d9 | j_mayer | break;
|
3042 | d9bce9d9 | j_mayer | } |
3043 | d9bce9d9 | j_mayer | } else {
|
3044 | d9bce9d9 | j_mayer | switch (bo & 0x6) { |
3045 | d9bce9d9 | j_mayer | case 0: |
3046 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3047 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3048 | d9bce9d9 | j_mayer | gen_op_test_ctr_false_64(mask); |
3049 | d9bce9d9 | j_mayer | else
|
3050 | d9bce9d9 | j_mayer | #endif
|
3051 | d9bce9d9 | j_mayer | gen_op_test_ctr_false(mask); |
3052 | 3b46e624 | ths | break;
|
3053 | d9bce9d9 | j_mayer | case 2: |
3054 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3055 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3056 | d9bce9d9 | j_mayer | gen_op_test_ctrz_false_64(mask); |
3057 | d9bce9d9 | j_mayer | else
|
3058 | d9bce9d9 | j_mayer | #endif
|
3059 | d9bce9d9 | j_mayer | gen_op_test_ctrz_false(mask); |
3060 | d9bce9d9 | j_mayer | break;
|
3061 | e98a6e40 | bellard | default:
|
3062 | d9bce9d9 | j_mayer | case 4: |
3063 | d9bce9d9 | j_mayer | case 6: |
3064 | e98a6e40 | bellard | gen_op_test_false(mask); |
3065 | d9bce9d9 | j_mayer | break;
|
3066 | d9bce9d9 | j_mayer | } |
3067 | d9bce9d9 | j_mayer | } |
3068 | d9bce9d9 | j_mayer | } |
3069 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3070 | c53be334 | bellard | int l1 = gen_new_label();
|
3071 | c53be334 | bellard | gen_op_jz_T0(l1); |
3072 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3073 | c53be334 | bellard | gen_set_label(l1); |
3074 | c1942362 | bellard | gen_goto_tb(ctx, 1, ctx->nip);
|
3075 | e98a6e40 | bellard | } else {
|
3076 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3077 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3078 | d9bce9d9 | j_mayer | gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
|
3079 | d9bce9d9 | j_mayer | else
|
3080 | d9bce9d9 | j_mayer | #endif
|
3081 | d9bce9d9 | j_mayer | gen_op_btest_T1(ctx->nip); |
3082 | 36081602 | j_mayer | no_test:
|
3083 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3084 | 8cbcb4fa | aurel32 | gen_update_nip(ctx, ctx->nip); |
3085 | 08e46e54 | j_mayer | gen_op_debug(); |
3086 | 8cbcb4fa | aurel32 | } |
3087 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3088 | 08e46e54 | j_mayer | } |
3089 | e98a6e40 | bellard | } |
3090 | e98a6e40 | bellard | |
3091 | e98a6e40 | bellard | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
3092 | 3b46e624 | ths | { |
3093 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
3094 | e98a6e40 | bellard | } |
3095 | e98a6e40 | bellard | |
3096 | e98a6e40 | bellard | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
3097 | 3b46e624 | ths | { |
3098 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
3099 | e98a6e40 | bellard | } |
3100 | e98a6e40 | bellard | |
3101 | e98a6e40 | bellard | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
3102 | 3b46e624 | ths | { |
3103 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
3104 | e98a6e40 | bellard | } |
3105 | 79aceca5 | bellard | |
3106 | 79aceca5 | bellard | /*** Condition register logical ***/
|
3107 | 79aceca5 | bellard | #define GEN_CRLOGIC(op, opc) \
|
3108 | 79aceca5 | bellard | GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
3109 | 79aceca5 | bellard | { \ |
3110 | fc0d441e | j_mayer | uint8_t bitmask; \ |
3111 | fc0d441e | j_mayer | int sh; \
|
3112 | 79aceca5 | bellard | gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
|
3113 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3114 | fc0d441e | j_mayer | if (sh > 0) \ |
3115 | fc0d441e | j_mayer | gen_op_srli_T0(sh); \ |
3116 | fc0d441e | j_mayer | else if (sh < 0) \ |
3117 | fc0d441e | j_mayer | gen_op_sli_T0(-sh); \ |
3118 | 79aceca5 | bellard | gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
|
3119 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3120 | fc0d441e | j_mayer | if (sh > 0) \ |
3121 | fc0d441e | j_mayer | gen_op_srli_T1(sh); \ |
3122 | fc0d441e | j_mayer | else if (sh < 0) \ |
3123 | fc0d441e | j_mayer | gen_op_sli_T1(-sh); \ |
3124 | 79aceca5 | bellard | gen_op_##op(); \ |
3125 | fc0d441e | j_mayer | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3126 | fc0d441e | j_mayer | gen_op_andi_T0(bitmask); \ |
3127 | 79aceca5 | bellard | gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
|
3128 | fc0d441e | j_mayer | gen_op_andi_T1(~bitmask); \ |
3129 | fc0d441e | j_mayer | gen_op_or(); \ |
3130 | fc0d441e | j_mayer | gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
|
3131 | 79aceca5 | bellard | } |
3132 | 79aceca5 | bellard | |
3133 | 79aceca5 | bellard | /* crand */
|
3134 | 76a66253 | j_mayer | GEN_CRLOGIC(and, 0x08);
|
3135 | 79aceca5 | bellard | /* crandc */
|
3136 | 76a66253 | j_mayer | GEN_CRLOGIC(andc, 0x04);
|
3137 | 79aceca5 | bellard | /* creqv */
|
3138 | 76a66253 | j_mayer | GEN_CRLOGIC(eqv, 0x09);
|
3139 | 79aceca5 | bellard | /* crnand */
|
3140 | 76a66253 | j_mayer | GEN_CRLOGIC(nand, 0x07);
|
3141 | 79aceca5 | bellard | /* crnor */
|
3142 | 76a66253 | j_mayer | GEN_CRLOGIC(nor, 0x01);
|
3143 | 79aceca5 | bellard | /* cror */
|
3144 | 76a66253 | j_mayer | GEN_CRLOGIC(or, 0x0E);
|
3145 | 79aceca5 | bellard | /* crorc */
|
3146 | 76a66253 | j_mayer | GEN_CRLOGIC(orc, 0x0D);
|
3147 | 79aceca5 | bellard | /* crxor */
|
3148 | 76a66253 | j_mayer | GEN_CRLOGIC(xor, 0x06);
|
3149 | 79aceca5 | bellard | /* mcrf */
|
3150 | 79aceca5 | bellard | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
3151 | 79aceca5 | bellard | { |
3152 | 79aceca5 | bellard | gen_op_load_crf_T0(crfS(ctx->opcode)); |
3153 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
3154 | 79aceca5 | bellard | } |
3155 | 79aceca5 | bellard | |
3156 | 79aceca5 | bellard | /*** System linkage ***/
|
3157 | 79aceca5 | bellard | /* rfi (supervisor only) */
|
3158 | 76a66253 | j_mayer | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) |
3159 | 79aceca5 | bellard | { |
3160 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3161 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3162 | 9a64fbe4 | bellard | #else
|
3163 | 9a64fbe4 | bellard | /* Restore CPU state */
|
3164 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3165 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3166 | 9fddaa0c | bellard | return;
|
3167 | 9a64fbe4 | bellard | } |
3168 | a42bd6cc | j_mayer | gen_op_rfi(); |
3169 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
3170 | 9a64fbe4 | bellard | #endif
|
3171 | 79aceca5 | bellard | } |
3172 | 79aceca5 | bellard | |
3173 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3174 | a750fc0b | j_mayer | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) |
3175 | 426613db | j_mayer | { |
3176 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3177 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3178 | 426613db | j_mayer | #else
|
3179 | 426613db | j_mayer | /* Restore CPU state */
|
3180 | 426613db | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3181 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3182 | 426613db | j_mayer | return;
|
3183 | 426613db | j_mayer | } |
3184 | a42bd6cc | j_mayer | gen_op_rfid(); |
3185 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
3186 | 426613db | j_mayer | #endif
|
3187 | 426613db | j_mayer | } |
3188 | 426613db | j_mayer | |
3189 | 5b8105fa | j_mayer | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) |
3190 | be147d08 | j_mayer | { |
3191 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3192 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3193 | be147d08 | j_mayer | #else
|
3194 | be147d08 | j_mayer | /* Restore CPU state */
|
3195 | be147d08 | j_mayer | if (unlikely(ctx->supervisor <= 1)) { |
3196 | be147d08 | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3197 | be147d08 | j_mayer | return;
|
3198 | be147d08 | j_mayer | } |
3199 | be147d08 | j_mayer | gen_op_hrfid(); |
3200 | be147d08 | j_mayer | GEN_SYNC(ctx); |
3201 | be147d08 | j_mayer | #endif
|
3202 | be147d08 | j_mayer | } |
3203 | be147d08 | j_mayer | #endif
|
3204 | be147d08 | j_mayer | |
3205 | 79aceca5 | bellard | /* sc */
|
3206 | 417bf010 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3207 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3208 | 417bf010 | j_mayer | #else
|
3209 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3210 | 417bf010 | j_mayer | #endif
|
3211 | e1833e1f | j_mayer | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) |
3212 | 79aceca5 | bellard | { |
3213 | e1833e1f | j_mayer | uint32_t lev; |
3214 | e1833e1f | j_mayer | |
3215 | e1833e1f | j_mayer | lev = (ctx->opcode >> 5) & 0x7F; |
3216 | 417bf010 | j_mayer | GEN_EXCP(ctx, POWERPC_SYSCALL, lev); |
3217 | 79aceca5 | bellard | } |
3218 | 79aceca5 | bellard | |
3219 | 79aceca5 | bellard | /*** Trap ***/
|
3220 | 79aceca5 | bellard | /* tw */
|
3221 | 76a66253 | j_mayer | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) |
3222 | 79aceca5 | bellard | { |
3223 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3224 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3225 | a0ae05aa | ths | /* Update the nip since this might generate a trap exception */
|
3226 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3227 | 9a64fbe4 | bellard | gen_op_tw(TO(ctx->opcode)); |
3228 | 79aceca5 | bellard | } |
3229 | 79aceca5 | bellard | |
3230 | 79aceca5 | bellard | /* twi */
|
3231 | 79aceca5 | bellard | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
3232 | 79aceca5 | bellard | { |
3233 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3234 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
3235 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3236 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3237 | 76a66253 | j_mayer | gen_op_tw(TO(ctx->opcode)); |
3238 | 79aceca5 | bellard | } |
3239 | 79aceca5 | bellard | |
3240 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3241 | d9bce9d9 | j_mayer | /* td */
|
3242 | d9bce9d9 | j_mayer | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) |
3243 | d9bce9d9 | j_mayer | { |
3244 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3245 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3246 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3247 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3248 | d9bce9d9 | j_mayer | gen_op_td(TO(ctx->opcode)); |
3249 | d9bce9d9 | j_mayer | } |
3250 | d9bce9d9 | j_mayer | |
3251 | d9bce9d9 | j_mayer | /* tdi */
|
3252 | d9bce9d9 | j_mayer | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) |
3253 | d9bce9d9 | j_mayer | { |
3254 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3255 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
3256 | d9bce9d9 | j_mayer | /* Update the nip since this might generate a trap exception */
|
3257 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3258 | d9bce9d9 | j_mayer | gen_op_td(TO(ctx->opcode)); |
3259 | d9bce9d9 | j_mayer | } |
3260 | d9bce9d9 | j_mayer | #endif
|
3261 | d9bce9d9 | j_mayer | |
3262 | 79aceca5 | bellard | /*** Processor control ***/
|
3263 | 79aceca5 | bellard | /* mcrxr */
|
3264 | 79aceca5 | bellard | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
3265 | 79aceca5 | bellard | { |
3266 | 79aceca5 | bellard | gen_op_load_xer_cr(); |
3267 | 79aceca5 | bellard | gen_op_store_T0_crf(crfD(ctx->opcode)); |
3268 | e864cabd | j_mayer | gen_op_clear_xer_ov(); |
3269 | e864cabd | j_mayer | gen_op_clear_xer_ca(); |
3270 | 79aceca5 | bellard | } |
3271 | 79aceca5 | bellard | |
3272 | 79aceca5 | bellard | /* mfcr */
|
3273 | 76a66253 | j_mayer | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) |
3274 | 79aceca5 | bellard | { |
3275 | 76a66253 | j_mayer | uint32_t crm, crn; |
3276 | 3b46e624 | ths | |
3277 | 76a66253 | j_mayer | if (likely(ctx->opcode & 0x00100000)) { |
3278 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3279 | 76a66253 | j_mayer | if (likely((crm ^ (crm - 1)) == 0)) { |
3280 | 76a66253 | j_mayer | crn = ffs(crm); |
3281 | 6676f424 | aurel32 | gen_op_load_cro(7 - crn);
|
3282 | 76a66253 | j_mayer | } |
3283 | d9bce9d9 | j_mayer | } else {
|
3284 | 6676f424 | aurel32 | gen_op_load_cr(); |
3285 | d9bce9d9 | j_mayer | } |
3286 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3287 | 79aceca5 | bellard | } |
3288 | 79aceca5 | bellard | |
3289 | 79aceca5 | bellard | /* mfmsr */
|
3290 | 79aceca5 | bellard | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
3291 | 79aceca5 | bellard | { |
3292 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3293 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3294 | 9a64fbe4 | bellard | #else
|
3295 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3296 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3297 | 9fddaa0c | bellard | return;
|
3298 | 9a64fbe4 | bellard | } |
3299 | 6676f424 | aurel32 | gen_op_load_msr(); |
3300 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3301 | 9a64fbe4 | bellard | #endif
|
3302 | 79aceca5 | bellard | } |
3303 | 79aceca5 | bellard | |
3304 | a11b8151 | j_mayer | #if 1 |
3305 | 6f2d8978 | j_mayer | #define SPR_NOACCESS ((void *)(-1UL)) |
3306 | 3fc6c082 | bellard | #else
|
3307 | 3fc6c082 | bellard | static void spr_noaccess (void *opaque, int sprn) |
3308 | 3fc6c082 | bellard | { |
3309 | 3fc6c082 | bellard | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3310 | 3fc6c082 | bellard | printf("ERROR: try to access SPR %d !\n", sprn);
|
3311 | 3fc6c082 | bellard | } |
3312 | 3fc6c082 | bellard | #define SPR_NOACCESS (&spr_noaccess)
|
3313 | 3fc6c082 | bellard | #endif
|
3314 | 3fc6c082 | bellard | |
3315 | 79aceca5 | bellard | /* mfspr */
|
3316 | b068d6a7 | j_mayer | static always_inline void gen_op_mfspr (DisasContext *ctx) |
3317 | 79aceca5 | bellard | { |
3318 | 3fc6c082 | bellard | void (*read_cb)(void *opaque, int sprn); |
3319 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3320 | 79aceca5 | bellard | |
3321 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3322 | be147d08 | j_mayer | if (ctx->supervisor == 2) |
3323 | be147d08 | j_mayer | read_cb = ctx->spr_cb[sprn].hea_read; |
3324 | 7863667f | j_mayer | else if (ctx->supervisor) |
3325 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].oea_read; |
3326 | 3fc6c082 | bellard | else
|
3327 | 9a64fbe4 | bellard | #endif
|
3328 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].uea_read; |
3329 | 76a66253 | j_mayer | if (likely(read_cb != NULL)) { |
3330 | 76a66253 | j_mayer | if (likely(read_cb != SPR_NOACCESS)) {
|
3331 | 3fc6c082 | bellard | (*read_cb)(ctx, sprn); |
3332 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3333 | 3fc6c082 | bellard | } else {
|
3334 | 3fc6c082 | bellard | /* Privilege exception */
|
3335 | 9fceefa7 | j_mayer | /* This is a hack to avoid warnings when running Linux:
|
3336 | 9fceefa7 | j_mayer | * this OS breaks the PowerPC virtualisation model,
|
3337 | 9fceefa7 | j_mayer | * allowing userland application to read the PVR
|
3338 | 9fceefa7 | j_mayer | */
|
3339 | 9fceefa7 | j_mayer | if (sprn != SPR_PVR) {
|
3340 | 9fceefa7 | j_mayer | if (loglevel != 0) { |
3341 | 6b542af7 | j_mayer | fprintf(logfile, "Trying to read privileged spr %d %03x at "
|
3342 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3343 | 9fceefa7 | j_mayer | } |
3344 | 077fc206 | j_mayer | printf("Trying to read privileged spr %d %03x at " ADDRX "\n", |
3345 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3346 | f24e5695 | bellard | } |
3347 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3348 | 79aceca5 | bellard | } |
3349 | 3fc6c082 | bellard | } else {
|
3350 | 3fc6c082 | bellard | /* Not defined */
|
3351 | 4a057712 | j_mayer | if (loglevel != 0) { |
3352 | 077fc206 | j_mayer | fprintf(logfile, "Trying to read invalid spr %d %03x at "
|
3353 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3354 | f24e5695 | bellard | } |
3355 | 077fc206 | j_mayer | printf("Trying to read invalid spr %d %03x at " ADDRX "\n", |
3356 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3357 | e1833e1f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
3358 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
3359 | 79aceca5 | bellard | } |
3360 | 79aceca5 | bellard | } |
3361 | 79aceca5 | bellard | |
3362 | 3fc6c082 | bellard | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
3363 | 79aceca5 | bellard | { |
3364 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3365 | 76a66253 | j_mayer | } |
3366 | 3fc6c082 | bellard | |
3367 | 3fc6c082 | bellard | /* mftb */
|
3368 | a750fc0b | j_mayer | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB) |
3369 | 3fc6c082 | bellard | { |
3370 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3371 | 79aceca5 | bellard | } |
3372 | 79aceca5 | bellard | |
3373 | 79aceca5 | bellard | /* mtcrf */
|
3374 | 8dd4983c | bellard | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) |
3375 | 79aceca5 | bellard | { |
3376 | 76a66253 | j_mayer | uint32_t crm, crn; |
3377 | 3b46e624 | ths | |
3378 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3379 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3380 | 76a66253 | j_mayer | if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { |
3381 | 76a66253 | j_mayer | crn = ffs(crm); |
3382 | 76a66253 | j_mayer | gen_op_srli_T0(crn * 4);
|
3383 | 6676f424 | aurel32 | gen_op_andi_T0(0xF);
|
3384 | 6676f424 | aurel32 | gen_op_store_cro(7 - crn);
|
3385 | 76a66253 | j_mayer | } else {
|
3386 | 6676f424 | aurel32 | gen_op_store_cr(crm); |
3387 | 76a66253 | j_mayer | } |
3388 | 79aceca5 | bellard | } |
3389 | 79aceca5 | bellard | |
3390 | 79aceca5 | bellard | /* mtmsr */
|
3391 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3392 | be147d08 | j_mayer | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) |
3393 | 426613db | j_mayer | { |
3394 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3395 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3396 | 426613db | j_mayer | #else
|
3397 | 426613db | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3398 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3399 | 426613db | j_mayer | return;
|
3400 | 426613db | j_mayer | } |
3401 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3402 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3403 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3404 | be147d08 | j_mayer | gen_op_update_riee(); |
3405 | be147d08 | j_mayer | } else {
|
3406 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3407 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3408 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3409 | 056b05f8 | j_mayer | */
|
3410 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3411 | 6676f424 | aurel32 | gen_op_store_msr(); |
3412 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3413 | be147d08 | j_mayer | /* Note that mtmsr is not always defined as context-synchronizing */
|
3414 | 056b05f8 | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
3415 | be147d08 | j_mayer | } |
3416 | 426613db | j_mayer | #endif
|
3417 | 426613db | j_mayer | } |
3418 | 426613db | j_mayer | #endif
|
3419 | 426613db | j_mayer | |
3420 | 79aceca5 | bellard | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
3421 | 79aceca5 | bellard | { |
3422 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3423 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3424 | 9a64fbe4 | bellard | #else
|
3425 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3426 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3427 | 9fddaa0c | bellard | return;
|
3428 | 9a64fbe4 | bellard | } |
3429 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3430 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3431 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3432 | be147d08 | j_mayer | gen_op_update_riee(); |
3433 | be147d08 | j_mayer | } else {
|
3434 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3435 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3436 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3437 | 056b05f8 | j_mayer | */
|
3438 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3439 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3440 | be147d08 | j_mayer | if (!ctx->sf_mode)
|
3441 | 6676f424 | aurel32 | gen_op_store_msr_32(); |
3442 | be147d08 | j_mayer | else
|
3443 | d9bce9d9 | j_mayer | #endif
|
3444 | 6676f424 | aurel32 | gen_op_store_msr(); |
3445 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3446 | be147d08 | j_mayer | /* Note that mtmsrd is not always defined as context-synchronizing */
|
3447 | 056b05f8 | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
3448 | be147d08 | j_mayer | } |
3449 | 9a64fbe4 | bellard | #endif
|
3450 | 79aceca5 | bellard | } |
3451 | 79aceca5 | bellard | |
3452 | 79aceca5 | bellard | /* mtspr */
|
3453 | 79aceca5 | bellard | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
3454 | 79aceca5 | bellard | { |
3455 | 3fc6c082 | bellard | void (*write_cb)(void *opaque, int sprn); |
3456 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3457 | 79aceca5 | bellard | |
3458 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3459 | be147d08 | j_mayer | if (ctx->supervisor == 2) |
3460 | be147d08 | j_mayer | write_cb = ctx->spr_cb[sprn].hea_write; |
3461 | 7863667f | j_mayer | else if (ctx->supervisor) |
3462 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].oea_write; |
3463 | 3fc6c082 | bellard | else
|
3464 | 9a64fbe4 | bellard | #endif
|
3465 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].uea_write; |
3466 | 76a66253 | j_mayer | if (likely(write_cb != NULL)) { |
3467 | 76a66253 | j_mayer | if (likely(write_cb != SPR_NOACCESS)) {
|
3468 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3469 | 3fc6c082 | bellard | (*write_cb)(ctx, sprn); |
3470 | 3fc6c082 | bellard | } else {
|
3471 | 3fc6c082 | bellard | /* Privilege exception */
|
3472 | 4a057712 | j_mayer | if (loglevel != 0) { |
3473 | 077fc206 | j_mayer | fprintf(logfile, "Trying to write privileged spr %d %03x at "
|
3474 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3475 | f24e5695 | bellard | } |
3476 | 077fc206 | j_mayer | printf("Trying to write privileged spr %d %03x at " ADDRX "\n", |
3477 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3478 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3479 | 76a66253 | j_mayer | } |
3480 | 3fc6c082 | bellard | } else {
|
3481 | 3fc6c082 | bellard | /* Not defined */
|
3482 | 4a057712 | j_mayer | if (loglevel != 0) { |
3483 | 077fc206 | j_mayer | fprintf(logfile, "Trying to write invalid spr %d %03x at "
|
3484 | 077fc206 | j_mayer | ADDRX "\n", sprn, sprn, ctx->nip);
|
3485 | f24e5695 | bellard | } |
3486 | 077fc206 | j_mayer | printf("Trying to write invalid spr %d %03x at " ADDRX "\n", |
3487 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3488 | e1833e1f | j_mayer | GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM, |
3489 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR); |
3490 | 79aceca5 | bellard | } |
3491 | 79aceca5 | bellard | } |
3492 | 79aceca5 | bellard | |
3493 | 79aceca5 | bellard | /*** Cache management ***/
|
3494 | 79aceca5 | bellard | /* dcbf */
|
3495 | 0db1b20e | j_mayer | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) |
3496 | 79aceca5 | bellard | { |
3497 | dac454af | j_mayer | /* XXX: specification says this is treated as a load by the MMU */
|
3498 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3499 | a541f297 | bellard | op_ldst(lbz); |
3500 | 79aceca5 | bellard | } |
3501 | 79aceca5 | bellard | |
3502 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
3503 | 9a64fbe4 | bellard | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
3504 | 79aceca5 | bellard | { |
3505 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
3506 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3507 | a541f297 | bellard | #else
|
3508 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3509 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3510 | 9fddaa0c | bellard | return;
|
3511 | 9a64fbe4 | bellard | } |
3512 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3513 | 76a66253 | j_mayer | /* XXX: specification says this should be treated as a store by the MMU */
|
3514 | dac454af | j_mayer | op_ldst(lbz); |
3515 | a541f297 | bellard | op_ldst(stb); |
3516 | a541f297 | bellard | #endif
|
3517 | 79aceca5 | bellard | } |
3518 | 79aceca5 | bellard | |
3519 | 79aceca5 | bellard | /* dcdst */
|
3520 | 9a64fbe4 | bellard | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
3521 | 79aceca5 | bellard | { |
3522 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU */
|
3523 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3524 | a541f297 | bellard | op_ldst(lbz); |
3525 | 79aceca5 | bellard | } |
3526 | 79aceca5 | bellard | |
3527 | 79aceca5 | bellard | /* dcbt */
|
3528 | 0db1b20e | j_mayer | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE) |
3529 | 79aceca5 | bellard | { |
3530 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3531 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3532 | 76a66253 | j_mayer | * but does not generate any exception
|
3533 | 76a66253 | j_mayer | */
|
3534 | 79aceca5 | bellard | } |
3535 | 79aceca5 | bellard | |
3536 | 79aceca5 | bellard | /* dcbtst */
|
3537 | 0db1b20e | j_mayer | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE) |
3538 | 79aceca5 | bellard | { |
3539 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3540 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3541 | 76a66253 | j_mayer | * but does not generate any exception
|
3542 | 76a66253 | j_mayer | */
|
3543 | 79aceca5 | bellard | } |
3544 | 79aceca5 | bellard | |
3545 | 79aceca5 | bellard | /* dcbz */
|
3546 | d63001d1 | j_mayer | #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
|
3547 | 7863667f | j_mayer | static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = { |
3548 | 7863667f | j_mayer | /* 32 bytes cache line size */
|
3549 | d63001d1 | j_mayer | { |
3550 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
|
3551 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
|
3552 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
|
3553 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
|
3554 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
|
3555 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
|
3556 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
|
3557 | 7863667f | j_mayer | #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
|
3558 | 7863667f | j_mayer | GEN_MEM_FUNCS(dcbz_l32), |
3559 | d63001d1 | j_mayer | }, |
3560 | 7863667f | j_mayer | /* 64 bytes cache line size */
|
3561 | d63001d1 | j_mayer | { |
3562 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
|
3563 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
|
3564 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
|
3565 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
|
3566 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
|
3567 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
|
3568 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
|
3569 | 7863667f | j_mayer | #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
|
3570 | 7863667f | j_mayer | GEN_MEM_FUNCS(dcbz_l64), |
3571 | d63001d1 | j_mayer | }, |
3572 | 7863667f | j_mayer | /* 128 bytes cache line size */
|
3573 | d63001d1 | j_mayer | { |
3574 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
|
3575 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
|
3576 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
|
3577 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
|
3578 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
|
3579 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
|
3580 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
|
3581 | 7863667f | j_mayer | #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
|
3582 | 7863667f | j_mayer | GEN_MEM_FUNCS(dcbz_l128), |
3583 | d63001d1 | j_mayer | }, |
3584 | 7863667f | j_mayer | /* tunable cache line size */
|
3585 | d63001d1 | j_mayer | { |
3586 | 7863667f | j_mayer | #define gen_op_dcbz_le_raw gen_op_dcbz_raw
|
3587 | 7863667f | j_mayer | #define gen_op_dcbz_le_user gen_op_dcbz_user
|
3588 | 7863667f | j_mayer | #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
|
3589 | 7863667f | j_mayer | #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
|
3590 | 7863667f | j_mayer | #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
|
3591 | 7863667f | j_mayer | #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
|
3592 | 7863667f | j_mayer | #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
|
3593 | 7863667f | j_mayer | #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
|
3594 | 7863667f | j_mayer | GEN_MEM_FUNCS(dcbz), |
3595 | d63001d1 | j_mayer | }, |
3596 | 76a66253 | j_mayer | }; |
3597 | 9a64fbe4 | bellard | |
3598 | b068d6a7 | j_mayer | static always_inline void handler_dcbz (DisasContext *ctx, |
3599 | b068d6a7 | j_mayer | int dcache_line_size)
|
3600 | d63001d1 | j_mayer | { |
3601 | d63001d1 | j_mayer | int n;
|
3602 | d63001d1 | j_mayer | |
3603 | d63001d1 | j_mayer | switch (dcache_line_size) {
|
3604 | d63001d1 | j_mayer | case 32: |
3605 | d63001d1 | j_mayer | n = 0;
|
3606 | d63001d1 | j_mayer | break;
|
3607 | d63001d1 | j_mayer | case 64: |
3608 | d63001d1 | j_mayer | n = 1;
|
3609 | d63001d1 | j_mayer | break;
|
3610 | d63001d1 | j_mayer | case 128: |
3611 | d63001d1 | j_mayer | n = 2;
|
3612 | d63001d1 | j_mayer | break;
|
3613 | d63001d1 | j_mayer | default:
|
3614 | d63001d1 | j_mayer | n = 3;
|
3615 | d63001d1 | j_mayer | break;
|
3616 | d63001d1 | j_mayer | } |
3617 | d63001d1 | j_mayer | op_dcbz(n); |
3618 | d63001d1 | j_mayer | } |
3619 | d63001d1 | j_mayer | |
3620 | d63001d1 | j_mayer | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) |
3621 | 79aceca5 | bellard | { |
3622 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3623 | d63001d1 | j_mayer | handler_dcbz(ctx, ctx->dcache_line_size); |
3624 | d63001d1 | j_mayer | gen_op_check_reservation(); |
3625 | d63001d1 | j_mayer | } |
3626 | d63001d1 | j_mayer | |
3627 | c7697e1f | j_mayer | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) |
3628 | d63001d1 | j_mayer | { |
3629 | d63001d1 | j_mayer | gen_addr_reg_index(ctx); |
3630 | d63001d1 | j_mayer | if (ctx->opcode & 0x00200000) |
3631 | d63001d1 | j_mayer | handler_dcbz(ctx, ctx->dcache_line_size); |
3632 | d63001d1 | j_mayer | else
|
3633 | d63001d1 | j_mayer | handler_dcbz(ctx, -1);
|
3634 | 4b3686fa | bellard | gen_op_check_reservation(); |
3635 | 79aceca5 | bellard | } |
3636 | 79aceca5 | bellard | |
3637 | 79aceca5 | bellard | /* icbi */
|
3638 | 36f69651 | j_mayer | #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
|
3639 | 7863667f | j_mayer | #define gen_op_icbi_le_raw gen_op_icbi_raw
|
3640 | 7863667f | j_mayer | #define gen_op_icbi_le_user gen_op_icbi_user
|
3641 | 7863667f | j_mayer | #define gen_op_icbi_le_kernel gen_op_icbi_kernel
|
3642 | 7863667f | j_mayer | #define gen_op_icbi_le_hypv gen_op_icbi_hypv
|
3643 | 7863667f | j_mayer | #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
|
3644 | 7863667f | j_mayer | #define gen_op_icbi_le_64_user gen_op_icbi_64_user
|
3645 | 7863667f | j_mayer | #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
|
3646 | 7863667f | j_mayer | #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
|
3647 | 7863667f | j_mayer | static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
|
3648 | 7863667f | j_mayer | GEN_MEM_FUNCS(icbi), |
3649 | 36f69651 | j_mayer | }; |
3650 | e1833e1f | j_mayer | |
3651 | 1b413d55 | j_mayer | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) |
3652 | 79aceca5 | bellard | { |
3653 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
3654 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3655 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3656 | 36f69651 | j_mayer | op_icbi(); |
3657 | 79aceca5 | bellard | } |
3658 | 79aceca5 | bellard | |
3659 | 79aceca5 | bellard | /* Optional: */
|
3660 | 79aceca5 | bellard | /* dcba */
|
3661 | a750fc0b | j_mayer | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA) |
3662 | 79aceca5 | bellard | { |
3663 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3664 | 0db1b20e | j_mayer | /* XXX: specification say this is treated as a store by the MMU
|
3665 | 0db1b20e | j_mayer | * but does not generate any exception
|
3666 | 0db1b20e | j_mayer | */
|
3667 | 79aceca5 | bellard | } |
3668 | 79aceca5 | bellard | |
3669 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
3670 | 79aceca5 | bellard | /* Supervisor only: */
|
3671 | 79aceca5 | bellard | /* mfsr */
|
3672 | 79aceca5 | bellard | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
3673 | 79aceca5 | bellard | { |
3674 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3675 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3676 | 9a64fbe4 | bellard | #else
|
3677 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3678 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3679 | 9fddaa0c | bellard | return;
|
3680 | 9a64fbe4 | bellard | } |
3681 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3682 | 76a66253 | j_mayer | gen_op_load_sr(); |
3683 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3684 | 9a64fbe4 | bellard | #endif
|
3685 | 79aceca5 | bellard | } |
3686 | 79aceca5 | bellard | |
3687 | 79aceca5 | bellard | /* mfsrin */
|
3688 | 9a64fbe4 | bellard | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
3689 | 79aceca5 | bellard | { |
3690 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3691 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3692 | 9a64fbe4 | bellard | #else
|
3693 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3694 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3695 | 9fddaa0c | bellard | return;
|
3696 | 9a64fbe4 | bellard | } |
3697 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3698 | 76a66253 | j_mayer | gen_op_srli_T1(28);
|
3699 | 76a66253 | j_mayer | gen_op_load_sr(); |
3700 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3701 | 9a64fbe4 | bellard | #endif
|
3702 | 79aceca5 | bellard | } |
3703 | 79aceca5 | bellard | |
3704 | 79aceca5 | bellard | /* mtsr */
|
3705 | e63c59cb | bellard | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
3706 | 79aceca5 | bellard | { |
3707 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3708 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3709 | 9a64fbe4 | bellard | #else
|
3710 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3711 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3712 | 9fddaa0c | bellard | return;
|
3713 | 9a64fbe4 | bellard | } |
3714 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3715 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3716 | 76a66253 | j_mayer | gen_op_store_sr(); |
3717 | 9a64fbe4 | bellard | #endif
|
3718 | 79aceca5 | bellard | } |
3719 | 79aceca5 | bellard | |
3720 | 79aceca5 | bellard | /* mtsrin */
|
3721 | 9a64fbe4 | bellard | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
3722 | 79aceca5 | bellard | { |
3723 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3724 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3725 | 9a64fbe4 | bellard | #else
|
3726 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3727 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3728 | 9fddaa0c | bellard | return;
|
3729 | 9a64fbe4 | bellard | } |
3730 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3731 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3732 | 76a66253 | j_mayer | gen_op_srli_T1(28);
|
3733 | 76a66253 | j_mayer | gen_op_store_sr(); |
3734 | 9a64fbe4 | bellard | #endif
|
3735 | 79aceca5 | bellard | } |
3736 | 79aceca5 | bellard | |
3737 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
3738 | 12de9a39 | j_mayer | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
3739 | 12de9a39 | j_mayer | /* mfsr */
|
3740 | c7697e1f | j_mayer | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) |
3741 | 12de9a39 | j_mayer | { |
3742 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3743 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3744 | 12de9a39 | j_mayer | #else
|
3745 | 12de9a39 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3746 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3747 | 12de9a39 | j_mayer | return;
|
3748 | 12de9a39 | j_mayer | } |
3749 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3750 | 12de9a39 | j_mayer | gen_op_load_slb(); |
3751 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3752 | 12de9a39 | j_mayer | #endif
|
3753 | 12de9a39 | j_mayer | } |
3754 | 12de9a39 | j_mayer | |
3755 | 12de9a39 | j_mayer | /* mfsrin */
|
3756 | c7697e1f | j_mayer | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
3757 | c7697e1f | j_mayer | PPC_SEGMENT_64B) |
3758 | 12de9a39 | j_mayer | { |
3759 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3760 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3761 | 12de9a39 | j_mayer | #else
|
3762 | 12de9a39 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3763 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3764 | 12de9a39 | j_mayer | return;
|
3765 | 12de9a39 | j_mayer | } |
3766 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3767 | 12de9a39 | j_mayer | gen_op_srli_T1(28);
|
3768 | 12de9a39 | j_mayer | gen_op_load_slb(); |
3769 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3770 | 12de9a39 | j_mayer | #endif
|
3771 | 12de9a39 | j_mayer | } |
3772 | 12de9a39 | j_mayer | |
3773 | 12de9a39 | j_mayer | /* mtsr */
|
3774 | c7697e1f | j_mayer | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) |
3775 | 12de9a39 | j_mayer | { |
3776 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3777 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3778 | 12de9a39 | j_mayer | #else
|
3779 | 12de9a39 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3780 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3781 | 12de9a39 | j_mayer | return;
|
3782 | 12de9a39 | j_mayer | } |
3783 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3784 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
|
3785 | 12de9a39 | j_mayer | gen_op_store_slb(); |
3786 | 12de9a39 | j_mayer | #endif
|
3787 | 12de9a39 | j_mayer | } |
3788 | 12de9a39 | j_mayer | |
3789 | 12de9a39 | j_mayer | /* mtsrin */
|
3790 | c7697e1f | j_mayer | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
3791 | c7697e1f | j_mayer | PPC_SEGMENT_64B) |
3792 | 12de9a39 | j_mayer | { |
3793 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3794 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3795 | 12de9a39 | j_mayer | #else
|
3796 | 12de9a39 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3797 | 12de9a39 | j_mayer | GEN_EXCP_PRIVREG(ctx); |
3798 | 12de9a39 | j_mayer | return;
|
3799 | 12de9a39 | j_mayer | } |
3800 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
3801 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3802 | 12de9a39 | j_mayer | gen_op_srli_T1(28);
|
3803 | 12de9a39 | j_mayer | gen_op_store_slb(); |
3804 | 12de9a39 | j_mayer | #endif
|
3805 | 12de9a39 | j_mayer | } |
3806 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
3807 | 12de9a39 | j_mayer | |
3808 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
3809 | 79aceca5 | bellard | /* Optional & supervisor only: */
|
3810 | 79aceca5 | bellard | /* tlbia */
|
3811 | 3fc6c082 | bellard | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) |
3812 | 79aceca5 | bellard | { |
3813 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3814 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3815 | 9a64fbe4 | bellard | #else
|
3816 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3817 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3818 | 9fddaa0c | bellard | return;
|
3819 | 9a64fbe4 | bellard | } |
3820 | 9a64fbe4 | bellard | gen_op_tlbia(); |
3821 | 9a64fbe4 | bellard | #endif
|
3822 | 79aceca5 | bellard | } |
3823 | 79aceca5 | bellard | |
3824 | 79aceca5 | bellard | /* tlbie */
|
3825 | 76a66253 | j_mayer | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) |
3826 | 79aceca5 | bellard | { |
3827 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3828 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3829 | 9a64fbe4 | bellard | #else
|
3830 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3831 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3832 | 9fddaa0c | bellard | return;
|
3833 | 9a64fbe4 | bellard | } |
3834 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
3835 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3836 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3837 | d9bce9d9 | j_mayer | gen_op_tlbie_64(); |
3838 | d9bce9d9 | j_mayer | else
|
3839 | d9bce9d9 | j_mayer | #endif
|
3840 | d9bce9d9 | j_mayer | gen_op_tlbie(); |
3841 | 9a64fbe4 | bellard | #endif
|
3842 | 79aceca5 | bellard | } |
3843 | 79aceca5 | bellard | |
3844 | 79aceca5 | bellard | /* tlbsync */
|
3845 | 76a66253 | j_mayer | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) |
3846 | 79aceca5 | bellard | { |
3847 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3848 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3849 | 9a64fbe4 | bellard | #else
|
3850 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3851 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3852 | 9fddaa0c | bellard | return;
|
3853 | 9a64fbe4 | bellard | } |
3854 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
3855 | 9a64fbe4 | bellard | * tlbie have completed
|
3856 | 9a64fbe4 | bellard | */
|
3857 | e1833e1f | j_mayer | GEN_STOP(ctx); |
3858 | 9a64fbe4 | bellard | #endif
|
3859 | 79aceca5 | bellard | } |
3860 | 79aceca5 | bellard | |
3861 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3862 | 426613db | j_mayer | /* slbia */
|
3863 | 426613db | j_mayer | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) |
3864 | 426613db | j_mayer | { |
3865 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3866 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3867 | 426613db | j_mayer | #else
|
3868 | 426613db | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3869 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3870 | 426613db | j_mayer | return;
|
3871 | 426613db | j_mayer | } |
3872 | 426613db | j_mayer | gen_op_slbia(); |
3873 | 426613db | j_mayer | #endif
|
3874 | 426613db | j_mayer | } |
3875 | 426613db | j_mayer | |
3876 | 426613db | j_mayer | /* slbie */
|
3877 | 426613db | j_mayer | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) |
3878 | 426613db | j_mayer | { |
3879 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3880 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3881 | 426613db | j_mayer | #else
|
3882 | 426613db | j_mayer | if (unlikely(!ctx->supervisor)) {
|
3883 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
3884 | 426613db | j_mayer | return;
|
3885 | 426613db | j_mayer | } |
3886 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
3887 | 426613db | j_mayer | gen_op_slbie(); |
3888 | 426613db | j_mayer | #endif
|
3889 | 426613db | j_mayer | } |
3890 | 426613db | j_mayer | #endif
|
3891 | 426613db | j_mayer | |
3892 | 79aceca5 | bellard | /*** External control ***/
|
3893 | 79aceca5 | bellard | /* Optional: */
|
3894 | 9a64fbe4 | bellard | #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
|
3895 | 9a64fbe4 | bellard | #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
|
3896 | 7863667f | j_mayer | static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
|
3897 | 7863667f | j_mayer | GEN_MEM_FUNCS(eciwx), |
3898 | 111bfab3 | bellard | }; |
3899 | 7863667f | j_mayer | static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
|
3900 | 7863667f | j_mayer | GEN_MEM_FUNCS(ecowx), |
3901 | 111bfab3 | bellard | }; |
3902 | 9a64fbe4 | bellard | |
3903 | 111bfab3 | bellard | /* eciwx */
|
3904 | 79aceca5 | bellard | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
3905 | 79aceca5 | bellard | { |
3906 | 9a64fbe4 | bellard | /* Should check EAR[E] & alignment ! */
|
3907 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3908 | 76a66253 | j_mayer | op_eciwx(); |
3909 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3910 | 76a66253 | j_mayer | } |
3911 | 76a66253 | j_mayer | |
3912 | 76a66253 | j_mayer | /* ecowx */
|
3913 | 76a66253 | j_mayer | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
3914 | 76a66253 | j_mayer | { |
3915 | 76a66253 | j_mayer | /* Should check EAR[E] & alignment ! */
|
3916 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
3917 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
3918 | 76a66253 | j_mayer | op_ecowx(); |
3919 | 76a66253 | j_mayer | } |
3920 | 76a66253 | j_mayer | |
3921 | 76a66253 | j_mayer | /* PowerPC 601 specific instructions */
|
3922 | 76a66253 | j_mayer | /* abs - abs. */
|
3923 | 76a66253 | j_mayer | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) |
3924 | 76a66253 | j_mayer | { |
3925 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3926 | 76a66253 | j_mayer | gen_op_POWER_abs(); |
3927 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3928 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3929 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3930 | 76a66253 | j_mayer | } |
3931 | 76a66253 | j_mayer | |
3932 | 76a66253 | j_mayer | /* abso - abso. */
|
3933 | 76a66253 | j_mayer | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) |
3934 | 76a66253 | j_mayer | { |
3935 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3936 | 76a66253 | j_mayer | gen_op_POWER_abso(); |
3937 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3938 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3939 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3940 | 76a66253 | j_mayer | } |
3941 | 76a66253 | j_mayer | |
3942 | 76a66253 | j_mayer | /* clcs */
|
3943 | a750fc0b | j_mayer | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) |
3944 | 76a66253 | j_mayer | { |
3945 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3946 | 76a66253 | j_mayer | gen_op_POWER_clcs(); |
3947 | c7697e1f | j_mayer | /* Rc=1 sets CR0 to an undefined state */
|
3948 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3949 | 76a66253 | j_mayer | } |
3950 | 76a66253 | j_mayer | |
3951 | 76a66253 | j_mayer | /* div - div. */
|
3952 | 76a66253 | j_mayer | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) |
3953 | 76a66253 | j_mayer | { |
3954 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3955 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3956 | 76a66253 | j_mayer | gen_op_POWER_div(); |
3957 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3958 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3959 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3960 | 76a66253 | j_mayer | } |
3961 | 76a66253 | j_mayer | |
3962 | 76a66253 | j_mayer | /* divo - divo. */
|
3963 | 76a66253 | j_mayer | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) |
3964 | 76a66253 | j_mayer | { |
3965 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3966 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3967 | 76a66253 | j_mayer | gen_op_POWER_divo(); |
3968 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3969 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3970 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3971 | 76a66253 | j_mayer | } |
3972 | 76a66253 | j_mayer | |
3973 | 76a66253 | j_mayer | /* divs - divs. */
|
3974 | 76a66253 | j_mayer | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) |
3975 | 76a66253 | j_mayer | { |
3976 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3977 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3978 | 76a66253 | j_mayer | gen_op_POWER_divs(); |
3979 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3980 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3981 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3982 | 76a66253 | j_mayer | } |
3983 | 76a66253 | j_mayer | |
3984 | 76a66253 | j_mayer | /* divso - divso. */
|
3985 | 76a66253 | j_mayer | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) |
3986 | 76a66253 | j_mayer | { |
3987 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3988 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
3989 | 76a66253 | j_mayer | gen_op_POWER_divso(); |
3990 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
3991 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
3992 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
3993 | 76a66253 | j_mayer | } |
3994 | 76a66253 | j_mayer | |
3995 | 76a66253 | j_mayer | /* doz - doz. */
|
3996 | 76a66253 | j_mayer | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) |
3997 | 76a66253 | j_mayer | { |
3998 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
3999 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4000 | 76a66253 | j_mayer | gen_op_POWER_doz(); |
4001 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4002 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4003 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4004 | 76a66253 | j_mayer | } |
4005 | 76a66253 | j_mayer | |
4006 | 76a66253 | j_mayer | /* dozo - dozo. */
|
4007 | 76a66253 | j_mayer | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) |
4008 | 76a66253 | j_mayer | { |
4009 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4010 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4011 | 76a66253 | j_mayer | gen_op_POWER_dozo(); |
4012 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4013 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4014 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4015 | 76a66253 | j_mayer | } |
4016 | 76a66253 | j_mayer | |
4017 | 76a66253 | j_mayer | /* dozi */
|
4018 | 76a66253 | j_mayer | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
4019 | 76a66253 | j_mayer | { |
4020 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4021 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
4022 | 76a66253 | j_mayer | gen_op_POWER_doz(); |
4023 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4024 | 76a66253 | j_mayer | } |
4025 | 76a66253 | j_mayer | |
4026 | 7863667f | j_mayer | /* As lscbx load from memory byte after byte, it's always endian safe.
|
4027 | 7863667f | j_mayer | * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
|
4028 | 7863667f | j_mayer | */
|
4029 | 2857068e | j_mayer | #define op_POWER_lscbx(start, ra, rb) \
|
4030 | 76a66253 | j_mayer | (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb) |
4031 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
|
4032 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
|
4033 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
|
4034 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
|
4035 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
|
4036 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
|
4037 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
|
4038 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
|
4039 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
|
4040 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
|
4041 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
|
4042 | 7863667f | j_mayer | #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
|
4043 | 7863667f | j_mayer | static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
|
4044 | 7863667f | j_mayer | GEN_MEM_FUNCS(POWER_lscbx), |
4045 | 76a66253 | j_mayer | }; |
4046 | 76a66253 | j_mayer | |
4047 | 76a66253 | j_mayer | /* lscbx - lscbx. */
|
4048 | 76a66253 | j_mayer | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) |
4049 | 76a66253 | j_mayer | { |
4050 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4051 | 76a66253 | j_mayer | int rb = rB(ctx->opcode);
|
4052 | 76a66253 | j_mayer | |
4053 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4054 | 76a66253 | j_mayer | if (ra == 0) { |
4055 | 76a66253 | j_mayer | ra = rb; |
4056 | 76a66253 | j_mayer | } |
4057 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4058 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4059 | 76a66253 | j_mayer | gen_op_load_xer_bc(); |
4060 | 76a66253 | j_mayer | gen_op_load_xer_cmp(); |
4061 | 76a66253 | j_mayer | op_POWER_lscbx(rD(ctx->opcode), ra, rb); |
4062 | 76a66253 | j_mayer | gen_op_store_xer_bc(); |
4063 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4064 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4065 | 76a66253 | j_mayer | } |
4066 | 76a66253 | j_mayer | |
4067 | 76a66253 | j_mayer | /* maskg - maskg. */
|
4068 | 76a66253 | j_mayer | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) |
4069 | 76a66253 | j_mayer | { |
4070 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4071 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4072 | 76a66253 | j_mayer | gen_op_POWER_maskg(); |
4073 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4074 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4075 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4076 | 76a66253 | j_mayer | } |
4077 | 76a66253 | j_mayer | |
4078 | 76a66253 | j_mayer | /* maskir - maskir. */
|
4079 | 76a66253 | j_mayer | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) |
4080 | 76a66253 | j_mayer | { |
4081 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4082 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4083 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4084 | 76a66253 | j_mayer | gen_op_POWER_maskir(); |
4085 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4086 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4087 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4088 | 76a66253 | j_mayer | } |
4089 | 76a66253 | j_mayer | |
4090 | 76a66253 | j_mayer | /* mul - mul. */
|
4091 | 76a66253 | j_mayer | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) |
4092 | 76a66253 | j_mayer | { |
4093 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4094 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4095 | 76a66253 | j_mayer | gen_op_POWER_mul(); |
4096 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4097 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4098 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4099 | 76a66253 | j_mayer | } |
4100 | 76a66253 | j_mayer | |
4101 | 76a66253 | j_mayer | /* mulo - mulo. */
|
4102 | 76a66253 | j_mayer | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) |
4103 | 76a66253 | j_mayer | { |
4104 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4105 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4106 | 76a66253 | j_mayer | gen_op_POWER_mulo(); |
4107 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4108 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4109 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4110 | 76a66253 | j_mayer | } |
4111 | 76a66253 | j_mayer | |
4112 | 76a66253 | j_mayer | /* nabs - nabs. */
|
4113 | 76a66253 | j_mayer | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) |
4114 | 76a66253 | j_mayer | { |
4115 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4116 | 76a66253 | j_mayer | gen_op_POWER_nabs(); |
4117 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4118 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4119 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4120 | 76a66253 | j_mayer | } |
4121 | 76a66253 | j_mayer | |
4122 | 76a66253 | j_mayer | /* nabso - nabso. */
|
4123 | 76a66253 | j_mayer | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) |
4124 | 76a66253 | j_mayer | { |
4125 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4126 | 76a66253 | j_mayer | gen_op_POWER_nabso(); |
4127 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4128 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4129 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4130 | 76a66253 | j_mayer | } |
4131 | 76a66253 | j_mayer | |
4132 | 76a66253 | j_mayer | /* rlmi - rlmi. */
|
4133 | 76a66253 | j_mayer | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) |
4134 | 76a66253 | j_mayer | { |
4135 | 76a66253 | j_mayer | uint32_t mb, me; |
4136 | 76a66253 | j_mayer | |
4137 | 76a66253 | j_mayer | mb = MB(ctx->opcode); |
4138 | 76a66253 | j_mayer | me = ME(ctx->opcode); |
4139 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4140 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
4141 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4142 | 76a66253 | j_mayer | gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); |
4143 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4144 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4145 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4146 | 76a66253 | j_mayer | } |
4147 | 76a66253 | j_mayer | |
4148 | 76a66253 | j_mayer | /* rrib - rrib. */
|
4149 | 76a66253 | j_mayer | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) |
4150 | 76a66253 | j_mayer | { |
4151 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4152 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
|
4153 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
|
4154 | 76a66253 | j_mayer | gen_op_POWER_rrib(); |
4155 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4156 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4157 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4158 | 76a66253 | j_mayer | } |
4159 | 76a66253 | j_mayer | |
4160 | 76a66253 | j_mayer | /* sle - sle. */
|
4161 | 76a66253 | j_mayer | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) |
4162 | 76a66253 | j_mayer | { |
4163 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4164 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4165 | 76a66253 | j_mayer | gen_op_POWER_sle(); |
4166 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4167 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4168 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4169 | 76a66253 | j_mayer | } |
4170 | 76a66253 | j_mayer | |
4171 | 76a66253 | j_mayer | /* sleq - sleq. */
|
4172 | 76a66253 | j_mayer | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) |
4173 | 76a66253 | j_mayer | { |
4174 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4175 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4176 | 76a66253 | j_mayer | gen_op_POWER_sleq(); |
4177 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4178 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4179 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4180 | 76a66253 | j_mayer | } |
4181 | 76a66253 | j_mayer | |
4182 | 76a66253 | j_mayer | /* sliq - sliq. */
|
4183 | 76a66253 | j_mayer | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) |
4184 | 76a66253 | j_mayer | { |
4185 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4186 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4187 | 76a66253 | j_mayer | gen_op_POWER_sle(); |
4188 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4189 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4190 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4191 | 76a66253 | j_mayer | } |
4192 | 76a66253 | j_mayer | |
4193 | 76a66253 | j_mayer | /* slliq - slliq. */
|
4194 | 76a66253 | j_mayer | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) |
4195 | 76a66253 | j_mayer | { |
4196 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4197 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4198 | 76a66253 | j_mayer | gen_op_POWER_sleq(); |
4199 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4200 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4201 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4202 | 76a66253 | j_mayer | } |
4203 | 76a66253 | j_mayer | |
4204 | 76a66253 | j_mayer | /* sllq - sllq. */
|
4205 | 76a66253 | j_mayer | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) |
4206 | 76a66253 | j_mayer | { |
4207 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4208 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4209 | 76a66253 | j_mayer | gen_op_POWER_sllq(); |
4210 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4211 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4212 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4213 | 76a66253 | j_mayer | } |
4214 | 76a66253 | j_mayer | |
4215 | 76a66253 | j_mayer | /* slq - slq. */
|
4216 | 76a66253 | j_mayer | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) |
4217 | 76a66253 | j_mayer | { |
4218 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4219 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4220 | 76a66253 | j_mayer | gen_op_POWER_slq(); |
4221 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4222 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4223 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4224 | 76a66253 | j_mayer | } |
4225 | 76a66253 | j_mayer | |
4226 | d9bce9d9 | j_mayer | /* sraiq - sraiq. */
|
4227 | 76a66253 | j_mayer | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) |
4228 | 76a66253 | j_mayer | { |
4229 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4230 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4231 | 76a66253 | j_mayer | gen_op_POWER_sraq(); |
4232 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4233 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4234 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4235 | 76a66253 | j_mayer | } |
4236 | 76a66253 | j_mayer | |
4237 | 76a66253 | j_mayer | /* sraq - sraq. */
|
4238 | 76a66253 | j_mayer | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) |
4239 | 76a66253 | j_mayer | { |
4240 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4241 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4242 | 76a66253 | j_mayer | gen_op_POWER_sraq(); |
4243 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4244 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4245 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4246 | 76a66253 | j_mayer | } |
4247 | 76a66253 | j_mayer | |
4248 | 76a66253 | j_mayer | /* sre - sre. */
|
4249 | 76a66253 | j_mayer | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) |
4250 | 76a66253 | j_mayer | { |
4251 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4252 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4253 | 76a66253 | j_mayer | gen_op_POWER_sre(); |
4254 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4255 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4256 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4257 | 76a66253 | j_mayer | } |
4258 | 76a66253 | j_mayer | |
4259 | 76a66253 | j_mayer | /* srea - srea. */
|
4260 | 76a66253 | j_mayer | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) |
4261 | 76a66253 | j_mayer | { |
4262 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4263 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4264 | 76a66253 | j_mayer | gen_op_POWER_srea(); |
4265 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4266 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4267 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4268 | 76a66253 | j_mayer | } |
4269 | 76a66253 | j_mayer | |
4270 | 76a66253 | j_mayer | /* sreq */
|
4271 | 76a66253 | j_mayer | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) |
4272 | 76a66253 | j_mayer | { |
4273 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4274 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4275 | 76a66253 | j_mayer | gen_op_POWER_sreq(); |
4276 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4277 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4278 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4279 | 76a66253 | j_mayer | } |
4280 | 76a66253 | j_mayer | |
4281 | 76a66253 | j_mayer | /* sriq */
|
4282 | 76a66253 | j_mayer | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) |
4283 | 76a66253 | j_mayer | { |
4284 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4285 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4286 | 76a66253 | j_mayer | gen_op_POWER_srq(); |
4287 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4288 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4289 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4290 | 76a66253 | j_mayer | } |
4291 | 76a66253 | j_mayer | |
4292 | 76a66253 | j_mayer | /* srliq */
|
4293 | 76a66253 | j_mayer | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) |
4294 | 76a66253 | j_mayer | { |
4295 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4296 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4297 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
|
4298 | 76a66253 | j_mayer | gen_op_POWER_srlq(); |
4299 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4300 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4301 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4302 | 76a66253 | j_mayer | } |
4303 | 76a66253 | j_mayer | |
4304 | 76a66253 | j_mayer | /* srlq */
|
4305 | 76a66253 | j_mayer | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) |
4306 | 76a66253 | j_mayer | { |
4307 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4308 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4309 | 76a66253 | j_mayer | gen_op_POWER_srlq(); |
4310 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4311 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4312 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4313 | 76a66253 | j_mayer | } |
4314 | 76a66253 | j_mayer | |
4315 | 76a66253 | j_mayer | /* srq */
|
4316 | 76a66253 | j_mayer | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) |
4317 | 76a66253 | j_mayer | { |
4318 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
4319 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
4320 | 76a66253 | j_mayer | gen_op_POWER_srq(); |
4321 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
4322 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4323 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4324 | 76a66253 | j_mayer | } |
4325 | 76a66253 | j_mayer | |
4326 | 76a66253 | j_mayer | /* PowerPC 602 specific instructions */
|
4327 | 76a66253 | j_mayer | /* dsa */
|
4328 | 76a66253 | j_mayer | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC) |
4329 | 76a66253 | j_mayer | { |
4330 | 76a66253 | j_mayer | /* XXX: TODO */
|
4331 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
4332 | 76a66253 | j_mayer | } |
4333 | 76a66253 | j_mayer | |
4334 | 76a66253 | j_mayer | /* esa */
|
4335 | 76a66253 | j_mayer | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC) |
4336 | 76a66253 | j_mayer | { |
4337 | 76a66253 | j_mayer | /* XXX: TODO */
|
4338 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
4339 | 76a66253 | j_mayer | } |
4340 | 76a66253 | j_mayer | |
4341 | 76a66253 | j_mayer | /* mfrom */
|
4342 | 76a66253 | j_mayer | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) |
4343 | 76a66253 | j_mayer | { |
4344 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4345 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4346 | 76a66253 | j_mayer | #else
|
4347 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4348 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4349 | 76a66253 | j_mayer | return;
|
4350 | 76a66253 | j_mayer | } |
4351 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4352 | 76a66253 | j_mayer | gen_op_602_mfrom(); |
4353 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4354 | 76a66253 | j_mayer | #endif
|
4355 | 76a66253 | j_mayer | } |
4356 | 76a66253 | j_mayer | |
4357 | 76a66253 | j_mayer | /* 602 - 603 - G2 TLB management */
|
4358 | 76a66253 | j_mayer | /* tlbld */
|
4359 | c7697e1f | j_mayer | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) |
4360 | 76a66253 | j_mayer | { |
4361 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4362 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4363 | 76a66253 | j_mayer | #else
|
4364 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4365 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4366 | 76a66253 | j_mayer | return;
|
4367 | 76a66253 | j_mayer | } |
4368 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4369 | 76a66253 | j_mayer | gen_op_6xx_tlbld(); |
4370 | 76a66253 | j_mayer | #endif
|
4371 | 76a66253 | j_mayer | } |
4372 | 76a66253 | j_mayer | |
4373 | 76a66253 | j_mayer | /* tlbli */
|
4374 | c7697e1f | j_mayer | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) |
4375 | 76a66253 | j_mayer | { |
4376 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4377 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4378 | 76a66253 | j_mayer | #else
|
4379 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4380 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4381 | 76a66253 | j_mayer | return;
|
4382 | 76a66253 | j_mayer | } |
4383 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4384 | 76a66253 | j_mayer | gen_op_6xx_tlbli(); |
4385 | 76a66253 | j_mayer | #endif
|
4386 | 76a66253 | j_mayer | } |
4387 | 76a66253 | j_mayer | |
4388 | 7dbe11ac | j_mayer | /* 74xx TLB management */
|
4389 | 7dbe11ac | j_mayer | /* tlbld */
|
4390 | c7697e1f | j_mayer | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) |
4391 | 7dbe11ac | j_mayer | { |
4392 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4393 | 7dbe11ac | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4394 | 7dbe11ac | j_mayer | #else
|
4395 | 7dbe11ac | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4396 | 7dbe11ac | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4397 | 7dbe11ac | j_mayer | return;
|
4398 | 7dbe11ac | j_mayer | } |
4399 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4400 | 7dbe11ac | j_mayer | gen_op_74xx_tlbld(); |
4401 | 7dbe11ac | j_mayer | #endif
|
4402 | 7dbe11ac | j_mayer | } |
4403 | 7dbe11ac | j_mayer | |
4404 | 7dbe11ac | j_mayer | /* tlbli */
|
4405 | c7697e1f | j_mayer | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) |
4406 | 7dbe11ac | j_mayer | { |
4407 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4408 | 7dbe11ac | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4409 | 7dbe11ac | j_mayer | #else
|
4410 | 7dbe11ac | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4411 | 7dbe11ac | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4412 | 7dbe11ac | j_mayer | return;
|
4413 | 7dbe11ac | j_mayer | } |
4414 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
|
4415 | 7dbe11ac | j_mayer | gen_op_74xx_tlbli(); |
4416 | 7dbe11ac | j_mayer | #endif
|
4417 | 7dbe11ac | j_mayer | } |
4418 | 7dbe11ac | j_mayer | |
4419 | 76a66253 | j_mayer | /* POWER instructions not in PowerPC 601 */
|
4420 | 76a66253 | j_mayer | /* clf */
|
4421 | 76a66253 | j_mayer | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER) |
4422 | 76a66253 | j_mayer | { |
4423 | 76a66253 | j_mayer | /* Cache line flush: implemented as no-op */
|
4424 | 76a66253 | j_mayer | } |
4425 | 76a66253 | j_mayer | |
4426 | 76a66253 | j_mayer | /* cli */
|
4427 | 76a66253 | j_mayer | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) |
4428 | 76a66253 | j_mayer | { |
4429 | 7f75ffd3 | blueswir1 | /* Cache line invalidate: privileged and treated as no-op */
|
4430 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4431 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4432 | 76a66253 | j_mayer | #else
|
4433 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4434 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4435 | 76a66253 | j_mayer | return;
|
4436 | 76a66253 | j_mayer | } |
4437 | 76a66253 | j_mayer | #endif
|
4438 | 76a66253 | j_mayer | } |
4439 | 76a66253 | j_mayer | |
4440 | 76a66253 | j_mayer | /* dclst */
|
4441 | 76a66253 | j_mayer | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER) |
4442 | 76a66253 | j_mayer | { |
4443 | 76a66253 | j_mayer | /* Data cache line store: treated as no-op */
|
4444 | 76a66253 | j_mayer | } |
4445 | 76a66253 | j_mayer | |
4446 | 76a66253 | j_mayer | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) |
4447 | 76a66253 | j_mayer | { |
4448 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4449 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4450 | 76a66253 | j_mayer | #else
|
4451 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4452 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4453 | 76a66253 | j_mayer | return;
|
4454 | 76a66253 | j_mayer | } |
4455 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4456 | 76a66253 | j_mayer | int rd = rD(ctx->opcode);
|
4457 | 76a66253 | j_mayer | |
4458 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4459 | 76a66253 | j_mayer | gen_op_POWER_mfsri(); |
4460 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
|
4461 | 76a66253 | j_mayer | if (ra != 0 && ra != rd) |
4462 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
|
4463 | 76a66253 | j_mayer | #endif
|
4464 | 76a66253 | j_mayer | } |
4465 | 76a66253 | j_mayer | |
4466 | 76a66253 | j_mayer | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) |
4467 | 76a66253 | j_mayer | { |
4468 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4469 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4470 | 76a66253 | j_mayer | #else
|
4471 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4472 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4473 | 76a66253 | j_mayer | return;
|
4474 | 76a66253 | j_mayer | } |
4475 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4476 | 76a66253 | j_mayer | gen_op_POWER_rac(); |
4477 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4478 | 76a66253 | j_mayer | #endif
|
4479 | 76a66253 | j_mayer | } |
4480 | 76a66253 | j_mayer | |
4481 | 76a66253 | j_mayer | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) |
4482 | 76a66253 | j_mayer | { |
4483 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4484 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4485 | 76a66253 | j_mayer | #else
|
4486 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4487 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4488 | 76a66253 | j_mayer | return;
|
4489 | 76a66253 | j_mayer | } |
4490 | 76a66253 | j_mayer | gen_op_POWER_rfsvc(); |
4491 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
4492 | 76a66253 | j_mayer | #endif
|
4493 | 76a66253 | j_mayer | } |
4494 | 76a66253 | j_mayer | |
4495 | 76a66253 | j_mayer | /* svc is not implemented for now */
|
4496 | 76a66253 | j_mayer | |
4497 | 76a66253 | j_mayer | /* POWER2 specific instructions */
|
4498 | 76a66253 | j_mayer | /* Quad manipulation (load/store two floats at a time) */
|
4499 | 7863667f | j_mayer | /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
|
4500 | 76a66253 | j_mayer | #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
|
4501 | 76a66253 | j_mayer | #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
|
4502 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
|
4503 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
|
4504 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
|
4505 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
|
4506 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
|
4507 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
|
4508 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
|
4509 | 7863667f | j_mayer | #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
|
4510 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
|
4511 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
|
4512 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
|
4513 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
|
4514 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
|
4515 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
|
4516 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
|
4517 | 7863667f | j_mayer | #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
|
4518 | 7863667f | j_mayer | static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
|
4519 | 7863667f | j_mayer | GEN_MEM_FUNCS(POWER2_lfq), |
4520 | 76a66253 | j_mayer | }; |
4521 | 7863667f | j_mayer | static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
|
4522 | 7863667f | j_mayer | GEN_MEM_FUNCS(POWER2_stfq), |
4523 | 76a66253 | j_mayer | }; |
4524 | 76a66253 | j_mayer | |
4525 | 76a66253 | j_mayer | /* lfq */
|
4526 | 76a66253 | j_mayer | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4527 | 76a66253 | j_mayer | { |
4528 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4529 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4530 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
4531 | 76a66253 | j_mayer | op_POWER2_lfq(); |
4532 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4533 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4534 | 76a66253 | j_mayer | } |
4535 | 76a66253 | j_mayer | |
4536 | 76a66253 | j_mayer | /* lfqu */
|
4537 | 76a66253 | j_mayer | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4538 | 76a66253 | j_mayer | { |
4539 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4540 | 76a66253 | j_mayer | |
4541 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4542 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4543 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
4544 | 76a66253 | j_mayer | op_POWER2_lfq(); |
4545 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4546 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4547 | 76a66253 | j_mayer | if (ra != 0) |
4548 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4549 | 76a66253 | j_mayer | } |
4550 | 76a66253 | j_mayer | |
4551 | 76a66253 | j_mayer | /* lfqux */
|
4552 | 76a66253 | j_mayer | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) |
4553 | 76a66253 | j_mayer | { |
4554 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4555 | 76a66253 | j_mayer | |
4556 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4557 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4558 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4559 | 76a66253 | j_mayer | op_POWER2_lfq(); |
4560 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4561 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4562 | 76a66253 | j_mayer | if (ra != 0) |
4563 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4564 | 76a66253 | j_mayer | } |
4565 | 76a66253 | j_mayer | |
4566 | 76a66253 | j_mayer | /* lfqx */
|
4567 | 76a66253 | j_mayer | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) |
4568 | 76a66253 | j_mayer | { |
4569 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4570 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4571 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4572 | 76a66253 | j_mayer | op_POWER2_lfq(); |
4573 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
|
4574 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); |
4575 | 76a66253 | j_mayer | } |
4576 | 76a66253 | j_mayer | |
4577 | 76a66253 | j_mayer | /* stfq */
|
4578 | 76a66253 | j_mayer | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4579 | 76a66253 | j_mayer | { |
4580 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4581 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4582 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
4583 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4584 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4585 | 76a66253 | j_mayer | op_POWER2_stfq(); |
4586 | 76a66253 | j_mayer | } |
4587 | 76a66253 | j_mayer | |
4588 | 76a66253 | j_mayer | /* stfqu */
|
4589 | 76a66253 | j_mayer | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) |
4590 | 76a66253 | j_mayer | { |
4591 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4592 | 76a66253 | j_mayer | |
4593 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4594 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4595 | 9d53c753 | j_mayer | gen_addr_imm_index(ctx, 0);
|
4596 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4597 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4598 | 76a66253 | j_mayer | op_POWER2_stfq(); |
4599 | 76a66253 | j_mayer | if (ra != 0) |
4600 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4601 | 76a66253 | j_mayer | } |
4602 | 76a66253 | j_mayer | |
4603 | 76a66253 | j_mayer | /* stfqux */
|
4604 | 76a66253 | j_mayer | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) |
4605 | 76a66253 | j_mayer | { |
4606 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
4607 | 76a66253 | j_mayer | |
4608 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4609 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4610 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4611 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4612 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4613 | 76a66253 | j_mayer | op_POWER2_stfq(); |
4614 | 76a66253 | j_mayer | if (ra != 0) |
4615 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
|
4616 | 76a66253 | j_mayer | } |
4617 | 76a66253 | j_mayer | |
4618 | 76a66253 | j_mayer | /* stfqx */
|
4619 | 76a66253 | j_mayer | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) |
4620 | 76a66253 | j_mayer | { |
4621 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4622 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4623 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4624 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
|
4625 | a5e26afa | aurel32 | tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); |
4626 | 76a66253 | j_mayer | op_POWER2_stfq(); |
4627 | 76a66253 | j_mayer | } |
4628 | 76a66253 | j_mayer | |
4629 | 76a66253 | j_mayer | /* BookE specific instructions */
|
4630 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
4631 | 05332d70 | j_mayer | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI) |
4632 | 76a66253 | j_mayer | { |
4633 | 76a66253 | j_mayer | /* XXX: TODO */
|
4634 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
4635 | 76a66253 | j_mayer | } |
4636 | 76a66253 | j_mayer | |
4637 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
4638 | 05332d70 | j_mayer | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) |
4639 | 76a66253 | j_mayer | { |
4640 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4641 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4642 | 76a66253 | j_mayer | #else
|
4643 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4644 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4645 | 76a66253 | j_mayer | return;
|
4646 | 76a66253 | j_mayer | } |
4647 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4648 | 76a66253 | j_mayer | /* Use the same micro-ops as for tlbie */
|
4649 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
4650 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
4651 | d9bce9d9 | j_mayer | gen_op_tlbie_64(); |
4652 | d9bce9d9 | j_mayer | else
|
4653 | d9bce9d9 | j_mayer | #endif
|
4654 | d9bce9d9 | j_mayer | gen_op_tlbie(); |
4655 | 76a66253 | j_mayer | #endif
|
4656 | 76a66253 | j_mayer | } |
4657 | 76a66253 | j_mayer | |
4658 | 76a66253 | j_mayer | /* All 405 MAC instructions are translated here */
|
4659 | b068d6a7 | j_mayer | static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
4660 | b068d6a7 | j_mayer | int opc2, int opc3, |
4661 | b068d6a7 | j_mayer | int ra, int rb, int rt, int Rc) |
4662 | 76a66253 | j_mayer | { |
4663 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
|
4664 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
|
4665 | 76a66253 | j_mayer | switch (opc3 & 0x0D) { |
4666 | 76a66253 | j_mayer | case 0x05: |
4667 | 76a66253 | j_mayer | /* macchw - macchw. - macchwo - macchwo. */
|
4668 | 76a66253 | j_mayer | /* macchws - macchws. - macchwso - macchwso. */
|
4669 | 76a66253 | j_mayer | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
4670 | 76a66253 | j_mayer | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
4671 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
4672 | 76a66253 | j_mayer | gen_op_405_mulchw(); |
4673 | 76a66253 | j_mayer | break;
|
4674 | 76a66253 | j_mayer | case 0x04: |
4675 | 76a66253 | j_mayer | /* macchwu - macchwu. - macchwuo - macchwuo. */
|
4676 | 76a66253 | j_mayer | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
4677 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
4678 | 76a66253 | j_mayer | gen_op_405_mulchwu(); |
4679 | 76a66253 | j_mayer | break;
|
4680 | 76a66253 | j_mayer | case 0x01: |
4681 | 76a66253 | j_mayer | /* machhw - machhw. - machhwo - machhwo. */
|
4682 | 76a66253 | j_mayer | /* machhws - machhws. - machhwso - machhwso. */
|
4683 | 76a66253 | j_mayer | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
4684 | 76a66253 | j_mayer | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
4685 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
4686 | 76a66253 | j_mayer | gen_op_405_mulhhw(); |
4687 | 76a66253 | j_mayer | break;
|
4688 | 76a66253 | j_mayer | case 0x00: |
4689 | 76a66253 | j_mayer | /* machhwu - machhwu. - machhwuo - machhwuo. */
|
4690 | 76a66253 | j_mayer | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
4691 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
4692 | 76a66253 | j_mayer | gen_op_405_mulhhwu(); |
4693 | 76a66253 | j_mayer | break;
|
4694 | 76a66253 | j_mayer | case 0x0D: |
4695 | 76a66253 | j_mayer | /* maclhw - maclhw. - maclhwo - maclhwo. */
|
4696 | 76a66253 | j_mayer | /* maclhws - maclhws. - maclhwso - maclhwso. */
|
4697 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
4698 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
4699 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
4700 | 76a66253 | j_mayer | gen_op_405_mullhw(); |
4701 | 76a66253 | j_mayer | break;
|
4702 | 76a66253 | j_mayer | case 0x0C: |
4703 | 76a66253 | j_mayer | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
4704 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
4705 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
4706 | 76a66253 | j_mayer | gen_op_405_mullhwu(); |
4707 | 76a66253 | j_mayer | break;
|
4708 | 76a66253 | j_mayer | } |
4709 | 76a66253 | j_mayer | if (opc2 & 0x02) { |
4710 | 76a66253 | j_mayer | /* nmultiply-and-accumulate (0x0E) */
|
4711 | 76a66253 | j_mayer | gen_op_neg(); |
4712 | 76a66253 | j_mayer | } |
4713 | 76a66253 | j_mayer | if (opc2 & 0x04) { |
4714 | 76a66253 | j_mayer | /* (n)multiply-and-accumulate (0x0C - 0x0E) */
|
4715 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
|
4716 | e55fd934 | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
4717 | 76a66253 | j_mayer | gen_op_405_add_T0_T2(); |
4718 | 76a66253 | j_mayer | } |
4719 | 76a66253 | j_mayer | if (opc3 & 0x10) { |
4720 | 76a66253 | j_mayer | /* Check overflow */
|
4721 | 76a66253 | j_mayer | if (opc3 & 0x01) |
4722 | c3e10c7b | j_mayer | gen_op_check_addo(); |
4723 | 76a66253 | j_mayer | else
|
4724 | 76a66253 | j_mayer | gen_op_405_check_ovu(); |
4725 | 76a66253 | j_mayer | } |
4726 | 76a66253 | j_mayer | if (opc3 & 0x02) { |
4727 | 76a66253 | j_mayer | /* Saturate */
|
4728 | 76a66253 | j_mayer | if (opc3 & 0x01) |
4729 | 76a66253 | j_mayer | gen_op_405_check_sat(); |
4730 | 76a66253 | j_mayer | else
|
4731 | 76a66253 | j_mayer | gen_op_405_check_satu(); |
4732 | 76a66253 | j_mayer | } |
4733 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
|
4734 | 76a66253 | j_mayer | if (unlikely(Rc) != 0) { |
4735 | 76a66253 | j_mayer | /* Update Rc0 */
|
4736 | 76a66253 | j_mayer | gen_set_Rc0(ctx); |
4737 | 76a66253 | j_mayer | } |
4738 | 76a66253 | j_mayer | } |
4739 | 76a66253 | j_mayer | |
4740 | a750fc0b | j_mayer | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
4741 | a750fc0b | j_mayer | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ |
4742 | 76a66253 | j_mayer | { \ |
4743 | 76a66253 | j_mayer | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
4744 | 76a66253 | j_mayer | rD(ctx->opcode), Rc(ctx->opcode)); \ |
4745 | 76a66253 | j_mayer | } |
4746 | 76a66253 | j_mayer | |
4747 | 76a66253 | j_mayer | /* macchw - macchw. */
|
4748 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
4749 | 76a66253 | j_mayer | /* macchwo - macchwo. */
|
4750 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
4751 | 76a66253 | j_mayer | /* macchws - macchws. */
|
4752 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
4753 | 76a66253 | j_mayer | /* macchwso - macchwso. */
|
4754 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
4755 | 76a66253 | j_mayer | /* macchwsu - macchwsu. */
|
4756 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
4757 | 76a66253 | j_mayer | /* macchwsuo - macchwsuo. */
|
4758 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
4759 | 76a66253 | j_mayer | /* macchwu - macchwu. */
|
4760 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
4761 | 76a66253 | j_mayer | /* macchwuo - macchwuo. */
|
4762 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
4763 | 76a66253 | j_mayer | /* machhw - machhw. */
|
4764 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
4765 | 76a66253 | j_mayer | /* machhwo - machhwo. */
|
4766 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
4767 | 76a66253 | j_mayer | /* machhws - machhws. */
|
4768 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
4769 | 76a66253 | j_mayer | /* machhwso - machhwso. */
|
4770 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
4771 | 76a66253 | j_mayer | /* machhwsu - machhwsu. */
|
4772 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
4773 | 76a66253 | j_mayer | /* machhwsuo - machhwsuo. */
|
4774 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
4775 | 76a66253 | j_mayer | /* machhwu - machhwu. */
|
4776 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
4777 | 76a66253 | j_mayer | /* machhwuo - machhwuo. */
|
4778 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
4779 | 76a66253 | j_mayer | /* maclhw - maclhw. */
|
4780 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
4781 | 76a66253 | j_mayer | /* maclhwo - maclhwo. */
|
4782 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
4783 | 76a66253 | j_mayer | /* maclhws - maclhws. */
|
4784 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
4785 | 76a66253 | j_mayer | /* maclhwso - maclhwso. */
|
4786 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
4787 | 76a66253 | j_mayer | /* maclhwu - maclhwu. */
|
4788 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
4789 | 76a66253 | j_mayer | /* maclhwuo - maclhwuo. */
|
4790 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
4791 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. */
|
4792 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
4793 | 76a66253 | j_mayer | /* maclhwsuo - maclhwsuo. */
|
4794 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
4795 | 76a66253 | j_mayer | /* nmacchw - nmacchw. */
|
4796 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
4797 | 76a66253 | j_mayer | /* nmacchwo - nmacchwo. */
|
4798 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
4799 | 76a66253 | j_mayer | /* nmacchws - nmacchws. */
|
4800 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
4801 | 76a66253 | j_mayer | /* nmacchwso - nmacchwso. */
|
4802 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
4803 | 76a66253 | j_mayer | /* nmachhw - nmachhw. */
|
4804 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
4805 | 76a66253 | j_mayer | /* nmachhwo - nmachhwo. */
|
4806 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
4807 | 76a66253 | j_mayer | /* nmachhws - nmachhws. */
|
4808 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
4809 | 76a66253 | j_mayer | /* nmachhwso - nmachhwso. */
|
4810 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
4811 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. */
|
4812 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
4813 | 76a66253 | j_mayer | /* nmaclhwo - nmaclhwo. */
|
4814 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
4815 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. */
|
4816 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
4817 | 76a66253 | j_mayer | /* nmaclhwso - nmaclhwso. */
|
4818 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
4819 | 76a66253 | j_mayer | |
4820 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
4821 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
4822 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
4823 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
4824 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
4825 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
4826 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
4827 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
4828 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
4829 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
4830 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
4831 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
4832 | 76a66253 | j_mayer | |
4833 | 76a66253 | j_mayer | /* mfdcr */
|
4834 | 05332d70 | j_mayer | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) |
4835 | 76a66253 | j_mayer | { |
4836 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4837 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4838 | 76a66253 | j_mayer | #else
|
4839 | 76a66253 | j_mayer | uint32_t dcrn = SPR(ctx->opcode); |
4840 | 76a66253 | j_mayer | |
4841 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4842 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4843 | 76a66253 | j_mayer | return;
|
4844 | 76a66253 | j_mayer | } |
4845 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[0], dcrn);
|
4846 | a42bd6cc | j_mayer | gen_op_load_dcr(); |
4847 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4848 | 76a66253 | j_mayer | #endif
|
4849 | 76a66253 | j_mayer | } |
4850 | 76a66253 | j_mayer | |
4851 | 76a66253 | j_mayer | /* mtdcr */
|
4852 | 05332d70 | j_mayer | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) |
4853 | 76a66253 | j_mayer | { |
4854 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4855 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4856 | 76a66253 | j_mayer | #else
|
4857 | 76a66253 | j_mayer | uint32_t dcrn = SPR(ctx->opcode); |
4858 | 76a66253 | j_mayer | |
4859 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4860 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4861 | 76a66253 | j_mayer | return;
|
4862 | 76a66253 | j_mayer | } |
4863 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[0], dcrn);
|
4864 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4865 | a42bd6cc | j_mayer | gen_op_store_dcr(); |
4866 | a42bd6cc | j_mayer | #endif
|
4867 | a42bd6cc | j_mayer | } |
4868 | a42bd6cc | j_mayer | |
4869 | a42bd6cc | j_mayer | /* mfdcrx */
|
4870 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
4871 | 05332d70 | j_mayer | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) |
4872 | a42bd6cc | j_mayer | { |
4873 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4874 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4875 | a42bd6cc | j_mayer | #else
|
4876 | a42bd6cc | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4877 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4878 | a42bd6cc | j_mayer | return;
|
4879 | a42bd6cc | j_mayer | } |
4880 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4881 | a42bd6cc | j_mayer | gen_op_load_dcr(); |
4882 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4883 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
4884 | a42bd6cc | j_mayer | #endif
|
4885 | a42bd6cc | j_mayer | } |
4886 | a42bd6cc | j_mayer | |
4887 | a42bd6cc | j_mayer | /* mtdcrx */
|
4888 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
4889 | 05332d70 | j_mayer | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) |
4890 | a42bd6cc | j_mayer | { |
4891 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4892 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4893 | a42bd6cc | j_mayer | #else
|
4894 | a42bd6cc | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4895 | e1833e1f | j_mayer | GEN_EXCP_PRIVREG(ctx); |
4896 | a42bd6cc | j_mayer | return;
|
4897 | a42bd6cc | j_mayer | } |
4898 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4899 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4900 | a42bd6cc | j_mayer | gen_op_store_dcr(); |
4901 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
4902 | 76a66253 | j_mayer | #endif
|
4903 | 76a66253 | j_mayer | } |
4904 | 76a66253 | j_mayer | |
4905 | a750fc0b | j_mayer | /* mfdcrux (PPC 460) : user-mode access to DCR */
|
4906 | a750fc0b | j_mayer | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) |
4907 | a750fc0b | j_mayer | { |
4908 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4909 | a750fc0b | j_mayer | gen_op_load_dcr(); |
4910 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4911 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
4912 | a750fc0b | j_mayer | } |
4913 | a750fc0b | j_mayer | |
4914 | a750fc0b | j_mayer | /* mtdcrux (PPC 460) : user-mode access to DCR */
|
4915 | a750fc0b | j_mayer | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) |
4916 | a750fc0b | j_mayer | { |
4917 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
4918 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
4919 | a750fc0b | j_mayer | gen_op_store_dcr(); |
4920 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
4921 | a750fc0b | j_mayer | } |
4922 | a750fc0b | j_mayer | |
4923 | 76a66253 | j_mayer | /* dccci */
|
4924 | 76a66253 | j_mayer | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) |
4925 | 76a66253 | j_mayer | { |
4926 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4927 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4928 | 76a66253 | j_mayer | #else
|
4929 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4930 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4931 | 76a66253 | j_mayer | return;
|
4932 | 76a66253 | j_mayer | } |
4933 | 76a66253 | j_mayer | /* interpreted as no-op */
|
4934 | 76a66253 | j_mayer | #endif
|
4935 | 76a66253 | j_mayer | } |
4936 | 76a66253 | j_mayer | |
4937 | 76a66253 | j_mayer | /* dcread */
|
4938 | 76a66253 | j_mayer | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) |
4939 | 76a66253 | j_mayer | { |
4940 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4941 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4942 | 76a66253 | j_mayer | #else
|
4943 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4944 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4945 | 76a66253 | j_mayer | return;
|
4946 | 76a66253 | j_mayer | } |
4947 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
4948 | 76a66253 | j_mayer | op_ldst(lwz); |
4949 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
4950 | 76a66253 | j_mayer | #endif
|
4951 | 76a66253 | j_mayer | } |
4952 | 76a66253 | j_mayer | |
4953 | 76a66253 | j_mayer | /* icbt */
|
4954 | c7697e1f | j_mayer | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) |
4955 | 76a66253 | j_mayer | { |
4956 | 76a66253 | j_mayer | /* interpreted as no-op */
|
4957 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
4958 | 76a66253 | j_mayer | * but does not generate any exception
|
4959 | 76a66253 | j_mayer | */
|
4960 | 76a66253 | j_mayer | } |
4961 | 76a66253 | j_mayer | |
4962 | 76a66253 | j_mayer | /* iccci */
|
4963 | 76a66253 | j_mayer | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) |
4964 | 76a66253 | j_mayer | { |
4965 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4966 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4967 | 76a66253 | j_mayer | #else
|
4968 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4969 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4970 | 76a66253 | j_mayer | return;
|
4971 | 76a66253 | j_mayer | } |
4972 | 76a66253 | j_mayer | /* interpreted as no-op */
|
4973 | 76a66253 | j_mayer | #endif
|
4974 | 76a66253 | j_mayer | } |
4975 | 76a66253 | j_mayer | |
4976 | 76a66253 | j_mayer | /* icread */
|
4977 | 76a66253 | j_mayer | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) |
4978 | 76a66253 | j_mayer | { |
4979 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4980 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4981 | 76a66253 | j_mayer | #else
|
4982 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4983 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4984 | 76a66253 | j_mayer | return;
|
4985 | 76a66253 | j_mayer | } |
4986 | 76a66253 | j_mayer | /* interpreted as no-op */
|
4987 | 76a66253 | j_mayer | #endif
|
4988 | 76a66253 | j_mayer | } |
4989 | 76a66253 | j_mayer | |
4990 | 76a66253 | j_mayer | /* rfci (supervisor only) */
|
4991 | c7697e1f | j_mayer | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) |
4992 | a42bd6cc | j_mayer | { |
4993 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4994 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4995 | a42bd6cc | j_mayer | #else
|
4996 | a42bd6cc | j_mayer | if (unlikely(!ctx->supervisor)) {
|
4997 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
4998 | a42bd6cc | j_mayer | return;
|
4999 | a42bd6cc | j_mayer | } |
5000 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5001 | a42bd6cc | j_mayer | gen_op_40x_rfci(); |
5002 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
5003 | a42bd6cc | j_mayer | #endif
|
5004 | a42bd6cc | j_mayer | } |
5005 | a42bd6cc | j_mayer | |
5006 | a42bd6cc | j_mayer | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) |
5007 | a42bd6cc | j_mayer | { |
5008 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5009 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5010 | a42bd6cc | j_mayer | #else
|
5011 | a42bd6cc | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5012 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5013 | a42bd6cc | j_mayer | return;
|
5014 | a42bd6cc | j_mayer | } |
5015 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5016 | a42bd6cc | j_mayer | gen_op_rfci(); |
5017 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
5018 | a42bd6cc | j_mayer | #endif
|
5019 | a42bd6cc | j_mayer | } |
5020 | a42bd6cc | j_mayer | |
5021 | a42bd6cc | j_mayer | /* BookE specific */
|
5022 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5023 | 05332d70 | j_mayer | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) |
5024 | 76a66253 | j_mayer | { |
5025 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5026 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5027 | 76a66253 | j_mayer | #else
|
5028 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5029 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5030 | 76a66253 | j_mayer | return;
|
5031 | 76a66253 | j_mayer | } |
5032 | 76a66253 | j_mayer | /* Restore CPU state */
|
5033 | a42bd6cc | j_mayer | gen_op_rfdi(); |
5034 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
5035 | 76a66253 | j_mayer | #endif
|
5036 | 76a66253 | j_mayer | } |
5037 | 76a66253 | j_mayer | |
5038 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5039 | a750fc0b | j_mayer | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) |
5040 | a42bd6cc | j_mayer | { |
5041 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5042 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5043 | a42bd6cc | j_mayer | #else
|
5044 | a42bd6cc | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5045 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5046 | a42bd6cc | j_mayer | return;
|
5047 | a42bd6cc | j_mayer | } |
5048 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5049 | a42bd6cc | j_mayer | gen_op_rfmci(); |
5050 | e1833e1f | j_mayer | GEN_SYNC(ctx); |
5051 | a42bd6cc | j_mayer | #endif
|
5052 | a42bd6cc | j_mayer | } |
5053 | 5eb7995e | j_mayer | |
5054 | d9bce9d9 | j_mayer | /* TLB management - PowerPC 405 implementation */
|
5055 | 76a66253 | j_mayer | /* tlbre */
|
5056 | c7697e1f | j_mayer | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) |
5057 | 76a66253 | j_mayer | { |
5058 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5059 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5060 | 76a66253 | j_mayer | #else
|
5061 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5062 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5063 | 76a66253 | j_mayer | return;
|
5064 | 76a66253 | j_mayer | } |
5065 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5066 | 76a66253 | j_mayer | case 0: |
5067 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5068 | 76a66253 | j_mayer | gen_op_4xx_tlbre_hi(); |
5069 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5070 | 76a66253 | j_mayer | break;
|
5071 | 76a66253 | j_mayer | case 1: |
5072 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5073 | 76a66253 | j_mayer | gen_op_4xx_tlbre_lo(); |
5074 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5075 | 76a66253 | j_mayer | break;
|
5076 | 76a66253 | j_mayer | default:
|
5077 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
5078 | 76a66253 | j_mayer | break;
|
5079 | 9a64fbe4 | bellard | } |
5080 | 76a66253 | j_mayer | #endif
|
5081 | 76a66253 | j_mayer | } |
5082 | 76a66253 | j_mayer | |
5083 | d9bce9d9 | j_mayer | /* tlbsx - tlbsx. */
|
5084 | c7697e1f | j_mayer | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) |
5085 | 76a66253 | j_mayer | { |
5086 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5087 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5088 | 76a66253 | j_mayer | #else
|
5089 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5090 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5091 | 76a66253 | j_mayer | return;
|
5092 | 76a66253 | j_mayer | } |
5093 | 76a66253 | j_mayer | gen_addr_reg_index(ctx); |
5094 | daf4f96e | j_mayer | gen_op_4xx_tlbsx(); |
5095 | 76a66253 | j_mayer | if (Rc(ctx->opcode))
|
5096 | daf4f96e | j_mayer | gen_op_4xx_tlbsx_check(); |
5097 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5098 | 76a66253 | j_mayer | #endif
|
5099 | 79aceca5 | bellard | } |
5100 | 79aceca5 | bellard | |
5101 | 76a66253 | j_mayer | /* tlbwe */
|
5102 | c7697e1f | j_mayer | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) |
5103 | 79aceca5 | bellard | { |
5104 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5105 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5106 | 76a66253 | j_mayer | #else
|
5107 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5108 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5109 | 76a66253 | j_mayer | return;
|
5110 | 76a66253 | j_mayer | } |
5111 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5112 | 76a66253 | j_mayer | case 0: |
5113 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5114 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5115 | 76a66253 | j_mayer | gen_op_4xx_tlbwe_hi(); |
5116 | 76a66253 | j_mayer | break;
|
5117 | 76a66253 | j_mayer | case 1: |
5118 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5119 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5120 | 76a66253 | j_mayer | gen_op_4xx_tlbwe_lo(); |
5121 | 76a66253 | j_mayer | break;
|
5122 | 76a66253 | j_mayer | default:
|
5123 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
5124 | 76a66253 | j_mayer | break;
|
5125 | 9a64fbe4 | bellard | } |
5126 | 76a66253 | j_mayer | #endif
|
5127 | 76a66253 | j_mayer | } |
5128 | 76a66253 | j_mayer | |
5129 | a4bb6c3e | j_mayer | /* TLB management - PowerPC 440 implementation */
|
5130 | 5eb7995e | j_mayer | /* tlbre */
|
5131 | c7697e1f | j_mayer | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) |
5132 | 5eb7995e | j_mayer | { |
5133 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5134 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5135 | 5eb7995e | j_mayer | #else
|
5136 | 5eb7995e | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5137 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5138 | 5eb7995e | j_mayer | return;
|
5139 | 5eb7995e | j_mayer | } |
5140 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5141 | 5eb7995e | j_mayer | case 0: |
5142 | 5eb7995e | j_mayer | case 1: |
5143 | 5eb7995e | j_mayer | case 2: |
5144 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5145 | a4bb6c3e | j_mayer | gen_op_440_tlbre(rB(ctx->opcode)); |
5146 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5147 | 5eb7995e | j_mayer | break;
|
5148 | 5eb7995e | j_mayer | default:
|
5149 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
5150 | 5eb7995e | j_mayer | break;
|
5151 | 5eb7995e | j_mayer | } |
5152 | 5eb7995e | j_mayer | #endif
|
5153 | 5eb7995e | j_mayer | } |
5154 | 5eb7995e | j_mayer | |
5155 | 5eb7995e | j_mayer | /* tlbsx - tlbsx. */
|
5156 | c7697e1f | j_mayer | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) |
5157 | 5eb7995e | j_mayer | { |
5158 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5159 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5160 | 5eb7995e | j_mayer | #else
|
5161 | 5eb7995e | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5162 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5163 | 5eb7995e | j_mayer | return;
|
5164 | 5eb7995e | j_mayer | } |
5165 | 5eb7995e | j_mayer | gen_addr_reg_index(ctx); |
5166 | daf4f96e | j_mayer | gen_op_440_tlbsx(); |
5167 | 5eb7995e | j_mayer | if (Rc(ctx->opcode))
|
5168 | daf4f96e | j_mayer | gen_op_4xx_tlbsx_check(); |
5169 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5170 | 5eb7995e | j_mayer | #endif
|
5171 | 5eb7995e | j_mayer | } |
5172 | 5eb7995e | j_mayer | |
5173 | 5eb7995e | j_mayer | /* tlbwe */
|
5174 | c7697e1f | j_mayer | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) |
5175 | 5eb7995e | j_mayer | { |
5176 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5177 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5178 | 5eb7995e | j_mayer | #else
|
5179 | 5eb7995e | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5180 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5181 | 5eb7995e | j_mayer | return;
|
5182 | 5eb7995e | j_mayer | } |
5183 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5184 | 5eb7995e | j_mayer | case 0: |
5185 | 5eb7995e | j_mayer | case 1: |
5186 | 5eb7995e | j_mayer | case 2: |
5187 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5188 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
|
5189 | a4bb6c3e | j_mayer | gen_op_440_tlbwe(rB(ctx->opcode)); |
5190 | 5eb7995e | j_mayer | break;
|
5191 | 5eb7995e | j_mayer | default:
|
5192 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
5193 | 5eb7995e | j_mayer | break;
|
5194 | 5eb7995e | j_mayer | } |
5195 | 5eb7995e | j_mayer | #endif
|
5196 | 5eb7995e | j_mayer | } |
5197 | 5eb7995e | j_mayer | |
5198 | 76a66253 | j_mayer | /* wrtee */
|
5199 | 05332d70 | j_mayer | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) |
5200 | 76a66253 | j_mayer | { |
5201 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5202 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5203 | 76a66253 | j_mayer | #else
|
5204 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5205 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5206 | 76a66253 | j_mayer | return;
|
5207 | 76a66253 | j_mayer | } |
5208 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
|
5209 | a42bd6cc | j_mayer | gen_op_wrte(); |
5210 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
5211 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
5212 | dee96f6c | j_mayer | */
|
5213 | e1833e1f | j_mayer | GEN_STOP(ctx); |
5214 | 76a66253 | j_mayer | #endif
|
5215 | 76a66253 | j_mayer | } |
5216 | 76a66253 | j_mayer | |
5217 | 76a66253 | j_mayer | /* wrteei */
|
5218 | 05332d70 | j_mayer | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) |
5219 | 76a66253 | j_mayer | { |
5220 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5221 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5222 | 76a66253 | j_mayer | #else
|
5223 | 76a66253 | j_mayer | if (unlikely(!ctx->supervisor)) {
|
5224 | e1833e1f | j_mayer | GEN_EXCP_PRIVOPC(ctx); |
5225 | 76a66253 | j_mayer | return;
|
5226 | 76a66253 | j_mayer | } |
5227 | 86c581dc | aurel32 | tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000); |
5228 | a42bd6cc | j_mayer | gen_op_wrte(); |
5229 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
5230 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
5231 | dee96f6c | j_mayer | */
|
5232 | e1833e1f | j_mayer | GEN_STOP(ctx); |
5233 | 76a66253 | j_mayer | #endif
|
5234 | 76a66253 | j_mayer | } |
5235 | 76a66253 | j_mayer | |
5236 | 08e46e54 | j_mayer | /* PowerPC 440 specific instructions */
|
5237 | 76a66253 | j_mayer | /* dlmzb */
|
5238 | 76a66253 | j_mayer | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) |
5239 | 76a66253 | j_mayer | { |
5240 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
|
5241 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
5242 | 76a66253 | j_mayer | gen_op_440_dlmzb(); |
5243 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
|
5244 | 76a66253 | j_mayer | gen_op_store_xer_bc(); |
5245 | 76a66253 | j_mayer | if (Rc(ctx->opcode)) {
|
5246 | 76a66253 | j_mayer | gen_op_440_dlmzb_update_Rc(); |
5247 | 76a66253 | j_mayer | gen_op_store_T0_crf(0);
|
5248 | 76a66253 | j_mayer | } |
5249 | 76a66253 | j_mayer | } |
5250 | 76a66253 | j_mayer | |
5251 | 76a66253 | j_mayer | /* mbar replaces eieio on 440 */
|
5252 | 76a66253 | j_mayer | GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE) |
5253 | 76a66253 | j_mayer | { |
5254 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5255 | 76a66253 | j_mayer | } |
5256 | 76a66253 | j_mayer | |
5257 | 76a66253 | j_mayer | /* msync replaces sync on 440 */
|
5258 | 0db1b20e | j_mayer | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE) |
5259 | 76a66253 | j_mayer | { |
5260 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5261 | 76a66253 | j_mayer | } |
5262 | 76a66253 | j_mayer | |
5263 | 76a66253 | j_mayer | /* icbt */
|
5264 | c7697e1f | j_mayer | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) |
5265 | 76a66253 | j_mayer | { |
5266 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5267 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
5268 | 76a66253 | j_mayer | * but does not generate any exception
|
5269 | 76a66253 | j_mayer | */
|
5270 | 79aceca5 | bellard | } |
5271 | 79aceca5 | bellard | |
5272 | a9d9eb8f | j_mayer | /*** Altivec vector extension ***/
|
5273 | a9d9eb8f | j_mayer | /* Altivec registers moves */
|
5274 | a9d9eb8f | j_mayer | |
5275 | 1d542695 | aurel32 | static always_inline void gen_load_avr(int t, int reg) { |
5276 | 1d542695 | aurel32 | tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); |
5277 | 1d542695 | aurel32 | tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); |
5278 | 1d542695 | aurel32 | } |
5279 | 1d542695 | aurel32 | |
5280 | 1d542695 | aurel32 | static always_inline void gen_store_avr(int reg, int t) { |
5281 | 1d542695 | aurel32 | tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); |
5282 | 1d542695 | aurel32 | tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); |
5283 | 1d542695 | aurel32 | } |
5284 | a9d9eb8f | j_mayer | |
5285 | a9d9eb8f | j_mayer | #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
5286 | a9d9eb8f | j_mayer | #define OP_VR_LD_TABLE(name) \
|
5287 | 7863667f | j_mayer | static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \ |
5288 | 7863667f | j_mayer | GEN_MEM_FUNCS(vr_l##name), \ |
5289 | a9d9eb8f | j_mayer | }; |
5290 | a9d9eb8f | j_mayer | #define OP_VR_ST_TABLE(name) \
|
5291 | 7863667f | j_mayer | static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \ |
5292 | 7863667f | j_mayer | GEN_MEM_FUNCS(vr_st##name), \ |
5293 | a9d9eb8f | j_mayer | }; |
5294 | a9d9eb8f | j_mayer | |
5295 | a9d9eb8f | j_mayer | #define GEN_VR_LDX(name, opc2, opc3) \
|
5296 | a9d9eb8f | j_mayer | GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
5297 | a9d9eb8f | j_mayer | { \ |
5298 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
5299 | a9d9eb8f | j_mayer | GEN_EXCP_NO_VR(ctx); \ |
5300 | a9d9eb8f | j_mayer | return; \
|
5301 | a9d9eb8f | j_mayer | } \ |
5302 | a9d9eb8f | j_mayer | gen_addr_reg_index(ctx); \ |
5303 | a9d9eb8f | j_mayer | op_vr_ldst(vr_l##name); \ |
5304 | 1d542695 | aurel32 | gen_store_avr(rD(ctx->opcode), 0); \
|
5305 | a9d9eb8f | j_mayer | } |
5306 | a9d9eb8f | j_mayer | |
5307 | a9d9eb8f | j_mayer | #define GEN_VR_STX(name, opc2, opc3) \
|
5308 | a9d9eb8f | j_mayer | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ |
5309 | a9d9eb8f | j_mayer | { \ |
5310 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
5311 | a9d9eb8f | j_mayer | GEN_EXCP_NO_VR(ctx); \ |
5312 | a9d9eb8f | j_mayer | return; \
|
5313 | a9d9eb8f | j_mayer | } \ |
5314 | a9d9eb8f | j_mayer | gen_addr_reg_index(ctx); \ |
5315 | 1d542695 | aurel32 | gen_load_avr(0, rS(ctx->opcode)); \
|
5316 | a9d9eb8f | j_mayer | op_vr_ldst(vr_st##name); \ |
5317 | a9d9eb8f | j_mayer | } |
5318 | a9d9eb8f | j_mayer | |
5319 | a9d9eb8f | j_mayer | OP_VR_LD_TABLE(vx); |
5320 | a9d9eb8f | j_mayer | GEN_VR_LDX(vx, 0x07, 0x03); |
5321 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
5322 | a9d9eb8f | j_mayer | #define gen_op_vr_lvxl gen_op_vr_lvx
|
5323 | a9d9eb8f | j_mayer | GEN_VR_LDX(vxl, 0x07, 0x0B); |
5324 | a9d9eb8f | j_mayer | |
5325 | a9d9eb8f | j_mayer | OP_VR_ST_TABLE(vx); |
5326 | a9d9eb8f | j_mayer | GEN_VR_STX(vx, 0x07, 0x07); |
5327 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
5328 | a9d9eb8f | j_mayer | #define gen_op_vr_stvxl gen_op_vr_stvx
|
5329 | a9d9eb8f | j_mayer | GEN_VR_STX(vxl, 0x07, 0x0F); |
5330 | a9d9eb8f | j_mayer | |
5331 | 0487d6a8 | j_mayer | /*** SPE extension ***/
|
5332 | 0487d6a8 | j_mayer | /* Register moves */
|
5333 | 3cd7d1dd | j_mayer | |
5334 | f78fb44e | aurel32 | static always_inline void gen_load_gpr64(TCGv t, int reg) { |
5335 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
5336 | f78fb44e | aurel32 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
5337 | f78fb44e | aurel32 | #else
|
5338 | f78fb44e | aurel32 | tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); |
5339 | f78fb44e | aurel32 | tcg_gen_shli_i64(t, t, 32);
|
5340 | f78fb44e | aurel32 | TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); |
5341 | f78fb44e | aurel32 | tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); |
5342 | f78fb44e | aurel32 | tcg_gen_or_i64(t, t, tmp); |
5343 | f78fb44e | aurel32 | tcg_temp_free(tmp); |
5344 | 3cd7d1dd | j_mayer | #endif
|
5345 | f78fb44e | aurel32 | } |
5346 | 3cd7d1dd | j_mayer | |
5347 | f78fb44e | aurel32 | static always_inline void gen_store_gpr64(int reg, TCGv t) { |
5348 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
5349 | f78fb44e | aurel32 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
5350 | f78fb44e | aurel32 | #else
|
5351 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
5352 | f78fb44e | aurel32 | TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); |
5353 | f78fb44e | aurel32 | tcg_gen_shri_i64(tmp, t, 32);
|
5354 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
5355 | f78fb44e | aurel32 | tcg_temp_free(tmp); |
5356 | 3cd7d1dd | j_mayer | #endif
|
5357 | f78fb44e | aurel32 | } |
5358 | 3cd7d1dd | j_mayer | |
5359 | 0487d6a8 | j_mayer | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
5360 | 0487d6a8 | j_mayer | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ |
5361 | 0487d6a8 | j_mayer | { \ |
5362 | 0487d6a8 | j_mayer | if (Rc(ctx->opcode)) \
|
5363 | 0487d6a8 | j_mayer | gen_##name1(ctx); \ |
5364 | 0487d6a8 | j_mayer | else \
|
5365 | 0487d6a8 | j_mayer | gen_##name0(ctx); \ |
5366 | 0487d6a8 | j_mayer | } |
5367 | 0487d6a8 | j_mayer | |
5368 | 0487d6a8 | j_mayer | /* Handler for undefined SPE opcodes */
|
5369 | b068d6a7 | j_mayer | static always_inline void gen_speundef (DisasContext *ctx) |
5370 | 0487d6a8 | j_mayer | { |
5371 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctx); |
5372 | 0487d6a8 | j_mayer | } |
5373 | 0487d6a8 | j_mayer | |
5374 | 0487d6a8 | j_mayer | /* SPE load and stores */
|
5375 | b068d6a7 | j_mayer | static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) |
5376 | 0487d6a8 | j_mayer | { |
5377 | 0487d6a8 | j_mayer | target_long simm = rB(ctx->opcode); |
5378 | 0487d6a8 | j_mayer | |
5379 | 0487d6a8 | j_mayer | if (rA(ctx->opcode) == 0) { |
5380 | 02f4f6c2 | aurel32 | tcg_gen_movi_tl(cpu_T[0], simm << sh);
|
5381 | 0487d6a8 | j_mayer | } else {
|
5382 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5383 | 0487d6a8 | j_mayer | if (likely(simm != 0)) |
5384 | 0487d6a8 | j_mayer | gen_op_addi(simm << sh); |
5385 | 0487d6a8 | j_mayer | } |
5386 | 0487d6a8 | j_mayer | } |
5387 | 0487d6a8 | j_mayer | |
5388 | 0487d6a8 | j_mayer | #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
5389 | 0487d6a8 | j_mayer | #define OP_SPE_LD_TABLE(name) \
|
5390 | 7863667f | j_mayer | static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \ |
5391 | 7863667f | j_mayer | GEN_MEM_FUNCS(spe_l##name), \ |
5392 | 0487d6a8 | j_mayer | }; |
5393 | 0487d6a8 | j_mayer | #define OP_SPE_ST_TABLE(name) \
|
5394 | 7863667f | j_mayer | static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \ |
5395 | 7863667f | j_mayer | GEN_MEM_FUNCS(spe_st##name), \ |
5396 | 2857068e | j_mayer | }; |
5397 | 0487d6a8 | j_mayer | |
5398 | 0487d6a8 | j_mayer | #define GEN_SPE_LD(name, sh) \
|
5399 | b068d6a7 | j_mayer | static always_inline void gen_evl##name (DisasContext *ctx) \ |
5400 | 0487d6a8 | j_mayer | { \ |
5401 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5402 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5403 | 0487d6a8 | j_mayer | return; \
|
5404 | 0487d6a8 | j_mayer | } \ |
5405 | 0487d6a8 | j_mayer | gen_addr_spe_imm_index(ctx, sh); \ |
5406 | 0487d6a8 | j_mayer | op_spe_ldst(spe_l##name); \ |
5407 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
|
5408 | 0487d6a8 | j_mayer | } |
5409 | 0487d6a8 | j_mayer | |
5410 | 0487d6a8 | j_mayer | #define GEN_SPE_LDX(name) \
|
5411 | b068d6a7 | j_mayer | static always_inline void gen_evl##name##x (DisasContext *ctx) \ |
5412 | 0487d6a8 | j_mayer | { \ |
5413 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5414 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5415 | 0487d6a8 | j_mayer | return; \
|
5416 | 0487d6a8 | j_mayer | } \ |
5417 | 0487d6a8 | j_mayer | gen_addr_reg_index(ctx); \ |
5418 | 0487d6a8 | j_mayer | op_spe_ldst(spe_l##name); \ |
5419 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
|
5420 | 0487d6a8 | j_mayer | } |
5421 | 0487d6a8 | j_mayer | |
5422 | 0487d6a8 | j_mayer | #define GEN_SPEOP_LD(name, sh) \
|
5423 | 0487d6a8 | j_mayer | OP_SPE_LD_TABLE(name); \ |
5424 | 0487d6a8 | j_mayer | GEN_SPE_LD(name, sh); \ |
5425 | 0487d6a8 | j_mayer | GEN_SPE_LDX(name) |
5426 | 0487d6a8 | j_mayer | |
5427 | 0487d6a8 | j_mayer | #define GEN_SPE_ST(name, sh) \
|
5428 | b068d6a7 | j_mayer | static always_inline void gen_evst##name (DisasContext *ctx) \ |
5429 | 0487d6a8 | j_mayer | { \ |
5430 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5431 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5432 | 0487d6a8 | j_mayer | return; \
|
5433 | 0487d6a8 | j_mayer | } \ |
5434 | 0487d6a8 | j_mayer | gen_addr_spe_imm_index(ctx, sh); \ |
5435 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
|
5436 | 0487d6a8 | j_mayer | op_spe_ldst(spe_st##name); \ |
5437 | 0487d6a8 | j_mayer | } |
5438 | 0487d6a8 | j_mayer | |
5439 | 0487d6a8 | j_mayer | #define GEN_SPE_STX(name) \
|
5440 | b068d6a7 | j_mayer | static always_inline void gen_evst##name##x (DisasContext *ctx) \ |
5441 | 0487d6a8 | j_mayer | { \ |
5442 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5443 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5444 | 0487d6a8 | j_mayer | return; \
|
5445 | 0487d6a8 | j_mayer | } \ |
5446 | 0487d6a8 | j_mayer | gen_addr_reg_index(ctx); \ |
5447 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
|
5448 | 0487d6a8 | j_mayer | op_spe_ldst(spe_st##name); \ |
5449 | 0487d6a8 | j_mayer | } |
5450 | 0487d6a8 | j_mayer | |
5451 | 0487d6a8 | j_mayer | #define GEN_SPEOP_ST(name, sh) \
|
5452 | 0487d6a8 | j_mayer | OP_SPE_ST_TABLE(name); \ |
5453 | 0487d6a8 | j_mayer | GEN_SPE_ST(name, sh); \ |
5454 | 0487d6a8 | j_mayer | GEN_SPE_STX(name) |
5455 | 0487d6a8 | j_mayer | |
5456 | 0487d6a8 | j_mayer | #define GEN_SPEOP_LDST(name, sh) \
|
5457 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(name, sh); \ |
5458 | 0487d6a8 | j_mayer | GEN_SPEOP_ST(name, sh) |
5459 | 0487d6a8 | j_mayer | |
5460 | 0487d6a8 | j_mayer | /* SPE arithmetic and logic */
|
5461 | 0487d6a8 | j_mayer | #define GEN_SPEOP_ARITH2(name) \
|
5462 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
5463 | 0487d6a8 | j_mayer | { \ |
5464 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5465 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5466 | 0487d6a8 | j_mayer | return; \
|
5467 | 0487d6a8 | j_mayer | } \ |
5468 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5469 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
|
5470 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5471 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5472 | 0487d6a8 | j_mayer | } |
5473 | 0487d6a8 | j_mayer | |
5474 | 0487d6a8 | j_mayer | #define GEN_SPEOP_ARITH1(name) \
|
5475 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
5476 | 0487d6a8 | j_mayer | { \ |
5477 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5478 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5479 | 0487d6a8 | j_mayer | return; \
|
5480 | 0487d6a8 | j_mayer | } \ |
5481 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5482 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5483 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5484 | 0487d6a8 | j_mayer | } |
5485 | 0487d6a8 | j_mayer | |
5486 | 0487d6a8 | j_mayer | #define GEN_SPEOP_COMP(name) \
|
5487 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
5488 | 0487d6a8 | j_mayer | { \ |
5489 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5490 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5491 | 0487d6a8 | j_mayer | return; \
|
5492 | 0487d6a8 | j_mayer | } \ |
5493 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5494 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
|
5495 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5496 | 0487d6a8 | j_mayer | gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
5497 | 0487d6a8 | j_mayer | } |
5498 | 0487d6a8 | j_mayer | |
5499 | 0487d6a8 | j_mayer | /* Logical */
|
5500 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evand); |
5501 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evandc); |
5502 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evxor); |
5503 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evor); |
5504 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evnor); |
5505 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(eveqv); |
5506 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evorc); |
5507 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evnand); |
5508 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evsrwu); |
5509 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evsrws); |
5510 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evslw); |
5511 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evrlw); |
5512 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evmergehi); |
5513 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evmergelo); |
5514 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evmergehilo); |
5515 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evmergelohi); |
5516 | 0487d6a8 | j_mayer | |
5517 | 0487d6a8 | j_mayer | /* Arithmetic */
|
5518 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evaddw); |
5519 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evsubfw); |
5520 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evabs); |
5521 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evneg); |
5522 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evextsb); |
5523 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evextsh); |
5524 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evrndw); |
5525 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evcntlzw); |
5526 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evcntlsw); |
5527 | b068d6a7 | j_mayer | static always_inline void gen_brinc (DisasContext *ctx) |
5528 | 0487d6a8 | j_mayer | { |
5529 | 0487d6a8 | j_mayer | /* Note: brinc is usable even if SPE is disabled */
|
5530 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
|
5531 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
|
5532 | 0487d6a8 | j_mayer | gen_op_brinc(); |
5533 | f78fb44e | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
|
5534 | 0487d6a8 | j_mayer | } |
5535 | 0487d6a8 | j_mayer | |
5536 | 0487d6a8 | j_mayer | #define GEN_SPEOP_ARITH_IMM2(name) \
|
5537 | b068d6a7 | j_mayer | static always_inline void gen_##name##i (DisasContext *ctx) \ |
5538 | 0487d6a8 | j_mayer | { \ |
5539 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5540 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5541 | 0487d6a8 | j_mayer | return; \
|
5542 | 0487d6a8 | j_mayer | } \ |
5543 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
|
5544 | 0487d6a8 | j_mayer | gen_op_splatwi_T1_64(rA(ctx->opcode)); \ |
5545 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5546 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5547 | 0487d6a8 | j_mayer | } |
5548 | 0487d6a8 | j_mayer | |
5549 | 0487d6a8 | j_mayer | #define GEN_SPEOP_LOGIC_IMM2(name) \
|
5550 | b068d6a7 | j_mayer | static always_inline void gen_##name##i (DisasContext *ctx) \ |
5551 | 0487d6a8 | j_mayer | { \ |
5552 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
5553 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); \ |
5554 | 0487d6a8 | j_mayer | return; \
|
5555 | 0487d6a8 | j_mayer | } \ |
5556 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
|
5557 | 0487d6a8 | j_mayer | gen_op_splatwi_T1_64(rB(ctx->opcode)); \ |
5558 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5559 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5560 | 0487d6a8 | j_mayer | } |
5561 | 0487d6a8 | j_mayer | |
5562 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH_IMM2(evaddw); |
5563 | 0487d6a8 | j_mayer | #define gen_evaddiw gen_evaddwi
|
5564 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH_IMM2(evsubfw); |
5565 | 0487d6a8 | j_mayer | #define gen_evsubifw gen_evsubfwi
|
5566 | 0487d6a8 | j_mayer | GEN_SPEOP_LOGIC_IMM2(evslw); |
5567 | 0487d6a8 | j_mayer | GEN_SPEOP_LOGIC_IMM2(evsrwu); |
5568 | 0487d6a8 | j_mayer | #define gen_evsrwis gen_evsrwsi
|
5569 | 0487d6a8 | j_mayer | GEN_SPEOP_LOGIC_IMM2(evsrws); |
5570 | 0487d6a8 | j_mayer | #define gen_evsrwiu gen_evsrwui
|
5571 | 0487d6a8 | j_mayer | GEN_SPEOP_LOGIC_IMM2(evrlw); |
5572 | 0487d6a8 | j_mayer | |
5573 | b068d6a7 | j_mayer | static always_inline void gen_evsplati (DisasContext *ctx) |
5574 | 0487d6a8 | j_mayer | { |
5575 | 0487d6a8 | j_mayer | int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27; |
5576 | 0487d6a8 | j_mayer | |
5577 | 0487d6a8 | j_mayer | gen_op_splatwi_T0_64(imm); |
5578 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5579 | 0487d6a8 | j_mayer | } |
5580 | 0487d6a8 | j_mayer | |
5581 | b068d6a7 | j_mayer | static always_inline void gen_evsplatfi (DisasContext *ctx) |
5582 | 0487d6a8 | j_mayer | { |
5583 | 0487d6a8 | j_mayer | uint32_t imm = rA(ctx->opcode) << 27;
|
5584 | 0487d6a8 | j_mayer | |
5585 | 0487d6a8 | j_mayer | gen_op_splatwi_T0_64(imm); |
5586 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5587 | 0487d6a8 | j_mayer | } |
5588 | 0487d6a8 | j_mayer | |
5589 | 0487d6a8 | j_mayer | /* Comparison */
|
5590 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evcmpgtu); |
5591 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evcmpgts); |
5592 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evcmpltu); |
5593 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evcmplts); |
5594 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evcmpeq); |
5595 | 0487d6a8 | j_mayer | |
5596 | 0487d6a8 | j_mayer | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
5597 | 0487d6a8 | j_mayer | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
5598 | 0487d6a8 | j_mayer | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
5599 | 0487d6a8 | j_mayer | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
5600 | 0487d6a8 | j_mayer | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
5601 | 0487d6a8 | j_mayer | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
5602 | 0487d6a8 | j_mayer | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
5603 | 0487d6a8 | j_mayer | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
5604 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
5605 | 0487d6a8 | j_mayer | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
5606 | 0487d6a8 | j_mayer | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
5607 | 0487d6a8 | j_mayer | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
5608 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
5609 | 0487d6a8 | j_mayer | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
5610 | 0487d6a8 | j_mayer | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
5611 | 0487d6a8 | j_mayer | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
5612 | 0487d6a8 | j_mayer | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
5613 | 0487d6a8 | j_mayer | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
5614 | 0487d6a8 | j_mayer | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
5615 | 0487d6a8 | j_mayer | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
5616 | 0487d6a8 | j_mayer | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
5617 | 0487d6a8 | j_mayer | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
5618 | 0487d6a8 | j_mayer | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
5619 | 0487d6a8 | j_mayer | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
5620 | 0487d6a8 | j_mayer | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
5621 | 0487d6a8 | j_mayer | |
5622 | b068d6a7 | j_mayer | static always_inline void gen_evsel (DisasContext *ctx) |
5623 | 0487d6a8 | j_mayer | { |
5624 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) {
|
5625 | e1833e1f | j_mayer | GEN_EXCP_NO_AP(ctx); |
5626 | 0487d6a8 | j_mayer | return;
|
5627 | 0487d6a8 | j_mayer | } |
5628 | 0487d6a8 | j_mayer | gen_op_load_crf_T0(ctx->opcode & 0x7);
|
5629 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
|
5630 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
|
5631 | 0487d6a8 | j_mayer | gen_op_evsel(); |
5632 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
|
5633 | 0487d6a8 | j_mayer | } |
5634 | 0487d6a8 | j_mayer | |
5635 | c7697e1f | j_mayer | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE) |
5636 | 0487d6a8 | j_mayer | { |
5637 | 0487d6a8 | j_mayer | gen_evsel(ctx); |
5638 | 0487d6a8 | j_mayer | } |
5639 | c7697e1f | j_mayer | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE) |
5640 | 0487d6a8 | j_mayer | { |
5641 | 0487d6a8 | j_mayer | gen_evsel(ctx); |
5642 | 0487d6a8 | j_mayer | } |
5643 | c7697e1f | j_mayer | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE) |
5644 | 0487d6a8 | j_mayer | { |
5645 | 0487d6a8 | j_mayer | gen_evsel(ctx); |
5646 | 0487d6a8 | j_mayer | } |
5647 | c7697e1f | j_mayer | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE) |
5648 | 0487d6a8 | j_mayer | { |
5649 | 0487d6a8 | j_mayer | gen_evsel(ctx); |
5650 | 0487d6a8 | j_mayer | } |
5651 | 0487d6a8 | j_mayer | |
5652 | 0487d6a8 | j_mayer | /* Load and stores */
|
5653 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
5654 | 0487d6a8 | j_mayer | /* In that case, we already have 64 bits load & stores
|
5655 | 0487d6a8 | j_mayer | * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
|
5656 | 0487d6a8 | j_mayer | */
|
5657 | 7863667f | j_mayer | #define gen_op_spe_ldd_raw gen_op_ld_raw
|
5658 | 7863667f | j_mayer | #define gen_op_spe_ldd_user gen_op_ld_user
|
5659 | 7863667f | j_mayer | #define gen_op_spe_ldd_kernel gen_op_ld_kernel
|
5660 | 7863667f | j_mayer | #define gen_op_spe_ldd_hypv gen_op_ld_hypv
|
5661 | 7863667f | j_mayer | #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
|
5662 | 7863667f | j_mayer | #define gen_op_spe_ldd_64_user gen_op_ld_64_user
|
5663 | 7863667f | j_mayer | #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
|
5664 | 7863667f | j_mayer | #define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
|
5665 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
|
5666 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_user gen_op_ld_le_user
|
5667 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
|
5668 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
|
5669 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
|
5670 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
|
5671 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
|
5672 | 7863667f | j_mayer | #define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
|
5673 | 7863667f | j_mayer | #define gen_op_spe_stdd_raw gen_op_std_raw
|
5674 | 7863667f | j_mayer | #define gen_op_spe_stdd_user gen_op_std_user
|
5675 | 7863667f | j_mayer | #define gen_op_spe_stdd_kernel gen_op_std_kernel
|
5676 | 7863667f | j_mayer | #define gen_op_spe_stdd_hypv gen_op_std_hypv
|
5677 | 7863667f | j_mayer | #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
|
5678 | 7863667f | j_mayer | #define gen_op_spe_stdd_64_user gen_op_std_64_user
|
5679 | 7863667f | j_mayer | #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
|
5680 | 7863667f | j_mayer | #define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
|
5681 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
|
5682 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_user gen_op_std_le_user
|
5683 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
|
5684 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
|
5685 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
|
5686 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
|
5687 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
|
5688 | 7863667f | j_mayer | #define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
|
5689 | 0487d6a8 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
5690 | 0487d6a8 | j_mayer | GEN_SPEOP_LDST(dd, 3);
|
5691 | 0487d6a8 | j_mayer | GEN_SPEOP_LDST(dw, 3);
|
5692 | 0487d6a8 | j_mayer | GEN_SPEOP_LDST(dh, 3);
|
5693 | 0487d6a8 | j_mayer | GEN_SPEOP_LDST(whe, 2);
|
5694 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(whou, 2);
|
5695 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(whos, 2);
|
5696 | 0487d6a8 | j_mayer | GEN_SPEOP_ST(who, 2);
|
5697 | 0487d6a8 | j_mayer | |
5698 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
5699 | 0487d6a8 | j_mayer | /* In that case, spe_stwwo is equivalent to stw */
|
5700 | 7863667f | j_mayer | #define gen_op_spe_stwwo_raw gen_op_stw_raw
|
5701 | 7863667f | j_mayer | #define gen_op_spe_stwwo_user gen_op_stw_user
|
5702 | 7863667f | j_mayer | #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
|
5703 | 7863667f | j_mayer | #define gen_op_spe_stwwo_hypv gen_op_stw_hypv
|
5704 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
|
5705 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
|
5706 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
|
5707 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
|
5708 | 7863667f | j_mayer | #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
|
5709 | 7863667f | j_mayer | #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
|
5710 | 7863667f | j_mayer | #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
|
5711 | 7863667f | j_mayer | #define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
|
5712 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
|
5713 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
|
5714 | 0487d6a8 | j_mayer | #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
|
5715 | 7863667f | j_mayer | #define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
|
5716 | 0487d6a8 | j_mayer | #endif
|
5717 | 0487d6a8 | j_mayer | #define _GEN_OP_SPE_STWWE(suffix) \
|
5718 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_stwwe_##suffix (void) \ |
5719 | 0487d6a8 | j_mayer | { \ |
5720 | 0487d6a8 | j_mayer | gen_op_srli32_T1_64(); \ |
5721 | 0487d6a8 | j_mayer | gen_op_spe_stwwo_##suffix(); \ |
5722 | 0487d6a8 | j_mayer | } |
5723 | 0487d6a8 | j_mayer | #define _GEN_OP_SPE_STWWE_LE(suffix) \
|
5724 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_stwwe_le_##suffix (void) \ |
5725 | 0487d6a8 | j_mayer | { \ |
5726 | 0487d6a8 | j_mayer | gen_op_srli32_T1_64(); \ |
5727 | 0487d6a8 | j_mayer | gen_op_spe_stwwo_le_##suffix(); \ |
5728 | 0487d6a8 | j_mayer | } |
5729 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
5730 | 0487d6a8 | j_mayer | #define GEN_OP_SPE_STWWE(suffix) \
|
5731 | 0487d6a8 | j_mayer | _GEN_OP_SPE_STWWE(suffix); \ |
5732 | 0487d6a8 | j_mayer | _GEN_OP_SPE_STWWE_LE(suffix); \ |
5733 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_stwwe_64_##suffix (void) \ |
5734 | 0487d6a8 | j_mayer | { \ |
5735 | 0487d6a8 | j_mayer | gen_op_srli32_T1_64(); \ |
5736 | 0487d6a8 | j_mayer | gen_op_spe_stwwo_64_##suffix(); \ |
5737 | 0487d6a8 | j_mayer | } \ |
5738 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \ |
5739 | 0487d6a8 | j_mayer | { \ |
5740 | 0487d6a8 | j_mayer | gen_op_srli32_T1_64(); \ |
5741 | 0487d6a8 | j_mayer | gen_op_spe_stwwo_le_64_##suffix(); \ |
5742 | 0487d6a8 | j_mayer | } |
5743 | 0487d6a8 | j_mayer | #else
|
5744 | 0487d6a8 | j_mayer | #define GEN_OP_SPE_STWWE(suffix) \
|
5745 | 0487d6a8 | j_mayer | _GEN_OP_SPE_STWWE(suffix); \ |
5746 | 0487d6a8 | j_mayer | _GEN_OP_SPE_STWWE_LE(suffix) |
5747 | 0487d6a8 | j_mayer | #endif
|
5748 | 0487d6a8 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5749 | 0487d6a8 | j_mayer | GEN_OP_SPE_STWWE(raw); |
5750 | 0487d6a8 | j_mayer | #else /* defined(CONFIG_USER_ONLY) */ |
5751 | 0487d6a8 | j_mayer | GEN_OP_SPE_STWWE(user); |
5752 | 7863667f | j_mayer | GEN_OP_SPE_STWWE(kernel); |
5753 | 7863667f | j_mayer | GEN_OP_SPE_STWWE(hypv); |
5754 | 0487d6a8 | j_mayer | #endif /* defined(CONFIG_USER_ONLY) */ |
5755 | 0487d6a8 | j_mayer | GEN_SPEOP_ST(wwe, 2);
|
5756 | 0487d6a8 | j_mayer | GEN_SPEOP_ST(wwo, 2);
|
5757 | 0487d6a8 | j_mayer | |
5758 | 0487d6a8 | j_mayer | #define GEN_SPE_LDSPLAT(name, op, suffix) \
|
5759 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_l##name##_##suffix (void) \ |
5760 | 0487d6a8 | j_mayer | { \ |
5761 | 0487d6a8 | j_mayer | gen_op_##op##_##suffix(); \ |
5762 | 0487d6a8 | j_mayer | gen_op_splatw_T1_64(); \ |
5763 | 0487d6a8 | j_mayer | } |
5764 | 0487d6a8 | j_mayer | |
5765 | 0487d6a8 | j_mayer | #define GEN_OP_SPE_LHE(suffix) \
|
5766 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_lhe_##suffix (void) \ |
5767 | 0487d6a8 | j_mayer | { \ |
5768 | 0487d6a8 | j_mayer | gen_op_spe_lh_##suffix(); \ |
5769 | 0487d6a8 | j_mayer | gen_op_sli16_T1_64(); \ |
5770 | 0487d6a8 | j_mayer | } |
5771 | 0487d6a8 | j_mayer | |
5772 | 0487d6a8 | j_mayer | #define GEN_OP_SPE_LHX(suffix) \
|
5773 | b068d6a7 | j_mayer | static always_inline void gen_op_spe_lhx_##suffix (void) \ |
5774 | 0487d6a8 | j_mayer | { \ |
5775 | 0487d6a8 | j_mayer | gen_op_spe_lh_##suffix(); \ |
5776 | 0487d6a8 | j_mayer | gen_op_extsh_T1_64(); \ |
5777 | 0487d6a8 | j_mayer | } |
5778 | 0487d6a8 | j_mayer | |
5779 | 0487d6a8 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5780 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(raw); |
5781 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw); |
5782 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(le_raw); |
5783 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw); |
5784 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw); |
5785 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw); |
5786 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(raw); |
5787 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw); |
5788 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(le_raw); |
5789 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw); |
5790 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
5791 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(64_raw);
|
5792 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
|
5793 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(le_64_raw); |
5794 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw); |
5795 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
|
5796 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw); |
5797 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(64_raw);
|
5798 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
|
5799 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(le_64_raw); |
5800 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw); |
5801 | 0487d6a8 | j_mayer | #endif
|
5802 | 0487d6a8 | j_mayer | #else
|
5803 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(user); |
5804 | 7863667f | j_mayer | GEN_OP_SPE_LHE(kernel); |
5805 | 7863667f | j_mayer | GEN_OP_SPE_LHE(hypv); |
5806 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user); |
5807 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel); |
5808 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv); |
5809 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(le_user); |
5810 | 7863667f | j_mayer | GEN_OP_SPE_LHE(le_kernel); |
5811 | 7863667f | j_mayer | GEN_OP_SPE_LHE(le_hypv); |
5812 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user); |
5813 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel); |
5814 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv); |
5815 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, user); |
5816 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel); |
5817 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv); |
5818 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user); |
5819 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel); |
5820 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv); |
5821 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(user); |
5822 | 7863667f | j_mayer | GEN_OP_SPE_LHX(kernel); |
5823 | 7863667f | j_mayer | GEN_OP_SPE_LHX(hypv); |
5824 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user); |
5825 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel); |
5826 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv); |
5827 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(le_user); |
5828 | 7863667f | j_mayer | GEN_OP_SPE_LHX(le_kernel); |
5829 | 7863667f | j_mayer | GEN_OP_SPE_LHX(le_hypv); |
5830 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user); |
5831 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel); |
5832 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv); |
5833 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
5834 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(64_user);
|
5835 | 7863667f | j_mayer | GEN_OP_SPE_LHE(64_kernel);
|
5836 | 7863667f | j_mayer | GEN_OP_SPE_LHE(64_hypv);
|
5837 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
|
5838 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
|
5839 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
|
5840 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHE(le_64_user); |
5841 | 7863667f | j_mayer | GEN_OP_SPE_LHE(le_64_kernel); |
5842 | 7863667f | j_mayer | GEN_OP_SPE_LHE(le_64_hypv); |
5843 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user); |
5844 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel); |
5845 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv); |
5846 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
|
5847 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
|
5848 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
|
5849 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user); |
5850 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel); |
5851 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv); |
5852 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(64_user);
|
5853 | 7863667f | j_mayer | GEN_OP_SPE_LHX(64_kernel);
|
5854 | 7863667f | j_mayer | GEN_OP_SPE_LHX(64_hypv);
|
5855 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
|
5856 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
|
5857 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
|
5858 | 0487d6a8 | j_mayer | GEN_OP_SPE_LHX(le_64_user); |
5859 | 7863667f | j_mayer | GEN_OP_SPE_LHX(le_64_kernel); |
5860 | 7863667f | j_mayer | GEN_OP_SPE_LHX(le_64_hypv); |
5861 | 0487d6a8 | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user); |
5862 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel); |
5863 | 7863667f | j_mayer | GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv); |
5864 | 0487d6a8 | j_mayer | #endif
|
5865 | 0487d6a8 | j_mayer | #endif
|
5866 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(hhesplat, 1);
|
5867 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(hhousplat, 1);
|
5868 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(hhossplat, 1);
|
5869 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(wwsplat, 2);
|
5870 | 0487d6a8 | j_mayer | GEN_SPEOP_LD(whsplat, 2);
|
5871 | 0487d6a8 | j_mayer | |
5872 | 0487d6a8 | j_mayer | GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); // |
5873 | 0487d6a8 | j_mayer | GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); // |
5874 | 0487d6a8 | j_mayer | GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); // |
5875 | 0487d6a8 | j_mayer | GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); // |
5876 | 0487d6a8 | j_mayer | GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); // |
5877 | 0487d6a8 | j_mayer | GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); // |
5878 | 0487d6a8 | j_mayer | GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); // |
5879 | 0487d6a8 | j_mayer | GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); // |
5880 | 0487d6a8 | j_mayer | GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); // |
5881 | 0487d6a8 | j_mayer | GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); // |
5882 | 0487d6a8 | j_mayer | GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); // |
5883 | 0487d6a8 | j_mayer | GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); // |
5884 | 0487d6a8 | j_mayer | GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); // |
5885 | 0487d6a8 | j_mayer | GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); // |
5886 | 0487d6a8 | j_mayer | GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); // |
5887 | 0487d6a8 | j_mayer | GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); // |
5888 | 0487d6a8 | j_mayer | GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); // |
5889 | 0487d6a8 | j_mayer | GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); // |
5890 | 0487d6a8 | j_mayer | |
5891 | 0487d6a8 | j_mayer | /* Multiply and add - TODO */
|
5892 | 0487d6a8 | j_mayer | #if 0
|
5893 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
|
5894 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
|
5895 | 0487d6a8 | j_mayer | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
|
5896 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
|
5897 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
|
5898 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
|
5899 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
|
5900 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
|
5901 | 0487d6a8 | j_mayer | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
|
5902 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
|
5903 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
|
5904 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
|
5905 | 0487d6a8 | j_mayer | |
5906 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
|
5907 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
|
5908 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
|
5909 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
|
5910 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
|
5911 | 0487d6a8 | j_mayer | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
|
5912 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
|
5913 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
|
5914 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
|
5915 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
|
5916 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
|
5917 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
|
5918 | 0487d6a8 | j_mayer | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
|
5919 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
|
5920 | 0487d6a8 | j_mayer | |
5921 | 0487d6a8 | j_mayer | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
|
5922 | 0487d6a8 | j_mayer | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
|
5923 | 0487d6a8 | j_mayer | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
|
5924 | 0487d6a8 | j_mayer | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
|
5925 | 0487d6a8 | j_mayer | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
|
5926 | 0487d6a8 | j_mayer | GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
|
5927 | 0487d6a8 | j_mayer | |
5928 | 0487d6a8 | j_mayer | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
|
5929 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
|
5930 | 0487d6a8 | j_mayer | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
|
5931 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
|
5932 | 0487d6a8 | j_mayer | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
|
5933 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
|
5934 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
|
5935 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
|
5936 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
|
5937 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
|
5938 | 0487d6a8 | j_mayer | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
|
5939 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
|
5940 | 0487d6a8 | j_mayer | |
5941 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
|
5942 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
|
5943 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
|
5944 | 0487d6a8 | j_mayer | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
|
5945 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
|
5946 | 0487d6a8 | j_mayer | |
5947 | 0487d6a8 | j_mayer | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
|
5948 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
|
5949 | 0487d6a8 | j_mayer | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
|
5950 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
|
5951 | 0487d6a8 | j_mayer | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
|
5952 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
|
5953 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
|
5954 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
|
5955 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
|
5956 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
|
5957 | 0487d6a8 | j_mayer | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
|
5958 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
|
5959 | 0487d6a8 | j_mayer | |
5960 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
|
5961 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
|
5962 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
|
5963 | 0487d6a8 | j_mayer | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
|
5964 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
|
5965 | 0487d6a8 | j_mayer | #endif
|
5966 | 0487d6a8 | j_mayer | |
5967 | 0487d6a8 | j_mayer | /*** SPE floating-point extension ***/
|
5968 | 0487d6a8 | j_mayer | #define GEN_SPEFPUOP_CONV(name) \
|
5969 | b068d6a7 | j_mayer | static always_inline void gen_##name (DisasContext *ctx) \ |
5970 | 0487d6a8 | j_mayer | { \ |
5971 | f78fb44e | aurel32 | gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
|
5972 | 0487d6a8 | j_mayer | gen_op_##name(); \ |
5973 | f78fb44e | aurel32 | gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
|
5974 | 0487d6a8 | j_mayer | } |
5975 | 0487d6a8 | j_mayer | |
5976 | 0487d6a8 | j_mayer | /* Single precision floating-point vectors operations */
|
5977 | 0487d6a8 | j_mayer | /* Arithmetic */
|
5978 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evfsadd); |
5979 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evfssub); |
5980 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evfsmul); |
5981 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(evfsdiv); |
5982 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evfsabs); |
5983 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evfsnabs); |
5984 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(evfsneg); |
5985 | 0487d6a8 | j_mayer | /* Conversion */
|
5986 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfscfui); |
5987 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfscfsi); |
5988 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfscfuf); |
5989 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfscfsf); |
5990 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctui); |
5991 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctsi); |
5992 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctuf); |
5993 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctsf); |
5994 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctuiz); |
5995 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(evfsctsiz); |
5996 | 0487d6a8 | j_mayer | /* Comparison */
|
5997 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfscmpgt); |
5998 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfscmplt); |
5999 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfscmpeq); |
6000 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfststgt); |
6001 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfststlt); |
6002 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(evfststeq); |
6003 | 0487d6a8 | j_mayer | |
6004 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
6005 | 0487d6a8 | j_mayer | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); // |
6006 | 0487d6a8 | j_mayer | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); // |
6007 | 0487d6a8 | j_mayer | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); // |
6008 | 0487d6a8 | j_mayer | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); // |
6009 | 0487d6a8 | j_mayer | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); // |
6010 | 0487d6a8 | j_mayer | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); // |
6011 | 0487d6a8 | j_mayer | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); // |
6012 | 0487d6a8 | j_mayer | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); // |
6013 | 0487d6a8 | j_mayer | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); // |
6014 | 0487d6a8 | j_mayer | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); // |
6015 | 0487d6a8 | j_mayer | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); // |
6016 | 0487d6a8 | j_mayer | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); // |
6017 | 0487d6a8 | j_mayer | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); // |
6018 | 0487d6a8 | j_mayer | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); // |
6019 | 0487d6a8 | j_mayer | |
6020 | 0487d6a8 | j_mayer | /* Single precision floating-point operations */
|
6021 | 0487d6a8 | j_mayer | /* Arithmetic */
|
6022 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efsadd); |
6023 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efssub); |
6024 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efsmul); |
6025 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efsdiv); |
6026 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efsabs); |
6027 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efsnabs); |
6028 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efsneg); |
6029 | 0487d6a8 | j_mayer | /* Conversion */
|
6030 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efscfui); |
6031 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efscfsi); |
6032 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efscfuf); |
6033 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efscfsf); |
6034 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctui); |
6035 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctsi); |
6036 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctuf); |
6037 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctsf); |
6038 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctuiz); |
6039 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efsctsiz); |
6040 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efscfd); |
6041 | 0487d6a8 | j_mayer | /* Comparison */
|
6042 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efscmpgt); |
6043 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efscmplt); |
6044 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efscmpeq); |
6045 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efststgt); |
6046 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efststlt); |
6047 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efststeq); |
6048 | 0487d6a8 | j_mayer | |
6049 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
6050 | 05332d70 | j_mayer | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); // |
6051 | 0487d6a8 | j_mayer | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6052 | 0487d6a8 | j_mayer | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6053 | 0487d6a8 | j_mayer | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); // |
6054 | 0487d6a8 | j_mayer | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); // |
6055 | 0487d6a8 | j_mayer | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); // |
6056 | 0487d6a8 | j_mayer | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); // |
6057 | 0487d6a8 | j_mayer | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); // |
6058 | 0487d6a8 | j_mayer | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); // |
6059 | 0487d6a8 | j_mayer | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); // |
6060 | 9ceb2a77 | ths | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); // |
6061 | 9ceb2a77 | ths | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); // |
6062 | 0487d6a8 | j_mayer | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); // |
6063 | 0487d6a8 | j_mayer | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); // |
6064 | 0487d6a8 | j_mayer | |
6065 | 0487d6a8 | j_mayer | /* Double precision floating-point operations */
|
6066 | 0487d6a8 | j_mayer | /* Arithmetic */
|
6067 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efdadd); |
6068 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efdsub); |
6069 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efdmul); |
6070 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH2(efddiv); |
6071 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efdabs); |
6072 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efdnabs); |
6073 | 0487d6a8 | j_mayer | GEN_SPEOP_ARITH1(efdneg); |
6074 | 0487d6a8 | j_mayer | /* Conversion */
|
6075 | 0487d6a8 | j_mayer | |
6076 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfui); |
6077 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfsi); |
6078 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfuf); |
6079 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfsf); |
6080 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctui); |
6081 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctsi); |
6082 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctuf); |
6083 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctsf); |
6084 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctuiz); |
6085 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctsiz); |
6086 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfs); |
6087 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfuid); |
6088 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdcfsid); |
6089 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctuidz); |
6090 | 0487d6a8 | j_mayer | GEN_SPEFPUOP_CONV(efdctsidz); |
6091 | 0487d6a8 | j_mayer | /* Comparison */
|
6092 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdcmpgt); |
6093 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdcmplt); |
6094 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdcmpeq); |
6095 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdtstgt); |
6096 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdtstlt); |
6097 | 0487d6a8 | j_mayer | GEN_SPEOP_COMP(efdtsteq); |
6098 | 0487d6a8 | j_mayer | |
6099 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
6100 | 0487d6a8 | j_mayer | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); // |
6101 | 0487d6a8 | j_mayer | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); // |
6102 | 0487d6a8 | j_mayer | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6103 | 0487d6a8 | j_mayer | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); // |
6104 | 0487d6a8 | j_mayer | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); // |
6105 | 0487d6a8 | j_mayer | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); // |
6106 | 0487d6a8 | j_mayer | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); // |
6107 | 0487d6a8 | j_mayer | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); // |
6108 | 0487d6a8 | j_mayer | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); // |
6109 | 0487d6a8 | j_mayer | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); // |
6110 | 0487d6a8 | j_mayer | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); // |
6111 | 0487d6a8 | j_mayer | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); // |
6112 | 0487d6a8 | j_mayer | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); // |
6113 | 0487d6a8 | j_mayer | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); // |
6114 | 0487d6a8 | j_mayer | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); // |
6115 | 0487d6a8 | j_mayer | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); // |
6116 | 0487d6a8 | j_mayer | |
6117 | 79aceca5 | bellard | /* End opcode list */
|
6118 | 79aceca5 | bellard | GEN_OPCODE_MARK(end); |
6119 | 79aceca5 | bellard | |
6120 | 3fc6c082 | bellard | #include "translate_init.c" |
6121 | 0411a972 | j_mayer | #include "helper_regs.h" |
6122 | 79aceca5 | bellard | |
6123 | 9a64fbe4 | bellard | /*****************************************************************************/
|
6124 | 3fc6c082 | bellard | /* Misc PowerPC helpers */
|
6125 | 36081602 | j_mayer | void cpu_dump_state (CPUState *env, FILE *f,
|
6126 | 36081602 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
6127 | 36081602 | j_mayer | int flags)
|
6128 | 79aceca5 | bellard | { |
6129 | 3fc6c082 | bellard | #define RGPL 4 |
6130 | 3fc6c082 | bellard | #define RFPL 4 |
6131 | 3fc6c082 | bellard | |
6132 | 79aceca5 | bellard | int i;
|
6133 | 79aceca5 | bellard | |
6134 | 077fc206 | j_mayer | cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", |
6135 | 077fc206 | j_mayer | env->nip, env->lr, env->ctr, hreg_load_xer(env)); |
6136 | 6b542af7 | j_mayer | cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", |
6137 | 6b542af7 | j_mayer | env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); |
6138 | d9bce9d9 | j_mayer | #if !defined(NO_TIMER_DUMP)
|
6139 | 077fc206 | j_mayer | cpu_fprintf(f, "TB %08x %08x "
|
6140 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
6141 | 76a66253 | j_mayer | "DECR %08x"
|
6142 | 76a66253 | j_mayer | #endif
|
6143 | 76a66253 | j_mayer | "\n",
|
6144 | 077fc206 | j_mayer | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
6145 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
6146 | 76a66253 | j_mayer | , cpu_ppc_load_decr(env) |
6147 | 76a66253 | j_mayer | #endif
|
6148 | 76a66253 | j_mayer | ); |
6149 | 077fc206 | j_mayer | #endif
|
6150 | 76a66253 | j_mayer | for (i = 0; i < 32; i++) { |
6151 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == 0) |
6152 | 3fc6c082 | bellard | cpu_fprintf(f, "GPR%02d", i);
|
6153 | 6b542af7 | j_mayer | cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
|
6154 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == (RGPL - 1)) |
6155 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
6156 | 76a66253 | j_mayer | } |
6157 | 3fc6c082 | bellard | cpu_fprintf(f, "CR ");
|
6158 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) |
6159 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
6160 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
6161 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) { |
6162 | 76a66253 | j_mayer | char a = '-'; |
6163 | 76a66253 | j_mayer | if (env->crf[i] & 0x08) |
6164 | 76a66253 | j_mayer | a = 'L';
|
6165 | 76a66253 | j_mayer | else if (env->crf[i] & 0x04) |
6166 | 76a66253 | j_mayer | a = 'G';
|
6167 | 76a66253 | j_mayer | else if (env->crf[i] & 0x02) |
6168 | 76a66253 | j_mayer | a = 'E';
|
6169 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
6170 | 76a66253 | j_mayer | } |
6171 | 6b542af7 | j_mayer | cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
6172 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
6173 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == 0) |
6174 | 3fc6c082 | bellard | cpu_fprintf(f, "FPR%02d", i);
|
6175 | 26a76461 | bellard | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
6176 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == (RFPL - 1)) |
6177 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
6178 | 79aceca5 | bellard | } |
6179 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
6180 | 6b542af7 | j_mayer | cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", |
6181 | 3fc6c082 | bellard | env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
6182 | f2e63a42 | j_mayer | #endif
|
6183 | 79aceca5 | bellard | |
6184 | 3fc6c082 | bellard | #undef RGPL
|
6185 | 3fc6c082 | bellard | #undef RFPL
|
6186 | 79aceca5 | bellard | } |
6187 | 79aceca5 | bellard | |
6188 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE*f,
|
6189 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
6190 | 76a66253 | j_mayer | int flags)
|
6191 | 76a66253 | j_mayer | { |
6192 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
6193 | 76a66253 | j_mayer | opc_handler_t **t1, **t2, **t3, *handler; |
6194 | 76a66253 | j_mayer | int op1, op2, op3;
|
6195 | 76a66253 | j_mayer | |
6196 | 76a66253 | j_mayer | t1 = env->opcodes; |
6197 | 76a66253 | j_mayer | for (op1 = 0; op1 < 64; op1++) { |
6198 | 76a66253 | j_mayer | handler = t1[op1]; |
6199 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
6200 | 76a66253 | j_mayer | t2 = ind_table(handler); |
6201 | 76a66253 | j_mayer | for (op2 = 0; op2 < 32; op2++) { |
6202 | 76a66253 | j_mayer | handler = t2[op2]; |
6203 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
6204 | 76a66253 | j_mayer | t3 = ind_table(handler); |
6205 | 76a66253 | j_mayer | for (op3 = 0; op3 < 32; op3++) { |
6206 | 76a66253 | j_mayer | handler = t3[op3]; |
6207 | 76a66253 | j_mayer | if (handler->count == 0) |
6208 | 76a66253 | j_mayer | continue;
|
6209 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
6210 | 76a66253 | j_mayer | "%016llx %lld\n",
|
6211 | 76a66253 | j_mayer | op1, op2, op3, op1, (op3 << 5) | op2,
|
6212 | 76a66253 | j_mayer | handler->oname, |
6213 | 76a66253 | j_mayer | handler->count, handler->count); |
6214 | 76a66253 | j_mayer | } |
6215 | 76a66253 | j_mayer | } else {
|
6216 | 76a66253 | j_mayer | if (handler->count == 0) |
6217 | 76a66253 | j_mayer | continue;
|
6218 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
6219 | 76a66253 | j_mayer | "%016llx %lld\n",
|
6220 | 76a66253 | j_mayer | op1, op2, op1, op2, handler->oname, |
6221 | 76a66253 | j_mayer | handler->count, handler->count); |
6222 | 76a66253 | j_mayer | } |
6223 | 76a66253 | j_mayer | } |
6224 | 76a66253 | j_mayer | } else {
|
6225 | 76a66253 | j_mayer | if (handler->count == 0) |
6226 | 76a66253 | j_mayer | continue;
|
6227 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
|
6228 | 76a66253 | j_mayer | op1, op1, handler->oname, |
6229 | 76a66253 | j_mayer | handler->count, handler->count); |
6230 | 76a66253 | j_mayer | } |
6231 | 76a66253 | j_mayer | } |
6232 | 76a66253 | j_mayer | #endif
|
6233 | 76a66253 | j_mayer | } |
6234 | 76a66253 | j_mayer | |
6235 | 9a64fbe4 | bellard | /*****************************************************************************/
|
6236 | 2cfc5f17 | ths | static always_inline void gen_intermediate_code_internal (CPUState *env, |
6237 | 2cfc5f17 | ths | TranslationBlock *tb, |
6238 | 2cfc5f17 | ths | int search_pc)
|
6239 | 79aceca5 | bellard | { |
6240 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
6241 | 79aceca5 | bellard | opc_handler_t **table, *handler; |
6242 | 0fa85d43 | bellard | target_ulong pc_start; |
6243 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
6244 | 056401ea | j_mayer | int supervisor, little_endian;
|
6245 | 79aceca5 | bellard | int j, lj = -1; |
6246 | 2e70f6ef | pbrook | int num_insns;
|
6247 | 2e70f6ef | pbrook | int max_insns;
|
6248 | 79aceca5 | bellard | |
6249 | 79aceca5 | bellard | pc_start = tb->pc; |
6250 | 79aceca5 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
6251 | 7c58044c | j_mayer | #if defined(OPTIMIZE_FPRF_UPDATE)
|
6252 | 7c58044c | j_mayer | gen_fprf_ptr = gen_fprf_buf; |
6253 | 7c58044c | j_mayer | #endif
|
6254 | 046d6672 | bellard | ctx.nip = pc_start; |
6255 | 79aceca5 | bellard | ctx.tb = tb; |
6256 | e1833e1f | j_mayer | ctx.exception = POWERPC_EXCP_NONE; |
6257 | 3fc6c082 | bellard | ctx.spr_cb = env->spr_cb; |
6258 | 6ebbf390 | j_mayer | supervisor = env->mmu_idx; |
6259 | 6ebbf390 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
6260 | 2857068e | j_mayer | ctx.supervisor = supervisor; |
6261 | d9bce9d9 | j_mayer | #endif
|
6262 | 056401ea | j_mayer | little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0; |
6263 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
6264 | d9bce9d9 | j_mayer | ctx.sf_mode = msr_sf; |
6265 | 056401ea | j_mayer | ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian; |
6266 | 2857068e | j_mayer | #else
|
6267 | 056401ea | j_mayer | ctx.mem_idx = (supervisor << 1) | little_endian;
|
6268 | 9a64fbe4 | bellard | #endif
|
6269 | d63001d1 | j_mayer | ctx.dcache_line_size = env->dcache_line_size; |
6270 | 3cc62370 | bellard | ctx.fpu_enabled = msr_fp; |
6271 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
6272 | d26bfc9a | j_mayer | ctx.spe_enabled = msr_spe; |
6273 | d26bfc9a | j_mayer | else
|
6274 | d26bfc9a | j_mayer | ctx.spe_enabled = 0;
|
6275 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
6276 | a9d9eb8f | j_mayer | ctx.altivec_enabled = msr_vr; |
6277 | a9d9eb8f | j_mayer | else
|
6278 | a9d9eb8f | j_mayer | ctx.altivec_enabled = 0;
|
6279 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
6280 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
6281 | d26bfc9a | j_mayer | else
|
6282 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = 0;
|
6283 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
6284 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
6285 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled))
|
6286 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
6287 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
6288 | 9a64fbe4 | bellard | /* Single step trace mode */
|
6289 | 9a64fbe4 | bellard | msr_se = 1;
|
6290 | 9a64fbe4 | bellard | #endif
|
6291 | 2e70f6ef | pbrook | num_insns = 0;
|
6292 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
6293 | 2e70f6ef | pbrook | if (max_insns == 0) |
6294 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
6295 | 2e70f6ef | pbrook | |
6296 | 2e70f6ef | pbrook | gen_icount_start(); |
6297 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
6298 | e1833e1f | j_mayer | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
6299 | 76a66253 | j_mayer | if (unlikely(env->nb_breakpoints > 0)) { |
6300 | 76a66253 | j_mayer | for (j = 0; j < env->nb_breakpoints; j++) { |
6301 | ea4e754f | bellard | if (env->breakpoints[j] == ctx.nip) {
|
6302 | 5fafdf24 | ths | gen_update_nip(&ctx, ctx.nip); |
6303 | ea4e754f | bellard | gen_op_debug(); |
6304 | ea4e754f | bellard | break;
|
6305 | ea4e754f | bellard | } |
6306 | ea4e754f | bellard | } |
6307 | ea4e754f | bellard | } |
6308 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
6309 | 79aceca5 | bellard | j = gen_opc_ptr - gen_opc_buf; |
6310 | 79aceca5 | bellard | if (lj < j) {
|
6311 | 79aceca5 | bellard | lj++; |
6312 | 79aceca5 | bellard | while (lj < j)
|
6313 | 79aceca5 | bellard | gen_opc_instr_start[lj++] = 0;
|
6314 | 046d6672 | bellard | gen_opc_pc[lj] = ctx.nip; |
6315 | 79aceca5 | bellard | gen_opc_instr_start[lj] = 1;
|
6316 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
6317 | 79aceca5 | bellard | } |
6318 | 79aceca5 | bellard | } |
6319 | 9fddaa0c | bellard | #if defined PPC_DEBUG_DISAS
|
6320 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6321 | 79aceca5 | bellard | fprintf(logfile, "----------------\n");
|
6322 | 1b9eb036 | j_mayer | fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n", |
6323 | 0411a972 | j_mayer | ctx.nip, supervisor, (int)msr_ir);
|
6324 | 9a64fbe4 | bellard | } |
6325 | 9a64fbe4 | bellard | #endif
|
6326 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
6327 | 2e70f6ef | pbrook | gen_io_start(); |
6328 | 056401ea | j_mayer | if (unlikely(little_endian)) {
|
6329 | 056401ea | j_mayer | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
6330 | 056401ea | j_mayer | } else {
|
6331 | 056401ea | j_mayer | ctx.opcode = ldl_code(ctx.nip); |
6332 | 111bfab3 | bellard | } |
6333 | 9fddaa0c | bellard | #if defined PPC_DEBUG_DISAS
|
6334 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6335 | 111bfab3 | bellard | fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
|
6336 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
6337 | 056401ea | j_mayer | opc3(ctx.opcode), little_endian ? "little" : "big"); |
6338 | 79aceca5 | bellard | } |
6339 | 79aceca5 | bellard | #endif
|
6340 | 046d6672 | bellard | ctx.nip += 4;
|
6341 | 3fc6c082 | bellard | table = env->opcodes; |
6342 | 2e70f6ef | pbrook | num_insns++; |
6343 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
6344 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
6345 | 79aceca5 | bellard | table = ind_table(handler); |
6346 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
6347 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
6348 | 79aceca5 | bellard | table = ind_table(handler); |
6349 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
6350 | 79aceca5 | bellard | } |
6351 | 79aceca5 | bellard | } |
6352 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
6353 | 76a66253 | j_mayer | if (unlikely(handler->handler == &gen_invalid)) {
|
6354 | 4a057712 | j_mayer | if (loglevel != 0) { |
6355 | 76a66253 | j_mayer | fprintf(logfile, "invalid/unsupported opcode: "
|
6356 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
6357 | 76a66253 | j_mayer | opc1(ctx.opcode), opc2(ctx.opcode), |
6358 | 0411a972 | j_mayer | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
6359 | 4b3686fa | bellard | } else {
|
6360 | 4b3686fa | bellard | printf("invalid/unsupported opcode: "
|
6361 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
6362 | 4b3686fa | bellard | opc1(ctx.opcode), opc2(ctx.opcode), |
6363 | 0411a972 | j_mayer | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
6364 | 4b3686fa | bellard | } |
6365 | 76a66253 | j_mayer | } else {
|
6366 | 76a66253 | j_mayer | if (unlikely((ctx.opcode & handler->inval) != 0)) { |
6367 | 4a057712 | j_mayer | if (loglevel != 0) { |
6368 | 79aceca5 | bellard | fprintf(logfile, "invalid bits: %08x for opcode: "
|
6369 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
6370 | 79aceca5 | bellard | ctx.opcode & handler->inval, opc1(ctx.opcode), |
6371 | 79aceca5 | bellard | opc2(ctx.opcode), opc3(ctx.opcode), |
6372 | 046d6672 | bellard | ctx.opcode, ctx.nip - 4);
|
6373 | 9a64fbe4 | bellard | } else {
|
6374 | 9a64fbe4 | bellard | printf("invalid bits: %08x for opcode: "
|
6375 | 6b542af7 | j_mayer | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
6376 | 76a66253 | j_mayer | ctx.opcode & handler->inval, opc1(ctx.opcode), |
6377 | 76a66253 | j_mayer | opc2(ctx.opcode), opc3(ctx.opcode), |
6378 | 046d6672 | bellard | ctx.opcode, ctx.nip - 4);
|
6379 | 76a66253 | j_mayer | } |
6380 | e1833e1f | j_mayer | GEN_EXCP_INVAL(ctxp); |
6381 | 4b3686fa | bellard | break;
|
6382 | 79aceca5 | bellard | } |
6383 | 79aceca5 | bellard | } |
6384 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
6385 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
6386 | 76a66253 | j_mayer | handler->count++; |
6387 | 76a66253 | j_mayer | #endif
|
6388 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
6389 | 8cbcb4fa | aurel32 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
6390 | 8cbcb4fa | aurel32 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
6391 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_SYSCALL && |
6392 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_TRAP && |
6393 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
6394 | e1833e1f | j_mayer | GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
|
6395 | d26bfc9a | j_mayer | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
6396 | 2e70f6ef | pbrook | (env->singlestep_enabled) || |
6397 | 2e70f6ef | pbrook | num_insns >= max_insns)) { |
6398 | d26bfc9a | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
6399 | d26bfc9a | j_mayer | * generation
|
6400 | d26bfc9a | j_mayer | */
|
6401 | 8dd4983c | bellard | break;
|
6402 | 76a66253 | j_mayer | } |
6403 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP)
|
6404 | 3fc6c082 | bellard | break;
|
6405 | 3fc6c082 | bellard | #endif
|
6406 | 3fc6c082 | bellard | } |
6407 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
6408 | 2e70f6ef | pbrook | gen_io_end(); |
6409 | e1833e1f | j_mayer | if (ctx.exception == POWERPC_EXCP_NONE) {
|
6410 | c1942362 | bellard | gen_goto_tb(&ctx, 0, ctx.nip);
|
6411 | e1833e1f | j_mayer | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
6412 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled)) {
|
6413 | 8cbcb4fa | aurel32 | gen_update_nip(&ctx, ctx.nip); |
6414 | 8cbcb4fa | aurel32 | gen_op_debug(); |
6415 | 8cbcb4fa | aurel32 | } |
6416 | 76a66253 | j_mayer | /* Generate the return instruction */
|
6417 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
6418 | 9a64fbe4 | bellard | } |
6419 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
6420 | 79aceca5 | bellard | *gen_opc_ptr = INDEX_op_end; |
6421 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
6422 | 9a64fbe4 | bellard | j = gen_opc_ptr - gen_opc_buf; |
6423 | 9a64fbe4 | bellard | lj++; |
6424 | 9a64fbe4 | bellard | while (lj <= j)
|
6425 | 9a64fbe4 | bellard | gen_opc_instr_start[lj++] = 0;
|
6426 | 9a64fbe4 | bellard | } else {
|
6427 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
6428 | 2e70f6ef | pbrook | tb->icount = num_insns; |
6429 | 9a64fbe4 | bellard | } |
6430 | d9bce9d9 | j_mayer | #if defined(DEBUG_DISAS)
|
6431 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
6432 | 9a64fbe4 | bellard | fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
|
6433 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
6434 | 9fddaa0c | bellard | } |
6435 | 9fddaa0c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6436 | 76a66253 | j_mayer | int flags;
|
6437 | 237c0af0 | j_mayer | flags = env->bfd_mach; |
6438 | 056401ea | j_mayer | flags |= little_endian << 16;
|
6439 | 0fa85d43 | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
6440 | 76a66253 | j_mayer | target_disas(logfile, pc_start, ctx.nip - pc_start, flags); |
6441 | 79aceca5 | bellard | fprintf(logfile, "\n");
|
6442 | 9fddaa0c | bellard | } |
6443 | 79aceca5 | bellard | #endif
|
6444 | 79aceca5 | bellard | } |
6445 | 79aceca5 | bellard | |
6446 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
6447 | 79aceca5 | bellard | { |
6448 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
6449 | 79aceca5 | bellard | } |
6450 | 79aceca5 | bellard | |
6451 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
6452 | 79aceca5 | bellard | { |
6453 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
6454 | 79aceca5 | bellard | } |
6455 | d2856f1a | aurel32 | |
6456 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
6457 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
6458 | d2856f1a | aurel32 | { |
6459 | d2856f1a | aurel32 | int type, c;
|
6460 | d2856f1a | aurel32 | /* for PPC, we need to look at the micro operation to get the
|
6461 | d2856f1a | aurel32 | * access type */
|
6462 | d2856f1a | aurel32 | env->nip = gen_opc_pc[pc_pos]; |
6463 | d2856f1a | aurel32 | c = gen_opc_buf[pc_pos]; |
6464 | d2856f1a | aurel32 | switch(c) {
|
6465 | d2856f1a | aurel32 | #if defined(CONFIG_USER_ONLY)
|
6466 | d2856f1a | aurel32 | #define CASE3(op)\
|
6467 | d2856f1a | aurel32 | case INDEX_op_ ## op ## _raw |
6468 | d2856f1a | aurel32 | #else
|
6469 | d2856f1a | aurel32 | #define CASE3(op)\
|
6470 | d2856f1a | aurel32 | case INDEX_op_ ## op ## _user:\ |
6471 | d2856f1a | aurel32 | case INDEX_op_ ## op ## _kernel:\ |
6472 | d2856f1a | aurel32 | case INDEX_op_ ## op ## _hypv |
6473 | d2856f1a | aurel32 | #endif
|
6474 | d2856f1a | aurel32 | |
6475 | d2856f1a | aurel32 | CASE3(stfd): |
6476 | d2856f1a | aurel32 | CASE3(stfs): |
6477 | d2856f1a | aurel32 | CASE3(lfd): |
6478 | d2856f1a | aurel32 | CASE3(lfs): |
6479 | d2856f1a | aurel32 | type = ACCESS_FLOAT; |
6480 | d2856f1a | aurel32 | break;
|
6481 | d2856f1a | aurel32 | CASE3(lwarx): |
6482 | d2856f1a | aurel32 | type = ACCESS_RES; |
6483 | d2856f1a | aurel32 | break;
|
6484 | d2856f1a | aurel32 | CASE3(stwcx): |
6485 | d2856f1a | aurel32 | type = ACCESS_RES; |
6486 | d2856f1a | aurel32 | break;
|
6487 | d2856f1a | aurel32 | CASE3(eciwx): |
6488 | d2856f1a | aurel32 | CASE3(ecowx): |
6489 | d2856f1a | aurel32 | type = ACCESS_EXT; |
6490 | d2856f1a | aurel32 | break;
|
6491 | d2856f1a | aurel32 | default:
|
6492 | d2856f1a | aurel32 | type = ACCESS_INT; |
6493 | d2856f1a | aurel32 | break;
|
6494 | d2856f1a | aurel32 | } |
6495 | d2856f1a | aurel32 | env->access_type = type; |
6496 | d2856f1a | aurel32 | } |