ppc: fix fpr TCG registers creation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: Convert FPR moves to TCG
Replace op_{load,store}_fpr with tcg_gen_mov_i64.Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].
This obsoletes op_template.h for REG > 7.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
ppc: Convert Altivec register moves to TCG
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], andcpu_AVR{h,l}[0..2].
ppc: cleanup register types
- use target_ulong for gpr and dyngen registers- remove ppc_gpr_t type- define 64-bit dyngen registers for GPE register on 32-bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.Introduce TCG variables cpu_gpr[0..31].
For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers...
alpha: convert a few more instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: directly access ir registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
convert of few alpha insn to TCG
(based on a patch from Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
hw/pcnet: use qemu_socket.h
(Jan Kiszka)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5149 c046a42c-6fe2-441c-8c8c-71466251a162
Implement no-fault loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5148 c046a42c-6fe2-441c-8c8c-71466251a162
View all revisions | View revisions
Also available in: Atom