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/*
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 *  virtual page mapping and translated block handling
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#ifdef _WIN32
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#include <windows.h>
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#else
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#include <sys/types.h>
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#include <sys/mman.h>
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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#endif
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//#define DEBUG_TB_INVALIDATE
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//#define DEBUG_FLUSH
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//#define DEBUG_TLB
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//#define DEBUG_UNASSIGNED
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/* make various TB consistency checks */
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//#define DEBUG_TB_CHECK
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//#define DEBUG_TLB_CHECK
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//#define DEBUG_IOPORT
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//#define DEBUG_SUBPAGE
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#if !defined(CONFIG_USER_ONLY)
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/* TB consistency checks only implemented for usermode emulation.  */
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#undef DEBUG_TB_CHECK
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#endif
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/* threshold to flush the translated code buffer */
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#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
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#define SMC_BITMAP_USE_THRESHOLD 10
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#define MMAP_AREA_START        0x00000000
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#define MMAP_AREA_END          0xa8000000
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#if defined(TARGET_SPARC64)
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#define TARGET_PHYS_ADDR_SPACE_BITS 41
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#elif defined(TARGET_SPARC)
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#define TARGET_PHYS_ADDR_SPACE_BITS 36
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#elif defined(TARGET_ALPHA)
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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#define TARGET_VIRT_ADDR_SPACE_BITS 42
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#elif defined(TARGET_PPC64)
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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#else
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/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#endif
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TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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int nb_tbs;
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/* any access to the tbs or the page table must use this lock */
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spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));
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uint8_t *code_gen_ptr;
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int phys_ram_size;
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int phys_ram_fd;
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uint8_t *phys_ram_base;
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uint8_t *phys_ram_dirty;
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static ram_addr_t phys_ram_alloc_offset = 0;
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CPUState *first_cpu;
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/* current CPU in the current thread. It is only valid inside
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   cpu_exec() */
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CPUState *cpu_single_env;
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typedef struct PageDesc {
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    /* list of TBs intersecting this ram page */
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    TranslationBlock *first_tb;
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    /* in order to optimize self modifying code, we count the number
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       of lookups we do to a given page to use a bitmap */
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    unsigned int code_write_count;
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    uint8_t *code_bitmap;
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#if defined(CONFIG_USER_ONLY)
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    unsigned long flags;
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#endif
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} PageDesc;
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typedef struct PhysPageDesc {
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    /* offset in host memory of the page + io_index in the low 12 bits */
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    uint32_t phys_offset;
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} PhysPageDesc;
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#define L2_BITS 10
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
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/* XXX: this is a temporary hack for alpha target.
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 *      In the future, this is to be replaced by a multi-level table
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 *      to actually be able to handle the complete 64 bits address space.
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 */
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#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
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#else
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#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
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#endif
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#define L1_SIZE (1 << L1_BITS)
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#define L2_SIZE (1 << L2_BITS)
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static void io_mem_init(void);
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unsigned long qemu_real_host_page_size;
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unsigned long qemu_host_page_bits;
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unsigned long qemu_host_page_size;
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unsigned long qemu_host_page_mask;
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/* XXX: for system emulation, it could just be an array */
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static PageDesc *l1_map[L1_SIZE];
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PhysPageDesc **l1_phys_map;
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/* io memory support */
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CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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static int io_mem_nb;
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#if defined(CONFIG_SOFTMMU)
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static int io_mem_watch;
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#endif
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/* log support */
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char *logfilename = "/tmp/qemu.log";
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FILE *logfile;
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int loglevel;
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static int log_append = 0;
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/* statistics */
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static int tlb_flush_count;
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static int tb_flush_count;
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static int tb_phys_invalidate_count;
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#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
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typedef struct subpage_t {
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    target_phys_addr_t base;
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    CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE];
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    CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE];
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    void *opaque[TARGET_PAGE_SIZE];
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} subpage_t;
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static void page_init(void)
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{
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    /* NOTE: we can always suppose that qemu_host_page_size >=
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       TARGET_PAGE_SIZE */
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#ifdef _WIN32
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    {
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        SYSTEM_INFO system_info;
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        DWORD old_protect;
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        GetSystemInfo(&system_info);
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        qemu_real_host_page_size = system_info.dwPageSize;
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        VirtualProtect(code_gen_buffer, sizeof(code_gen_buffer),
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                       PAGE_EXECUTE_READWRITE, &old_protect);
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    }
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#else
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    qemu_real_host_page_size = getpagesize();
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    {
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        unsigned long start, end;
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        start = (unsigned long)code_gen_buffer;
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        start &= ~(qemu_real_host_page_size - 1);
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        end = (unsigned long)code_gen_buffer + sizeof(code_gen_buffer);
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        end += qemu_real_host_page_size - 1;
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        end &= ~(qemu_real_host_page_size - 1);
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        mprotect((void *)start, end - start,
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                 PROT_READ | PROT_WRITE | PROT_EXEC);
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    }
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#endif
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    if (qemu_host_page_size == 0)
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        qemu_host_page_size = qemu_real_host_page_size;
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    if (qemu_host_page_size < TARGET_PAGE_SIZE)
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        qemu_host_page_size = TARGET_PAGE_SIZE;
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    qemu_host_page_bits = 0;
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    while ((1 << qemu_host_page_bits) < qemu_host_page_size)
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        qemu_host_page_bits++;
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    qemu_host_page_mask = ~(qemu_host_page_size - 1);
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    l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
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    memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
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}
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static inline PageDesc *page_find_alloc(unsigned int index)
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{
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    PageDesc **lp, *p;
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    lp = &l1_map[index >> L2_BITS];
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    p = *lp;
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    if (!p) {
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        /* allocate if not found */
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        p = qemu_malloc(sizeof(PageDesc) * L2_SIZE);
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        memset(p, 0, sizeof(PageDesc) * L2_SIZE);
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        *lp = p;
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    }
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    return p + (index & (L2_SIZE - 1));
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}
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static inline PageDesc *page_find(unsigned int index)
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{
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    PageDesc *p;
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    p = l1_map[index >> L2_BITS];
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    if (!p)
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        return 0;
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    return p + (index & (L2_SIZE - 1));
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}
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static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
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{
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    void **lp, **p;
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    PhysPageDesc *pd;
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    p = (void **)l1_phys_map;
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#if TARGET_PHYS_ADDR_SPACE_BITS > 32
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#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
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#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
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#endif
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    lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
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    p = *lp;
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    if (!p) {
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        /* allocate if not found */
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        if (!alloc)
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            return NULL;
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        p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
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        memset(p, 0, sizeof(void *) * L1_SIZE);
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        *lp = p;
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    }
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#endif
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    lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
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    pd = *lp;
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    if (!pd) {
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        int i;
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        /* allocate if not found */
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        if (!alloc)
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            return NULL;
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        pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
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        *lp = pd;
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        for (i = 0; i < L2_SIZE; i++)
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          pd[i].phys_offset = IO_MEM_UNASSIGNED;
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    }
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    return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
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}
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static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
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{
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    return phys_page_find_alloc(index, 0);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void tlb_protect_code(ram_addr_t ram_addr);
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static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
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                                    target_ulong vaddr);
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#endif
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void cpu_exec_init(CPUState *env)
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{
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    CPUState **penv;
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    int cpu_index;
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    if (!code_gen_ptr) {
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        code_gen_ptr = code_gen_buffer;
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        page_init();
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        io_mem_init();
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    }
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    env->next_cpu = NULL;
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    penv = &first_cpu;
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    cpu_index = 0;
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    while (*penv != NULL) {
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        penv = (CPUState **)&(*penv)->next_cpu;
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        cpu_index++;
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    }
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    env->cpu_index = cpu_index;
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    env->nb_watchpoints = 0;
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    *penv = env;
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}
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static inline void invalidate_page_bitmap(PageDesc *p)
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{
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    if (p->code_bitmap) {
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        qemu_free(p->code_bitmap);
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        p->code_bitmap = NULL;
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    }
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    p->code_write_count = 0;
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}
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/* set to NULL all the 'first_tb' fields in all PageDescs */
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static void page_flush_tb(void)
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{
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    int i, j;
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    PageDesc *p;
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    for(i = 0; i < L1_SIZE; i++) {
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        p = l1_map[i];
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        if (p) {
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            for(j = 0; j < L2_SIZE; j++) {
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                p->first_tb = NULL;
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                invalidate_page_bitmap(p);
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                p++;
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            }
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        }
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    }
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}
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/* flush all the translation blocks */
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/* XXX: tb_flush is currently not thread safe */
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void tb_flush(CPUState *env1)
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{
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    CPUState *env;
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#if defined(DEBUG_FLUSH)
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    printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
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           (unsigned long)(code_gen_ptr - code_gen_buffer),
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           nb_tbs, nb_tbs > 0 ?
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           ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
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#endif
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    nb_tbs = 0;
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    for(env = first_cpu; env != NULL; env = env->next_cpu) {
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        memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
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    }
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    memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
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    page_flush_tb();
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    code_gen_ptr = code_gen_buffer;
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    /* XXX: flush processor icache at this point if cache flush is
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       expensive */
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    tb_flush_count++;
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}
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#ifdef DEBUG_TB_CHECK
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static void tb_invalidate_check(target_ulong address)
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{
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    TranslationBlock *tb;
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    int i;
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    address &= TARGET_PAGE_MASK;
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    for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
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        for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
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            if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
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                  address >= tb->pc + tb->size)) {
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                printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
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                       address, (long)tb->pc, tb->size);
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            }
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        }
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    }
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}
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/* verify that all the pages have correct rights for code */
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static void tb_page_check(void)
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{
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    TranslationBlock *tb;
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    int i, flags1, flags2;
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    for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
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        for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
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            flags1 = page_get_flags(tb->pc);
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            flags2 = page_get_flags(tb->pc + tb->size - 1);
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            if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
391 fd6ce8f6 bellard
                printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
392 99773bd4 pbrook
                       (long)tb->pc, tb->size, flags1, flags2);
393 fd6ce8f6 bellard
            }
394 fd6ce8f6 bellard
        }
395 fd6ce8f6 bellard
    }
396 fd6ce8f6 bellard
}
397 fd6ce8f6 bellard
398 d4e8164f bellard
void tb_jmp_check(TranslationBlock *tb)
399 d4e8164f bellard
{
400 d4e8164f bellard
    TranslationBlock *tb1;
401 d4e8164f bellard
    unsigned int n1;
402 d4e8164f bellard
403 d4e8164f bellard
    /* suppress any remaining jumps to this TB */
404 d4e8164f bellard
    tb1 = tb->jmp_first;
405 d4e8164f bellard
    for(;;) {
406 d4e8164f bellard
        n1 = (long)tb1 & 3;
407 d4e8164f bellard
        tb1 = (TranslationBlock *)((long)tb1 & ~3);
408 d4e8164f bellard
        if (n1 == 2)
409 d4e8164f bellard
            break;
410 d4e8164f bellard
        tb1 = tb1->jmp_next[n1];
411 d4e8164f bellard
    }
412 d4e8164f bellard
    /* check end of list */
413 d4e8164f bellard
    if (tb1 != tb) {
414 d4e8164f bellard
        printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
415 d4e8164f bellard
    }
416 d4e8164f bellard
}
417 d4e8164f bellard
418 fd6ce8f6 bellard
#endif
419 fd6ce8f6 bellard
420 fd6ce8f6 bellard
/* invalidate one TB */
421 fd6ce8f6 bellard
static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
422 fd6ce8f6 bellard
                             int next_offset)
423 fd6ce8f6 bellard
{
424 fd6ce8f6 bellard
    TranslationBlock *tb1;
425 fd6ce8f6 bellard
    for(;;) {
426 fd6ce8f6 bellard
        tb1 = *ptb;
427 fd6ce8f6 bellard
        if (tb1 == tb) {
428 fd6ce8f6 bellard
            *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
429 fd6ce8f6 bellard
            break;
430 fd6ce8f6 bellard
        }
431 fd6ce8f6 bellard
        ptb = (TranslationBlock **)((char *)tb1 + next_offset);
432 fd6ce8f6 bellard
    }
433 fd6ce8f6 bellard
}
434 fd6ce8f6 bellard
435 9fa3e853 bellard
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
436 9fa3e853 bellard
{
437 9fa3e853 bellard
    TranslationBlock *tb1;
438 9fa3e853 bellard
    unsigned int n1;
439 9fa3e853 bellard
440 9fa3e853 bellard
    for(;;) {
441 9fa3e853 bellard
        tb1 = *ptb;
442 9fa3e853 bellard
        n1 = (long)tb1 & 3;
443 9fa3e853 bellard
        tb1 = (TranslationBlock *)((long)tb1 & ~3);
444 9fa3e853 bellard
        if (tb1 == tb) {
445 9fa3e853 bellard
            *ptb = tb1->page_next[n1];
446 9fa3e853 bellard
            break;
447 9fa3e853 bellard
        }
448 9fa3e853 bellard
        ptb = &tb1->page_next[n1];
449 9fa3e853 bellard
    }
450 9fa3e853 bellard
}
451 9fa3e853 bellard
452 d4e8164f bellard
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
453 d4e8164f bellard
{
454 d4e8164f bellard
    TranslationBlock *tb1, **ptb;
455 d4e8164f bellard
    unsigned int n1;
456 d4e8164f bellard
457 d4e8164f bellard
    ptb = &tb->jmp_next[n];
458 d4e8164f bellard
    tb1 = *ptb;
459 d4e8164f bellard
    if (tb1) {
460 d4e8164f bellard
        /* find tb(n) in circular list */
461 d4e8164f bellard
        for(;;) {
462 d4e8164f bellard
            tb1 = *ptb;
463 d4e8164f bellard
            n1 = (long)tb1 & 3;
464 d4e8164f bellard
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
465 d4e8164f bellard
            if (n1 == n && tb1 == tb)
466 d4e8164f bellard
                break;
467 d4e8164f bellard
            if (n1 == 2) {
468 d4e8164f bellard
                ptb = &tb1->jmp_first;
469 d4e8164f bellard
            } else {
470 d4e8164f bellard
                ptb = &tb1->jmp_next[n1];
471 d4e8164f bellard
            }
472 d4e8164f bellard
        }
473 d4e8164f bellard
        /* now we can suppress tb(n) from the list */
474 d4e8164f bellard
        *ptb = tb->jmp_next[n];
475 d4e8164f bellard
476 d4e8164f bellard
        tb->jmp_next[n] = NULL;
477 d4e8164f bellard
    }
478 d4e8164f bellard
}
479 d4e8164f bellard
480 d4e8164f bellard
/* reset the jump entry 'n' of a TB so that it is not chained to
481 d4e8164f bellard
   another TB */
482 d4e8164f bellard
static inline void tb_reset_jump(TranslationBlock *tb, int n)
483 d4e8164f bellard
{
484 d4e8164f bellard
    tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
485 d4e8164f bellard
}
486 d4e8164f bellard
487 8a40a180 bellard
static inline void tb_phys_invalidate(TranslationBlock *tb, unsigned int page_addr)
488 fd6ce8f6 bellard
{
489 6a00d601 bellard
    CPUState *env;
490 8a40a180 bellard
    PageDesc *p;
491 d4e8164f bellard
    unsigned int h, n1;
492 8a40a180 bellard
    target_ulong phys_pc;
493 8a40a180 bellard
    TranslationBlock *tb1, *tb2;
494 3b46e624 ths
495 8a40a180 bellard
    /* remove the TB from the hash list */
496 8a40a180 bellard
    phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
497 8a40a180 bellard
    h = tb_phys_hash_func(phys_pc);
498 5fafdf24 ths
    tb_remove(&tb_phys_hash[h], tb,
499 8a40a180 bellard
              offsetof(TranslationBlock, phys_hash_next));
500 8a40a180 bellard
501 8a40a180 bellard
    /* remove the TB from the page list */
502 8a40a180 bellard
    if (tb->page_addr[0] != page_addr) {
503 8a40a180 bellard
        p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
504 8a40a180 bellard
        tb_page_remove(&p->first_tb, tb);
505 8a40a180 bellard
        invalidate_page_bitmap(p);
506 8a40a180 bellard
    }
507 8a40a180 bellard
    if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
508 8a40a180 bellard
        p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
509 8a40a180 bellard
        tb_page_remove(&p->first_tb, tb);
510 8a40a180 bellard
        invalidate_page_bitmap(p);
511 8a40a180 bellard
    }
512 8a40a180 bellard
513 36bdbe54 bellard
    tb_invalidated_flag = 1;
514 59817ccb bellard
515 fd6ce8f6 bellard
    /* remove the TB from the hash list */
516 8a40a180 bellard
    h = tb_jmp_cache_hash_func(tb->pc);
517 6a00d601 bellard
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
518 6a00d601 bellard
        if (env->tb_jmp_cache[h] == tb)
519 6a00d601 bellard
            env->tb_jmp_cache[h] = NULL;
520 6a00d601 bellard
    }
521 d4e8164f bellard
522 d4e8164f bellard
    /* suppress this TB from the two jump lists */
523 d4e8164f bellard
    tb_jmp_remove(tb, 0);
524 d4e8164f bellard
    tb_jmp_remove(tb, 1);
525 d4e8164f bellard
526 d4e8164f bellard
    /* suppress any remaining jumps to this TB */
527 d4e8164f bellard
    tb1 = tb->jmp_first;
528 d4e8164f bellard
    for(;;) {
529 d4e8164f bellard
        n1 = (long)tb1 & 3;
530 d4e8164f bellard
        if (n1 == 2)
531 d4e8164f bellard
            break;
532 d4e8164f bellard
        tb1 = (TranslationBlock *)((long)tb1 & ~3);
533 d4e8164f bellard
        tb2 = tb1->jmp_next[n1];
534 d4e8164f bellard
        tb_reset_jump(tb1, n1);
535 d4e8164f bellard
        tb1->jmp_next[n1] = NULL;
536 d4e8164f bellard
        tb1 = tb2;
537 d4e8164f bellard
    }
538 d4e8164f bellard
    tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
539 9fa3e853 bellard
540 e3db7226 bellard
    tb_phys_invalidate_count++;
541 9fa3e853 bellard
}
542 9fa3e853 bellard
543 9fa3e853 bellard
static inline void set_bits(uint8_t *tab, int start, int len)
544 9fa3e853 bellard
{
545 9fa3e853 bellard
    int end, mask, end1;
546 9fa3e853 bellard
547 9fa3e853 bellard
    end = start + len;
548 9fa3e853 bellard
    tab += start >> 3;
549 9fa3e853 bellard
    mask = 0xff << (start & 7);
550 9fa3e853 bellard
    if ((start & ~7) == (end & ~7)) {
551 9fa3e853 bellard
        if (start < end) {
552 9fa3e853 bellard
            mask &= ~(0xff << (end & 7));
553 9fa3e853 bellard
            *tab |= mask;
554 9fa3e853 bellard
        }
555 9fa3e853 bellard
    } else {
556 9fa3e853 bellard
        *tab++ |= mask;
557 9fa3e853 bellard
        start = (start + 8) & ~7;
558 9fa3e853 bellard
        end1 = end & ~7;
559 9fa3e853 bellard
        while (start < end1) {
560 9fa3e853 bellard
            *tab++ = 0xff;
561 9fa3e853 bellard
            start += 8;
562 9fa3e853 bellard
        }
563 9fa3e853 bellard
        if (start < end) {
564 9fa3e853 bellard
            mask = ~(0xff << (end & 7));
565 9fa3e853 bellard
            *tab |= mask;
566 9fa3e853 bellard
        }
567 9fa3e853 bellard
    }
568 9fa3e853 bellard
}
569 9fa3e853 bellard
570 9fa3e853 bellard
static void build_page_bitmap(PageDesc *p)
571 9fa3e853 bellard
{
572 9fa3e853 bellard
    int n, tb_start, tb_end;
573 9fa3e853 bellard
    TranslationBlock *tb;
574 3b46e624 ths
575 59817ccb bellard
    p->code_bitmap = qemu_malloc(TARGET_PAGE_SIZE / 8);
576 9fa3e853 bellard
    if (!p->code_bitmap)
577 9fa3e853 bellard
        return;
578 9fa3e853 bellard
    memset(p->code_bitmap, 0, TARGET_PAGE_SIZE / 8);
579 9fa3e853 bellard
580 9fa3e853 bellard
    tb = p->first_tb;
581 9fa3e853 bellard
    while (tb != NULL) {
582 9fa3e853 bellard
        n = (long)tb & 3;
583 9fa3e853 bellard
        tb = (TranslationBlock *)((long)tb & ~3);
584 9fa3e853 bellard
        /* NOTE: this is subtle as a TB may span two physical pages */
585 9fa3e853 bellard
        if (n == 0) {
586 9fa3e853 bellard
            /* NOTE: tb_end may be after the end of the page, but
587 9fa3e853 bellard
               it is not a problem */
588 9fa3e853 bellard
            tb_start = tb->pc & ~TARGET_PAGE_MASK;
589 9fa3e853 bellard
            tb_end = tb_start + tb->size;
590 9fa3e853 bellard
            if (tb_end > TARGET_PAGE_SIZE)
591 9fa3e853 bellard
                tb_end = TARGET_PAGE_SIZE;
592 9fa3e853 bellard
        } else {
593 9fa3e853 bellard
            tb_start = 0;
594 9fa3e853 bellard
            tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
595 9fa3e853 bellard
        }
596 9fa3e853 bellard
        set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
597 9fa3e853 bellard
        tb = tb->page_next[n];
598 9fa3e853 bellard
    }
599 9fa3e853 bellard
}
600 9fa3e853 bellard
601 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
602 d720b93d bellard
603 5fafdf24 ths
static void tb_gen_code(CPUState *env,
604 d720b93d bellard
                        target_ulong pc, target_ulong cs_base, int flags,
605 d720b93d bellard
                        int cflags)
606 d720b93d bellard
{
607 d720b93d bellard
    TranslationBlock *tb;
608 d720b93d bellard
    uint8_t *tc_ptr;
609 d720b93d bellard
    target_ulong phys_pc, phys_page2, virt_page2;
610 d720b93d bellard
    int code_gen_size;
611 d720b93d bellard
612 c27004ec bellard
    phys_pc = get_phys_addr_code(env, pc);
613 c27004ec bellard
    tb = tb_alloc(pc);
614 d720b93d bellard
    if (!tb) {
615 d720b93d bellard
        /* flush must be done */
616 d720b93d bellard
        tb_flush(env);
617 d720b93d bellard
        /* cannot fail at this point */
618 c27004ec bellard
        tb = tb_alloc(pc);
619 d720b93d bellard
    }
620 d720b93d bellard
    tc_ptr = code_gen_ptr;
621 d720b93d bellard
    tb->tc_ptr = tc_ptr;
622 d720b93d bellard
    tb->cs_base = cs_base;
623 d720b93d bellard
    tb->flags = flags;
624 d720b93d bellard
    tb->cflags = cflags;
625 d720b93d bellard
    cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
626 d720b93d bellard
    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
627 3b46e624 ths
628 d720b93d bellard
    /* check next page if needed */
629 c27004ec bellard
    virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
630 d720b93d bellard
    phys_page2 = -1;
631 c27004ec bellard
    if ((pc & TARGET_PAGE_MASK) != virt_page2) {
632 d720b93d bellard
        phys_page2 = get_phys_addr_code(env, virt_page2);
633 d720b93d bellard
    }
634 d720b93d bellard
    tb_link_phys(tb, phys_pc, phys_page2);
635 d720b93d bellard
}
636 d720b93d bellard
#endif
637 3b46e624 ths
638 9fa3e853 bellard
/* invalidate all TBs which intersect with the target physical page
639 9fa3e853 bellard
   starting in range [start;end[. NOTE: start and end must refer to
640 d720b93d bellard
   the same physical page. 'is_cpu_write_access' should be true if called
641 d720b93d bellard
   from a real cpu write access: the virtual CPU will exit the current
642 d720b93d bellard
   TB if code is modified inside this TB. */
643 5fafdf24 ths
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
644 d720b93d bellard
                                   int is_cpu_write_access)
645 d720b93d bellard
{
646 d720b93d bellard
    int n, current_tb_modified, current_tb_not_found, current_flags;
647 d720b93d bellard
    CPUState *env = cpu_single_env;
648 9fa3e853 bellard
    PageDesc *p;
649 ea1c1802 bellard
    TranslationBlock *tb, *tb_next, *current_tb, *saved_tb;
650 9fa3e853 bellard
    target_ulong tb_start, tb_end;
651 d720b93d bellard
    target_ulong current_pc, current_cs_base;
652 9fa3e853 bellard
653 9fa3e853 bellard
    p = page_find(start >> TARGET_PAGE_BITS);
654 5fafdf24 ths
    if (!p)
655 9fa3e853 bellard
        return;
656 5fafdf24 ths
    if (!p->code_bitmap &&
657 d720b93d bellard
        ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
658 d720b93d bellard
        is_cpu_write_access) {
659 9fa3e853 bellard
        /* build code bitmap */
660 9fa3e853 bellard
        build_page_bitmap(p);
661 9fa3e853 bellard
    }
662 9fa3e853 bellard
663 9fa3e853 bellard
    /* we remove all the TBs in the range [start, end[ */
664 9fa3e853 bellard
    /* XXX: see if in some cases it could be faster to invalidate all the code */
665 d720b93d bellard
    current_tb_not_found = is_cpu_write_access;
666 d720b93d bellard
    current_tb_modified = 0;
667 d720b93d bellard
    current_tb = NULL; /* avoid warning */
668 d720b93d bellard
    current_pc = 0; /* avoid warning */
669 d720b93d bellard
    current_cs_base = 0; /* avoid warning */
670 d720b93d bellard
    current_flags = 0; /* avoid warning */
671 9fa3e853 bellard
    tb = p->first_tb;
672 9fa3e853 bellard
    while (tb != NULL) {
673 9fa3e853 bellard
        n = (long)tb & 3;
674 9fa3e853 bellard
        tb = (TranslationBlock *)((long)tb & ~3);
675 9fa3e853 bellard
        tb_next = tb->page_next[n];
676 9fa3e853 bellard
        /* NOTE: this is subtle as a TB may span two physical pages */
677 9fa3e853 bellard
        if (n == 0) {
678 9fa3e853 bellard
            /* NOTE: tb_end may be after the end of the page, but
679 9fa3e853 bellard
               it is not a problem */
680 9fa3e853 bellard
            tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
681 9fa3e853 bellard
            tb_end = tb_start + tb->size;
682 9fa3e853 bellard
        } else {
683 9fa3e853 bellard
            tb_start = tb->page_addr[1];
684 9fa3e853 bellard
            tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
685 9fa3e853 bellard
        }
686 9fa3e853 bellard
        if (!(tb_end <= start || tb_start >= end)) {
687 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
688 d720b93d bellard
            if (current_tb_not_found) {
689 d720b93d bellard
                current_tb_not_found = 0;
690 d720b93d bellard
                current_tb = NULL;
691 d720b93d bellard
                if (env->mem_write_pc) {
692 d720b93d bellard
                    /* now we have a real cpu fault */
693 d720b93d bellard
                    current_tb = tb_find_pc(env->mem_write_pc);
694 d720b93d bellard
                }
695 d720b93d bellard
            }
696 d720b93d bellard
            if (current_tb == tb &&
697 d720b93d bellard
                !(current_tb->cflags & CF_SINGLE_INSN)) {
698 d720b93d bellard
                /* If we are modifying the current TB, we must stop
699 d720b93d bellard
                its execution. We could be more precise by checking
700 d720b93d bellard
                that the modification is after the current PC, but it
701 d720b93d bellard
                would require a specialized function to partially
702 d720b93d bellard
                restore the CPU state */
703 3b46e624 ths
704 d720b93d bellard
                current_tb_modified = 1;
705 5fafdf24 ths
                cpu_restore_state(current_tb, env,
706 d720b93d bellard
                                  env->mem_write_pc, NULL);
707 d720b93d bellard
#if defined(TARGET_I386)
708 d720b93d bellard
                current_flags = env->hflags;
709 d720b93d bellard
                current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
710 d720b93d bellard
                current_cs_base = (target_ulong)env->segs[R_CS].base;
711 d720b93d bellard
                current_pc = current_cs_base + env->eip;
712 d720b93d bellard
#else
713 d720b93d bellard
#error unsupported CPU
714 d720b93d bellard
#endif
715 d720b93d bellard
            }
716 d720b93d bellard
#endif /* TARGET_HAS_PRECISE_SMC */
717 6f5a9f7e bellard
            /* we need to do that to handle the case where a signal
718 6f5a9f7e bellard
               occurs while doing tb_phys_invalidate() */
719 6f5a9f7e bellard
            saved_tb = NULL;
720 6f5a9f7e bellard
            if (env) {
721 6f5a9f7e bellard
                saved_tb = env->current_tb;
722 6f5a9f7e bellard
                env->current_tb = NULL;
723 6f5a9f7e bellard
            }
724 9fa3e853 bellard
            tb_phys_invalidate(tb, -1);
725 6f5a9f7e bellard
            if (env) {
726 6f5a9f7e bellard
                env->current_tb = saved_tb;
727 6f5a9f7e bellard
                if (env->interrupt_request && env->current_tb)
728 6f5a9f7e bellard
                    cpu_interrupt(env, env->interrupt_request);
729 6f5a9f7e bellard
            }
730 9fa3e853 bellard
        }
731 9fa3e853 bellard
        tb = tb_next;
732 9fa3e853 bellard
    }
733 9fa3e853 bellard
#if !defined(CONFIG_USER_ONLY)
734 9fa3e853 bellard
    /* if no code remaining, no need to continue to use slow writes */
735 9fa3e853 bellard
    if (!p->first_tb) {
736 9fa3e853 bellard
        invalidate_page_bitmap(p);
737 d720b93d bellard
        if (is_cpu_write_access) {
738 d720b93d bellard
            tlb_unprotect_code_phys(env, start, env->mem_write_vaddr);
739 d720b93d bellard
        }
740 d720b93d bellard
    }
741 d720b93d bellard
#endif
742 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
743 d720b93d bellard
    if (current_tb_modified) {
744 d720b93d bellard
        /* we generate a block containing just the instruction
745 d720b93d bellard
           modifying the memory. It will ensure that it cannot modify
746 d720b93d bellard
           itself */
747 ea1c1802 bellard
        env->current_tb = NULL;
748 5fafdf24 ths
        tb_gen_code(env, current_pc, current_cs_base, current_flags,
749 d720b93d bellard
                    CF_SINGLE_INSN);
750 d720b93d bellard
        cpu_resume_from_signal(env, NULL);
751 9fa3e853 bellard
    }
752 fd6ce8f6 bellard
#endif
753 9fa3e853 bellard
}
754 fd6ce8f6 bellard
755 9fa3e853 bellard
/* len must be <= 8 and start must be a multiple of len */
756 d720b93d bellard
static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
757 9fa3e853 bellard
{
758 9fa3e853 bellard
    PageDesc *p;
759 9fa3e853 bellard
    int offset, b;
760 59817ccb bellard
#if 0
761 a4193c8a bellard
    if (1) {
762 a4193c8a bellard
        if (loglevel) {
763 5fafdf24 ths
            fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
764 5fafdf24 ths
                   cpu_single_env->mem_write_vaddr, len,
765 5fafdf24 ths
                   cpu_single_env->eip,
766 a4193c8a bellard
                   cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
767 a4193c8a bellard
        }
768 59817ccb bellard
    }
769 59817ccb bellard
#endif
770 9fa3e853 bellard
    p = page_find(start >> TARGET_PAGE_BITS);
771 5fafdf24 ths
    if (!p)
772 9fa3e853 bellard
        return;
773 9fa3e853 bellard
    if (p->code_bitmap) {
774 9fa3e853 bellard
        offset = start & ~TARGET_PAGE_MASK;
775 9fa3e853 bellard
        b = p->code_bitmap[offset >> 3] >> (offset & 7);
776 9fa3e853 bellard
        if (b & ((1 << len) - 1))
777 9fa3e853 bellard
            goto do_invalidate;
778 9fa3e853 bellard
    } else {
779 9fa3e853 bellard
    do_invalidate:
780 d720b93d bellard
        tb_invalidate_phys_page_range(start, start + len, 1);
781 9fa3e853 bellard
    }
782 9fa3e853 bellard
}
783 9fa3e853 bellard
784 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
785 5fafdf24 ths
static void tb_invalidate_phys_page(target_ulong addr,
786 d720b93d bellard
                                    unsigned long pc, void *puc)
787 9fa3e853 bellard
{
788 d720b93d bellard
    int n, current_flags, current_tb_modified;
789 d720b93d bellard
    target_ulong current_pc, current_cs_base;
790 9fa3e853 bellard
    PageDesc *p;
791 d720b93d bellard
    TranslationBlock *tb, *current_tb;
792 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
793 d720b93d bellard
    CPUState *env = cpu_single_env;
794 d720b93d bellard
#endif
795 9fa3e853 bellard
796 9fa3e853 bellard
    addr &= TARGET_PAGE_MASK;
797 9fa3e853 bellard
    p = page_find(addr >> TARGET_PAGE_BITS);
798 5fafdf24 ths
    if (!p)
799 9fa3e853 bellard
        return;
800 9fa3e853 bellard
    tb = p->first_tb;
801 d720b93d bellard
    current_tb_modified = 0;
802 d720b93d bellard
    current_tb = NULL;
803 d720b93d bellard
    current_pc = 0; /* avoid warning */
804 d720b93d bellard
    current_cs_base = 0; /* avoid warning */
805 d720b93d bellard
    current_flags = 0; /* avoid warning */
806 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
807 d720b93d bellard
    if (tb && pc != 0) {
808 d720b93d bellard
        current_tb = tb_find_pc(pc);
809 d720b93d bellard
    }
810 d720b93d bellard
#endif
811 9fa3e853 bellard
    while (tb != NULL) {
812 9fa3e853 bellard
        n = (long)tb & 3;
813 9fa3e853 bellard
        tb = (TranslationBlock *)((long)tb & ~3);
814 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
815 d720b93d bellard
        if (current_tb == tb &&
816 d720b93d bellard
            !(current_tb->cflags & CF_SINGLE_INSN)) {
817 d720b93d bellard
                /* If we are modifying the current TB, we must stop
818 d720b93d bellard
                   its execution. We could be more precise by checking
819 d720b93d bellard
                   that the modification is after the current PC, but it
820 d720b93d bellard
                   would require a specialized function to partially
821 d720b93d bellard
                   restore the CPU state */
822 3b46e624 ths
823 d720b93d bellard
            current_tb_modified = 1;
824 d720b93d bellard
            cpu_restore_state(current_tb, env, pc, puc);
825 d720b93d bellard
#if defined(TARGET_I386)
826 d720b93d bellard
            current_flags = env->hflags;
827 d720b93d bellard
            current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
828 d720b93d bellard
            current_cs_base = (target_ulong)env->segs[R_CS].base;
829 d720b93d bellard
            current_pc = current_cs_base + env->eip;
830 d720b93d bellard
#else
831 d720b93d bellard
#error unsupported CPU
832 d720b93d bellard
#endif
833 d720b93d bellard
        }
834 d720b93d bellard
#endif /* TARGET_HAS_PRECISE_SMC */
835 9fa3e853 bellard
        tb_phys_invalidate(tb, addr);
836 9fa3e853 bellard
        tb = tb->page_next[n];
837 9fa3e853 bellard
    }
838 fd6ce8f6 bellard
    p->first_tb = NULL;
839 d720b93d bellard
#ifdef TARGET_HAS_PRECISE_SMC
840 d720b93d bellard
    if (current_tb_modified) {
841 d720b93d bellard
        /* we generate a block containing just the instruction
842 d720b93d bellard
           modifying the memory. It will ensure that it cannot modify
843 d720b93d bellard
           itself */
844 ea1c1802 bellard
        env->current_tb = NULL;
845 5fafdf24 ths
        tb_gen_code(env, current_pc, current_cs_base, current_flags,
846 d720b93d bellard
                    CF_SINGLE_INSN);
847 d720b93d bellard
        cpu_resume_from_signal(env, puc);
848 d720b93d bellard
    }
849 d720b93d bellard
#endif
850 fd6ce8f6 bellard
}
851 9fa3e853 bellard
#endif
852 fd6ce8f6 bellard
853 fd6ce8f6 bellard
/* add the tb in the target page and protect it if necessary */
854 5fafdf24 ths
static inline void tb_alloc_page(TranslationBlock *tb,
855 53a5960a pbrook
                                 unsigned int n, target_ulong page_addr)
856 fd6ce8f6 bellard
{
857 fd6ce8f6 bellard
    PageDesc *p;
858 9fa3e853 bellard
    TranslationBlock *last_first_tb;
859 9fa3e853 bellard
860 9fa3e853 bellard
    tb->page_addr[n] = page_addr;
861 3a7d929e bellard
    p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
862 9fa3e853 bellard
    tb->page_next[n] = p->first_tb;
863 9fa3e853 bellard
    last_first_tb = p->first_tb;
864 9fa3e853 bellard
    p->first_tb = (TranslationBlock *)((long)tb | n);
865 9fa3e853 bellard
    invalidate_page_bitmap(p);
866 fd6ce8f6 bellard
867 107db443 bellard
#if defined(TARGET_HAS_SMC) || 1
868 d720b93d bellard
869 9fa3e853 bellard
#if defined(CONFIG_USER_ONLY)
870 fd6ce8f6 bellard
    if (p->flags & PAGE_WRITE) {
871 53a5960a pbrook
        target_ulong addr;
872 53a5960a pbrook
        PageDesc *p2;
873 9fa3e853 bellard
        int prot;
874 9fa3e853 bellard
875 fd6ce8f6 bellard
        /* force the host page as non writable (writes will have a
876 fd6ce8f6 bellard
           page fault + mprotect overhead) */
877 53a5960a pbrook
        page_addr &= qemu_host_page_mask;
878 fd6ce8f6 bellard
        prot = 0;
879 53a5960a pbrook
        for(addr = page_addr; addr < page_addr + qemu_host_page_size;
880 53a5960a pbrook
            addr += TARGET_PAGE_SIZE) {
881 53a5960a pbrook
882 53a5960a pbrook
            p2 = page_find (addr >> TARGET_PAGE_BITS);
883 53a5960a pbrook
            if (!p2)
884 53a5960a pbrook
                continue;
885 53a5960a pbrook
            prot |= p2->flags;
886 53a5960a pbrook
            p2->flags &= ~PAGE_WRITE;
887 53a5960a pbrook
            page_get_flags(addr);
888 53a5960a pbrook
          }
889 5fafdf24 ths
        mprotect(g2h(page_addr), qemu_host_page_size,
890 fd6ce8f6 bellard
                 (prot & PAGE_BITS) & ~PAGE_WRITE);
891 fd6ce8f6 bellard
#ifdef DEBUG_TB_INVALIDATE
892 ab3d1727 blueswir1
        printf("protecting code page: 0x" TARGET_FMT_lx "\n",
893 53a5960a pbrook
               page_addr);
894 fd6ce8f6 bellard
#endif
895 fd6ce8f6 bellard
    }
896 9fa3e853 bellard
#else
897 9fa3e853 bellard
    /* if some code is already present, then the pages are already
898 9fa3e853 bellard
       protected. So we handle the case where only the first TB is
899 9fa3e853 bellard
       allocated in a physical page */
900 9fa3e853 bellard
    if (!last_first_tb) {
901 6a00d601 bellard
        tlb_protect_code(page_addr);
902 9fa3e853 bellard
    }
903 9fa3e853 bellard
#endif
904 d720b93d bellard
905 d720b93d bellard
#endif /* TARGET_HAS_SMC */
906 fd6ce8f6 bellard
}
907 fd6ce8f6 bellard
908 fd6ce8f6 bellard
/* Allocate a new translation block. Flush the translation buffer if
909 fd6ce8f6 bellard
   too many translation blocks or too much generated code. */
910 c27004ec bellard
TranslationBlock *tb_alloc(target_ulong pc)
911 fd6ce8f6 bellard
{
912 fd6ce8f6 bellard
    TranslationBlock *tb;
913 fd6ce8f6 bellard
914 5fafdf24 ths
    if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
915 fd6ce8f6 bellard
        (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
916 d4e8164f bellard
        return NULL;
917 fd6ce8f6 bellard
    tb = &tbs[nb_tbs++];
918 fd6ce8f6 bellard
    tb->pc = pc;
919 b448f2f3 bellard
    tb->cflags = 0;
920 d4e8164f bellard
    return tb;
921 d4e8164f bellard
}
922 d4e8164f bellard
923 9fa3e853 bellard
/* add a new TB and link it to the physical page tables. phys_page2 is
924 9fa3e853 bellard
   (-1) to indicate that only one page contains the TB. */
925 5fafdf24 ths
void tb_link_phys(TranslationBlock *tb,
926 9fa3e853 bellard
                  target_ulong phys_pc, target_ulong phys_page2)
927 d4e8164f bellard
{
928 9fa3e853 bellard
    unsigned int h;
929 9fa3e853 bellard
    TranslationBlock **ptb;
930 9fa3e853 bellard
931 9fa3e853 bellard
    /* add in the physical hash table */
932 9fa3e853 bellard
    h = tb_phys_hash_func(phys_pc);
933 9fa3e853 bellard
    ptb = &tb_phys_hash[h];
934 9fa3e853 bellard
    tb->phys_hash_next = *ptb;
935 9fa3e853 bellard
    *ptb = tb;
936 fd6ce8f6 bellard
937 fd6ce8f6 bellard
    /* add in the page list */
938 9fa3e853 bellard
    tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
939 9fa3e853 bellard
    if (phys_page2 != -1)
940 9fa3e853 bellard
        tb_alloc_page(tb, 1, phys_page2);
941 9fa3e853 bellard
    else
942 9fa3e853 bellard
        tb->page_addr[1] = -1;
943 9fa3e853 bellard
944 d4e8164f bellard
    tb->jmp_first = (TranslationBlock *)((long)tb | 2);
945 d4e8164f bellard
    tb->jmp_next[0] = NULL;
946 d4e8164f bellard
    tb->jmp_next[1] = NULL;
947 d4e8164f bellard
948 d4e8164f bellard
    /* init original jump addresses */
949 d4e8164f bellard
    if (tb->tb_next_offset[0] != 0xffff)
950 d4e8164f bellard
        tb_reset_jump(tb, 0);
951 d4e8164f bellard
    if (tb->tb_next_offset[1] != 0xffff)
952 d4e8164f bellard
        tb_reset_jump(tb, 1);
953 8a40a180 bellard
954 8a40a180 bellard
#ifdef DEBUG_TB_CHECK
955 8a40a180 bellard
    tb_page_check();
956 8a40a180 bellard
#endif
957 fd6ce8f6 bellard
}
958 fd6ce8f6 bellard
959 9fa3e853 bellard
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
960 9fa3e853 bellard
   tb[1].tc_ptr. Return NULL if not found */
961 9fa3e853 bellard
TranslationBlock *tb_find_pc(unsigned long tc_ptr)
962 fd6ce8f6 bellard
{
963 9fa3e853 bellard
    int m_min, m_max, m;
964 9fa3e853 bellard
    unsigned long v;
965 9fa3e853 bellard
    TranslationBlock *tb;
966 a513fe19 bellard
967 a513fe19 bellard
    if (nb_tbs <= 0)
968 a513fe19 bellard
        return NULL;
969 a513fe19 bellard
    if (tc_ptr < (unsigned long)code_gen_buffer ||
970 a513fe19 bellard
        tc_ptr >= (unsigned long)code_gen_ptr)
971 a513fe19 bellard
        return NULL;
972 a513fe19 bellard
    /* binary search (cf Knuth) */
973 a513fe19 bellard
    m_min = 0;
974 a513fe19 bellard
    m_max = nb_tbs - 1;
975 a513fe19 bellard
    while (m_min <= m_max) {
976 a513fe19 bellard
        m = (m_min + m_max) >> 1;
977 a513fe19 bellard
        tb = &tbs[m];
978 a513fe19 bellard
        v = (unsigned long)tb->tc_ptr;
979 a513fe19 bellard
        if (v == tc_ptr)
980 a513fe19 bellard
            return tb;
981 a513fe19 bellard
        else if (tc_ptr < v) {
982 a513fe19 bellard
            m_max = m - 1;
983 a513fe19 bellard
        } else {
984 a513fe19 bellard
            m_min = m + 1;
985 a513fe19 bellard
        }
986 5fafdf24 ths
    }
987 a513fe19 bellard
    return &tbs[m_max];
988 a513fe19 bellard
}
989 7501267e bellard
990 ea041c0e bellard
static void tb_reset_jump_recursive(TranslationBlock *tb);
991 ea041c0e bellard
992 ea041c0e bellard
static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
993 ea041c0e bellard
{
994 ea041c0e bellard
    TranslationBlock *tb1, *tb_next, **ptb;
995 ea041c0e bellard
    unsigned int n1;
996 ea041c0e bellard
997 ea041c0e bellard
    tb1 = tb->jmp_next[n];
998 ea041c0e bellard
    if (tb1 != NULL) {
999 ea041c0e bellard
        /* find head of list */
1000 ea041c0e bellard
        for(;;) {
1001 ea041c0e bellard
            n1 = (long)tb1 & 3;
1002 ea041c0e bellard
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
1003 ea041c0e bellard
            if (n1 == 2)
1004 ea041c0e bellard
                break;
1005 ea041c0e bellard
            tb1 = tb1->jmp_next[n1];
1006 ea041c0e bellard
        }
1007 ea041c0e bellard
        /* we are now sure now that tb jumps to tb1 */
1008 ea041c0e bellard
        tb_next = tb1;
1009 ea041c0e bellard
1010 ea041c0e bellard
        /* remove tb from the jmp_first list */
1011 ea041c0e bellard
        ptb = &tb_next->jmp_first;
1012 ea041c0e bellard
        for(;;) {
1013 ea041c0e bellard
            tb1 = *ptb;
1014 ea041c0e bellard
            n1 = (long)tb1 & 3;
1015 ea041c0e bellard
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
1016 ea041c0e bellard
            if (n1 == n && tb1 == tb)
1017 ea041c0e bellard
                break;
1018 ea041c0e bellard
            ptb = &tb1->jmp_next[n1];
1019 ea041c0e bellard
        }
1020 ea041c0e bellard
        *ptb = tb->jmp_next[n];
1021 ea041c0e bellard
        tb->jmp_next[n] = NULL;
1022 3b46e624 ths
1023 ea041c0e bellard
        /* suppress the jump to next tb in generated code */
1024 ea041c0e bellard
        tb_reset_jump(tb, n);
1025 ea041c0e bellard
1026 0124311e bellard
        /* suppress jumps in the tb on which we could have jumped */
1027 ea041c0e bellard
        tb_reset_jump_recursive(tb_next);
1028 ea041c0e bellard
    }
1029 ea041c0e bellard
}
1030 ea041c0e bellard
1031 ea041c0e bellard
static void tb_reset_jump_recursive(TranslationBlock *tb)
1032 ea041c0e bellard
{
1033 ea041c0e bellard
    tb_reset_jump_recursive2(tb, 0);
1034 ea041c0e bellard
    tb_reset_jump_recursive2(tb, 1);
1035 ea041c0e bellard
}
1036 ea041c0e bellard
1037 1fddef4b bellard
#if defined(TARGET_HAS_ICE)
1038 d720b93d bellard
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1039 d720b93d bellard
{
1040 9b3c35e0 j_mayer
    target_phys_addr_t addr;
1041 9b3c35e0 j_mayer
    target_ulong pd;
1042 c2f07f81 pbrook
    ram_addr_t ram_addr;
1043 c2f07f81 pbrook
    PhysPageDesc *p;
1044 d720b93d bellard
1045 c2f07f81 pbrook
    addr = cpu_get_phys_page_debug(env, pc);
1046 c2f07f81 pbrook
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
1047 c2f07f81 pbrook
    if (!p) {
1048 c2f07f81 pbrook
        pd = IO_MEM_UNASSIGNED;
1049 c2f07f81 pbrook
    } else {
1050 c2f07f81 pbrook
        pd = p->phys_offset;
1051 c2f07f81 pbrook
    }
1052 c2f07f81 pbrook
    ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
1053 706cd4b5 pbrook
    tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1054 d720b93d bellard
}
1055 c27004ec bellard
#endif
1056 d720b93d bellard
1057 6658ffb8 pbrook
/* Add a watchpoint.  */
1058 6658ffb8 pbrook
int  cpu_watchpoint_insert(CPUState *env, target_ulong addr)
1059 6658ffb8 pbrook
{
1060 6658ffb8 pbrook
    int i;
1061 6658ffb8 pbrook
1062 6658ffb8 pbrook
    for (i = 0; i < env->nb_watchpoints; i++) {
1063 6658ffb8 pbrook
        if (addr == env->watchpoint[i].vaddr)
1064 6658ffb8 pbrook
            return 0;
1065 6658ffb8 pbrook
    }
1066 6658ffb8 pbrook
    if (env->nb_watchpoints >= MAX_WATCHPOINTS)
1067 6658ffb8 pbrook
        return -1;
1068 6658ffb8 pbrook
1069 6658ffb8 pbrook
    i = env->nb_watchpoints++;
1070 6658ffb8 pbrook
    env->watchpoint[i].vaddr = addr;
1071 6658ffb8 pbrook
    tlb_flush_page(env, addr);
1072 6658ffb8 pbrook
    /* FIXME: This flush is needed because of the hack to make memory ops
1073 6658ffb8 pbrook
       terminate the TB.  It can be removed once the proper IO trap and
1074 6658ffb8 pbrook
       re-execute bits are in.  */
1075 6658ffb8 pbrook
    tb_flush(env);
1076 6658ffb8 pbrook
    return i;
1077 6658ffb8 pbrook
}
1078 6658ffb8 pbrook
1079 6658ffb8 pbrook
/* Remove a watchpoint.  */
1080 6658ffb8 pbrook
int cpu_watchpoint_remove(CPUState *env, target_ulong addr)
1081 6658ffb8 pbrook
{
1082 6658ffb8 pbrook
    int i;
1083 6658ffb8 pbrook
1084 6658ffb8 pbrook
    for (i = 0; i < env->nb_watchpoints; i++) {
1085 6658ffb8 pbrook
        if (addr == env->watchpoint[i].vaddr) {
1086 6658ffb8 pbrook
            env->nb_watchpoints--;
1087 6658ffb8 pbrook
            env->watchpoint[i] = env->watchpoint[env->nb_watchpoints];
1088 6658ffb8 pbrook
            tlb_flush_page(env, addr);
1089 6658ffb8 pbrook
            return 0;
1090 6658ffb8 pbrook
        }
1091 6658ffb8 pbrook
    }
1092 6658ffb8 pbrook
    return -1;
1093 6658ffb8 pbrook
}
1094 6658ffb8 pbrook
1095 c33a346e bellard
/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
1096 c33a346e bellard
   breakpoint is reached */
1097 2e12669a bellard
int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
1098 4c3a88a2 bellard
{
1099 1fddef4b bellard
#if defined(TARGET_HAS_ICE)
1100 4c3a88a2 bellard
    int i;
1101 3b46e624 ths
1102 4c3a88a2 bellard
    for(i = 0; i < env->nb_breakpoints; i++) {
1103 4c3a88a2 bellard
        if (env->breakpoints[i] == pc)
1104 4c3a88a2 bellard
            return 0;
1105 4c3a88a2 bellard
    }
1106 4c3a88a2 bellard
1107 4c3a88a2 bellard
    if (env->nb_breakpoints >= MAX_BREAKPOINTS)
1108 4c3a88a2 bellard
        return -1;
1109 4c3a88a2 bellard
    env->breakpoints[env->nb_breakpoints++] = pc;
1110 3b46e624 ths
1111 d720b93d bellard
    breakpoint_invalidate(env, pc);
1112 4c3a88a2 bellard
    return 0;
1113 4c3a88a2 bellard
#else
1114 4c3a88a2 bellard
    return -1;
1115 4c3a88a2 bellard
#endif
1116 4c3a88a2 bellard
}
1117 4c3a88a2 bellard
1118 4c3a88a2 bellard
/* remove a breakpoint */
1119 2e12669a bellard
int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
1120 4c3a88a2 bellard
{
1121 1fddef4b bellard
#if defined(TARGET_HAS_ICE)
1122 4c3a88a2 bellard
    int i;
1123 4c3a88a2 bellard
    for(i = 0; i < env->nb_breakpoints; i++) {
1124 4c3a88a2 bellard
        if (env->breakpoints[i] == pc)
1125 4c3a88a2 bellard
            goto found;
1126 4c3a88a2 bellard
    }
1127 4c3a88a2 bellard
    return -1;
1128 4c3a88a2 bellard
 found:
1129 4c3a88a2 bellard
    env->nb_breakpoints--;
1130 1fddef4b bellard
    if (i < env->nb_breakpoints)
1131 1fddef4b bellard
      env->breakpoints[i] = env->breakpoints[env->nb_breakpoints];
1132 d720b93d bellard
1133 d720b93d bellard
    breakpoint_invalidate(env, pc);
1134 4c3a88a2 bellard
    return 0;
1135 4c3a88a2 bellard
#else
1136 4c3a88a2 bellard
    return -1;
1137 4c3a88a2 bellard
#endif
1138 4c3a88a2 bellard
}
1139 4c3a88a2 bellard
1140 c33a346e bellard
/* enable or disable single step mode. EXCP_DEBUG is returned by the
1141 c33a346e bellard
   CPU loop after each instruction */
1142 c33a346e bellard
void cpu_single_step(CPUState *env, int enabled)
1143 c33a346e bellard
{
1144 1fddef4b bellard
#if defined(TARGET_HAS_ICE)
1145 c33a346e bellard
    if (env->singlestep_enabled != enabled) {
1146 c33a346e bellard
        env->singlestep_enabled = enabled;
1147 c33a346e bellard
        /* must flush all the translated code to avoid inconsistancies */
1148 9fa3e853 bellard
        /* XXX: only flush what is necessary */
1149 0124311e bellard
        tb_flush(env);
1150 c33a346e bellard
    }
1151 c33a346e bellard
#endif
1152 c33a346e bellard
}
1153 c33a346e bellard
1154 34865134 bellard
/* enable or disable low levels log */
1155 34865134 bellard
void cpu_set_log(int log_flags)
1156 34865134 bellard
{
1157 34865134 bellard
    loglevel = log_flags;
1158 34865134 bellard
    if (loglevel && !logfile) {
1159 11fcfab4 pbrook
        logfile = fopen(logfilename, log_append ? "a" : "w");
1160 34865134 bellard
        if (!logfile) {
1161 34865134 bellard
            perror(logfilename);
1162 34865134 bellard
            _exit(1);
1163 34865134 bellard
        }
1164 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
1165 9fa3e853 bellard
        /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1166 9fa3e853 bellard
        {
1167 9fa3e853 bellard
            static uint8_t logfile_buf[4096];
1168 9fa3e853 bellard
            setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1169 9fa3e853 bellard
        }
1170 9fa3e853 bellard
#else
1171 34865134 bellard
        setvbuf(logfile, NULL, _IOLBF, 0);
1172 9fa3e853 bellard
#endif
1173 e735b91c pbrook
        log_append = 1;
1174 e735b91c pbrook
    }
1175 e735b91c pbrook
    if (!loglevel && logfile) {
1176 e735b91c pbrook
        fclose(logfile);
1177 e735b91c pbrook
        logfile = NULL;
1178 34865134 bellard
    }
1179 34865134 bellard
}
1180 34865134 bellard
1181 34865134 bellard
void cpu_set_log_filename(const char *filename)
1182 34865134 bellard
{
1183 34865134 bellard
    logfilename = strdup(filename);
1184 e735b91c pbrook
    if (logfile) {
1185 e735b91c pbrook
        fclose(logfile);
1186 e735b91c pbrook
        logfile = NULL;
1187 e735b91c pbrook
    }
1188 e735b91c pbrook
    cpu_set_log(loglevel);
1189 34865134 bellard
}
1190 c33a346e bellard
1191 0124311e bellard
/* mask must never be zero, except for A20 change call */
1192 68a79315 bellard
void cpu_interrupt(CPUState *env, int mask)
1193 ea041c0e bellard
{
1194 ea041c0e bellard
    TranslationBlock *tb;
1195 ee8b7021 bellard
    static int interrupt_lock;
1196 59817ccb bellard
1197 68a79315 bellard
    env->interrupt_request |= mask;
1198 ea041c0e bellard
    /* if the cpu is currently executing code, we must unlink it and
1199 ea041c0e bellard
       all the potentially executing TB */
1200 ea041c0e bellard
    tb = env->current_tb;
1201 ee8b7021 bellard
    if (tb && !testandset(&interrupt_lock)) {
1202 ee8b7021 bellard
        env->current_tb = NULL;
1203 ea041c0e bellard
        tb_reset_jump_recursive(tb);
1204 ee8b7021 bellard
        interrupt_lock = 0;
1205 ea041c0e bellard
    }
1206 ea041c0e bellard
}
1207 ea041c0e bellard
1208 b54ad049 bellard
void cpu_reset_interrupt(CPUState *env, int mask)
1209 b54ad049 bellard
{
1210 b54ad049 bellard
    env->interrupt_request &= ~mask;
1211 b54ad049 bellard
}
1212 b54ad049 bellard
1213 f193c797 bellard
CPULogItem cpu_log_items[] = {
1214 5fafdf24 ths
    { CPU_LOG_TB_OUT_ASM, "out_asm",
1215 f193c797 bellard
      "show generated host assembly code for each compiled TB" },
1216 f193c797 bellard
    { CPU_LOG_TB_IN_ASM, "in_asm",
1217 f193c797 bellard
      "show target assembly code for each compiled TB" },
1218 5fafdf24 ths
    { CPU_LOG_TB_OP, "op",
1219 f193c797 bellard
      "show micro ops for each compiled TB (only usable if 'in_asm' used)" },
1220 f193c797 bellard
#ifdef TARGET_I386
1221 f193c797 bellard
    { CPU_LOG_TB_OP_OPT, "op_opt",
1222 f193c797 bellard
      "show micro ops after optimization for each compiled TB" },
1223 f193c797 bellard
#endif
1224 f193c797 bellard
    { CPU_LOG_INT, "int",
1225 f193c797 bellard
      "show interrupts/exceptions in short format" },
1226 f193c797 bellard
    { CPU_LOG_EXEC, "exec",
1227 f193c797 bellard
      "show trace before each executed TB (lots of logs)" },
1228 9fddaa0c bellard
    { CPU_LOG_TB_CPU, "cpu",
1229 e91c8a77 ths
      "show CPU state before block translation" },
1230 f193c797 bellard
#ifdef TARGET_I386
1231 f193c797 bellard
    { CPU_LOG_PCALL, "pcall",
1232 f193c797 bellard
      "show protected mode far calls/returns/exceptions" },
1233 f193c797 bellard
#endif
1234 8e3a9fd2 bellard
#ifdef DEBUG_IOPORT
1235 fd872598 bellard
    { CPU_LOG_IOPORT, "ioport",
1236 fd872598 bellard
      "show all i/o ports accesses" },
1237 8e3a9fd2 bellard
#endif
1238 f193c797 bellard
    { 0, NULL, NULL },
1239 f193c797 bellard
};
1240 f193c797 bellard
1241 f193c797 bellard
static int cmp1(const char *s1, int n, const char *s2)
1242 f193c797 bellard
{
1243 f193c797 bellard
    if (strlen(s2) != n)
1244 f193c797 bellard
        return 0;
1245 f193c797 bellard
    return memcmp(s1, s2, n) == 0;
1246 f193c797 bellard
}
1247 3b46e624 ths
1248 f193c797 bellard
/* takes a comma separated list of log masks. Return 0 if error. */
1249 f193c797 bellard
int cpu_str_to_log_mask(const char *str)
1250 f193c797 bellard
{
1251 f193c797 bellard
    CPULogItem *item;
1252 f193c797 bellard
    int mask;
1253 f193c797 bellard
    const char *p, *p1;
1254 f193c797 bellard
1255 f193c797 bellard
    p = str;
1256 f193c797 bellard
    mask = 0;
1257 f193c797 bellard
    for(;;) {
1258 f193c797 bellard
        p1 = strchr(p, ',');
1259 f193c797 bellard
        if (!p1)
1260 f193c797 bellard
            p1 = p + strlen(p);
1261 8e3a9fd2 bellard
        if(cmp1(p,p1-p,"all")) {
1262 8e3a9fd2 bellard
                for(item = cpu_log_items; item->mask != 0; item++) {
1263 8e3a9fd2 bellard
                        mask |= item->mask;
1264 8e3a9fd2 bellard
                }
1265 8e3a9fd2 bellard
        } else {
1266 f193c797 bellard
        for(item = cpu_log_items; item->mask != 0; item++) {
1267 f193c797 bellard
            if (cmp1(p, p1 - p, item->name))
1268 f193c797 bellard
                goto found;
1269 f193c797 bellard
        }
1270 f193c797 bellard
        return 0;
1271 8e3a9fd2 bellard
        }
1272 f193c797 bellard
    found:
1273 f193c797 bellard
        mask |= item->mask;
1274 f193c797 bellard
        if (*p1 != ',')
1275 f193c797 bellard
            break;
1276 f193c797 bellard
        p = p1 + 1;
1277 f193c797 bellard
    }
1278 f193c797 bellard
    return mask;
1279 f193c797 bellard
}
1280 ea041c0e bellard
1281 7501267e bellard
void cpu_abort(CPUState *env, const char *fmt, ...)
1282 7501267e bellard
{
1283 7501267e bellard
    va_list ap;
1284 7501267e bellard
1285 7501267e bellard
    va_start(ap, fmt);
1286 7501267e bellard
    fprintf(stderr, "qemu: fatal: ");
1287 7501267e bellard
    vfprintf(stderr, fmt, ap);
1288 7501267e bellard
    fprintf(stderr, "\n");
1289 7501267e bellard
#ifdef TARGET_I386
1290 0573fbfc ths
    if(env->intercept & INTERCEPT_SVM_MASK) {
1291 0573fbfc ths
        /* most probably the virtual machine should not
1292 0573fbfc ths
           be shut down but rather caught by the VMM */
1293 0573fbfc ths
        vmexit(SVM_EXIT_SHUTDOWN, 0);
1294 0573fbfc ths
    }
1295 7fe48483 bellard
    cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1296 7fe48483 bellard
#else
1297 7fe48483 bellard
    cpu_dump_state(env, stderr, fprintf, 0);
1298 7501267e bellard
#endif
1299 924edcae balrog
    if (logfile) {
1300 f9373291 j_mayer
        fprintf(logfile, "qemu: fatal: ");
1301 f9373291 j_mayer
        vfprintf(logfile, fmt, ap);
1302 f9373291 j_mayer
        fprintf(logfile, "\n");
1303 f9373291 j_mayer
#ifdef TARGET_I386
1304 f9373291 j_mayer
        cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1305 f9373291 j_mayer
#else
1306 f9373291 j_mayer
        cpu_dump_state(env, logfile, fprintf, 0);
1307 f9373291 j_mayer
#endif
1308 924edcae balrog
        fflush(logfile);
1309 924edcae balrog
        fclose(logfile);
1310 924edcae balrog
    }
1311 f9373291 j_mayer
    va_end(ap);
1312 7501267e bellard
    abort();
1313 7501267e bellard
}
1314 7501267e bellard
1315 c5be9f08 ths
CPUState *cpu_copy(CPUState *env)
1316 c5be9f08 ths
{
1317 c5be9f08 ths
    CPUState *new_env = cpu_init();
1318 c5be9f08 ths
    /* preserve chaining and index */
1319 c5be9f08 ths
    CPUState *next_cpu = new_env->next_cpu;
1320 c5be9f08 ths
    int cpu_index = new_env->cpu_index;
1321 c5be9f08 ths
    memcpy(new_env, env, sizeof(CPUState));
1322 c5be9f08 ths
    new_env->next_cpu = next_cpu;
1323 c5be9f08 ths
    new_env->cpu_index = cpu_index;
1324 c5be9f08 ths
    return new_env;
1325 c5be9f08 ths
}
1326 c5be9f08 ths
1327 0124311e bellard
#if !defined(CONFIG_USER_ONLY)
1328 0124311e bellard
1329 ee8b7021 bellard
/* NOTE: if flush_global is true, also flush global entries (not
1330 ee8b7021 bellard
   implemented yet) */
1331 ee8b7021 bellard
void tlb_flush(CPUState *env, int flush_global)
1332 33417e70 bellard
{
1333 33417e70 bellard
    int i;
1334 0124311e bellard
1335 9fa3e853 bellard
#if defined(DEBUG_TLB)
1336 9fa3e853 bellard
    printf("tlb_flush:\n");
1337 9fa3e853 bellard
#endif
1338 0124311e bellard
    /* must reset current TB so that interrupts cannot modify the
1339 0124311e bellard
       links while we are modifying them */
1340 0124311e bellard
    env->current_tb = NULL;
1341 0124311e bellard
1342 33417e70 bellard
    for(i = 0; i < CPU_TLB_SIZE; i++) {
1343 84b7b8e7 bellard
        env->tlb_table[0][i].addr_read = -1;
1344 84b7b8e7 bellard
        env->tlb_table[0][i].addr_write = -1;
1345 84b7b8e7 bellard
        env->tlb_table[0][i].addr_code = -1;
1346 84b7b8e7 bellard
        env->tlb_table[1][i].addr_read = -1;
1347 84b7b8e7 bellard
        env->tlb_table[1][i].addr_write = -1;
1348 84b7b8e7 bellard
        env->tlb_table[1][i].addr_code = -1;
1349 6fa4cea9 j_mayer
#if (NB_MMU_MODES >= 3)
1350 6fa4cea9 j_mayer
        env->tlb_table[2][i].addr_read = -1;
1351 6fa4cea9 j_mayer
        env->tlb_table[2][i].addr_write = -1;
1352 6fa4cea9 j_mayer
        env->tlb_table[2][i].addr_code = -1;
1353 6fa4cea9 j_mayer
#if (NB_MMU_MODES == 4)
1354 6fa4cea9 j_mayer
        env->tlb_table[3][i].addr_read = -1;
1355 6fa4cea9 j_mayer
        env->tlb_table[3][i].addr_write = -1;
1356 6fa4cea9 j_mayer
        env->tlb_table[3][i].addr_code = -1;
1357 6fa4cea9 j_mayer
#endif
1358 6fa4cea9 j_mayer
#endif
1359 33417e70 bellard
    }
1360 9fa3e853 bellard
1361 8a40a180 bellard
    memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1362 9fa3e853 bellard
1363 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
1364 9fa3e853 bellard
    munmap((void *)MMAP_AREA_START, MMAP_AREA_END - MMAP_AREA_START);
1365 9fa3e853 bellard
#endif
1366 0a962c02 bellard
#ifdef USE_KQEMU
1367 0a962c02 bellard
    if (env->kqemu_enabled) {
1368 0a962c02 bellard
        kqemu_flush(env, flush_global);
1369 0a962c02 bellard
    }
1370 0a962c02 bellard
#endif
1371 e3db7226 bellard
    tlb_flush_count++;
1372 33417e70 bellard
}
1373 33417e70 bellard
1374 274da6b2 bellard
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1375 61382a50 bellard
{
1376 5fafdf24 ths
    if (addr == (tlb_entry->addr_read &
1377 84b7b8e7 bellard
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1378 5fafdf24 ths
        addr == (tlb_entry->addr_write &
1379 84b7b8e7 bellard
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1380 5fafdf24 ths
        addr == (tlb_entry->addr_code &
1381 84b7b8e7 bellard
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1382 84b7b8e7 bellard
        tlb_entry->addr_read = -1;
1383 84b7b8e7 bellard
        tlb_entry->addr_write = -1;
1384 84b7b8e7 bellard
        tlb_entry->addr_code = -1;
1385 84b7b8e7 bellard
    }
1386 61382a50 bellard
}
1387 61382a50 bellard
1388 2e12669a bellard
void tlb_flush_page(CPUState *env, target_ulong addr)
1389 33417e70 bellard
{
1390 8a40a180 bellard
    int i;
1391 9fa3e853 bellard
    TranslationBlock *tb;
1392 0124311e bellard
1393 9fa3e853 bellard
#if defined(DEBUG_TLB)
1394 108c49b8 bellard
    printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1395 9fa3e853 bellard
#endif
1396 0124311e bellard
    /* must reset current TB so that interrupts cannot modify the
1397 0124311e bellard
       links while we are modifying them */
1398 0124311e bellard
    env->current_tb = NULL;
1399 61382a50 bellard
1400 61382a50 bellard
    addr &= TARGET_PAGE_MASK;
1401 61382a50 bellard
    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1402 84b7b8e7 bellard
    tlb_flush_entry(&env->tlb_table[0][i], addr);
1403 84b7b8e7 bellard
    tlb_flush_entry(&env->tlb_table[1][i], addr);
1404 6fa4cea9 j_mayer
#if (NB_MMU_MODES >= 3)
1405 6fa4cea9 j_mayer
    tlb_flush_entry(&env->tlb_table[2][i], addr);
1406 6fa4cea9 j_mayer
#if (NB_MMU_MODES == 4)
1407 6fa4cea9 j_mayer
    tlb_flush_entry(&env->tlb_table[3][i], addr);
1408 6fa4cea9 j_mayer
#endif
1409 6fa4cea9 j_mayer
#endif
1410 0124311e bellard
1411 b362e5e0 pbrook
    /* Discard jump cache entries for any tb which might potentially
1412 b362e5e0 pbrook
       overlap the flushed page.  */
1413 b362e5e0 pbrook
    i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1414 b362e5e0 pbrook
    memset (&env->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(tb));
1415 b362e5e0 pbrook
1416 b362e5e0 pbrook
    i = tb_jmp_cache_hash_page(addr);
1417 b362e5e0 pbrook
    memset (&env->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(tb));
1418 9fa3e853 bellard
1419 0124311e bellard
#if !defined(CONFIG_SOFTMMU)
1420 9fa3e853 bellard
    if (addr < MMAP_AREA_END)
1421 0124311e bellard
        munmap((void *)addr, TARGET_PAGE_SIZE);
1422 61382a50 bellard
#endif
1423 0a962c02 bellard
#ifdef USE_KQEMU
1424 0a962c02 bellard
    if (env->kqemu_enabled) {
1425 0a962c02 bellard
        kqemu_flush_page(env, addr);
1426 0a962c02 bellard
    }
1427 0a962c02 bellard
#endif
1428 9fa3e853 bellard
}
1429 9fa3e853 bellard
1430 9fa3e853 bellard
/* update the TLBs so that writes to code in the virtual page 'addr'
1431 9fa3e853 bellard
   can be detected */
1432 6a00d601 bellard
static void tlb_protect_code(ram_addr_t ram_addr)
1433 9fa3e853 bellard
{
1434 5fafdf24 ths
    cpu_physical_memory_reset_dirty(ram_addr,
1435 6a00d601 bellard
                                    ram_addr + TARGET_PAGE_SIZE,
1436 6a00d601 bellard
                                    CODE_DIRTY_FLAG);
1437 9fa3e853 bellard
}
1438 9fa3e853 bellard
1439 9fa3e853 bellard
/* update the TLB so that writes in physical page 'phys_addr' are no longer
1440 3a7d929e bellard
   tested for self modifying code */
1441 5fafdf24 ths
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1442 3a7d929e bellard
                                    target_ulong vaddr)
1443 9fa3e853 bellard
{
1444 3a7d929e bellard
    phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
1445 1ccde1cb bellard
}
1446 1ccde1cb bellard
1447 5fafdf24 ths
static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1448 1ccde1cb bellard
                                         unsigned long start, unsigned long length)
1449 1ccde1cb bellard
{
1450 1ccde1cb bellard
    unsigned long addr;
1451 84b7b8e7 bellard
    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1452 84b7b8e7 bellard
        addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1453 1ccde1cb bellard
        if ((addr - start) < length) {
1454 84b7b8e7 bellard
            tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_NOTDIRTY;
1455 1ccde1cb bellard
        }
1456 1ccde1cb bellard
    }
1457 1ccde1cb bellard
}
1458 1ccde1cb bellard
1459 3a7d929e bellard
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1460 0a962c02 bellard
                                     int dirty_flags)
1461 1ccde1cb bellard
{
1462 1ccde1cb bellard
    CPUState *env;
1463 4f2ac237 bellard
    unsigned long length, start1;
1464 0a962c02 bellard
    int i, mask, len;
1465 0a962c02 bellard
    uint8_t *p;
1466 1ccde1cb bellard
1467 1ccde1cb bellard
    start &= TARGET_PAGE_MASK;
1468 1ccde1cb bellard
    end = TARGET_PAGE_ALIGN(end);
1469 1ccde1cb bellard
1470 1ccde1cb bellard
    length = end - start;
1471 1ccde1cb bellard
    if (length == 0)
1472 1ccde1cb bellard
        return;
1473 0a962c02 bellard
    len = length >> TARGET_PAGE_BITS;
1474 3a7d929e bellard
#ifdef USE_KQEMU
1475 6a00d601 bellard
    /* XXX: should not depend on cpu context */
1476 6a00d601 bellard
    env = first_cpu;
1477 3a7d929e bellard
    if (env->kqemu_enabled) {
1478 f23db169 bellard
        ram_addr_t addr;
1479 f23db169 bellard
        addr = start;
1480 f23db169 bellard
        for(i = 0; i < len; i++) {
1481 f23db169 bellard
            kqemu_set_notdirty(env, addr);
1482 f23db169 bellard
            addr += TARGET_PAGE_SIZE;
1483 f23db169 bellard
        }
1484 3a7d929e bellard
    }
1485 3a7d929e bellard
#endif
1486 f23db169 bellard
    mask = ~dirty_flags;
1487 f23db169 bellard
    p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1488 f23db169 bellard
    for(i = 0; i < len; i++)
1489 f23db169 bellard
        p[i] &= mask;
1490 f23db169 bellard
1491 1ccde1cb bellard
    /* we modify the TLB cache so that the dirty bit will be set again
1492 1ccde1cb bellard
       when accessing the range */
1493 59817ccb bellard
    start1 = start + (unsigned long)phys_ram_base;
1494 6a00d601 bellard
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
1495 6a00d601 bellard
        for(i = 0; i < CPU_TLB_SIZE; i++)
1496 84b7b8e7 bellard
            tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
1497 6a00d601 bellard
        for(i = 0; i < CPU_TLB_SIZE; i++)
1498 84b7b8e7 bellard
            tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
1499 6fa4cea9 j_mayer
#if (NB_MMU_MODES >= 3)
1500 6fa4cea9 j_mayer
        for(i = 0; i < CPU_TLB_SIZE; i++)
1501 6fa4cea9 j_mayer
            tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1502 6fa4cea9 j_mayer
#if (NB_MMU_MODES == 4)
1503 6fa4cea9 j_mayer
        for(i = 0; i < CPU_TLB_SIZE; i++)
1504 6fa4cea9 j_mayer
            tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1505 6fa4cea9 j_mayer
#endif
1506 6fa4cea9 j_mayer
#endif
1507 6a00d601 bellard
    }
1508 59817ccb bellard
1509 59817ccb bellard
#if !defined(CONFIG_SOFTMMU)
1510 59817ccb bellard
    /* XXX: this is expensive */
1511 59817ccb bellard
    {
1512 59817ccb bellard
        VirtPageDesc *p;
1513 59817ccb bellard
        int j;
1514 59817ccb bellard
        target_ulong addr;
1515 59817ccb bellard
1516 59817ccb bellard
        for(i = 0; i < L1_SIZE; i++) {
1517 59817ccb bellard
            p = l1_virt_map[i];
1518 59817ccb bellard
            if (p) {
1519 59817ccb bellard
                addr = i << (TARGET_PAGE_BITS + L2_BITS);
1520 59817ccb bellard
                for(j = 0; j < L2_SIZE; j++) {
1521 59817ccb bellard
                    if (p->valid_tag == virt_valid_tag &&
1522 59817ccb bellard
                        p->phys_addr >= start && p->phys_addr < end &&
1523 59817ccb bellard
                        (p->prot & PROT_WRITE)) {
1524 59817ccb bellard
                        if (addr < MMAP_AREA_END) {
1525 5fafdf24 ths
                            mprotect((void *)addr, TARGET_PAGE_SIZE,
1526 59817ccb bellard
                                     p->prot & ~PROT_WRITE);
1527 59817ccb bellard
                        }
1528 59817ccb bellard
                    }
1529 59817ccb bellard
                    addr += TARGET_PAGE_SIZE;
1530 59817ccb bellard
                    p++;
1531 59817ccb bellard
                }
1532 59817ccb bellard
            }
1533 59817ccb bellard
        }
1534 59817ccb bellard
    }
1535 59817ccb bellard
#endif
1536 1ccde1cb bellard
}
1537 1ccde1cb bellard
1538 3a7d929e bellard
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1539 3a7d929e bellard
{
1540 3a7d929e bellard
    ram_addr_t ram_addr;
1541 3a7d929e bellard
1542 84b7b8e7 bellard
    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1543 5fafdf24 ths
        ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
1544 3a7d929e bellard
            tlb_entry->addend - (unsigned long)phys_ram_base;
1545 3a7d929e bellard
        if (!cpu_physical_memory_is_dirty(ram_addr)) {
1546 84b7b8e7 bellard
            tlb_entry->addr_write |= IO_MEM_NOTDIRTY;
1547 3a7d929e bellard
        }
1548 3a7d929e bellard
    }
1549 3a7d929e bellard
}
1550 3a7d929e bellard
1551 3a7d929e bellard
/* update the TLB according to the current state of the dirty bits */
1552 3a7d929e bellard
void cpu_tlb_update_dirty(CPUState *env)
1553 3a7d929e bellard
{
1554 3a7d929e bellard
    int i;
1555 3a7d929e bellard
    for(i = 0; i < CPU_TLB_SIZE; i++)
1556 84b7b8e7 bellard
        tlb_update_dirty(&env->tlb_table[0][i]);
1557 3a7d929e bellard
    for(i = 0; i < CPU_TLB_SIZE; i++)
1558 84b7b8e7 bellard
        tlb_update_dirty(&env->tlb_table[1][i]);
1559 6fa4cea9 j_mayer
#if (NB_MMU_MODES >= 3)
1560 6fa4cea9 j_mayer
    for(i = 0; i < CPU_TLB_SIZE; i++)
1561 6fa4cea9 j_mayer
        tlb_update_dirty(&env->tlb_table[2][i]);
1562 6fa4cea9 j_mayer
#if (NB_MMU_MODES == 4)
1563 6fa4cea9 j_mayer
    for(i = 0; i < CPU_TLB_SIZE; i++)
1564 6fa4cea9 j_mayer
        tlb_update_dirty(&env->tlb_table[3][i]);
1565 6fa4cea9 j_mayer
#endif
1566 6fa4cea9 j_mayer
#endif
1567 3a7d929e bellard
}
1568 3a7d929e bellard
1569 5fafdf24 ths
static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry,
1570 108c49b8 bellard
                                  unsigned long start)
1571 1ccde1cb bellard
{
1572 1ccde1cb bellard
    unsigned long addr;
1573 84b7b8e7 bellard
    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_NOTDIRTY) {
1574 84b7b8e7 bellard
        addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1575 1ccde1cb bellard
        if (addr == start) {
1576 84b7b8e7 bellard
            tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_RAM;
1577 1ccde1cb bellard
        }
1578 1ccde1cb bellard
    }
1579 1ccde1cb bellard
}
1580 1ccde1cb bellard
1581 1ccde1cb bellard
/* update the TLB corresponding to virtual page vaddr and phys addr
1582 1ccde1cb bellard
   addr so that it is no longer dirty */
1583 6a00d601 bellard
static inline void tlb_set_dirty(CPUState *env,
1584 6a00d601 bellard
                                 unsigned long addr, target_ulong vaddr)
1585 1ccde1cb bellard
{
1586 1ccde1cb bellard
    int i;
1587 1ccde1cb bellard
1588 1ccde1cb bellard
    addr &= TARGET_PAGE_MASK;
1589 1ccde1cb bellard
    i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1590 84b7b8e7 bellard
    tlb_set_dirty1(&env->tlb_table[0][i], addr);
1591 84b7b8e7 bellard
    tlb_set_dirty1(&env->tlb_table[1][i], addr);
1592 6fa4cea9 j_mayer
#if (NB_MMU_MODES >= 3)
1593 6fa4cea9 j_mayer
    tlb_set_dirty1(&env->tlb_table[2][i], addr);
1594 6fa4cea9 j_mayer
#if (NB_MMU_MODES == 4)
1595 6fa4cea9 j_mayer
    tlb_set_dirty1(&env->tlb_table[3][i], addr);
1596 6fa4cea9 j_mayer
#endif
1597 6fa4cea9 j_mayer
#endif
1598 9fa3e853 bellard
}
1599 9fa3e853 bellard
1600 59817ccb bellard
/* add a new TLB entry. At most one entry for a given virtual address
1601 59817ccb bellard
   is permitted. Return 0 if OK or 2 if the page could not be mapped
1602 59817ccb bellard
   (can only happen in non SOFTMMU mode for I/O pages or pages
1603 59817ccb bellard
   conflicting with the host address space). */
1604 5fafdf24 ths
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1605 5fafdf24 ths
                      target_phys_addr_t paddr, int prot,
1606 6ebbf390 j_mayer
                      int mmu_idx, int is_softmmu)
1607 9fa3e853 bellard
{
1608 92e873b9 bellard
    PhysPageDesc *p;
1609 4f2ac237 bellard
    unsigned long pd;
1610 9fa3e853 bellard
    unsigned int index;
1611 4f2ac237 bellard
    target_ulong address;
1612 108c49b8 bellard
    target_phys_addr_t addend;
1613 9fa3e853 bellard
    int ret;
1614 84b7b8e7 bellard
    CPUTLBEntry *te;
1615 6658ffb8 pbrook
    int i;
1616 9fa3e853 bellard
1617 92e873b9 bellard
    p = phys_page_find(paddr >> TARGET_PAGE_BITS);
1618 9fa3e853 bellard
    if (!p) {
1619 9fa3e853 bellard
        pd = IO_MEM_UNASSIGNED;
1620 9fa3e853 bellard
    } else {
1621 9fa3e853 bellard
        pd = p->phys_offset;
1622 9fa3e853 bellard
    }
1623 9fa3e853 bellard
#if defined(DEBUG_TLB)
1624 6ebbf390 j_mayer
    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1625 6ebbf390 j_mayer
           vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
1626 9fa3e853 bellard
#endif
1627 9fa3e853 bellard
1628 9fa3e853 bellard
    ret = 0;
1629 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
1630 5fafdf24 ths
    if (is_softmmu)
1631 9fa3e853 bellard
#endif
1632 9fa3e853 bellard
    {
1633 2a4188a3 bellard
        if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1634 9fa3e853 bellard
            /* IO memory case */
1635 9fa3e853 bellard
            address = vaddr | pd;
1636 9fa3e853 bellard
            addend = paddr;
1637 9fa3e853 bellard
        } else {
1638 9fa3e853 bellard
            /* standard memory */
1639 9fa3e853 bellard
            address = vaddr;
1640 9fa3e853 bellard
            addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1641 9fa3e853 bellard
        }
1642 6658ffb8 pbrook
1643 6658ffb8 pbrook
        /* Make accesses to pages with watchpoints go via the
1644 6658ffb8 pbrook
           watchpoint trap routines.  */
1645 6658ffb8 pbrook
        for (i = 0; i < env->nb_watchpoints; i++) {
1646 6658ffb8 pbrook
            if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) {
1647 6658ffb8 pbrook
                if (address & ~TARGET_PAGE_MASK) {
1648 d79acba4 balrog
                    env->watchpoint[i].addend = 0;
1649 6658ffb8 pbrook
                    address = vaddr | io_mem_watch;
1650 6658ffb8 pbrook
                } else {
1651 d79acba4 balrog
                    env->watchpoint[i].addend = pd - paddr +
1652 d79acba4 balrog
                        (unsigned long) phys_ram_base;
1653 6658ffb8 pbrook
                    /* TODO: Figure out how to make read watchpoints coexist
1654 6658ffb8 pbrook
                       with code.  */
1655 6658ffb8 pbrook
                    pd = (pd & TARGET_PAGE_MASK) | io_mem_watch | IO_MEM_ROMD;
1656 6658ffb8 pbrook
                }
1657 6658ffb8 pbrook
            }
1658 6658ffb8 pbrook
        }
1659 d79acba4 balrog
1660 90f18422 bellard
        index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1661 9fa3e853 bellard
        addend -= vaddr;
1662 6ebbf390 j_mayer
        te = &env->tlb_table[mmu_idx][index];
1663 84b7b8e7 bellard
        te->addend = addend;
1664 67b915a5 bellard
        if (prot & PAGE_READ) {
1665 84b7b8e7 bellard
            te->addr_read = address;
1666 84b7b8e7 bellard
        } else {
1667 84b7b8e7 bellard
            te->addr_read = -1;
1668 84b7b8e7 bellard
        }
1669 84b7b8e7 bellard
        if (prot & PAGE_EXEC) {
1670 84b7b8e7 bellard
            te->addr_code = address;
1671 9fa3e853 bellard
        } else {
1672 84b7b8e7 bellard
            te->addr_code = -1;
1673 9fa3e853 bellard
        }
1674 67b915a5 bellard
        if (prot & PAGE_WRITE) {
1675 5fafdf24 ths
            if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
1676 856074ec bellard
                (pd & IO_MEM_ROMD)) {
1677 856074ec bellard
                /* write access calls the I/O callback */
1678 5fafdf24 ths
                te->addr_write = vaddr |
1679 856074ec bellard
                    (pd & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
1680 5fafdf24 ths
            } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
1681 1ccde1cb bellard
                       !cpu_physical_memory_is_dirty(pd)) {
1682 84b7b8e7 bellard
                te->addr_write = vaddr | IO_MEM_NOTDIRTY;
1683 9fa3e853 bellard
            } else {
1684 84b7b8e7 bellard
                te->addr_write = address;
1685 9fa3e853 bellard
            }
1686 9fa3e853 bellard
        } else {
1687 84b7b8e7 bellard
            te->addr_write = -1;
1688 9fa3e853 bellard
        }
1689 9fa3e853 bellard
    }
1690 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
1691 9fa3e853 bellard
    else {
1692 9fa3e853 bellard
        if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM) {
1693 9fa3e853 bellard
            /* IO access: no mapping is done as it will be handled by the
1694 9fa3e853 bellard
               soft MMU */
1695 9fa3e853 bellard
            if (!(env->hflags & HF_SOFTMMU_MASK))
1696 9fa3e853 bellard
                ret = 2;
1697 9fa3e853 bellard
        } else {
1698 9fa3e853 bellard
            void *map_addr;
1699 59817ccb bellard
1700 59817ccb bellard
            if (vaddr >= MMAP_AREA_END) {
1701 59817ccb bellard
                ret = 2;
1702 59817ccb bellard
            } else {
1703 59817ccb bellard
                if (prot & PROT_WRITE) {
1704 5fafdf24 ths
                    if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
1705 d720b93d bellard
#if defined(TARGET_HAS_SMC) || 1
1706 59817ccb bellard
                        first_tb ||
1707 d720b93d bellard
#endif
1708 5fafdf24 ths
                        ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
1709 59817ccb bellard
                         !cpu_physical_memory_is_dirty(pd))) {
1710 59817ccb bellard
                        /* ROM: we do as if code was inside */
1711 59817ccb bellard
                        /* if code is present, we only map as read only and save the
1712 59817ccb bellard
                           original mapping */
1713 59817ccb bellard
                        VirtPageDesc *vp;
1714 3b46e624 ths
1715 90f18422 bellard
                        vp = virt_page_find_alloc(vaddr >> TARGET_PAGE_BITS, 1);
1716 59817ccb bellard
                        vp->phys_addr = pd;
1717 59817ccb bellard
                        vp->prot = prot;
1718 59817ccb bellard
                        vp->valid_tag = virt_valid_tag;
1719 59817ccb bellard
                        prot &= ~PAGE_WRITE;
1720 59817ccb bellard
                    }
1721 59817ccb bellard
                }
1722 5fafdf24 ths
                map_addr = mmap((void *)vaddr, TARGET_PAGE_SIZE, prot,
1723 59817ccb bellard
                                MAP_SHARED | MAP_FIXED, phys_ram_fd, (pd & TARGET_PAGE_MASK));
1724 59817ccb bellard
                if (map_addr == MAP_FAILED) {
1725 59817ccb bellard
                    cpu_abort(env, "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
1726 59817ccb bellard
                              paddr, vaddr);
1727 9fa3e853 bellard
                }
1728 9fa3e853 bellard
            }
1729 9fa3e853 bellard
        }
1730 9fa3e853 bellard
    }
1731 9fa3e853 bellard
#endif
1732 9fa3e853 bellard
    return ret;
1733 9fa3e853 bellard
}
1734 9fa3e853 bellard
1735 9fa3e853 bellard
/* called from signal handler: invalidate the code and unprotect the
1736 9fa3e853 bellard
   page. Return TRUE if the fault was succesfully handled. */
1737 53a5960a pbrook
int page_unprotect(target_ulong addr, unsigned long pc, void *puc)
1738 9fa3e853 bellard
{
1739 9fa3e853 bellard
#if !defined(CONFIG_SOFTMMU)
1740 9fa3e853 bellard
    VirtPageDesc *vp;
1741 9fa3e853 bellard
1742 9fa3e853 bellard
#if defined(DEBUG_TLB)
1743 9fa3e853 bellard
    printf("page_unprotect: addr=0x%08x\n", addr);
1744 9fa3e853 bellard
#endif
1745 9fa3e853 bellard
    addr &= TARGET_PAGE_MASK;
1746 59817ccb bellard
1747 59817ccb bellard
    /* if it is not mapped, no need to worry here */
1748 59817ccb bellard
    if (addr >= MMAP_AREA_END)
1749 59817ccb bellard
        return 0;
1750 9fa3e853 bellard
    vp = virt_page_find(addr >> TARGET_PAGE_BITS);
1751 9fa3e853 bellard
    if (!vp)
1752 9fa3e853 bellard
        return 0;
1753 9fa3e853 bellard
    /* NOTE: in this case, validate_tag is _not_ tested as it
1754 9fa3e853 bellard
       validates only the code TLB */
1755 9fa3e853 bellard
    if (vp->valid_tag != virt_valid_tag)
1756 9fa3e853 bellard
        return 0;
1757 9fa3e853 bellard
    if (!(vp->prot & PAGE_WRITE))
1758 9fa3e853 bellard
        return 0;
1759 9fa3e853 bellard
#if defined(DEBUG_TLB)
1760 5fafdf24 ths
    printf("page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x\n",
1761 9fa3e853 bellard
           addr, vp->phys_addr, vp->prot);
1762 9fa3e853 bellard
#endif
1763 59817ccb bellard
    if (mprotect((void *)addr, TARGET_PAGE_SIZE, vp->prot) < 0)
1764 59817ccb bellard
        cpu_abort(cpu_single_env, "error mprotect addr=0x%lx prot=%d\n",
1765 59817ccb bellard
                  (unsigned long)addr, vp->prot);
1766 d720b93d bellard
    /* set the dirty bit */
1767 0a962c02 bellard
    phys_ram_dirty[vp->phys_addr >> TARGET_PAGE_BITS] = 0xff;
1768 d720b93d bellard
    /* flush the code inside */
1769 d720b93d bellard
    tb_invalidate_phys_page(vp->phys_addr, pc, puc);
1770 9fa3e853 bellard
    return 1;
1771 9fa3e853 bellard
#else
1772 9fa3e853 bellard
    return 0;
1773 9fa3e853 bellard
#endif
1774 33417e70 bellard
}
1775 33417e70 bellard
1776 0124311e bellard
#else
1777 0124311e bellard
1778 ee8b7021 bellard
void tlb_flush(CPUState *env, int flush_global)
1779 0124311e bellard
{
1780 0124311e bellard
}
1781 0124311e bellard
1782 2e12669a bellard
void tlb_flush_page(CPUState *env, target_ulong addr)
1783 0124311e bellard
{
1784 0124311e bellard
}
1785 0124311e bellard
1786 5fafdf24 ths
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1787 5fafdf24 ths
                      target_phys_addr_t paddr, int prot,
1788 6ebbf390 j_mayer
                      int mmu_idx, int is_softmmu)
1789 9fa3e853 bellard
{
1790 9fa3e853 bellard
    return 0;
1791 9fa3e853 bellard
}
1792 0124311e bellard
1793 9fa3e853 bellard
/* dump memory mappings */
1794 9fa3e853 bellard
void page_dump(FILE *f)
1795 33417e70 bellard
{
1796 9fa3e853 bellard
    unsigned long start, end;
1797 9fa3e853 bellard
    int i, j, prot, prot1;
1798 9fa3e853 bellard
    PageDesc *p;
1799 33417e70 bellard
1800 9fa3e853 bellard
    fprintf(f, "%-8s %-8s %-8s %s\n",
1801 9fa3e853 bellard
            "start", "end", "size", "prot");
1802 9fa3e853 bellard
    start = -1;
1803 9fa3e853 bellard
    end = -1;
1804 9fa3e853 bellard
    prot = 0;
1805 9fa3e853 bellard
    for(i = 0; i <= L1_SIZE; i++) {
1806 9fa3e853 bellard
        if (i < L1_SIZE)
1807 9fa3e853 bellard
            p = l1_map[i];
1808 9fa3e853 bellard
        else
1809 9fa3e853 bellard
            p = NULL;
1810 9fa3e853 bellard
        for(j = 0;j < L2_SIZE; j++) {
1811 9fa3e853 bellard
            if (!p)
1812 9fa3e853 bellard
                prot1 = 0;
1813 9fa3e853 bellard
            else
1814 9fa3e853 bellard
                prot1 = p[j].flags;
1815 9fa3e853 bellard
            if (prot1 != prot) {
1816 9fa3e853 bellard
                end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
1817 9fa3e853 bellard
                if (start != -1) {
1818 9fa3e853 bellard
                    fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
1819 5fafdf24 ths
                            start, end, end - start,
1820 9fa3e853 bellard
                            prot & PAGE_READ ? 'r' : '-',
1821 9fa3e853 bellard
                            prot & PAGE_WRITE ? 'w' : '-',
1822 9fa3e853 bellard
                            prot & PAGE_EXEC ? 'x' : '-');
1823 9fa3e853 bellard
                }
1824 9fa3e853 bellard
                if (prot1 != 0)
1825 9fa3e853 bellard
                    start = end;
1826 9fa3e853 bellard
                else
1827 9fa3e853 bellard
                    start = -1;
1828 9fa3e853 bellard
                prot = prot1;
1829 9fa3e853 bellard
            }
1830 9fa3e853 bellard
            if (!p)
1831 9fa3e853 bellard
                break;
1832 9fa3e853 bellard
        }
1833 33417e70 bellard
    }
1834 33417e70 bellard
}
1835 33417e70 bellard
1836 53a5960a pbrook
int page_get_flags(target_ulong address)
1837 33417e70 bellard
{
1838 9fa3e853 bellard
    PageDesc *p;
1839 9fa3e853 bellard
1840 9fa3e853 bellard
    p = page_find(address >> TARGET_PAGE_BITS);
1841 33417e70 bellard
    if (!p)
1842 9fa3e853 bellard
        return 0;
1843 9fa3e853 bellard
    return p->flags;
1844 9fa3e853 bellard
}
1845 9fa3e853 bellard
1846 9fa3e853 bellard
/* modify the flags of a page and invalidate the code if
1847 9fa3e853 bellard
   necessary. The flag PAGE_WRITE_ORG is positionned automatically
1848 9fa3e853 bellard
   depending on PAGE_WRITE */
1849 53a5960a pbrook
void page_set_flags(target_ulong start, target_ulong end, int flags)
1850 9fa3e853 bellard
{
1851 9fa3e853 bellard
    PageDesc *p;
1852 53a5960a pbrook
    target_ulong addr;
1853 9fa3e853 bellard
1854 9fa3e853 bellard
    start = start & TARGET_PAGE_MASK;
1855 9fa3e853 bellard
    end = TARGET_PAGE_ALIGN(end);
1856 9fa3e853 bellard
    if (flags & PAGE_WRITE)
1857 9fa3e853 bellard
        flags |= PAGE_WRITE_ORG;
1858 9fa3e853 bellard
    spin_lock(&tb_lock);
1859 9fa3e853 bellard
    for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
1860 9fa3e853 bellard
        p = page_find_alloc(addr >> TARGET_PAGE_BITS);
1861 9fa3e853 bellard
        /* if the write protection is set, then we invalidate the code
1862 9fa3e853 bellard
           inside */
1863 5fafdf24 ths
        if (!(p->flags & PAGE_WRITE) &&
1864 9fa3e853 bellard
            (flags & PAGE_WRITE) &&
1865 9fa3e853 bellard
            p->first_tb) {
1866 d720b93d bellard
            tb_invalidate_phys_page(addr, 0, NULL);
1867 9fa3e853 bellard
        }
1868 9fa3e853 bellard
        p->flags = flags;
1869 9fa3e853 bellard
    }
1870 9fa3e853 bellard
    spin_unlock(&tb_lock);
1871 33417e70 bellard
}
1872 33417e70 bellard
1873 3d97b40b ths
int page_check_range(target_ulong start, target_ulong len, int flags)
1874 3d97b40b ths
{
1875 3d97b40b ths
    PageDesc *p;
1876 3d97b40b ths
    target_ulong end;
1877 3d97b40b ths
    target_ulong addr;
1878 3d97b40b ths
1879 3d97b40b ths
    end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
1880 3d97b40b ths
    start = start & TARGET_PAGE_MASK;
1881 3d97b40b ths
1882 3d97b40b ths
    if( end < start )
1883 3d97b40b ths
        /* we've wrapped around */
1884 3d97b40b ths
        return -1;
1885 3d97b40b ths
    for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
1886 3d97b40b ths
        p = page_find(addr >> TARGET_PAGE_BITS);
1887 3d97b40b ths
        if( !p )
1888 3d97b40b ths
            return -1;
1889 3d97b40b ths
        if( !(p->flags & PAGE_VALID) )
1890 3d97b40b ths
            return -1;
1891 3d97b40b ths
1892 3d97b40b ths
        if (!(p->flags & PAGE_READ) && (flags & PAGE_READ) )
1893 3d97b40b ths
            return -1;
1894 3d97b40b ths
        if (!(p->flags & PAGE_WRITE) && (flags & PAGE_WRITE) )
1895 3d97b40b ths
            return -1;
1896 3d97b40b ths
    }
1897 3d97b40b ths
    return 0;
1898 3d97b40b ths
}
1899 3d97b40b ths
1900 9fa3e853 bellard
/* called from signal handler: invalidate the code and unprotect the
1901 9fa3e853 bellard
   page. Return TRUE if the fault was succesfully handled. */
1902 53a5960a pbrook
int page_unprotect(target_ulong address, unsigned long pc, void *puc)
1903 9fa3e853 bellard
{
1904 9fa3e853 bellard
    unsigned int page_index, prot, pindex;
1905 9fa3e853 bellard
    PageDesc *p, *p1;
1906 53a5960a pbrook
    target_ulong host_start, host_end, addr;
1907 9fa3e853 bellard
1908 83fb7adf bellard
    host_start = address & qemu_host_page_mask;
1909 9fa3e853 bellard
    page_index = host_start >> TARGET_PAGE_BITS;
1910 9fa3e853 bellard
    p1 = page_find(page_index);
1911 9fa3e853 bellard
    if (!p1)
1912 9fa3e853 bellard
        return 0;
1913 83fb7adf bellard
    host_end = host_start + qemu_host_page_size;
1914 9fa3e853 bellard
    p = p1;
1915 9fa3e853 bellard
    prot = 0;
1916 9fa3e853 bellard
    for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
1917 9fa3e853 bellard
        prot |= p->flags;
1918 9fa3e853 bellard
        p++;
1919 9fa3e853 bellard
    }
1920 9fa3e853 bellard
    /* if the page was really writable, then we change its
1921 9fa3e853 bellard
       protection back to writable */
1922 9fa3e853 bellard
    if (prot & PAGE_WRITE_ORG) {
1923 9fa3e853 bellard
        pindex = (address - host_start) >> TARGET_PAGE_BITS;
1924 9fa3e853 bellard
        if (!(p1[pindex].flags & PAGE_WRITE)) {
1925 5fafdf24 ths
            mprotect((void *)g2h(host_start), qemu_host_page_size,
1926 9fa3e853 bellard
                     (prot & PAGE_BITS) | PAGE_WRITE);
1927 9fa3e853 bellard
            p1[pindex].flags |= PAGE_WRITE;
1928 9fa3e853 bellard
            /* and since the content will be modified, we must invalidate
1929 9fa3e853 bellard
               the corresponding translated code. */
1930 d720b93d bellard
            tb_invalidate_phys_page(address, pc, puc);
1931 9fa3e853 bellard
#ifdef DEBUG_TB_CHECK
1932 9fa3e853 bellard
            tb_invalidate_check(address);
1933 9fa3e853 bellard
#endif
1934 9fa3e853 bellard
            return 1;
1935 9fa3e853 bellard
        }
1936 9fa3e853 bellard
    }
1937 9fa3e853 bellard
    return 0;
1938 9fa3e853 bellard
}
1939 9fa3e853 bellard
1940 9fa3e853 bellard
/* call this function when system calls directly modify a memory area */
1941 53a5960a pbrook
/* ??? This should be redundant now we have lock_user.  */
1942 53a5960a pbrook
void page_unprotect_range(target_ulong data, target_ulong data_size)
1943 9fa3e853 bellard
{
1944 53a5960a pbrook
    target_ulong start, end, addr;
1945 9fa3e853 bellard
1946 53a5960a pbrook
    start = data;
1947 9fa3e853 bellard
    end = start + data_size;
1948 9fa3e853 bellard
    start &= TARGET_PAGE_MASK;
1949 9fa3e853 bellard
    end = TARGET_PAGE_ALIGN(end);
1950 9fa3e853 bellard
    for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
1951 d720b93d bellard
        page_unprotect(addr, 0, NULL);
1952 9fa3e853 bellard
    }
1953 9fa3e853 bellard
}
1954 9fa3e853 bellard
1955 6a00d601 bellard
static inline void tlb_set_dirty(CPUState *env,
1956 6a00d601 bellard
                                 unsigned long addr, target_ulong vaddr)
1957 1ccde1cb bellard
{
1958 1ccde1cb bellard
}
1959 9fa3e853 bellard
#endif /* defined(CONFIG_USER_ONLY) */
1960 9fa3e853 bellard
1961 db7b5426 blueswir1
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1962 db7b5426 blueswir1
                             int memory);
1963 db7b5426 blueswir1
static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
1964 db7b5426 blueswir1
                           int orig_memory);
1965 db7b5426 blueswir1
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
1966 db7b5426 blueswir1
                      need_subpage)                                     \
1967 db7b5426 blueswir1
    do {                                                                \
1968 db7b5426 blueswir1
        if (addr > start_addr)                                          \
1969 db7b5426 blueswir1
            start_addr2 = 0;                                            \
1970 db7b5426 blueswir1
        else {                                                          \
1971 db7b5426 blueswir1
            start_addr2 = start_addr & ~TARGET_PAGE_MASK;               \
1972 db7b5426 blueswir1
            if (start_addr2 > 0)                                        \
1973 db7b5426 blueswir1
                need_subpage = 1;                                       \
1974 db7b5426 blueswir1
        }                                                               \
1975 db7b5426 blueswir1
                                                                        \
1976 49e9fba2 blueswir1
        if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE)        \
1977 db7b5426 blueswir1
            end_addr2 = TARGET_PAGE_SIZE - 1;                           \
1978 db7b5426 blueswir1
        else {                                                          \
1979 db7b5426 blueswir1
            end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
1980 db7b5426 blueswir1
            if (end_addr2 < TARGET_PAGE_SIZE - 1)                       \
1981 db7b5426 blueswir1
                need_subpage = 1;                                       \
1982 db7b5426 blueswir1
        }                                                               \
1983 db7b5426 blueswir1
    } while (0)
1984 db7b5426 blueswir1
1985 33417e70 bellard
/* register physical memory. 'size' must be a multiple of the target
1986 33417e70 bellard
   page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
1987 33417e70 bellard
   io memory page */
1988 5fafdf24 ths
void cpu_register_physical_memory(target_phys_addr_t start_addr,
1989 2e12669a bellard
                                  unsigned long size,
1990 2e12669a bellard
                                  unsigned long phys_offset)
1991 33417e70 bellard
{
1992 108c49b8 bellard
    target_phys_addr_t addr, end_addr;
1993 92e873b9 bellard
    PhysPageDesc *p;
1994 9d42037b bellard
    CPUState *env;
1995 db7b5426 blueswir1
    unsigned long orig_size = size;
1996 db7b5426 blueswir1
    void *subpage;
1997 33417e70 bellard
1998 5fd386f6 bellard
    size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
1999 49e9fba2 blueswir1
    end_addr = start_addr + (target_phys_addr_t)size;
2000 49e9fba2 blueswir1
    for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2001 db7b5426 blueswir1
        p = phys_page_find(addr >> TARGET_PAGE_BITS);
2002 db7b5426 blueswir1
        if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
2003 db7b5426 blueswir1
            unsigned long orig_memory = p->phys_offset;
2004 db7b5426 blueswir1
            target_phys_addr_t start_addr2, end_addr2;
2005 db7b5426 blueswir1
            int need_subpage = 0;
2006 db7b5426 blueswir1
2007 db7b5426 blueswir1
            CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2008 db7b5426 blueswir1
                          need_subpage);
2009 db7b5426 blueswir1
            if (need_subpage) {
2010 db7b5426 blueswir1
                if (!(orig_memory & IO_MEM_SUBPAGE)) {
2011 db7b5426 blueswir1
                    subpage = subpage_init((addr & TARGET_PAGE_MASK),
2012 db7b5426 blueswir1
                                           &p->phys_offset, orig_memory);
2013 db7b5426 blueswir1
                } else {
2014 db7b5426 blueswir1
                    subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2015 db7b5426 blueswir1
                                            >> IO_MEM_SHIFT];
2016 db7b5426 blueswir1
                }
2017 db7b5426 blueswir1
                subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2018 db7b5426 blueswir1
            } else {
2019 db7b5426 blueswir1
                p->phys_offset = phys_offset;
2020 db7b5426 blueswir1
                if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2021 db7b5426 blueswir1
                    (phys_offset & IO_MEM_ROMD))
2022 db7b5426 blueswir1
                    phys_offset += TARGET_PAGE_SIZE;
2023 db7b5426 blueswir1
            }
2024 db7b5426 blueswir1
        } else {
2025 db7b5426 blueswir1
            p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2026 db7b5426 blueswir1
            p->phys_offset = phys_offset;
2027 db7b5426 blueswir1
            if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2028 db7b5426 blueswir1
                (phys_offset & IO_MEM_ROMD))
2029 db7b5426 blueswir1
                phys_offset += TARGET_PAGE_SIZE;
2030 db7b5426 blueswir1
            else {
2031 db7b5426 blueswir1
                target_phys_addr_t start_addr2, end_addr2;
2032 db7b5426 blueswir1
                int need_subpage = 0;
2033 db7b5426 blueswir1
2034 db7b5426 blueswir1
                CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2035 db7b5426 blueswir1
                              end_addr2, need_subpage);
2036 db7b5426 blueswir1
2037 db7b5426 blueswir1
                if (need_subpage) {
2038 db7b5426 blueswir1
                    subpage = subpage_init((addr & TARGET_PAGE_MASK),
2039 db7b5426 blueswir1
                                           &p->phys_offset, IO_MEM_UNASSIGNED);
2040 db7b5426 blueswir1
                    subpage_register(subpage, start_addr2, end_addr2,
2041 db7b5426 blueswir1
                                     phys_offset);
2042 db7b5426 blueswir1
                }
2043 db7b5426 blueswir1
            }
2044 db7b5426 blueswir1
        }
2045 33417e70 bellard
    }
2046 3b46e624 ths
2047 9d42037b bellard
    /* since each CPU stores ram addresses in its TLB cache, we must
2048 9d42037b bellard
       reset the modified entries */
2049 9d42037b bellard
    /* XXX: slow ! */
2050 9d42037b bellard
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
2051 9d42037b bellard
        tlb_flush(env, 1);
2052 9d42037b bellard
    }
2053 33417e70 bellard
}
2054 33417e70 bellard
2055 ba863458 bellard
/* XXX: temporary until new memory mapping API */
2056 ba863458 bellard
uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2057 ba863458 bellard
{
2058 ba863458 bellard
    PhysPageDesc *p;
2059 ba863458 bellard
2060 ba863458 bellard
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
2061 ba863458 bellard
    if (!p)
2062 ba863458 bellard
        return IO_MEM_UNASSIGNED;
2063 ba863458 bellard
    return p->phys_offset;
2064 ba863458 bellard
}
2065 ba863458 bellard
2066 e9a1ab19 bellard
/* XXX: better than nothing */
2067 e9a1ab19 bellard
ram_addr_t qemu_ram_alloc(unsigned int size)
2068 e9a1ab19 bellard
{
2069 e9a1ab19 bellard
    ram_addr_t addr;
2070 e9a1ab19 bellard
    if ((phys_ram_alloc_offset + size) >= phys_ram_size) {
2071 5fafdf24 ths
        fprintf(stderr, "Not enough memory (requested_size = %u, max memory = %d)\n",
2072 e9a1ab19 bellard
                size, phys_ram_size);
2073 e9a1ab19 bellard
        abort();
2074 e9a1ab19 bellard
    }
2075 e9a1ab19 bellard
    addr = phys_ram_alloc_offset;
2076 e9a1ab19 bellard
    phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2077 e9a1ab19 bellard
    return addr;
2078 e9a1ab19 bellard
}
2079 e9a1ab19 bellard
2080 e9a1ab19 bellard
void qemu_ram_free(ram_addr_t addr)
2081 e9a1ab19 bellard
{
2082 e9a1ab19 bellard
}
2083 e9a1ab19 bellard
2084 a4193c8a bellard
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2085 33417e70 bellard
{
2086 67d3b957 pbrook
#ifdef DEBUG_UNASSIGNED
2087 ab3d1727 blueswir1
    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2088 67d3b957 pbrook
#endif
2089 b4f0a316 blueswir1
#ifdef TARGET_SPARC
2090 6c36d3fa blueswir1
    do_unassigned_access(addr, 0, 0, 0);
2091 f1ccf904 ths
#elif TARGET_CRIS
2092 f1ccf904 ths
    do_unassigned_access(addr, 0, 0, 0);
2093 b4f0a316 blueswir1
#endif
2094 33417e70 bellard
    return 0;
2095 33417e70 bellard
}
2096 33417e70 bellard
2097 a4193c8a bellard
static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2098 33417e70 bellard
{
2099 67d3b957 pbrook
#ifdef DEBUG_UNASSIGNED
2100 ab3d1727 blueswir1
    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2101 67d3b957 pbrook
#endif
2102 b4f0a316 blueswir1
#ifdef TARGET_SPARC
2103 6c36d3fa blueswir1
    do_unassigned_access(addr, 1, 0, 0);
2104 f1ccf904 ths
#elif TARGET_CRIS
2105 f1ccf904 ths
    do_unassigned_access(addr, 1, 0, 0);
2106 b4f0a316 blueswir1
#endif
2107 33417e70 bellard
}
2108 33417e70 bellard
2109 33417e70 bellard
static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2110 33417e70 bellard
    unassigned_mem_readb,
2111 33417e70 bellard
    unassigned_mem_readb,
2112 33417e70 bellard
    unassigned_mem_readb,
2113 33417e70 bellard
};
2114 33417e70 bellard
2115 33417e70 bellard
static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2116 33417e70 bellard
    unassigned_mem_writeb,
2117 33417e70 bellard
    unassigned_mem_writeb,
2118 33417e70 bellard
    unassigned_mem_writeb,
2119 33417e70 bellard
};
2120 33417e70 bellard
2121 3a7d929e bellard
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2122 9fa3e853 bellard
{
2123 3a7d929e bellard
    unsigned long ram_addr;
2124 3a7d929e bellard
    int dirty_flags;
2125 3a7d929e bellard
    ram_addr = addr - (unsigned long)phys_ram_base;
2126 3a7d929e bellard
    dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2127 3a7d929e bellard
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2128 9fa3e853 bellard
#if !defined(CONFIG_USER_ONLY)
2129 3a7d929e bellard
        tb_invalidate_phys_page_fast(ram_addr, 1);
2130 3a7d929e bellard
        dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2131 9fa3e853 bellard
#endif
2132 3a7d929e bellard
    }
2133 c27004ec bellard
    stb_p((uint8_t *)(long)addr, val);
2134 f32fc648 bellard
#ifdef USE_KQEMU
2135 f32fc648 bellard
    if (cpu_single_env->kqemu_enabled &&
2136 f32fc648 bellard
        (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2137 f32fc648 bellard
        kqemu_modify_page(cpu_single_env, ram_addr);
2138 f32fc648 bellard
#endif
2139 f23db169 bellard
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2140 f23db169 bellard
    phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2141 f23db169 bellard
    /* we remove the notdirty callback only if the code has been
2142 f23db169 bellard
       flushed */
2143 f23db169 bellard
    if (dirty_flags == 0xff)
2144 6a00d601 bellard
        tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
2145 9fa3e853 bellard
}
2146 9fa3e853 bellard
2147 3a7d929e bellard
static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2148 9fa3e853 bellard
{
2149 3a7d929e bellard
    unsigned long ram_addr;
2150 3a7d929e bellard
    int dirty_flags;
2151 3a7d929e bellard
    ram_addr = addr - (unsigned long)phys_ram_base;
2152 3a7d929e bellard
    dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2153 3a7d929e bellard
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2154 9fa3e853 bellard
#if !defined(CONFIG_USER_ONLY)
2155 3a7d929e bellard
        tb_invalidate_phys_page_fast(ram_addr, 2);
2156 3a7d929e bellard
        dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2157 9fa3e853 bellard
#endif
2158 3a7d929e bellard
    }
2159 c27004ec bellard
    stw_p((uint8_t *)(long)addr, val);
2160 f32fc648 bellard
#ifdef USE_KQEMU
2161 f32fc648 bellard
    if (cpu_single_env->kqemu_enabled &&
2162 f32fc648 bellard
        (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2163 f32fc648 bellard
        kqemu_modify_page(cpu_single_env, ram_addr);
2164 f32fc648 bellard
#endif
2165 f23db169 bellard
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2166 f23db169 bellard
    phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2167 f23db169 bellard
    /* we remove the notdirty callback only if the code has been
2168 f23db169 bellard
       flushed */
2169 f23db169 bellard
    if (dirty_flags == 0xff)
2170 6a00d601 bellard
        tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
2171 9fa3e853 bellard
}
2172 9fa3e853 bellard
2173 3a7d929e bellard
static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2174 9fa3e853 bellard
{
2175 3a7d929e bellard
    unsigned long ram_addr;
2176 3a7d929e bellard
    int dirty_flags;
2177 3a7d929e bellard
    ram_addr = addr - (unsigned long)phys_ram_base;
2178 3a7d929e bellard
    dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2179 3a7d929e bellard
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2180 9fa3e853 bellard
#if !defined(CONFIG_USER_ONLY)
2181 3a7d929e bellard
        tb_invalidate_phys_page_fast(ram_addr, 4);
2182 3a7d929e bellard
        dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2183 9fa3e853 bellard
#endif
2184 3a7d929e bellard
    }
2185 c27004ec bellard
    stl_p((uint8_t *)(long)addr, val);
2186 f32fc648 bellard
#ifdef USE_KQEMU
2187 f32fc648 bellard
    if (cpu_single_env->kqemu_enabled &&
2188 f32fc648 bellard
        (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2189 f32fc648 bellard
        kqemu_modify_page(cpu_single_env, ram_addr);
2190 f32fc648 bellard
#endif
2191 f23db169 bellard
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2192 f23db169 bellard
    phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2193 f23db169 bellard
    /* we remove the notdirty callback only if the code has been
2194 f23db169 bellard
       flushed */
2195 f23db169 bellard
    if (dirty_flags == 0xff)
2196 6a00d601 bellard
        tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
2197 9fa3e853 bellard
}
2198 9fa3e853 bellard
2199 3a7d929e bellard
static CPUReadMemoryFunc *error_mem_read[3] = {
2200 9fa3e853 bellard
    NULL, /* never used */
2201 9fa3e853 bellard
    NULL, /* never used */
2202 9fa3e853 bellard
    NULL, /* never used */
2203 9fa3e853 bellard
};
2204 9fa3e853 bellard
2205 1ccde1cb bellard
static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2206 1ccde1cb bellard
    notdirty_mem_writeb,
2207 1ccde1cb bellard
    notdirty_mem_writew,
2208 1ccde1cb bellard
    notdirty_mem_writel,
2209 1ccde1cb bellard
};
2210 1ccde1cb bellard
2211 6658ffb8 pbrook
#if defined(CONFIG_SOFTMMU)
2212 6658ffb8 pbrook
/* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,
2213 6658ffb8 pbrook
   so these check for a hit then pass through to the normal out-of-line
2214 6658ffb8 pbrook
   phys routines.  */
2215 6658ffb8 pbrook
static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2216 6658ffb8 pbrook
{
2217 6658ffb8 pbrook
    return ldub_phys(addr);
2218 6658ffb8 pbrook
}
2219 6658ffb8 pbrook
2220 6658ffb8 pbrook
static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2221 6658ffb8 pbrook
{
2222 6658ffb8 pbrook
    return lduw_phys(addr);
2223 6658ffb8 pbrook
}
2224 6658ffb8 pbrook
2225 6658ffb8 pbrook
static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2226 6658ffb8 pbrook
{
2227 6658ffb8 pbrook
    return ldl_phys(addr);
2228 6658ffb8 pbrook
}
2229 6658ffb8 pbrook
2230 6658ffb8 pbrook
/* Generate a debug exception if a watchpoint has been hit.
2231 6658ffb8 pbrook
   Returns the real physical address of the access.  addr will be a host
2232 d79acba4 balrog
   address in case of a RAM location.  */
2233 6658ffb8 pbrook
static target_ulong check_watchpoint(target_phys_addr_t addr)
2234 6658ffb8 pbrook
{
2235 6658ffb8 pbrook
    CPUState *env = cpu_single_env;
2236 6658ffb8 pbrook
    target_ulong watch;
2237 6658ffb8 pbrook
    target_ulong retaddr;
2238 6658ffb8 pbrook
    int i;
2239 6658ffb8 pbrook
2240 6658ffb8 pbrook
    retaddr = addr;
2241 6658ffb8 pbrook
    for (i = 0; i < env->nb_watchpoints; i++) {
2242 6658ffb8 pbrook
        watch = env->watchpoint[i].vaddr;
2243 6658ffb8 pbrook
        if (((env->mem_write_vaddr ^ watch) & TARGET_PAGE_MASK) == 0) {
2244 d79acba4 balrog
            retaddr = addr - env->watchpoint[i].addend;
2245 6658ffb8 pbrook
            if (((addr ^ watch) & ~TARGET_PAGE_MASK) == 0) {
2246 6658ffb8 pbrook
                cpu_single_env->watchpoint_hit = i + 1;
2247 6658ffb8 pbrook
                cpu_interrupt(cpu_single_env, CPU_INTERRUPT_DEBUG);
2248 6658ffb8 pbrook
                break;
2249 6658ffb8 pbrook
            }
2250 6658ffb8 pbrook
        }
2251 6658ffb8 pbrook
    }
2252 6658ffb8 pbrook
    return retaddr;
2253 6658ffb8 pbrook
}
2254 6658ffb8 pbrook
2255 6658ffb8 pbrook
static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2256 6658ffb8 pbrook
                             uint32_t val)
2257 6658ffb8 pbrook
{
2258 6658ffb8 pbrook
    addr = check_watchpoint(addr);
2259 6658ffb8 pbrook
    stb_phys(addr, val);
2260 6658ffb8 pbrook
}
2261 6658ffb8 pbrook
2262 6658ffb8 pbrook
static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2263 6658ffb8 pbrook
                             uint32_t val)
2264 6658ffb8 pbrook
{
2265 6658ffb8 pbrook
    addr = check_watchpoint(addr);
2266 6658ffb8 pbrook
    stw_phys(addr, val);
2267 6658ffb8 pbrook
}
2268 6658ffb8 pbrook
2269 6658ffb8 pbrook
static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2270 6658ffb8 pbrook
                             uint32_t val)
2271 6658ffb8 pbrook
{
2272 6658ffb8 pbrook
    addr = check_watchpoint(addr);
2273 6658ffb8 pbrook
    stl_phys(addr, val);
2274 6658ffb8 pbrook
}
2275 6658ffb8 pbrook
2276 6658ffb8 pbrook
static CPUReadMemoryFunc *watch_mem_read[3] = {
2277 6658ffb8 pbrook
    watch_mem_readb,
2278 6658ffb8 pbrook
    watch_mem_readw,
2279 6658ffb8 pbrook
    watch_mem_readl,
2280 6658ffb8 pbrook
};
2281 6658ffb8 pbrook
2282 6658ffb8 pbrook
static CPUWriteMemoryFunc *watch_mem_write[3] = {
2283 6658ffb8 pbrook
    watch_mem_writeb,
2284 6658ffb8 pbrook
    watch_mem_writew,
2285 6658ffb8 pbrook
    watch_mem_writel,
2286 6658ffb8 pbrook
};
2287 6658ffb8 pbrook
#endif
2288 6658ffb8 pbrook
2289 db7b5426 blueswir1
static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2290 db7b5426 blueswir1
                                 unsigned int len)
2291 db7b5426 blueswir1
{
2292 db7b5426 blueswir1
    CPUReadMemoryFunc **mem_read;
2293 db7b5426 blueswir1
    uint32_t ret;
2294 db7b5426 blueswir1
    unsigned int idx;
2295 db7b5426 blueswir1
2296 db7b5426 blueswir1
    idx = SUBPAGE_IDX(addr - mmio->base);
2297 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2298 db7b5426 blueswir1
    printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2299 db7b5426 blueswir1
           mmio, len, addr, idx);
2300 db7b5426 blueswir1
#endif
2301 db7b5426 blueswir1
    mem_read = mmio->mem_read[idx];
2302 db7b5426 blueswir1
    ret = (*mem_read[len])(mmio->opaque[idx], addr);
2303 db7b5426 blueswir1
2304 db7b5426 blueswir1
    return ret;
2305 db7b5426 blueswir1
}
2306 db7b5426 blueswir1
2307 db7b5426 blueswir1
static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2308 db7b5426 blueswir1
                              uint32_t value, unsigned int len)
2309 db7b5426 blueswir1
{
2310 db7b5426 blueswir1
    CPUWriteMemoryFunc **mem_write;
2311 db7b5426 blueswir1
    unsigned int idx;
2312 db7b5426 blueswir1
2313 db7b5426 blueswir1
    idx = SUBPAGE_IDX(addr - mmio->base);
2314 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2315 db7b5426 blueswir1
    printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2316 db7b5426 blueswir1
           mmio, len, addr, idx, value);
2317 db7b5426 blueswir1
#endif
2318 db7b5426 blueswir1
    mem_write = mmio->mem_write[idx];
2319 db7b5426 blueswir1
    (*mem_write[len])(mmio->opaque[idx], addr, value);
2320 db7b5426 blueswir1
}
2321 db7b5426 blueswir1
2322 db7b5426 blueswir1
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2323 db7b5426 blueswir1
{
2324 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2325 db7b5426 blueswir1
    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2326 db7b5426 blueswir1
#endif
2327 db7b5426 blueswir1
2328 db7b5426 blueswir1
    return subpage_readlen(opaque, addr, 0);
2329 db7b5426 blueswir1
}
2330 db7b5426 blueswir1
2331 db7b5426 blueswir1
static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2332 db7b5426 blueswir1
                            uint32_t value)
2333 db7b5426 blueswir1
{
2334 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2335 db7b5426 blueswir1
    printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2336 db7b5426 blueswir1
#endif
2337 db7b5426 blueswir1
    subpage_writelen(opaque, addr, value, 0);
2338 db7b5426 blueswir1
}
2339 db7b5426 blueswir1
2340 db7b5426 blueswir1
static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2341 db7b5426 blueswir1
{
2342 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2343 db7b5426 blueswir1
    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2344 db7b5426 blueswir1
#endif
2345 db7b5426 blueswir1
2346 db7b5426 blueswir1
    return subpage_readlen(opaque, addr, 1);
2347 db7b5426 blueswir1
}
2348 db7b5426 blueswir1
2349 db7b5426 blueswir1
static void subpage_writew (void *opaque, target_phys_addr_t addr,
2350 db7b5426 blueswir1
                            uint32_t value)
2351 db7b5426 blueswir1
{
2352 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2353 db7b5426 blueswir1
    printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2354 db7b5426 blueswir1
#endif
2355 db7b5426 blueswir1
    subpage_writelen(opaque, addr, value, 1);
2356 db7b5426 blueswir1
}
2357 db7b5426 blueswir1
2358 db7b5426 blueswir1
static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2359 db7b5426 blueswir1
{
2360 db7b5426 blueswir1
#if defined(DEBUG_SUBPAGE)
2361 db7b5426 blueswir1
    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2362 db7b5426 blueswir1
#endif
2363 db7b5426 blueswir1
2364 db7b5426 blueswir1
    return subpage_readlen(opaque, addr, 2);
2365 db7b5426 blueswir1
}
2366 db7b5426 blueswir1
2367 db7b5426 blueswir1
static void subpage_writel (void *opaque,
2368 db7b5426 blueswir1
                         target_phys_addr_t addr, uint32_t value)
2369 db7b5426 blueswir1
{
2370