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1
/*
2
 *  i386 emulator main execution loop
3
 *
4
 *  Copyright (c) 2003-2005 Fabrice Bellard
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include "config.h"
21
#include "exec.h"
22
#include "disas.h"
23

    
24
#if !defined(CONFIG_SOFTMMU)
25
#undef EAX
26
#undef ECX
27
#undef EDX
28
#undef EBX
29
#undef ESP
30
#undef EBP
31
#undef ESI
32
#undef EDI
33
#undef EIP
34
#include <signal.h>
35
#include <sys/ucontext.h>
36
#endif
37

    
38
int tb_invalidated_flag;
39

    
40
//#define DEBUG_EXEC
41
//#define DEBUG_SIGNAL
42

    
43
void cpu_loop_exit(void)
44
{
45
    /* NOTE: the register at this point must be saved by hand because
46
       longjmp restore them */
47
    regs_to_env();
48
    longjmp(env->jmp_env, 1);
49
}
50

    
51
#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52
#define reg_T2
53
#endif
54

    
55
/* exit the current TB from a signal handler. The host registers are
56
   restored in a state compatible with the CPU emulator
57
 */
58
void cpu_resume_from_signal(CPUState *env1, void *puc)
59
{
60
#if !defined(CONFIG_SOFTMMU)
61
    struct ucontext *uc = puc;
62
#endif
63

    
64
    env = env1;
65

    
66
    /* XXX: restore cpu registers saved in host registers */
67

    
68
#if !defined(CONFIG_SOFTMMU)
69
    if (puc) {
70
        /* XXX: use siglongjmp ? */
71
        sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72
    }
73
#endif
74
    longjmp(env->jmp_env, 1);
75
}
76

    
77

    
78
static TranslationBlock *tb_find_slow(target_ulong pc,
79
                                      target_ulong cs_base,
80
                                      uint64_t flags)
81
{
82
    TranslationBlock *tb, **ptb1;
83
    int code_gen_size;
84
    unsigned int h;
85
    target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86
    uint8_t *tc_ptr;
87

    
88
    spin_lock(&tb_lock);
89

    
90
    tb_invalidated_flag = 0;
91

    
92
    regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93

    
94
    /* find translated block using physical mappings */
95
    phys_pc = get_phys_addr_code(env, pc);
96
    phys_page1 = phys_pc & TARGET_PAGE_MASK;
97
    phys_page2 = -1;
98
    h = tb_phys_hash_func(phys_pc);
99
    ptb1 = &tb_phys_hash[h];
100
    for(;;) {
101
        tb = *ptb1;
102
        if (!tb)
103
            goto not_found;
104
        if (tb->pc == pc &&
105
            tb->page_addr[0] == phys_page1 &&
106
            tb->cs_base == cs_base &&
107
            tb->flags == flags) {
108
            /* check next page if needed */
109
            if (tb->page_addr[1] != -1) {
110
                virt_page2 = (pc & TARGET_PAGE_MASK) +
111
                    TARGET_PAGE_SIZE;
112
                phys_page2 = get_phys_addr_code(env, virt_page2);
113
                if (tb->page_addr[1] == phys_page2)
114
                    goto found;
115
            } else {
116
                goto found;
117
            }
118
        }
119
        ptb1 = &tb->phys_hash_next;
120
    }
121
 not_found:
122
    /* if no translated code available, then translate it now */
123
    tb = tb_alloc(pc);
124
    if (!tb) {
125
        /* flush must be done */
126
        tb_flush(env);
127
        /* cannot fail at this point */
128
        tb = tb_alloc(pc);
129
        /* don't forget to invalidate previous TB info */
130
        tb_invalidated_flag = 1;
131
    }
132
    tc_ptr = code_gen_ptr;
133
    tb->tc_ptr = tc_ptr;
134
    tb->cs_base = cs_base;
135
    tb->flags = flags;
136
    cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137
    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138

    
139
    /* check next page if needed */
140
    virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141
    phys_page2 = -1;
142
    if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143
        phys_page2 = get_phys_addr_code(env, virt_page2);
144
    }
145
    tb_link_phys(tb, phys_pc, phys_page2);
146

    
147
 found:
148
    /* we add the TB in the virtual pc hash table */
149
    env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150
    spin_unlock(&tb_lock);
151
    return tb;
152
}
153

    
154
static inline TranslationBlock *tb_find_fast(void)
155
{
156
    TranslationBlock *tb;
157
    target_ulong cs_base, pc;
158
    uint64_t flags;
159

    
160
    /* we record a subset of the CPU state. It will
161
       always be the same before a given translated block
162
       is executed. */
163
#if defined(TARGET_I386)
164
    flags = env->hflags;
165
    flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166
    flags |= env->intercept;
167
    cs_base = env->segs[R_CS].base;
168
    pc = cs_base + env->eip;
169
#elif defined(TARGET_ARM)
170
    flags = env->thumb | (env->vfp.vec_len << 1)
171
            | (env->vfp.vec_stride << 4);
172
    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173
        flags |= (1 << 6);
174
    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175
        flags |= (1 << 7);
176
    cs_base = 0;
177
    pc = env->regs[15];
178
#elif defined(TARGET_SPARC)
179
#ifdef TARGET_SPARC64
180
    // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181
    flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182
        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183
#else
184
    // FPU enable . Supervisor
185
    flags = (env->psref << 4) | env->psrs;
186
#endif
187
    cs_base = env->npc;
188
    pc = env->pc;
189
#elif defined(TARGET_PPC)
190
    flags = env->hflags;
191
    cs_base = 0;
192
    pc = env->nip;
193
#elif defined(TARGET_MIPS)
194
    flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
195
    cs_base = 0;
196
    pc = env->PC[env->current_tc];
197
#elif defined(TARGET_M68K)
198
    flags = (env->fpcr & M68K_FPCR_PREC)  /* Bit  6 */
199
            | (env->sr & SR_S)            /* Bit  13 */
200
            | ((env->macsr >> 4) & 0xf);  /* Bits 0-3 */
201
    cs_base = 0;
202
    pc = env->pc;
203
#elif defined(TARGET_SH4)
204
    flags = env->sr & (SR_MD | SR_RB);
205
    cs_base = 0;         /* XXXXX */
206
    pc = env->pc;
207
#elif defined(TARGET_ALPHA)
208
    flags = env->ps;
209
    cs_base = 0;
210
    pc = env->pc;
211
#elif defined(TARGET_CRIS)
212
    flags = 0;
213
    cs_base = 0;
214
    pc = env->pc;
215
#else
216
#error unsupported CPU
217
#endif
218
    tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
219
    if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
220
                         tb->flags != flags, 0)) {
221
        tb = tb_find_slow(pc, cs_base, flags);
222
        /* Note: we do it here to avoid a gcc bug on Mac OS X when
223
           doing it in tb_find_slow */
224
        if (tb_invalidated_flag) {
225
            /* as some TB could have been invalidated because
226
               of memory exceptions while generating the code, we
227
               must recompute the hash index here */
228
            T0 = 0;
229
        }
230
    }
231
    return tb;
232
}
233

    
234

    
235
/* main execution loop */
236

    
237
int cpu_exec(CPUState *env1)
238
{
239
#define DECLARE_HOST_REGS 1
240
#include "hostregs_helper.h"
241
#if defined(TARGET_SPARC)
242
#if defined(reg_REGWPTR)
243
    uint32_t *saved_regwptr;
244
#endif
245
#endif
246
#if defined(__sparc__) && !defined(HOST_SOLARIS)
247
    int saved_i7;
248
    target_ulong tmp_T0;
249
#endif
250
    int ret, interrupt_request;
251
    void (*gen_func)(void);
252
    TranslationBlock *tb;
253
    uint8_t *tc_ptr;
254

    
255
    if (cpu_halted(env1) == EXCP_HALTED)
256
        return EXCP_HALTED;
257

    
258
    cpu_single_env = env1;
259

    
260
    /* first we save global registers */
261
#define SAVE_HOST_REGS 1
262
#include "hostregs_helper.h"
263
    env = env1;
264
#if defined(__sparc__) && !defined(HOST_SOLARIS)
265
    /* we also save i7 because longjmp may not restore it */
266
    asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
267
#endif
268

    
269
    env_to_regs();
270
#if defined(TARGET_I386)
271
    /* put eflags in CPU temporary format */
272
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
273
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
274
    CC_OP = CC_OP_EFLAGS;
275
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
276
#elif defined(TARGET_SPARC)
277
#if defined(reg_REGWPTR)
278
    saved_regwptr = REGWPTR;
279
#endif
280
#elif defined(TARGET_M68K)
281
    env->cc_op = CC_OP_FLAGS;
282
    env->cc_dest = env->sr & 0xf;
283
    env->cc_x = (env->sr >> 4) & 1;
284
#elif defined(TARGET_ALPHA)
285
#elif defined(TARGET_ARM)
286
#elif defined(TARGET_PPC)
287
#elif defined(TARGET_MIPS)
288
#elif defined(TARGET_SH4)
289
#elif defined(TARGET_CRIS)
290
    /* XXXXX */
291
#else
292
#error unsupported target CPU
293
#endif
294
    env->exception_index = -1;
295

    
296
    /* prepare setjmp context for exception handling */
297
    for(;;) {
298
        if (setjmp(env->jmp_env) == 0) {
299
            env->current_tb = NULL;
300
            /* if an exception is pending, we execute it here */
301
            if (env->exception_index >= 0) {
302
                if (env->exception_index >= EXCP_INTERRUPT) {
303
                    /* exit request from the cpu execution loop */
304
                    ret = env->exception_index;
305
                    break;
306
                } else if (env->user_mode_only) {
307
                    /* if user mode only, we simulate a fake exception
308
                       which will be handled outside the cpu execution
309
                       loop */
310
#if defined(TARGET_I386)
311
                    do_interrupt_user(env->exception_index,
312
                                      env->exception_is_int,
313
                                      env->error_code,
314
                                      env->exception_next_eip);
315
#endif
316
                    ret = env->exception_index;
317
                    break;
318
                } else {
319
#if defined(TARGET_I386)
320
                    /* simulate a real cpu exception. On i386, it can
321
                       trigger new exceptions, but we do not handle
322
                       double or triple faults yet. */
323
                    do_interrupt(env->exception_index,
324
                                 env->exception_is_int,
325
                                 env->error_code,
326
                                 env->exception_next_eip, 0);
327
                    /* successfully delivered */
328
                    env->old_exception = -1;
329
#elif defined(TARGET_PPC)
330
                    do_interrupt(env);
331
#elif defined(TARGET_MIPS)
332
                    do_interrupt(env);
333
#elif defined(TARGET_SPARC)
334
                    do_interrupt(env->exception_index);
335
#elif defined(TARGET_ARM)
336
                    do_interrupt(env);
337
#elif defined(TARGET_SH4)
338
                    do_interrupt(env);
339
#elif defined(TARGET_ALPHA)
340
                    do_interrupt(env);
341
#elif defined(TARGET_CRIS)
342
                    do_interrupt(env);
343
#elif defined(TARGET_M68K)
344
                    do_interrupt(0);
345
#endif
346
                }
347
                env->exception_index = -1;
348
            }
349
#ifdef USE_KQEMU
350
            if (kqemu_is_ok(env) && env->interrupt_request == 0) {
351
                int ret;
352
                env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
353
                ret = kqemu_cpu_exec(env);
354
                /* put eflags in CPU temporary format */
355
                CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
356
                DF = 1 - (2 * ((env->eflags >> 10) & 1));
357
                CC_OP = CC_OP_EFLAGS;
358
                env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
359
                if (ret == 1) {
360
                    /* exception */
361
                    longjmp(env->jmp_env, 1);
362
                } else if (ret == 2) {
363
                    /* softmmu execution needed */
364
                } else {
365
                    if (env->interrupt_request != 0) {
366
                        /* hardware interrupt will be executed just after */
367
                    } else {
368
                        /* otherwise, we restart */
369
                        longjmp(env->jmp_env, 1);
370
                    }
371
                }
372
            }
373
#endif
374

    
375
            T0 = 0; /* force lookup of first TB */
376
            for(;;) {
377
#if defined(__sparc__) && !defined(HOST_SOLARIS)
378
                /* g1 can be modified by some libc? functions */
379
                tmp_T0 = T0;
380
#endif
381
                interrupt_request = env->interrupt_request;
382
                if (__builtin_expect(interrupt_request, 0)
383
#if defined(TARGET_I386)
384
                        && env->hflags & HF_GIF_MASK
385
#endif
386
                                ) {
387
                    if (interrupt_request & CPU_INTERRUPT_DEBUG) {
388
                        env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
389
                        env->exception_index = EXCP_DEBUG;
390
                        cpu_loop_exit();
391
                    }
392
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
393
    defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
394
                    if (interrupt_request & CPU_INTERRUPT_HALT) {
395
                        env->interrupt_request &= ~CPU_INTERRUPT_HALT;
396
                        env->halted = 1;
397
                        env->exception_index = EXCP_HLT;
398
                        cpu_loop_exit();
399
                    }
400
#endif
401
#if defined(TARGET_I386)
402
                    if ((interrupt_request & CPU_INTERRUPT_SMI) &&
403
                        !(env->hflags & HF_SMM_MASK)) {
404
                        svm_check_intercept(SVM_EXIT_SMI);
405
                        env->interrupt_request &= ~CPU_INTERRUPT_SMI;
406
                        do_smm_enter();
407
#if defined(__sparc__) && !defined(HOST_SOLARIS)
408
                        tmp_T0 = 0;
409
#else
410
                        T0 = 0;
411
#endif
412
                    } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
413
                        (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
414
                        !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
415
                        int intno;
416
                        svm_check_intercept(SVM_EXIT_INTR);
417
                        env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
418
                        intno = cpu_get_pic_interrupt(env);
419
                        if (loglevel & CPU_LOG_TB_IN_ASM) {
420
                            fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
421
                        }
422
                        do_interrupt(intno, 0, 0, 0, 1);
423
                        /* ensure that no TB jump will be modified as
424
                           the program flow was changed */
425
#if defined(__sparc__) && !defined(HOST_SOLARIS)
426
                        tmp_T0 = 0;
427
#else
428
                        T0 = 0;
429
#endif
430
#if !defined(CONFIG_USER_ONLY)
431
                    } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
432
                        (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
433
                         int intno;
434
                         /* FIXME: this should respect TPR */
435
                         env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
436
                         svm_check_intercept(SVM_EXIT_VINTR);
437
                         intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
438
                         if (loglevel & CPU_LOG_TB_IN_ASM)
439
                             fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
440
                         do_interrupt(intno, 0, 0, -1, 1);
441
                         stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
442
                                  ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
443
#if defined(__sparc__) && !defined(HOST_SOLARIS)
444
                         tmp_T0 = 0;
445
#else
446
                         T0 = 0;
447
#endif
448
#endif
449
                    }
450
#elif defined(TARGET_PPC)
451
#if 0
452
                    if ((interrupt_request & CPU_INTERRUPT_RESET)) {
453
                        cpu_ppc_reset(env);
454
                    }
455
#endif
456
                    if (interrupt_request & CPU_INTERRUPT_HARD) {
457
                        ppc_hw_interrupt(env);
458
                        if (env->pending_interrupts == 0)
459
                            env->interrupt_request &= ~CPU_INTERRUPT_HARD;
460
#if defined(__sparc__) && !defined(HOST_SOLARIS)
461
                        tmp_T0 = 0;
462
#else
463
                        T0 = 0;
464
#endif
465
                    }
466
#elif defined(TARGET_MIPS)
467
                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&
468
                        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
469
                        (env->CP0_Status & (1 << CP0St_IE)) &&
470
                        !(env->CP0_Status & (1 << CP0St_EXL)) &&
471
                        !(env->CP0_Status & (1 << CP0St_ERL)) &&
472
                        !(env->hflags & MIPS_HFLAG_DM)) {
473
                        /* Raise it */
474
                        env->exception_index = EXCP_EXT_INTERRUPT;
475
                        env->error_code = 0;
476
                        do_interrupt(env);
477
#if defined(__sparc__) && !defined(HOST_SOLARIS)
478
                        tmp_T0 = 0;
479
#else
480
                        T0 = 0;
481
#endif
482
                    }
483
#elif defined(TARGET_SPARC)
484
                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&
485
                        (env->psret != 0)) {
486
                        int pil = env->interrupt_index & 15;
487
                        int type = env->interrupt_index & 0xf0;
488

    
489
                        if (((type == TT_EXTINT) &&
490
                             (pil == 15 || pil > env->psrpil)) ||
491
                            type != TT_EXTINT) {
492
                            env->interrupt_request &= ~CPU_INTERRUPT_HARD;
493
                            do_interrupt(env->interrupt_index);
494
                            env->interrupt_index = 0;
495
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
496
                            cpu_check_irqs(env);
497
#endif
498
#if defined(__sparc__) && !defined(HOST_SOLARIS)
499
                            tmp_T0 = 0;
500
#else
501
                            T0 = 0;
502
#endif
503
                        }
504
                    } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
505
                        //do_interrupt(0, 0, 0, 0, 0);
506
                        env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
507
                    }
508
#elif defined(TARGET_ARM)
509
                    if (interrupt_request & CPU_INTERRUPT_FIQ
510
                        && !(env->uncached_cpsr & CPSR_F)) {
511
                        env->exception_index = EXCP_FIQ;
512
                        do_interrupt(env);
513
                    }
514
                    if (interrupt_request & CPU_INTERRUPT_HARD
515
                        && !(env->uncached_cpsr & CPSR_I)) {
516
                        env->exception_index = EXCP_IRQ;
517
                        do_interrupt(env);
518
                    }
519
#elif defined(TARGET_SH4)
520
                    /* XXXXX */
521
#elif defined(TARGET_ALPHA)
522
                    if (interrupt_request & CPU_INTERRUPT_HARD) {
523
                        do_interrupt(env);
524
                    }
525
#elif defined(TARGET_CRIS)
526
                    if (interrupt_request & CPU_INTERRUPT_HARD) {
527
                        do_interrupt(env);
528
                        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
529
                    }
530
#elif defined(TARGET_M68K)
531
                    if (interrupt_request & CPU_INTERRUPT_HARD
532
                        && ((env->sr & SR_I) >> SR_I_SHIFT)
533
                            < env->pending_level) {
534
                        /* Real hardware gets the interrupt vector via an
535
                           IACK cycle at this point.  Current emulated
536
                           hardware doesn't rely on this, so we
537
                           provide/save the vector when the interrupt is
538
                           first signalled.  */
539
                        env->exception_index = env->pending_vector;
540
                        do_interrupt(1);
541
                    }
542
#endif
543
                   /* Don't use the cached interupt_request value,
544
                      do_interrupt may have updated the EXITTB flag. */
545
                    if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
546
                        env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
547
                        /* ensure that no TB jump will be modified as
548
                           the program flow was changed */
549
#if defined(__sparc__) && !defined(HOST_SOLARIS)
550
                        tmp_T0 = 0;
551
#else
552
                        T0 = 0;
553
#endif
554
                    }
555
                    if (interrupt_request & CPU_INTERRUPT_EXIT) {
556
                        env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
557
                        env->exception_index = EXCP_INTERRUPT;
558
                        cpu_loop_exit();
559
                    }
560
                }
561
#ifdef DEBUG_EXEC
562
                if ((loglevel & CPU_LOG_TB_CPU)) {
563
                    /* restore flags in standard format */
564
                    regs_to_env();
565
#if defined(TARGET_I386)
566
                    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
567
                    cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
568
                    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
569
#elif defined(TARGET_ARM)
570
                    cpu_dump_state(env, logfile, fprintf, 0);
571
#elif defined(TARGET_SPARC)
572
                    REGWPTR = env->regbase + (env->cwp * 16);
573
                    env->regwptr = REGWPTR;
574
                    cpu_dump_state(env, logfile, fprintf, 0);
575
#elif defined(TARGET_PPC)
576
                    cpu_dump_state(env, logfile, fprintf, 0);
577
#elif defined(TARGET_M68K)
578
                    cpu_m68k_flush_flags(env, env->cc_op);
579
                    env->cc_op = CC_OP_FLAGS;
580
                    env->sr = (env->sr & 0xffe0)
581
                              | env->cc_dest | (env->cc_x << 4);
582
                    cpu_dump_state(env, logfile, fprintf, 0);
583
#elif defined(TARGET_MIPS)
584
                    cpu_dump_state(env, logfile, fprintf, 0);
585
#elif defined(TARGET_SH4)
586
                    cpu_dump_state(env, logfile, fprintf, 0);
587
#elif defined(TARGET_ALPHA)
588
                    cpu_dump_state(env, logfile, fprintf, 0);
589
#elif defined(TARGET_CRIS)
590
                    cpu_dump_state(env, logfile, fprintf, 0);
591
#else
592
#error unsupported target CPU
593
#endif
594
                }
595
#endif
596
                tb = tb_find_fast();
597
#ifdef DEBUG_EXEC
598
                if ((loglevel & CPU_LOG_EXEC)) {
599
                    fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
600
                            (long)tb->tc_ptr, tb->pc,
601
                            lookup_symbol(tb->pc));
602
                }
603
#endif
604
#if defined(__sparc__) && !defined(HOST_SOLARIS)
605
                T0 = tmp_T0;
606
#endif
607
                /* see if we can patch the calling TB. When the TB
608
                   spans two pages, we cannot safely do a direct
609
                   jump. */
610
                {
611
                    if (T0 != 0 &&
612
#if USE_KQEMU
613
                        (env->kqemu_enabled != 2) &&
614
#endif
615
                        tb->page_addr[1] == -1) {
616
                    spin_lock(&tb_lock);
617
                    tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
618
                    spin_unlock(&tb_lock);
619
                }
620
                }
621
                tc_ptr = tb->tc_ptr;
622
                env->current_tb = tb;
623
                /* execute the generated code */
624
                gen_func = (void *)tc_ptr;
625
#if defined(__sparc__)
626
                __asm__ __volatile__("call        %0\n\t"
627
                                     "mov        %%o7,%%i0"
628
                                     : /* no outputs */
629
                                     : "r" (gen_func)
630
                                     : "i0", "i1", "i2", "i3", "i4", "i5",
631
                                       "o0", "o1", "o2", "o3", "o4", "o5",
632
                                       "l0", "l1", "l2", "l3", "l4", "l5",
633
                                       "l6", "l7");
634
#elif defined(__arm__)
635
                asm volatile ("mov pc, %0\n\t"
636
                              ".global exec_loop\n\t"
637
                              "exec_loop:\n\t"
638
                              : /* no outputs */
639
                              : "r" (gen_func)
640
                              : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
641
#elif defined(__ia64)
642
                struct fptr {
643
                        void *ip;
644
                        void *gp;
645
                } fp;
646

    
647
                fp.ip = tc_ptr;
648
                fp.gp = code_gen_buffer + 2 * (1 << 20);
649
                (*(void (*)(void)) &fp)();
650
#else
651
                gen_func();
652
#endif
653
                env->current_tb = NULL;
654
                /* reset soft MMU for next block (it can currently
655
                   only be set by a memory fault) */
656
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
657
                if (env->hflags & HF_SOFTMMU_MASK) {
658
                    env->hflags &= ~HF_SOFTMMU_MASK;
659
                    /* do not allow linking to another block */
660
                    T0 = 0;
661
                }
662
#endif
663
#if defined(USE_KQEMU)
664
#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
665
                if (kqemu_is_ok(env) &&
666
                    (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
667
                    cpu_loop_exit();
668
                }
669
#endif
670
            } /* for(;;) */
671
        } else {
672
            env_to_regs();
673
        }
674
    } /* for(;;) */
675

    
676

    
677
#if defined(TARGET_I386)
678
    /* restore flags in standard format */
679
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
680
#elif defined(TARGET_ARM)
681
    /* XXX: Save/restore host fpu exception state?.  */
682
#elif defined(TARGET_SPARC)
683
#if defined(reg_REGWPTR)
684
    REGWPTR = saved_regwptr;
685
#endif
686
#elif defined(TARGET_PPC)
687
#elif defined(TARGET_M68K)
688
    cpu_m68k_flush_flags(env, env->cc_op);
689
    env->cc_op = CC_OP_FLAGS;
690
    env->sr = (env->sr & 0xffe0)
691
              | env->cc_dest | (env->cc_x << 4);
692
#elif defined(TARGET_MIPS)
693
#elif defined(TARGET_SH4)
694
#elif defined(TARGET_ALPHA)
695
#elif defined(TARGET_CRIS)
696
    /* XXXXX */
697
#else
698
#error unsupported target CPU
699
#endif
700

    
701
    /* restore global registers */
702
#if defined(__sparc__) && !defined(HOST_SOLARIS)
703
    asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
704
#endif
705
#include "hostregs_helper.h"
706

    
707
    /* fail safe : never use cpu_single_env outside cpu_exec() */
708
    cpu_single_env = NULL;
709
    return ret;
710
}
711

    
712
/* must only be called from the generated code as an exception can be
713
   generated */
714
void tb_invalidate_page_range(target_ulong start, target_ulong end)
715
{
716
    /* XXX: cannot enable it yet because it yields to MMU exception
717
       where NIP != read address on PowerPC */
718
#if 0
719
    target_ulong phys_addr;
720
    phys_addr = get_phys_addr_code(env, start);
721
    tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
722
#endif
723
}
724

    
725
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
726

    
727
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
728
{
729
    CPUX86State *saved_env;
730

    
731
    saved_env = env;
732
    env = s;
733
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
734
        selector &= 0xffff;
735
        cpu_x86_load_seg_cache(env, seg_reg, selector,
736
                               (selector << 4), 0xffff, 0);
737
    } else {
738
        load_seg(seg_reg, selector);
739
    }
740
    env = saved_env;
741
}
742

    
743
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
744
{
745
    CPUX86State *saved_env;
746

    
747
    saved_env = env;
748
    env = s;
749

    
750
    helper_fsave((target_ulong)ptr, data32);
751

    
752
    env = saved_env;
753
}
754

    
755
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
756
{
757
    CPUX86State *saved_env;
758

    
759
    saved_env = env;
760
    env = s;
761

    
762
    helper_frstor((target_ulong)ptr, data32);
763

    
764
    env = saved_env;
765
}
766

    
767
#endif /* TARGET_I386 */
768

    
769
#if !defined(CONFIG_SOFTMMU)
770

    
771
#if defined(TARGET_I386)
772

    
773
/* 'pc' is the host PC at which the exception was raised. 'address' is
774
   the effective address of the memory exception. 'is_write' is 1 if a
775
   write caused the exception and otherwise 0'. 'old_set' is the
776
   signal set which should be restored */
777
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
778
                                    int is_write, sigset_t *old_set,
779
                                    void *puc)
780
{
781
    TranslationBlock *tb;
782
    int ret;
783

    
784
    if (cpu_single_env)
785
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
786
#if defined(DEBUG_SIGNAL)
787
    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
788
                pc, address, is_write, *(unsigned long *)old_set);
789
#endif
790
    /* XXX: locking issue */
791
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
792
        return 1;
793
    }
794

    
795
    /* see if it is an MMU fault */
796
    ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
797
    if (ret < 0)
798
        return 0; /* not an MMU fault */
799
    if (ret == 0)
800
        return 1; /* the MMU fault was handled without causing real CPU fault */
801
    /* now we have a real cpu fault */
802
    tb = tb_find_pc(pc);
803
    if (tb) {
804
        /* the PC is inside the translated code. It means that we have
805
           a virtual CPU fault */
806
        cpu_restore_state(tb, env, pc, puc);
807
    }
808
    if (ret == 1) {
809
#if 0
810
        printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
811
               env->eip, env->cr[2], env->error_code);
812
#endif
813
        /* we restore the process signal mask as the sigreturn should
814
           do it (XXX: use sigsetjmp) */
815
        sigprocmask(SIG_SETMASK, old_set, NULL);
816
        raise_exception_err(env->exception_index, env->error_code);
817
    } else {
818
        /* activate soft MMU for this block */
819
        env->hflags |= HF_SOFTMMU_MASK;
820
        cpu_resume_from_signal(env, puc);
821
    }
822
    /* never comes here */
823
    return 1;
824
}
825

    
826
#elif defined(TARGET_ARM)
827
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
828
                                    int is_write, sigset_t *old_set,
829
                                    void *puc)
830
{
831
    TranslationBlock *tb;
832
    int ret;
833

    
834
    if (cpu_single_env)
835
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
836
#if defined(DEBUG_SIGNAL)
837
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
838
           pc, address, is_write, *(unsigned long *)old_set);
839
#endif
840
    /* XXX: locking issue */
841
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
842
        return 1;
843
    }
844
    /* see if it is an MMU fault */
845
    ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
846
    if (ret < 0)
847
        return 0; /* not an MMU fault */
848
    if (ret == 0)
849
        return 1; /* the MMU fault was handled without causing real CPU fault */
850
    /* now we have a real cpu fault */
851
    tb = tb_find_pc(pc);
852
    if (tb) {
853
        /* the PC is inside the translated code. It means that we have
854
           a virtual CPU fault */
855
        cpu_restore_state(tb, env, pc, puc);
856
    }
857
    /* we restore the process signal mask as the sigreturn should
858
       do it (XXX: use sigsetjmp) */
859
    sigprocmask(SIG_SETMASK, old_set, NULL);
860
    cpu_loop_exit();
861
}
862
#elif defined(TARGET_SPARC)
863
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
864
                                    int is_write, sigset_t *old_set,
865
                                    void *puc)
866
{
867
    TranslationBlock *tb;
868
    int ret;
869

    
870
    if (cpu_single_env)
871
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
872
#if defined(DEBUG_SIGNAL)
873
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
874
           pc, address, is_write, *(unsigned long *)old_set);
875
#endif
876
    /* XXX: locking issue */
877
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
878
        return 1;
879
    }
880
    /* see if it is an MMU fault */
881
    ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
882
    if (ret < 0)
883
        return 0; /* not an MMU fault */
884
    if (ret == 0)
885
        return 1; /* the MMU fault was handled without causing real CPU fault */
886
    /* now we have a real cpu fault */
887
    tb = tb_find_pc(pc);
888
    if (tb) {
889
        /* the PC is inside the translated code. It means that we have
890
           a virtual CPU fault */
891
        cpu_restore_state(tb, env, pc, puc);
892
    }
893
    /* we restore the process signal mask as the sigreturn should
894
       do it (XXX: use sigsetjmp) */
895
    sigprocmask(SIG_SETMASK, old_set, NULL);
896
    cpu_loop_exit();
897
}
898
#elif defined (TARGET_PPC)
899
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
900
                                    int is_write, sigset_t *old_set,
901
                                    void *puc)
902
{
903
    TranslationBlock *tb;
904
    int ret;
905

    
906
    if (cpu_single_env)
907
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
908
#if defined(DEBUG_SIGNAL)
909
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
910
           pc, address, is_write, *(unsigned long *)old_set);
911
#endif
912
    /* XXX: locking issue */
913
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
914
        return 1;
915
    }
916

    
917
    /* see if it is an MMU fault */
918
    ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
919
    if (ret < 0)
920
        return 0; /* not an MMU fault */
921
    if (ret == 0)
922
        return 1; /* the MMU fault was handled without causing real CPU fault */
923

    
924
    /* now we have a real cpu fault */
925
    tb = tb_find_pc(pc);
926
    if (tb) {
927
        /* the PC is inside the translated code. It means that we have
928
           a virtual CPU fault */
929
        cpu_restore_state(tb, env, pc, puc);
930
    }
931
    if (ret == 1) {
932
#if 0
933
        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
934
               env->nip, env->error_code, tb);
935
#endif
936
    /* we restore the process signal mask as the sigreturn should
937
       do it (XXX: use sigsetjmp) */
938
        sigprocmask(SIG_SETMASK, old_set, NULL);
939
        do_raise_exception_err(env->exception_index, env->error_code);
940
    } else {
941
        /* activate soft MMU for this block */
942
        cpu_resume_from_signal(env, puc);
943
    }
944
    /* never comes here */
945
    return 1;
946
}
947

    
948
#elif defined(TARGET_M68K)
949
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
950
                                    int is_write, sigset_t *old_set,
951
                                    void *puc)
952
{
953
    TranslationBlock *tb;
954
    int ret;
955

    
956
    if (cpu_single_env)
957
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
958
#if defined(DEBUG_SIGNAL)
959
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
960
           pc, address, is_write, *(unsigned long *)old_set);
961
#endif
962
    /* XXX: locking issue */
963
    if (is_write && page_unprotect(address, pc, puc)) {
964
        return 1;
965
    }
966
    /* see if it is an MMU fault */
967
    ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
968
    if (ret < 0)
969
        return 0; /* not an MMU fault */
970
    if (ret == 0)
971
        return 1; /* the MMU fault was handled without causing real CPU fault */
972
    /* now we have a real cpu fault */
973
    tb = tb_find_pc(pc);
974
    if (tb) {
975
        /* the PC is inside the translated code. It means that we have
976
           a virtual CPU fault */
977
        cpu_restore_state(tb, env, pc, puc);
978
    }
979
    /* we restore the process signal mask as the sigreturn should
980
       do it (XXX: use sigsetjmp) */
981
    sigprocmask(SIG_SETMASK, old_set, NULL);
982
    cpu_loop_exit();
983
    /* never comes here */
984
    return 1;
985
}
986

    
987
#elif defined (TARGET_MIPS)
988
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
989
                                    int is_write, sigset_t *old_set,
990
                                    void *puc)
991
{
992
    TranslationBlock *tb;
993
    int ret;
994

    
995
    if (cpu_single_env)
996
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
997
#if defined(DEBUG_SIGNAL)
998
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
999
           pc, address, is_write, *(unsigned long *)old_set);
1000
#endif
1001
    /* XXX: locking issue */
1002
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
1003
        return 1;
1004
    }
1005

    
1006
    /* see if it is an MMU fault */
1007
    ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1008
    if (ret < 0)
1009
        return 0; /* not an MMU fault */
1010
    if (ret == 0)
1011
        return 1; /* the MMU fault was handled without causing real CPU fault */
1012

    
1013
    /* now we have a real cpu fault */
1014
    tb = tb_find_pc(pc);
1015
    if (tb) {
1016
        /* the PC is inside the translated code. It means that we have
1017
           a virtual CPU fault */
1018
        cpu_restore_state(tb, env, pc, puc);
1019
    }
1020
    if (ret == 1) {
1021
#if 0
1022
        printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1023
               env->PC, env->error_code, tb);
1024
#endif
1025
    /* we restore the process signal mask as the sigreturn should
1026
       do it (XXX: use sigsetjmp) */
1027
        sigprocmask(SIG_SETMASK, old_set, NULL);
1028
        do_raise_exception_err(env->exception_index, env->error_code);
1029
    } else {
1030
        /* activate soft MMU for this block */
1031
        cpu_resume_from_signal(env, puc);
1032
    }
1033
    /* never comes here */
1034
    return 1;
1035
}
1036

    
1037
#elif defined (TARGET_SH4)
1038
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1039
                                    int is_write, sigset_t *old_set,
1040
                                    void *puc)
1041
{
1042
    TranslationBlock *tb;
1043
    int ret;
1044

    
1045
    if (cpu_single_env)
1046
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
1047
#if defined(DEBUG_SIGNAL)
1048
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1049
           pc, address, is_write, *(unsigned long *)old_set);
1050
#endif
1051
    /* XXX: locking issue */
1052
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
1053
        return 1;
1054
    }
1055

    
1056
    /* see if it is an MMU fault */
1057
    ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1058
    if (ret < 0)
1059
        return 0; /* not an MMU fault */
1060
    if (ret == 0)
1061
        return 1; /* the MMU fault was handled without causing real CPU fault */
1062

    
1063
    /* now we have a real cpu fault */
1064
    tb = tb_find_pc(pc);
1065
    if (tb) {
1066
        /* the PC is inside the translated code. It means that we have
1067
           a virtual CPU fault */
1068
        cpu_restore_state(tb, env, pc, puc);
1069
    }
1070
#if 0
1071
        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1072
               env->nip, env->error_code, tb);
1073
#endif
1074
    /* we restore the process signal mask as the sigreturn should
1075
       do it (XXX: use sigsetjmp) */
1076
    sigprocmask(SIG_SETMASK, old_set, NULL);
1077
    cpu_loop_exit();
1078
    /* never comes here */
1079
    return 1;
1080
}
1081

    
1082
#elif defined (TARGET_ALPHA)
1083
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1084
                                    int is_write, sigset_t *old_set,
1085
                                    void *puc)
1086
{
1087
    TranslationBlock *tb;
1088
    int ret;
1089

    
1090
    if (cpu_single_env)
1091
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
1092
#if defined(DEBUG_SIGNAL)
1093
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1094
           pc, address, is_write, *(unsigned long *)old_set);
1095
#endif
1096
    /* XXX: locking issue */
1097
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
1098
        return 1;
1099
    }
1100

    
1101
    /* see if it is an MMU fault */
1102
    ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1103
    if (ret < 0)
1104
        return 0; /* not an MMU fault */
1105
    if (ret == 0)
1106
        return 1; /* the MMU fault was handled without causing real CPU fault */
1107

    
1108
    /* now we have a real cpu fault */
1109
    tb = tb_find_pc(pc);
1110
    if (tb) {
1111
        /* the PC is inside the translated code. It means that we have
1112
           a virtual CPU fault */
1113
        cpu_restore_state(tb, env, pc, puc);
1114
    }
1115
#if 0
1116
        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1117
               env->nip, env->error_code, tb);
1118
#endif
1119
    /* we restore the process signal mask as the sigreturn should
1120
       do it (XXX: use sigsetjmp) */
1121
    sigprocmask(SIG_SETMASK, old_set, NULL);
1122
    cpu_loop_exit();
1123
    /* never comes here */
1124
    return 1;
1125
}
1126
#elif defined (TARGET_CRIS)
1127
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1128
                                    int is_write, sigset_t *old_set,
1129
                                    void *puc)
1130
{
1131
    TranslationBlock *tb;
1132
    int ret;
1133

    
1134
    if (cpu_single_env)
1135
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
1136
#if defined(DEBUG_SIGNAL)
1137
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1138
           pc, address, is_write, *(unsigned long *)old_set);
1139
#endif
1140
    /* XXX: locking issue */
1141
    if (is_write && page_unprotect(h2g(address), pc, puc)) {
1142
        return 1;
1143
    }
1144

    
1145
    /* see if it is an MMU fault */
1146
    ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1147
    if (ret < 0)
1148
        return 0; /* not an MMU fault */
1149
    if (ret == 0)
1150
        return 1; /* the MMU fault was handled without causing real CPU fault */
1151

    
1152
    /* now we have a real cpu fault */
1153
    tb = tb_find_pc(pc);
1154
    if (tb) {
1155
        /* the PC is inside the translated code. It means that we have
1156
           a virtual CPU fault */
1157
        cpu_restore_state(tb, env, pc, puc);
1158
    }
1159
#if 0
1160
        printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1161
               env->nip, env->error_code, tb);
1162
#endif
1163
    /* we restore the process signal mask as the sigreturn should
1164
       do it (XXX: use sigsetjmp) */
1165
    sigprocmask(SIG_SETMASK, old_set, NULL);
1166
    cpu_loop_exit();
1167
    /* never comes here */
1168
    return 1;
1169
}
1170

    
1171
#else
1172
#error unsupported target CPU
1173
#endif
1174

    
1175
#if defined(__i386__)
1176

    
1177
#if defined(__APPLE__)
1178
# include <sys/ucontext.h>
1179

    
1180
# define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1181
# define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
1182
# define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
1183
#else
1184
# define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
1185
# define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
1186
# define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
1187
#endif
1188

    
1189
int cpu_signal_handler(int host_signum, void *pinfo,
1190
                       void *puc)
1191
{
1192
    siginfo_t *info = pinfo;
1193
    struct ucontext *uc = puc;
1194
    unsigned long pc;
1195
    int trapno;
1196

    
1197
#ifndef REG_EIP
1198
/* for glibc 2.1 */
1199
#define REG_EIP    EIP
1200
#define REG_ERR    ERR
1201
#define REG_TRAPNO TRAPNO
1202
#endif
1203
    pc = EIP_sig(uc);
1204
    trapno = TRAP_sig(uc);
1205
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1206
                             trapno == 0xe ?
1207
                             (ERROR_sig(uc) >> 1) & 1 : 0,
1208
                             &uc->uc_sigmask, puc);
1209
}
1210

    
1211
#elif defined(__x86_64__)
1212

    
1213
int cpu_signal_handler(int host_signum, void *pinfo,
1214
                       void *puc)
1215
{
1216
    siginfo_t *info = pinfo;
1217
    struct ucontext *uc = puc;
1218
    unsigned long pc;
1219

    
1220
    pc = uc->uc_mcontext.gregs[REG_RIP];
1221
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1222
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1223
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1224
                             &uc->uc_sigmask, puc);
1225
}
1226

    
1227
#elif defined(__powerpc__)
1228

    
1229
/***********************************************************************
1230
 * signal context platform-specific definitions
1231
 * From Wine
1232
 */
1233
#ifdef linux
1234
/* All Registers access - only for local access */
1235
# define REG_sig(reg_name, context)                ((context)->uc_mcontext.regs->reg_name)
1236
/* Gpr Registers access  */
1237
# define GPR_sig(reg_num, context)                REG_sig(gpr[reg_num], context)
1238
# define IAR_sig(context)                        REG_sig(nip, context)        /* Program counter */
1239
# define MSR_sig(context)                        REG_sig(msr, context)   /* Machine State Register (Supervisor) */
1240
# define CTR_sig(context)                        REG_sig(ctr, context)   /* Count register */
1241
# define XER_sig(context)                        REG_sig(xer, context) /* User's integer exception register */
1242
# define LR_sig(context)                        REG_sig(link, context) /* Link register */
1243
# define CR_sig(context)                        REG_sig(ccr, context) /* Condition register */
1244
/* Float Registers access  */
1245
# define FLOAT_sig(reg_num, context)                (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1246
# define FPSCR_sig(context)                        (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1247
/* Exception Registers access */
1248
# define DAR_sig(context)                        REG_sig(dar, context)
1249
# define DSISR_sig(context)                        REG_sig(dsisr, context)
1250
# define TRAP_sig(context)                        REG_sig(trap, context)
1251
#endif /* linux */
1252

    
1253
#ifdef __APPLE__
1254
# include <sys/ucontext.h>
1255
typedef struct ucontext SIGCONTEXT;
1256
/* All Registers access - only for local access */
1257
# define REG_sig(reg_name, context)                ((context)->uc_mcontext->ss.reg_name)
1258
# define FLOATREG_sig(reg_name, context)        ((context)->uc_mcontext->fs.reg_name)
1259
# define EXCEPREG_sig(reg_name, context)        ((context)->uc_mcontext->es.reg_name)
1260
# define VECREG_sig(reg_name, context)                ((context)->uc_mcontext->vs.reg_name)
1261
/* Gpr Registers access */
1262
# define GPR_sig(reg_num, context)                REG_sig(r##reg_num, context)
1263
# define IAR_sig(context)                        REG_sig(srr0, context)        /* Program counter */
1264
# define MSR_sig(context)                        REG_sig(srr1, context)  /* Machine State Register (Supervisor) */
1265
# define CTR_sig(context)                        REG_sig(ctr, context)
1266
# define XER_sig(context)                        REG_sig(xer, context) /* Link register */
1267
# define LR_sig(context)                        REG_sig(lr, context)  /* User's integer exception register */
1268
# define CR_sig(context)                        REG_sig(cr, context)  /* Condition register */
1269
/* Float Registers access */
1270
# define FLOAT_sig(reg_num, context)                FLOATREG_sig(fpregs[reg_num], context)
1271
# define FPSCR_sig(context)                        ((double)FLOATREG_sig(fpscr, context))
1272
/* Exception Registers access */
1273
# define DAR_sig(context)                        EXCEPREG_sig(dar, context)     /* Fault registers for coredump */
1274
# define DSISR_sig(context)                        EXCEPREG_sig(dsisr, context)
1275
# define TRAP_sig(context)                        EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1276
#endif /* __APPLE__ */
1277

    
1278
int cpu_signal_handler(int host_signum, void *pinfo,
1279
                       void *puc)
1280
{
1281
    siginfo_t *info = pinfo;
1282
    struct ucontext *uc = puc;
1283
    unsigned long pc;
1284
    int is_write;
1285

    
1286
    pc = IAR_sig(uc);
1287
    is_write = 0;
1288
#if 0
1289
    /* ppc 4xx case */
1290
    if (DSISR_sig(uc) & 0x00800000)
1291
        is_write = 1;
1292
#else
1293
    if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1294
        is_write = 1;
1295
#endif
1296
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1297
                             is_write, &uc->uc_sigmask, puc);
1298
}
1299

    
1300
#elif defined(__alpha__)
1301

    
1302
int cpu_signal_handler(int host_signum, void *pinfo,
1303
                           void *puc)
1304
{
1305
    siginfo_t *info = pinfo;
1306
    struct ucontext *uc = puc;
1307
    uint32_t *pc = uc->uc_mcontext.sc_pc;
1308
    uint32_t insn = *pc;
1309
    int is_write = 0;
1310

    
1311
    /* XXX: need kernel patch to get write flag faster */
1312
    switch (insn >> 26) {
1313
    case 0x0d: // stw
1314
    case 0x0e: // stb
1315
    case 0x0f: // stq_u
1316
    case 0x24: // stf
1317
    case 0x25: // stg
1318
    case 0x26: // sts
1319
    case 0x27: // stt
1320
    case 0x2c: // stl
1321
    case 0x2d: // stq
1322
    case 0x2e: // stl_c
1323
    case 0x2f: // stq_c
1324
        is_write = 1;
1325
    }
1326

    
1327
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1328
                             is_write, &uc->uc_sigmask, puc);
1329
}
1330
#elif defined(__sparc__)
1331

    
1332
int cpu_signal_handler(int host_signum, void *pinfo,
1333
                       void *puc)
1334
{
1335
    siginfo_t *info = pinfo;
1336
    uint32_t *regs = (uint32_t *)(info + 1);
1337
    void *sigmask = (regs + 20);
1338
    unsigned long pc;
1339
    int is_write;
1340
    uint32_t insn;
1341

    
1342
    /* XXX: is there a standard glibc define ? */
1343
    pc = regs[1];
1344
    /* XXX: need kernel patch to get write flag faster */
1345
    is_write = 0;
1346
    insn = *(uint32_t *)pc;
1347
    if ((insn >> 30) == 3) {
1348
      switch((insn >> 19) & 0x3f) {
1349
      case 0x05: // stb
1350
      case 0x06: // sth
1351
      case 0x04: // st
1352
      case 0x07: // std
1353
      case 0x24: // stf
1354
      case 0x27: // stdf
1355
      case 0x25: // stfsr
1356
        is_write = 1;
1357
        break;
1358
      }
1359
    }
1360
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1361
                             is_write, sigmask, NULL);
1362
}
1363

    
1364
#elif defined(__arm__)
1365

    
1366
int cpu_signal_handler(int host_signum, void *pinfo,
1367
                       void *puc)
1368
{
1369
    siginfo_t *info = pinfo;
1370
    struct ucontext *uc = puc;
1371
    unsigned long pc;
1372
    int is_write;
1373

    
1374
    pc = uc->uc_mcontext.gregs[R15];
1375
    /* XXX: compute is_write */
1376
    is_write = 0;
1377
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1378
                             is_write,
1379
                             &uc->uc_sigmask, puc);
1380
}
1381

    
1382
#elif defined(__mc68000)
1383

    
1384
int cpu_signal_handler(int host_signum, void *pinfo,
1385
                       void *puc)
1386
{
1387
    siginfo_t *info = pinfo;
1388
    struct ucontext *uc = puc;
1389
    unsigned long pc;
1390
    int is_write;
1391

    
1392
    pc = uc->uc_mcontext.gregs[16];
1393
    /* XXX: compute is_write */
1394
    is_write = 0;
1395
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1396
                             is_write,
1397
                             &uc->uc_sigmask, puc);
1398
}
1399

    
1400
#elif defined(__ia64)
1401

    
1402
#ifndef __ISR_VALID
1403
  /* This ought to be in <bits/siginfo.h>... */
1404
# define __ISR_VALID        1
1405
#endif
1406

    
1407
int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1408
{
1409
    siginfo_t *info = pinfo;
1410
    struct ucontext *uc = puc;
1411
    unsigned long ip;
1412
    int is_write = 0;
1413

    
1414
    ip = uc->uc_mcontext.sc_ip;
1415
    switch (host_signum) {
1416
      case SIGILL:
1417
      case SIGFPE:
1418
      case SIGSEGV:
1419
      case SIGBUS:
1420
      case SIGTRAP:
1421
          if (info->si_code && (info->si_segvflags & __ISR_VALID))
1422
              /* ISR.W (write-access) is bit 33:  */
1423
              is_write = (info->si_isr >> 33) & 1;
1424
          break;
1425

    
1426
      default:
1427
          break;
1428
    }
1429
    return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1430
                             is_write,
1431
                             &uc->uc_sigmask, puc);
1432
}
1433

    
1434
#elif defined(__s390__)
1435

    
1436
int cpu_signal_handler(int host_signum, void *pinfo,
1437
                       void *puc)
1438
{
1439
    siginfo_t *info = pinfo;
1440
    struct ucontext *uc = puc;
1441
    unsigned long pc;
1442
    int is_write;
1443

    
1444
    pc = uc->uc_mcontext.psw.addr;
1445
    /* XXX: compute is_write */
1446
    is_write = 0;
1447
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1448
                             is_write, &uc->uc_sigmask, puc);
1449
}
1450

    
1451
#elif defined(__mips__)
1452

    
1453
int cpu_signal_handler(int host_signum, void *pinfo,
1454
                       void *puc)
1455
{
1456
    siginfo_t *info = pinfo;
1457
    struct ucontext *uc = puc;
1458
    greg_t pc = uc->uc_mcontext.pc;
1459
    int is_write;
1460

    
1461
    /* XXX: compute is_write */
1462
    is_write = 0;
1463
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1464
                             is_write, &uc->uc_sigmask, puc);
1465
}
1466

    
1467
#else
1468

    
1469
#error host CPU specific signal handler needed
1470

    
1471
#endif
1472

    
1473
#endif /* !defined(CONFIG_SOFTMMU) */