Revision eddf68a6
| b/cpu-all.h | ||
|---|---|---|
| 748 | 748 |
#define cpu_gen_code cpu_sh4_gen_code |
| 749 | 749 |
#define cpu_signal_handler cpu_sh4_signal_handler |
| 750 | 750 |
|
| 751 |
#elif defined(TARGET_ALPHA) |
|
| 752 |
#define CPUState CPUAlphaState |
|
| 753 |
#define cpu_init cpu_alpha_init |
|
| 754 |
#define cpu_exec cpu_alpha_exec |
|
| 755 |
#define cpu_gen_code cpu_alpha_gen_code |
|
| 756 |
#define cpu_signal_handler cpu_alpha_signal_handler |
|
| 757 |
|
|
| 751 | 758 |
#else |
| 752 | 759 |
|
| 753 | 760 |
#error unsupported target CPU |
| b/cpu-exec.c | ||
|---|---|---|
| 40 | 40 |
//#define DEBUG_EXEC |
| 41 | 41 |
//#define DEBUG_SIGNAL |
| 42 | 42 |
|
| 43 |
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) |
|
| 43 |
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \ |
|
| 44 |
defined(TARGET_ALPHA) |
|
| 44 | 45 |
/* XXX: unify with i386 target */ |
| 45 | 46 |
void cpu_loop_exit(void) |
| 46 | 47 |
{
|
| ... | ... | |
| 202 | 203 |
flags = env->sr & (SR_MD | SR_RB); |
| 203 | 204 |
cs_base = 0; /* XXXXX */ |
| 204 | 205 |
pc = env->pc; |
| 206 |
#elif defined(TARGET_ALPHA) |
|
| 207 |
flags = env->ps; |
|
| 208 |
cs_base = 0; |
|
| 209 |
pc = env->pc; |
|
| 205 | 210 |
#else |
| 206 | 211 |
#error unsupported CPU |
| 207 | 212 |
#endif |
| ... | ... | |
| 291 | 296 |
return EXCP_HALTED; |
| 292 | 297 |
} |
| 293 | 298 |
} |
| 299 |
#elif defined(TARGET_ALPHA) |
|
| 300 |
if (env1->halted) {
|
|
| 301 |
if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
|
|
| 302 |
env1->halted = 0; |
|
| 303 |
} else {
|
|
| 304 |
return EXCP_HALTED; |
|
| 305 |
} |
|
| 306 |
} |
|
| 294 | 307 |
#endif |
| 295 | 308 |
|
| 296 | 309 |
cpu_single_env = env1; |
| ... | ... | |
| 324 | 337 |
#elif defined(TARGET_MIPS) |
| 325 | 338 |
#elif defined(TARGET_SH4) |
| 326 | 339 |
/* XXXXX */ |
| 340 |
#elif defined(TARGET_ALPHA) |
|
| 341 |
env_to_regs(); |
|
| 327 | 342 |
#else |
| 328 | 343 |
#error unsupported target CPU |
| 329 | 344 |
#endif |
| ... | ... | |
| 372 | 387 |
do_interrupt(env); |
| 373 | 388 |
#elif defined(TARGET_SH4) |
| 374 | 389 |
do_interrupt(env); |
| 390 |
#elif defined(TARGET_ALPHA) |
|
| 391 |
do_interrupt(env); |
|
| 375 | 392 |
#endif |
| 376 | 393 |
} |
| 377 | 394 |
env->exception_index = -1; |
| ... | ... | |
| 518 | 535 |
} |
| 519 | 536 |
#elif defined(TARGET_SH4) |
| 520 | 537 |
/* XXXXX */ |
| 538 |
#elif defined(TARGET_ALPHA) |
|
| 539 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
| 540 |
do_interrupt(env); |
|
| 541 |
} |
|
| 521 | 542 |
#endif |
| 522 | 543 |
/* Don't use the cached interupt_request value, |
| 523 | 544 |
do_interrupt may have updated the EXITTB flag. */ |
| ... | ... | |
| 586 | 607 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 587 | 608 |
#elif defined(TARGET_SH4) |
| 588 | 609 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 610 |
#elif defined(TARGET_ALPHA) |
|
| 611 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 589 | 612 |
#else |
| 590 | 613 |
#error unsupported target CPU |
| 591 | 614 |
#endif |
| ... | ... | |
| 778 | 801 |
| env->cc_dest | (env->cc_x << 4); |
| 779 | 802 |
#elif defined(TARGET_MIPS) |
| 780 | 803 |
#elif defined(TARGET_SH4) |
| 804 |
#elif defined(TARGET_ALPHA) |
|
| 781 | 805 |
/* XXXXX */ |
| 782 | 806 |
#else |
| 783 | 807 |
#error unsupported target CPU |
| ... | ... | |
| 1164 | 1188 |
/* never comes here */ |
| 1165 | 1189 |
return 1; |
| 1166 | 1190 |
} |
| 1191 |
|
|
| 1192 |
#elif defined (TARGET_ALPHA) |
|
| 1193 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
|
| 1194 |
int is_write, sigset_t *old_set, |
|
| 1195 |
void *puc) |
|
| 1196 |
{
|
|
| 1197 |
TranslationBlock *tb; |
|
| 1198 |
int ret; |
|
| 1199 |
|
|
| 1200 |
if (cpu_single_env) |
|
| 1201 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
|
| 1202 |
#if defined(DEBUG_SIGNAL) |
|
| 1203 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
| 1204 |
pc, address, is_write, *(unsigned long *)old_set); |
|
| 1205 |
#endif |
|
| 1206 |
/* XXX: locking issue */ |
|
| 1207 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
|
| 1208 |
return 1; |
|
| 1209 |
} |
|
| 1210 |
|
|
| 1211 |
/* see if it is an MMU fault */ |
|
| 1212 |
ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0); |
|
| 1213 |
if (ret < 0) |
|
| 1214 |
return 0; /* not an MMU fault */ |
|
| 1215 |
if (ret == 0) |
|
| 1216 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
|
| 1217 |
|
|
| 1218 |
/* now we have a real cpu fault */ |
|
| 1219 |
tb = tb_find_pc(pc); |
|
| 1220 |
if (tb) {
|
|
| 1221 |
/* the PC is inside the translated code. It means that we have |
|
| 1222 |
a virtual CPU fault */ |
|
| 1223 |
cpu_restore_state(tb, env, pc, puc); |
|
| 1224 |
} |
|
| 1225 |
#if 0 |
|
| 1226 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
|
| 1227 |
env->nip, env->error_code, tb); |
|
| 1228 |
#endif |
|
| 1229 |
/* we restore the process signal mask as the sigreturn should |
|
| 1230 |
do it (XXX: use sigsetjmp) */ |
|
| 1231 |
sigprocmask(SIG_SETMASK, old_set, NULL); |
|
| 1232 |
cpu_loop_exit(); |
|
| 1233 |
/* never comes here */ |
|
| 1234 |
return 1; |
|
| 1235 |
} |
|
| 1167 | 1236 |
#else |
| 1168 | 1237 |
#error unsupported target CPU |
| 1169 | 1238 |
#endif |
| b/dis-asm.h | ||
|---|---|---|
| 181 | 181 |
#define bfd_mach_sh4al_dsp 0x4d |
| 182 | 182 |
#define bfd_mach_sh5 0x50 |
| 183 | 183 |
bfd_arch_alpha, /* Dec Alpha */ |
| 184 |
#define bfd_mach_alpha 1 |
|
| 184 | 185 |
bfd_arch_arm, /* Advanced Risc Machines ARM */ |
| 185 | 186 |
#define bfd_mach_arm_2 1 |
| 186 | 187 |
#define bfd_mach_arm_2a 2 |
| ... | ... | |
| 377 | 378 |
extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); |
| 378 | 379 |
extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); |
| 379 | 380 |
extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*)); |
| 381 |
extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); |
|
| 380 | 382 |
|
| 381 | 383 |
#if 0 |
| 382 | 384 |
/* Fetch the disassembler for a given BFD, if that support is available. */ |
| b/disas.c | ||
|---|---|---|
| 197 | 197 |
#elif defined(TARGET_SH4) |
| 198 | 198 |
disasm_info.mach = bfd_mach_sh4; |
| 199 | 199 |
print_insn = print_insn_sh; |
| 200 |
#elif defined(TARGET_ALPHA) |
|
| 201 |
disasm_info.mach = bfd_mach_alpha; |
|
| 202 |
print_insn = print_insn_alpha; |
|
| 200 | 203 |
#else |
| 201 | 204 |
fprintf(out, "0x" TARGET_FMT_lx |
| 202 | 205 |
": Asm output not supported on this arch\n", code); |
| b/exec-all.h | ||
|---|---|---|
| 572 | 572 |
is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); |
| 573 | 573 |
#elif defined (TARGET_SH4) |
| 574 | 574 |
is_user = ((env->sr & SR_MD) == 0); |
| 575 |
#elif defined (TARGET_ALPHA) |
|
| 576 |
is_user = ((env->ps >> 3) & 3); |
|
| 575 | 577 |
#else |
| 576 | 578 |
#error unimplemented CPU |
| 577 | 579 |
#endif |
| b/softmmu_header.h | ||
|---|---|---|
| 63 | 63 |
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) |
| 64 | 64 |
#elif defined (TARGET_SH4) |
| 65 | 65 |
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
| 66 |
#elif defined (TARGET_ALPHA) |
|
| 67 |
#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
|
| 66 | 68 |
#else |
| 67 | 69 |
#error unsupported CPU |
| 68 | 70 |
#endif |
| ... | ... | |
| 82 | 84 |
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) |
| 83 | 85 |
#elif defined (TARGET_SH4) |
| 84 | 86 |
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) |
| 87 |
#elif defined (TARGET_ALPHA) |
|
| 88 |
#define CPU_MEM_INDEX ((env->ps >> 3) & 3) |
|
| 85 | 89 |
#else |
| 86 | 90 |
#error unsupported CPU |
| 87 | 91 |
#endif |
| b/translate-all.c | ||
|---|---|---|
| 308 | 308 |
env->PC = gen_opc_pc[j]; |
| 309 | 309 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 310 | 310 |
env->hflags |= gen_opc_hflags[j]; |
| 311 |
#elif defined(TARGET_ALPHA) |
|
| 312 |
env->pc = gen_opc_pc[j]; |
|
| 311 | 313 |
#endif |
| 312 | 314 |
return 0; |
| 313 | 315 |
} |
| b/vl.c | ||
|---|---|---|
| 6707 | 6707 |
qemu_register_machine(&realview_machine); |
| 6708 | 6708 |
#elif defined(TARGET_SH4) |
| 6709 | 6709 |
qemu_register_machine(&shix_machine); |
| 6710 |
#elif defined(TARGET_ALPHA) |
|
| 6711 |
/* XXX: TODO */ |
|
| 6710 | 6712 |
#else |
| 6711 | 6713 |
#error unsupported CPU |
| 6712 | 6714 |
#endif |
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