root / target-sparc / op_helper.c @ ee0b03fd
History | View | Annotate | Download (40.8 kB)
| 1 | e8af50a3 | bellard | #include "exec.h" |
|---|---|---|---|
| 2 | e8af50a3 | bellard | |
| 3 | 83469015 | bellard | //#define DEBUG_PCALL
|
| 4 | e80cfcfc | bellard | //#define DEBUG_MMU
|
| 5 | 94554550 | blueswir1 | //#define DEBUG_UNALIGNED
|
| 6 | 6c36d3fa | blueswir1 | //#define DEBUG_UNASSIGNED
|
| 7 | e80cfcfc | bellard | |
| 8 | 9d893301 | bellard | void raise_exception(int tt) |
| 9 | 9d893301 | bellard | {
|
| 10 | 9d893301 | bellard | env->exception_index = tt; |
| 11 | 9d893301 | bellard | cpu_loop_exit(); |
| 12 | 3b46e624 | ths | } |
| 13 | 9d893301 | bellard | |
| 14 | 417454b0 | blueswir1 | void check_ieee_exceptions()
|
| 15 | 417454b0 | blueswir1 | {
|
| 16 | 417454b0 | blueswir1 | T0 = get_float_exception_flags(&env->fp_status); |
| 17 | 417454b0 | blueswir1 | if (T0)
|
| 18 | 417454b0 | blueswir1 | {
|
| 19 | 0f8a249a | blueswir1 | /* Copy IEEE 754 flags into FSR */
|
| 20 | 0f8a249a | blueswir1 | if (T0 & float_flag_invalid)
|
| 21 | 0f8a249a | blueswir1 | env->fsr |= FSR_NVC; |
| 22 | 0f8a249a | blueswir1 | if (T0 & float_flag_overflow)
|
| 23 | 0f8a249a | blueswir1 | env->fsr |= FSR_OFC; |
| 24 | 0f8a249a | blueswir1 | if (T0 & float_flag_underflow)
|
| 25 | 0f8a249a | blueswir1 | env->fsr |= FSR_UFC; |
| 26 | 0f8a249a | blueswir1 | if (T0 & float_flag_divbyzero)
|
| 27 | 0f8a249a | blueswir1 | env->fsr |= FSR_DZC; |
| 28 | 0f8a249a | blueswir1 | if (T0 & float_flag_inexact)
|
| 29 | 0f8a249a | blueswir1 | env->fsr |= FSR_NXC; |
| 30 | 0f8a249a | blueswir1 | |
| 31 | 0f8a249a | blueswir1 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) |
| 32 | 0f8a249a | blueswir1 | {
|
| 33 | 0f8a249a | blueswir1 | /* Unmasked exception, generate a trap */
|
| 34 | 0f8a249a | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; |
| 35 | 0f8a249a | blueswir1 | raise_exception(TT_FP_EXCP); |
| 36 | 0f8a249a | blueswir1 | } |
| 37 | 0f8a249a | blueswir1 | else
|
| 38 | 0f8a249a | blueswir1 | {
|
| 39 | 0f8a249a | blueswir1 | /* Accumulate exceptions */
|
| 40 | 0f8a249a | blueswir1 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
| 41 | 0f8a249a | blueswir1 | } |
| 42 | 417454b0 | blueswir1 | } |
| 43 | 417454b0 | blueswir1 | } |
| 44 | 417454b0 | blueswir1 | |
| 45 | a0c4cb4a | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
|
| 46 | a0c4cb4a | bellard | void do_fitos(void) |
| 47 | a0c4cb4a | bellard | {
|
| 48 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 49 | ec230928 | ths | FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
| 50 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 51 | a0c4cb4a | bellard | } |
| 52 | a0c4cb4a | bellard | |
| 53 | a0c4cb4a | bellard | void do_fitod(void) |
| 54 | a0c4cb4a | bellard | {
|
| 55 | ec230928 | ths | DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
| 56 | a0c4cb4a | bellard | } |
| 57 | a0c4cb4a | bellard | #endif
|
| 58 | a0c4cb4a | bellard | |
| 59 | a0c4cb4a | bellard | void do_fabss(void) |
| 60 | e8af50a3 | bellard | {
|
| 61 | 7a0e1f41 | bellard | FT0 = float32_abs(FT1); |
| 62 | e8af50a3 | bellard | } |
| 63 | e8af50a3 | bellard | |
| 64 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 65 | 3475187d | bellard | void do_fabsd(void) |
| 66 | 3475187d | bellard | {
|
| 67 | 3475187d | bellard | DT0 = float64_abs(DT1); |
| 68 | 3475187d | bellard | } |
| 69 | 3475187d | bellard | #endif
|
| 70 | 3475187d | bellard | |
| 71 | a0c4cb4a | bellard | void do_fsqrts(void) |
| 72 | e8af50a3 | bellard | {
|
| 73 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 74 | 7a0e1f41 | bellard | FT0 = float32_sqrt(FT1, &env->fp_status); |
| 75 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 76 | e8af50a3 | bellard | } |
| 77 | e8af50a3 | bellard | |
| 78 | a0c4cb4a | bellard | void do_fsqrtd(void) |
| 79 | e8af50a3 | bellard | {
|
| 80 | 417454b0 | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
| 81 | 7a0e1f41 | bellard | DT0 = float64_sqrt(DT1, &env->fp_status); |
| 82 | 417454b0 | blueswir1 | check_ieee_exceptions(); |
| 83 | e8af50a3 | bellard | } |
| 84 | e8af50a3 | bellard | |
| 85 | 417454b0 | blueswir1 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
|
| 86 | 65ce8c2f | bellard | void glue(do_, name) (void) \ |
| 87 | 65ce8c2f | bellard | { \
|
| 88 | 65ce8c2f | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
| 89 | 65ce8c2f | bellard | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
| 90 | 65ce8c2f | bellard | case float_relation_unordered: \
|
| 91 | 65ce8c2f | bellard | T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
| 92 | 417454b0 | blueswir1 | if ((env->fsr & FSR_NVM) || TRAP) { \
|
| 93 | 65ce8c2f | bellard | env->fsr |= T0; \ |
| 94 | 417454b0 | blueswir1 | env->fsr |= FSR_NVC; \ |
| 95 | 417454b0 | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
| 96 | 65ce8c2f | bellard | raise_exception(TT_FP_EXCP); \ |
| 97 | 65ce8c2f | bellard | } else { \
|
| 98 | 65ce8c2f | bellard | env->fsr |= FSR_NVA; \ |
| 99 | 65ce8c2f | bellard | } \ |
| 100 | 65ce8c2f | bellard | break; \
|
| 101 | 65ce8c2f | bellard | case float_relation_less: \
|
| 102 | 65ce8c2f | bellard | T0 = FSR_FCC0 << FS; \ |
| 103 | 65ce8c2f | bellard | break; \
|
| 104 | 65ce8c2f | bellard | case float_relation_greater: \
|
| 105 | 65ce8c2f | bellard | T0 = FSR_FCC1 << FS; \ |
| 106 | 65ce8c2f | bellard | break; \
|
| 107 | 65ce8c2f | bellard | default: \
|
| 108 | 65ce8c2f | bellard | T0 = 0; \
|
| 109 | 65ce8c2f | bellard | break; \
|
| 110 | 65ce8c2f | bellard | } \ |
| 111 | 65ce8c2f | bellard | env->fsr |= T0; \ |
| 112 | e8af50a3 | bellard | } |
| 113 | e8af50a3 | bellard | |
| 114 | 417454b0 | blueswir1 | GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
| 115 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
| 116 | 417454b0 | blueswir1 | |
| 117 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
| 118 | 417454b0 | blueswir1 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
| 119 | 3475187d | bellard | |
| 120 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
| 121 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
| 122 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
| 123 | 417454b0 | blueswir1 | |
| 124 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
| 125 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
| 126 | 417454b0 | blueswir1 | |
| 127 | 417454b0 | blueswir1 | GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
| 128 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
| 129 | 417454b0 | blueswir1 | |
| 130 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
| 131 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
| 132 | 3475187d | bellard | |
| 133 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
| 134 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
| 135 | 3475187d | bellard | |
| 136 | 417454b0 | blueswir1 | GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
| 137 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
| 138 | 3475187d | bellard | #endif
|
| 139 | 3475187d | bellard | |
| 140 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
| 141 | 81ad8ba2 | blueswir1 | #ifndef CONFIG_USER_ONLY
|
| 142 | a0c4cb4a | bellard | void helper_ld_asi(int asi, int size, int sign) |
| 143 | e8af50a3 | bellard | {
|
| 144 | 83469015 | bellard | uint32_t ret = 0;
|
| 145 | e80cfcfc | bellard | |
| 146 | e80cfcfc | bellard | switch (asi) {
|
| 147 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
| 148 | 6c36d3fa | blueswir1 | break;
|
| 149 | e8af50a3 | bellard | case 3: /* MMU probe */ |
| 150 | 0f8a249a | blueswir1 | {
|
| 151 | 0f8a249a | blueswir1 | int mmulev;
|
| 152 | 0f8a249a | blueswir1 | |
| 153 | 0f8a249a | blueswir1 | mmulev = (T0 >> 8) & 15; |
| 154 | 0f8a249a | blueswir1 | if (mmulev > 4) |
| 155 | 0f8a249a | blueswir1 | ret = 0;
|
| 156 | 0f8a249a | blueswir1 | else {
|
| 157 | 0f8a249a | blueswir1 | ret = mmu_probe(env, T0, mmulev); |
| 158 | 0f8a249a | blueswir1 | //bswap32s(&ret);
|
| 159 | 0f8a249a | blueswir1 | } |
| 160 | e80cfcfc | bellard | #ifdef DEBUG_MMU
|
| 161 | 0f8a249a | blueswir1 | printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
|
| 162 | e80cfcfc | bellard | #endif
|
| 163 | 0f8a249a | blueswir1 | } |
| 164 | 0f8a249a | blueswir1 | break;
|
| 165 | e8af50a3 | bellard | case 4: /* read MMU regs */ |
| 166 | 0f8a249a | blueswir1 | {
|
| 167 | 0f8a249a | blueswir1 | int reg = (T0 >> 8) & 0xf; |
| 168 | 3b46e624 | ths | |
| 169 | 0f8a249a | blueswir1 | ret = env->mmuregs[reg]; |
| 170 | 0f8a249a | blueswir1 | if (reg == 3) /* Fault status cleared on read */ |
| 171 | 0f8a249a | blueswir1 | env->mmuregs[reg] = 0;
|
| 172 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
| 173 | 0f8a249a | blueswir1 | printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
|
| 174 | 55754d9e | bellard | #endif
|
| 175 | 0f8a249a | blueswir1 | } |
| 176 | 0f8a249a | blueswir1 | break;
|
| 177 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access */ |
| 178 | 6c36d3fa | blueswir1 | switch(size) {
|
| 179 | 6c36d3fa | blueswir1 | case 1: |
| 180 | 6c36d3fa | blueswir1 | ret = ldub_code(T0); |
| 181 | 6c36d3fa | blueswir1 | break;
|
| 182 | 6c36d3fa | blueswir1 | case 2: |
| 183 | 6c36d3fa | blueswir1 | ret = lduw_code(T0 & ~1);
|
| 184 | 6c36d3fa | blueswir1 | break;
|
| 185 | 6c36d3fa | blueswir1 | default:
|
| 186 | 6c36d3fa | blueswir1 | case 4: |
| 187 | 6c36d3fa | blueswir1 | ret = ldl_code(T0 & ~3);
|
| 188 | 6c36d3fa | blueswir1 | break;
|
| 189 | 6c36d3fa | blueswir1 | case 8: |
| 190 | 6c36d3fa | blueswir1 | ret = ldl_code(T0 & ~3);
|
| 191 | 6c36d3fa | blueswir1 | T0 = ldl_code((T0 + 4) & ~3); |
| 192 | 6c36d3fa | blueswir1 | break;
|
| 193 | 6c36d3fa | blueswir1 | } |
| 194 | 6c36d3fa | blueswir1 | break;
|
| 195 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
| 196 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 197 | 81ad8ba2 | blueswir1 | case 1: |
| 198 | 81ad8ba2 | blueswir1 | ret = ldub_user(T0); |
| 199 | 81ad8ba2 | blueswir1 | break;
|
| 200 | 81ad8ba2 | blueswir1 | case 2: |
| 201 | 81ad8ba2 | blueswir1 | ret = lduw_user(T0 & ~1);
|
| 202 | 81ad8ba2 | blueswir1 | break;
|
| 203 | 81ad8ba2 | blueswir1 | default:
|
| 204 | 81ad8ba2 | blueswir1 | case 4: |
| 205 | 81ad8ba2 | blueswir1 | ret = ldl_user(T0 & ~3);
|
| 206 | 81ad8ba2 | blueswir1 | break;
|
| 207 | 81ad8ba2 | blueswir1 | case 8: |
| 208 | 81ad8ba2 | blueswir1 | ret = ldl_user(T0 & ~3);
|
| 209 | 81ad8ba2 | blueswir1 | T0 = ldl_user((T0 + 4) & ~3); |
| 210 | 81ad8ba2 | blueswir1 | break;
|
| 211 | 81ad8ba2 | blueswir1 | } |
| 212 | 81ad8ba2 | blueswir1 | break;
|
| 213 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
| 214 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 215 | 81ad8ba2 | blueswir1 | case 1: |
| 216 | 81ad8ba2 | blueswir1 | ret = ldub_kernel(T0); |
| 217 | 81ad8ba2 | blueswir1 | break;
|
| 218 | 81ad8ba2 | blueswir1 | case 2: |
| 219 | 81ad8ba2 | blueswir1 | ret = lduw_kernel(T0 & ~1);
|
| 220 | 81ad8ba2 | blueswir1 | break;
|
| 221 | 81ad8ba2 | blueswir1 | default:
|
| 222 | 81ad8ba2 | blueswir1 | case 4: |
| 223 | 81ad8ba2 | blueswir1 | ret = ldl_kernel(T0 & ~3);
|
| 224 | 81ad8ba2 | blueswir1 | break;
|
| 225 | 81ad8ba2 | blueswir1 | case 8: |
| 226 | 81ad8ba2 | blueswir1 | ret = ldl_kernel(T0 & ~3);
|
| 227 | 81ad8ba2 | blueswir1 | T0 = ldl_kernel((T0 + 4) & ~3); |
| 228 | 81ad8ba2 | blueswir1 | break;
|
| 229 | 81ad8ba2 | blueswir1 | } |
| 230 | 81ad8ba2 | blueswir1 | break;
|
| 231 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
| 232 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
| 233 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
| 234 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
| 235 | 6c36d3fa | blueswir1 | break;
|
| 236 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
| 237 | 02aab46a | bellard | switch(size) {
|
| 238 | 02aab46a | bellard | case 1: |
| 239 | 02aab46a | bellard | ret = ldub_phys(T0); |
| 240 | 02aab46a | bellard | break;
|
| 241 | 02aab46a | bellard | case 2: |
| 242 | 02aab46a | bellard | ret = lduw_phys(T0 & ~1);
|
| 243 | 02aab46a | bellard | break;
|
| 244 | 02aab46a | bellard | default:
|
| 245 | 02aab46a | bellard | case 4: |
| 246 | 02aab46a | bellard | ret = ldl_phys(T0 & ~3);
|
| 247 | 02aab46a | bellard | break;
|
| 248 | 9e61bde5 | bellard | case 8: |
| 249 | 0f8a249a | blueswir1 | ret = ldl_phys(T0 & ~3);
|
| 250 | 0f8a249a | blueswir1 | T0 = ldl_phys((T0 + 4) & ~3); |
| 251 | 0f8a249a | blueswir1 | break;
|
| 252 | 02aab46a | bellard | } |
| 253 | 0f8a249a | blueswir1 | break;
|
| 254 | 5dcb6b91 | blueswir1 | case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
| 255 | 5dcb6b91 | blueswir1 | case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
| 256 | 5dcb6b91 | blueswir1 | switch(size) {
|
| 257 | 5dcb6b91 | blueswir1 | case 1: |
| 258 | 5dcb6b91 | blueswir1 | ret = ldub_phys((target_phys_addr_t)T0 |
| 259 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 260 | 5dcb6b91 | blueswir1 | break;
|
| 261 | 5dcb6b91 | blueswir1 | case 2: |
| 262 | 5dcb6b91 | blueswir1 | ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
|
| 263 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 264 | 5dcb6b91 | blueswir1 | break;
|
| 265 | 5dcb6b91 | blueswir1 | default:
|
| 266 | 5dcb6b91 | blueswir1 | case 4: |
| 267 | 5dcb6b91 | blueswir1 | ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
|
| 268 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 269 | 5dcb6b91 | blueswir1 | break;
|
| 270 | 5dcb6b91 | blueswir1 | case 8: |
| 271 | 5dcb6b91 | blueswir1 | ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
|
| 272 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 273 | 5dcb6b91 | blueswir1 | T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
| 274 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
| 275 | 0f8a249a | blueswir1 | break;
|
| 276 | 5dcb6b91 | blueswir1 | } |
| 277 | 0f8a249a | blueswir1 | break;
|
| 278 | 5dcb6b91 | blueswir1 | case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
| 279 | e8af50a3 | bellard | default:
|
| 280 | 6c36d3fa | blueswir1 | do_unassigned_access(T0, 0, 0, 1); |
| 281 | 0f8a249a | blueswir1 | ret = 0;
|
| 282 | 0f8a249a | blueswir1 | break;
|
| 283 | e8af50a3 | bellard | } |
| 284 | 81ad8ba2 | blueswir1 | if (sign) {
|
| 285 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 286 | 81ad8ba2 | blueswir1 | case 1: |
| 287 | 81ad8ba2 | blueswir1 | T1 = (int8_t) ret; |
| 288 | e32664fb | blueswir1 | break;
|
| 289 | 81ad8ba2 | blueswir1 | case 2: |
| 290 | 81ad8ba2 | blueswir1 | T1 = (int16_t) ret; |
| 291 | e32664fb | blueswir1 | break;
|
| 292 | 81ad8ba2 | blueswir1 | default:
|
| 293 | 81ad8ba2 | blueswir1 | T1 = ret; |
| 294 | 81ad8ba2 | blueswir1 | break;
|
| 295 | 81ad8ba2 | blueswir1 | } |
| 296 | 81ad8ba2 | blueswir1 | } |
| 297 | 81ad8ba2 | blueswir1 | else
|
| 298 | 81ad8ba2 | blueswir1 | T1 = ret; |
| 299 | e8af50a3 | bellard | } |
| 300 | e8af50a3 | bellard | |
| 301 | 81ad8ba2 | blueswir1 | void helper_st_asi(int asi, int size) |
| 302 | e8af50a3 | bellard | {
|
| 303 | e8af50a3 | bellard | switch(asi) {
|
| 304 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
| 305 | 6c36d3fa | blueswir1 | break;
|
| 306 | e8af50a3 | bellard | case 3: /* MMU flush */ |
| 307 | 0f8a249a | blueswir1 | {
|
| 308 | 0f8a249a | blueswir1 | int mmulev;
|
| 309 | e80cfcfc | bellard | |
| 310 | 0f8a249a | blueswir1 | mmulev = (T0 >> 8) & 15; |
| 311 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
| 312 | 0f8a249a | blueswir1 | printf("mmu flush level %d\n", mmulev);
|
| 313 | 55754d9e | bellard | #endif
|
| 314 | 0f8a249a | blueswir1 | switch (mmulev) {
|
| 315 | 0f8a249a | blueswir1 | case 0: // flush page |
| 316 | 0f8a249a | blueswir1 | tlb_flush_page(env, T0 & 0xfffff000);
|
| 317 | 0f8a249a | blueswir1 | break;
|
| 318 | 0f8a249a | blueswir1 | case 1: // flush segment (256k) |
| 319 | 0f8a249a | blueswir1 | case 2: // flush region (16M) |
| 320 | 0f8a249a | blueswir1 | case 3: // flush context (4G) |
| 321 | 0f8a249a | blueswir1 | case 4: // flush entire |
| 322 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
| 323 | 0f8a249a | blueswir1 | break;
|
| 324 | 0f8a249a | blueswir1 | default:
|
| 325 | 0f8a249a | blueswir1 | break;
|
| 326 | 0f8a249a | blueswir1 | } |
| 327 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
| 328 | 0f8a249a | blueswir1 | dump_mmu(env); |
| 329 | 55754d9e | bellard | #endif
|
| 330 | 0f8a249a | blueswir1 | return;
|
| 331 | 0f8a249a | blueswir1 | } |
| 332 | e8af50a3 | bellard | case 4: /* write MMU regs */ |
| 333 | 0f8a249a | blueswir1 | {
|
| 334 | 0f8a249a | blueswir1 | int reg = (T0 >> 8) & 0xf; |
| 335 | 0f8a249a | blueswir1 | uint32_t oldreg; |
| 336 | 3b46e624 | ths | |
| 337 | 0f8a249a | blueswir1 | oldreg = env->mmuregs[reg]; |
| 338 | 55754d9e | bellard | switch(reg) {
|
| 339 | 55754d9e | bellard | case 0: |
| 340 | 40ce0a9a | blueswir1 | env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); |
| 341 | 40ce0a9a | blueswir1 | env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); |
| 342 | 0f8a249a | blueswir1 | // Mappings generated during no-fault mode or MMU
|
| 343 | 0f8a249a | blueswir1 | // disabled mode are invalid in normal mode
|
| 344 | 6f7e9aec | bellard | if (oldreg != env->mmuregs[reg])
|
| 345 | 55754d9e | bellard | tlb_flush(env, 1);
|
| 346 | 55754d9e | bellard | break;
|
| 347 | 55754d9e | bellard | case 2: |
| 348 | 0f8a249a | blueswir1 | env->mmuregs[reg] = T1; |
| 349 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
| 350 | 55754d9e | bellard | /* we flush when the MMU context changes because
|
| 351 | 55754d9e | bellard | QEMU has no MMU context support */
|
| 352 | 55754d9e | bellard | tlb_flush(env, 1);
|
| 353 | 55754d9e | bellard | } |
| 354 | 55754d9e | bellard | break;
|
| 355 | 55754d9e | bellard | case 3: |
| 356 | 55754d9e | bellard | case 4: |
| 357 | 55754d9e | bellard | break;
|
| 358 | 55754d9e | bellard | default:
|
| 359 | 0f8a249a | blueswir1 | env->mmuregs[reg] = T1; |
| 360 | 55754d9e | bellard | break;
|
| 361 | 55754d9e | bellard | } |
| 362 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
| 363 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
| 364 | 55754d9e | bellard | printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
| 365 | 55754d9e | bellard | } |
| 366 | 0f8a249a | blueswir1 | dump_mmu(env); |
| 367 | 55754d9e | bellard | #endif
|
| 368 | 0f8a249a | blueswir1 | return;
|
| 369 | 0f8a249a | blueswir1 | } |
| 370 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
| 371 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 372 | 81ad8ba2 | blueswir1 | case 1: |
| 373 | 81ad8ba2 | blueswir1 | stb_user(T0, T1); |
| 374 | 81ad8ba2 | blueswir1 | break;
|
| 375 | 81ad8ba2 | blueswir1 | case 2: |
| 376 | 81ad8ba2 | blueswir1 | stw_user(T0 & ~1, T1);
|
| 377 | 81ad8ba2 | blueswir1 | break;
|
| 378 | 81ad8ba2 | blueswir1 | default:
|
| 379 | 81ad8ba2 | blueswir1 | case 4: |
| 380 | 81ad8ba2 | blueswir1 | stl_user(T0 & ~3, T1);
|
| 381 | 81ad8ba2 | blueswir1 | break;
|
| 382 | 81ad8ba2 | blueswir1 | case 8: |
| 383 | 81ad8ba2 | blueswir1 | stl_user(T0 & ~3, T1);
|
| 384 | 81ad8ba2 | blueswir1 | stl_user((T0 + 4) & ~3, T2); |
| 385 | 81ad8ba2 | blueswir1 | break;
|
| 386 | 81ad8ba2 | blueswir1 | } |
| 387 | 81ad8ba2 | blueswir1 | break;
|
| 388 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
| 389 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 390 | 81ad8ba2 | blueswir1 | case 1: |
| 391 | 81ad8ba2 | blueswir1 | stb_kernel(T0, T1); |
| 392 | 81ad8ba2 | blueswir1 | break;
|
| 393 | 81ad8ba2 | blueswir1 | case 2: |
| 394 | 81ad8ba2 | blueswir1 | stw_kernel(T0 & ~1, T1);
|
| 395 | 81ad8ba2 | blueswir1 | break;
|
| 396 | 81ad8ba2 | blueswir1 | default:
|
| 397 | 81ad8ba2 | blueswir1 | case 4: |
| 398 | 81ad8ba2 | blueswir1 | stl_kernel(T0 & ~3, T1);
|
| 399 | 81ad8ba2 | blueswir1 | break;
|
| 400 | 81ad8ba2 | blueswir1 | case 8: |
| 401 | 81ad8ba2 | blueswir1 | stl_kernel(T0 & ~3, T1);
|
| 402 | 81ad8ba2 | blueswir1 | stl_kernel((T0 + 4) & ~3, T2); |
| 403 | 81ad8ba2 | blueswir1 | break;
|
| 404 | 81ad8ba2 | blueswir1 | } |
| 405 | 81ad8ba2 | blueswir1 | break;
|
| 406 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
| 407 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
| 408 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
| 409 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
| 410 | 6c36d3fa | blueswir1 | case 0x10: /* I/D-cache flush page */ |
| 411 | 6c36d3fa | blueswir1 | case 0x11: /* I/D-cache flush segment */ |
| 412 | 6c36d3fa | blueswir1 | case 0x12: /* I/D-cache flush region */ |
| 413 | 6c36d3fa | blueswir1 | case 0x13: /* I/D-cache flush context */ |
| 414 | 6c36d3fa | blueswir1 | case 0x14: /* I/D-cache flush user */ |
| 415 | 6c36d3fa | blueswir1 | break;
|
| 416 | e80cfcfc | bellard | case 0x17: /* Block copy, sta access */ |
| 417 | 0f8a249a | blueswir1 | {
|
| 418 | 0f8a249a | blueswir1 | // value (T1) = src
|
| 419 | 0f8a249a | blueswir1 | // address (T0) = dst
|
| 420 | 0f8a249a | blueswir1 | // copy 32 bytes
|
| 421 | 6c36d3fa | blueswir1 | unsigned int i; |
| 422 | 6c36d3fa | blueswir1 | uint32_t src = T1 & ~3, dst = T0 & ~3, temp; |
| 423 | 3b46e624 | ths | |
| 424 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
| 425 | 6c36d3fa | blueswir1 | temp = ldl_kernel(src); |
| 426 | 6c36d3fa | blueswir1 | stl_kernel(dst, temp); |
| 427 | 6c36d3fa | blueswir1 | } |
| 428 | 0f8a249a | blueswir1 | } |
| 429 | 0f8a249a | blueswir1 | return;
|
| 430 | e80cfcfc | bellard | case 0x1f: /* Block fill, stda access */ |
| 431 | 0f8a249a | blueswir1 | {
|
| 432 | 0f8a249a | blueswir1 | // value (T1, T2)
|
| 433 | 0f8a249a | blueswir1 | // address (T0) = dst
|
| 434 | 0f8a249a | blueswir1 | // fill 32 bytes
|
| 435 | 6c36d3fa | blueswir1 | unsigned int i; |
| 436 | 6c36d3fa | blueswir1 | uint32_t dst = T0 & 7;
|
| 437 | 6c36d3fa | blueswir1 | uint64_t val; |
| 438 | e80cfcfc | bellard | |
| 439 | 6c36d3fa | blueswir1 | val = (((uint64_t)T1) << 32) | T2;
|
| 440 | 6c36d3fa | blueswir1 | |
| 441 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 8, dst += 8) |
| 442 | 6c36d3fa | blueswir1 | stq_kernel(dst, val); |
| 443 | 0f8a249a | blueswir1 | } |
| 444 | 0f8a249a | blueswir1 | return;
|
| 445 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
| 446 | 0f8a249a | blueswir1 | {
|
| 447 | 02aab46a | bellard | switch(size) {
|
| 448 | 02aab46a | bellard | case 1: |
| 449 | 02aab46a | bellard | stb_phys(T0, T1); |
| 450 | 02aab46a | bellard | break;
|
| 451 | 02aab46a | bellard | case 2: |
| 452 | 02aab46a | bellard | stw_phys(T0 & ~1, T1);
|
| 453 | 02aab46a | bellard | break;
|
| 454 | 02aab46a | bellard | case 4: |
| 455 | 02aab46a | bellard | default:
|
| 456 | 02aab46a | bellard | stl_phys(T0 & ~3, T1);
|
| 457 | 02aab46a | bellard | break;
|
| 458 | 9e61bde5 | bellard | case 8: |
| 459 | 9e61bde5 | bellard | stl_phys(T0 & ~3, T1);
|
| 460 | 9e61bde5 | bellard | stl_phys((T0 + 4) & ~3, T2); |
| 461 | 9e61bde5 | bellard | break;
|
| 462 | 02aab46a | bellard | } |
| 463 | 0f8a249a | blueswir1 | } |
| 464 | 0f8a249a | blueswir1 | return;
|
| 465 | 5dcb6b91 | blueswir1 | case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
| 466 | 5dcb6b91 | blueswir1 | case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
| 467 | 0f8a249a | blueswir1 | {
|
| 468 | 5dcb6b91 | blueswir1 | switch(size) {
|
| 469 | 5dcb6b91 | blueswir1 | case 1: |
| 470 | 5dcb6b91 | blueswir1 | stb_phys((target_phys_addr_t)T0 |
| 471 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 472 | 5dcb6b91 | blueswir1 | break;
|
| 473 | 5dcb6b91 | blueswir1 | case 2: |
| 474 | 5dcb6b91 | blueswir1 | stw_phys((target_phys_addr_t)(T0 & ~1)
|
| 475 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 476 | 5dcb6b91 | blueswir1 | break;
|
| 477 | 5dcb6b91 | blueswir1 | case 4: |
| 478 | 5dcb6b91 | blueswir1 | default:
|
| 479 | 5dcb6b91 | blueswir1 | stl_phys((target_phys_addr_t)(T0 & ~3)
|
| 480 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 481 | 5dcb6b91 | blueswir1 | break;
|
| 482 | 5dcb6b91 | blueswir1 | case 8: |
| 483 | 5dcb6b91 | blueswir1 | stl_phys((target_phys_addr_t)(T0 & ~3)
|
| 484 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 485 | 5dcb6b91 | blueswir1 | stl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
| 486 | 5dcb6b91 | blueswir1 | | ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
| 487 | 5dcb6b91 | blueswir1 | break;
|
| 488 | 5dcb6b91 | blueswir1 | } |
| 489 | 0f8a249a | blueswir1 | } |
| 490 | 0f8a249a | blueswir1 | return;
|
| 491 | 6c36d3fa | blueswir1 | case 0x31: /* Ross RT620 I-cache flush */ |
| 492 | 6c36d3fa | blueswir1 | case 0x36: /* I-cache flash clear */ |
| 493 | 6c36d3fa | blueswir1 | case 0x37: /* D-cache flash clear */ |
| 494 | 6c36d3fa | blueswir1 | break;
|
| 495 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access, XXX */ |
| 496 | 5dcb6b91 | blueswir1 | case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
| 497 | e8af50a3 | bellard | default:
|
| 498 | 6c36d3fa | blueswir1 | do_unassigned_access(T0, 1, 0, 1); |
| 499 | 0f8a249a | blueswir1 | return;
|
| 500 | e8af50a3 | bellard | } |
| 501 | e8af50a3 | bellard | } |
| 502 | e8af50a3 | bellard | |
| 503 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
| 504 | 81ad8ba2 | blueswir1 | #else /* TARGET_SPARC64 */ |
| 505 | 81ad8ba2 | blueswir1 | |
| 506 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
| 507 | 81ad8ba2 | blueswir1 | void helper_ld_asi(int asi, int size, int sign) |
| 508 | 81ad8ba2 | blueswir1 | {
|
| 509 | 81ad8ba2 | blueswir1 | uint64_t ret = 0;
|
| 510 | 81ad8ba2 | blueswir1 | |
| 511 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
| 512 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
| 513 | 81ad8ba2 | blueswir1 | |
| 514 | 81ad8ba2 | blueswir1 | switch (asi) {
|
| 515 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
| 516 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
| 517 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 518 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
| 519 | 81ad8ba2 | blueswir1 | {
|
| 520 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 521 | 81ad8ba2 | blueswir1 | case 1: |
| 522 | 81ad8ba2 | blueswir1 | ret = ldub_raw(T0); |
| 523 | 81ad8ba2 | blueswir1 | break;
|
| 524 | 81ad8ba2 | blueswir1 | case 2: |
| 525 | 81ad8ba2 | blueswir1 | ret = lduw_raw(T0 & ~1);
|
| 526 | 81ad8ba2 | blueswir1 | break;
|
| 527 | 81ad8ba2 | blueswir1 | case 4: |
| 528 | 81ad8ba2 | blueswir1 | ret = ldl_raw(T0 & ~3);
|
| 529 | 81ad8ba2 | blueswir1 | break;
|
| 530 | 81ad8ba2 | blueswir1 | default:
|
| 531 | 81ad8ba2 | blueswir1 | case 8: |
| 532 | 81ad8ba2 | blueswir1 | ret = ldq_raw(T0 & ~7);
|
| 533 | 81ad8ba2 | blueswir1 | break;
|
| 534 | 81ad8ba2 | blueswir1 | } |
| 535 | 81ad8ba2 | blueswir1 | } |
| 536 | 81ad8ba2 | blueswir1 | break;
|
| 537 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
| 538 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault |
| 539 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 540 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
| 541 | 81ad8ba2 | blueswir1 | // XXX
|
| 542 | 81ad8ba2 | blueswir1 | break;
|
| 543 | 81ad8ba2 | blueswir1 | default:
|
| 544 | 81ad8ba2 | blueswir1 | break;
|
| 545 | 81ad8ba2 | blueswir1 | } |
| 546 | 81ad8ba2 | blueswir1 | |
| 547 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
| 548 | 81ad8ba2 | blueswir1 | switch (asi) {
|
| 549 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 550 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 551 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
| 552 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
| 553 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 554 | 81ad8ba2 | blueswir1 | case 2: |
| 555 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
| 556 | e32664fb | blueswir1 | break;
|
| 557 | 81ad8ba2 | blueswir1 | case 4: |
| 558 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
| 559 | e32664fb | blueswir1 | break;
|
| 560 | 81ad8ba2 | blueswir1 | case 8: |
| 561 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
| 562 | e32664fb | blueswir1 | break;
|
| 563 | 81ad8ba2 | blueswir1 | default:
|
| 564 | 81ad8ba2 | blueswir1 | break;
|
| 565 | 81ad8ba2 | blueswir1 | } |
| 566 | 81ad8ba2 | blueswir1 | default:
|
| 567 | 81ad8ba2 | blueswir1 | break;
|
| 568 | 81ad8ba2 | blueswir1 | } |
| 569 | 81ad8ba2 | blueswir1 | |
| 570 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
| 571 | 81ad8ba2 | blueswir1 | if (sign) {
|
| 572 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 573 | 81ad8ba2 | blueswir1 | case 1: |
| 574 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
| 575 | e32664fb | blueswir1 | break;
|
| 576 | 81ad8ba2 | blueswir1 | case 2: |
| 577 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
| 578 | e32664fb | blueswir1 | break;
|
| 579 | 81ad8ba2 | blueswir1 | case 4: |
| 580 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
| 581 | e32664fb | blueswir1 | break;
|
| 582 | 81ad8ba2 | blueswir1 | default:
|
| 583 | 81ad8ba2 | blueswir1 | break;
|
| 584 | 81ad8ba2 | blueswir1 | } |
| 585 | 81ad8ba2 | blueswir1 | } |
| 586 | 81ad8ba2 | blueswir1 | T1 = ret; |
| 587 | 81ad8ba2 | blueswir1 | } |
| 588 | 81ad8ba2 | blueswir1 | |
| 589 | 81ad8ba2 | blueswir1 | void helper_st_asi(int asi, int size) |
| 590 | 81ad8ba2 | blueswir1 | {
|
| 591 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
| 592 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
| 593 | 81ad8ba2 | blueswir1 | |
| 594 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
| 595 | 81ad8ba2 | blueswir1 | switch (asi) {
|
| 596 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 597 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 598 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 599 | 81ad8ba2 | blueswir1 | case 2: |
| 600 | 81ad8ba2 | blueswir1 | T0 = bswap16(T0); |
| 601 | e32664fb | blueswir1 | break;
|
| 602 | 81ad8ba2 | blueswir1 | case 4: |
| 603 | 81ad8ba2 | blueswir1 | T0 = bswap32(T0); |
| 604 | e32664fb | blueswir1 | break;
|
| 605 | 81ad8ba2 | blueswir1 | case 8: |
| 606 | 81ad8ba2 | blueswir1 | T0 = bswap64(T0); |
| 607 | e32664fb | blueswir1 | break;
|
| 608 | 81ad8ba2 | blueswir1 | default:
|
| 609 | 81ad8ba2 | blueswir1 | break;
|
| 610 | 81ad8ba2 | blueswir1 | } |
| 611 | 81ad8ba2 | blueswir1 | default:
|
| 612 | 81ad8ba2 | blueswir1 | break;
|
| 613 | 81ad8ba2 | blueswir1 | } |
| 614 | 81ad8ba2 | blueswir1 | |
| 615 | 81ad8ba2 | blueswir1 | switch(asi) {
|
| 616 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
| 617 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 618 | 81ad8ba2 | blueswir1 | {
|
| 619 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 620 | 81ad8ba2 | blueswir1 | case 1: |
| 621 | 81ad8ba2 | blueswir1 | stb_raw(T0, T1); |
| 622 | 81ad8ba2 | blueswir1 | break;
|
| 623 | 81ad8ba2 | blueswir1 | case 2: |
| 624 | 81ad8ba2 | blueswir1 | stw_raw(T0 & ~1, T1);
|
| 625 | 81ad8ba2 | blueswir1 | break;
|
| 626 | 81ad8ba2 | blueswir1 | case 4: |
| 627 | 81ad8ba2 | blueswir1 | stl_raw(T0 & ~3, T1);
|
| 628 | 81ad8ba2 | blueswir1 | break;
|
| 629 | 81ad8ba2 | blueswir1 | case 8: |
| 630 | 81ad8ba2 | blueswir1 | default:
|
| 631 | 81ad8ba2 | blueswir1 | stq_raw(T0 & ~7, T1);
|
| 632 | 81ad8ba2 | blueswir1 | break;
|
| 633 | 81ad8ba2 | blueswir1 | } |
| 634 | 81ad8ba2 | blueswir1 | } |
| 635 | 81ad8ba2 | blueswir1 | break;
|
| 636 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
| 637 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 638 | 81ad8ba2 | blueswir1 | // XXX
|
| 639 | 81ad8ba2 | blueswir1 | return;
|
| 640 | 81ad8ba2 | blueswir1 | |
| 641 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault, RO |
| 642 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault, RO |
| 643 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE, RO |
| 644 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE, RO |
| 645 | 81ad8ba2 | blueswir1 | default:
|
| 646 | 81ad8ba2 | blueswir1 | do_unassigned_access(T0, 1, 0, 1); |
| 647 | 81ad8ba2 | blueswir1 | return;
|
| 648 | 81ad8ba2 | blueswir1 | } |
| 649 | 81ad8ba2 | blueswir1 | } |
| 650 | 81ad8ba2 | blueswir1 | |
| 651 | 81ad8ba2 | blueswir1 | #else /* CONFIG_USER_ONLY */ |
| 652 | 3475187d | bellard | |
| 653 | 3475187d | bellard | void helper_ld_asi(int asi, int size, int sign) |
| 654 | 3475187d | bellard | {
|
| 655 | 83469015 | bellard | uint64_t ret = 0;
|
| 656 | 3475187d | bellard | |
| 657 | 3475187d | bellard | if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 658 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
| 659 | 3475187d | bellard | |
| 660 | 3475187d | bellard | switch (asi) {
|
| 661 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
| 662 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
| 663 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
| 664 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
| 665 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 666 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
| 667 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
| 668 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 669 | 81ad8ba2 | blueswir1 | case 1: |
| 670 | 81ad8ba2 | blueswir1 | ret = ldub_kernel(T0); |
| 671 | 81ad8ba2 | blueswir1 | break;
|
| 672 | 81ad8ba2 | blueswir1 | case 2: |
| 673 | 81ad8ba2 | blueswir1 | ret = lduw_kernel(T0 & ~1);
|
| 674 | 81ad8ba2 | blueswir1 | break;
|
| 675 | 81ad8ba2 | blueswir1 | case 4: |
| 676 | 81ad8ba2 | blueswir1 | ret = ldl_kernel(T0 & ~3);
|
| 677 | 81ad8ba2 | blueswir1 | break;
|
| 678 | 81ad8ba2 | blueswir1 | default:
|
| 679 | 81ad8ba2 | blueswir1 | case 8: |
| 680 | 81ad8ba2 | blueswir1 | ret = ldq_kernel(T0 & ~7);
|
| 681 | 81ad8ba2 | blueswir1 | break;
|
| 682 | 81ad8ba2 | blueswir1 | } |
| 683 | 81ad8ba2 | blueswir1 | } else {
|
| 684 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 685 | 81ad8ba2 | blueswir1 | case 1: |
| 686 | 81ad8ba2 | blueswir1 | ret = ldub_user(T0); |
| 687 | 81ad8ba2 | blueswir1 | break;
|
| 688 | 81ad8ba2 | blueswir1 | case 2: |
| 689 | 81ad8ba2 | blueswir1 | ret = lduw_user(T0 & ~1);
|
| 690 | 81ad8ba2 | blueswir1 | break;
|
| 691 | 81ad8ba2 | blueswir1 | case 4: |
| 692 | 81ad8ba2 | blueswir1 | ret = ldl_user(T0 & ~3);
|
| 693 | 81ad8ba2 | blueswir1 | break;
|
| 694 | 81ad8ba2 | blueswir1 | default:
|
| 695 | 81ad8ba2 | blueswir1 | case 8: |
| 696 | 81ad8ba2 | blueswir1 | ret = ldq_user(T0 & ~7);
|
| 697 | 81ad8ba2 | blueswir1 | break;
|
| 698 | 81ad8ba2 | blueswir1 | } |
| 699 | 81ad8ba2 | blueswir1 | } |
| 700 | 81ad8ba2 | blueswir1 | break;
|
| 701 | 3475187d | bellard | case 0x14: // Bypass |
| 702 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
| 703 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
| 704 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
| 705 | 0f8a249a | blueswir1 | {
|
| 706 | 02aab46a | bellard | switch(size) {
|
| 707 | 02aab46a | bellard | case 1: |
| 708 | 02aab46a | bellard | ret = ldub_phys(T0); |
| 709 | 02aab46a | bellard | break;
|
| 710 | 02aab46a | bellard | case 2: |
| 711 | 02aab46a | bellard | ret = lduw_phys(T0 & ~1);
|
| 712 | 02aab46a | bellard | break;
|
| 713 | 02aab46a | bellard | case 4: |
| 714 | 02aab46a | bellard | ret = ldl_phys(T0 & ~3);
|
| 715 | 02aab46a | bellard | break;
|
| 716 | 02aab46a | bellard | default:
|
| 717 | 02aab46a | bellard | case 8: |
| 718 | 02aab46a | bellard | ret = ldq_phys(T0 & ~7);
|
| 719 | 02aab46a | bellard | break;
|
| 720 | 02aab46a | bellard | } |
| 721 | 0f8a249a | blueswir1 | break;
|
| 722 | 0f8a249a | blueswir1 | } |
| 723 | 83469015 | bellard | case 0x04: // Nucleus |
| 724 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
| 725 | 83469015 | bellard | case 0x11: // As if user secondary |
| 726 | 83469015 | bellard | case 0x19: // As if user secondary LE |
| 727 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
| 728 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
| 729 | 83469015 | bellard | case 0x4a: // UPA config |
| 730 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
| 731 | 83469015 | bellard | case 0x83: // Secondary no-fault |
| 732 | 83469015 | bellard | case 0x89: // Secondary LE |
| 733 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE |
| 734 | 0f8a249a | blueswir1 | // XXX
|
| 735 | 0f8a249a | blueswir1 | break;
|
| 736 | 3475187d | bellard | case 0x45: // LSU |
| 737 | 0f8a249a | blueswir1 | ret = env->lsu; |
| 738 | 0f8a249a | blueswir1 | break;
|
| 739 | 3475187d | bellard | case 0x50: // I-MMU regs |
| 740 | 0f8a249a | blueswir1 | {
|
| 741 | 0f8a249a | blueswir1 | int reg = (T0 >> 3) & 0xf; |
| 742 | 3475187d | bellard | |
| 743 | 0f8a249a | blueswir1 | ret = env->immuregs[reg]; |
| 744 | 0f8a249a | blueswir1 | break;
|
| 745 | 0f8a249a | blueswir1 | } |
| 746 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer |
| 747 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer |
| 748 | 3475187d | bellard | case 0x55: // I-MMU data access |
| 749 | 0f8a249a | blueswir1 | // XXX
|
| 750 | 0f8a249a | blueswir1 | break;
|
| 751 | 83469015 | bellard | case 0x56: // I-MMU tag read |
| 752 | 0f8a249a | blueswir1 | {
|
| 753 | 0f8a249a | blueswir1 | unsigned int i; |
| 754 | 0f8a249a | blueswir1 | |
| 755 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 756 | 0f8a249a | blueswir1 | // Valid, ctx match, vaddr match
|
| 757 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
| 758 | 0f8a249a | blueswir1 | env->itlb_tag[i] == T0) {
|
| 759 | 0f8a249a | blueswir1 | ret = env->itlb_tag[i]; |
| 760 | 0f8a249a | blueswir1 | break;
|
| 761 | 0f8a249a | blueswir1 | } |
| 762 | 0f8a249a | blueswir1 | } |
| 763 | 0f8a249a | blueswir1 | break;
|
| 764 | 0f8a249a | blueswir1 | } |
| 765 | 3475187d | bellard | case 0x58: // D-MMU regs |
| 766 | 0f8a249a | blueswir1 | {
|
| 767 | 0f8a249a | blueswir1 | int reg = (T0 >> 3) & 0xf; |
| 768 | 3475187d | bellard | |
| 769 | 0f8a249a | blueswir1 | ret = env->dmmuregs[reg]; |
| 770 | 0f8a249a | blueswir1 | break;
|
| 771 | 0f8a249a | blueswir1 | } |
| 772 | 83469015 | bellard | case 0x5e: // D-MMU tag read |
| 773 | 0f8a249a | blueswir1 | {
|
| 774 | 0f8a249a | blueswir1 | unsigned int i; |
| 775 | 0f8a249a | blueswir1 | |
| 776 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 777 | 0f8a249a | blueswir1 | // Valid, ctx match, vaddr match
|
| 778 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
| 779 | 0f8a249a | blueswir1 | env->dtlb_tag[i] == T0) {
|
| 780 | 0f8a249a | blueswir1 | ret = env->dtlb_tag[i]; |
| 781 | 0f8a249a | blueswir1 | break;
|
| 782 | 0f8a249a | blueswir1 | } |
| 783 | 0f8a249a | blueswir1 | } |
| 784 | 0f8a249a | blueswir1 | break;
|
| 785 | 0f8a249a | blueswir1 | } |
| 786 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer |
| 787 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer |
| 788 | 3475187d | bellard | case 0x5b: // D-MMU data pointer |
| 789 | 3475187d | bellard | case 0x5d: // D-MMU data access |
| 790 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
| 791 | 83469015 | bellard | case 0x49: // Interrupt data receive |
| 792 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
| 793 | 0f8a249a | blueswir1 | // XXX
|
| 794 | 0f8a249a | blueswir1 | break;
|
| 795 | 3475187d | bellard | case 0x54: // I-MMU data in, WO |
| 796 | 3475187d | bellard | case 0x57: // I-MMU demap, WO |
| 797 | 3475187d | bellard | case 0x5c: // D-MMU data in, WO |
| 798 | 3475187d | bellard | case 0x5f: // D-MMU demap, WO |
| 799 | 83469015 | bellard | case 0x77: // Interrupt vector, WO |
| 800 | 3475187d | bellard | default:
|
| 801 | 6c36d3fa | blueswir1 | do_unassigned_access(T0, 0, 0, 1); |
| 802 | 0f8a249a | blueswir1 | ret = 0;
|
| 803 | 0f8a249a | blueswir1 | break;
|
| 804 | 3475187d | bellard | } |
| 805 | 81ad8ba2 | blueswir1 | |
| 806 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
| 807 | 81ad8ba2 | blueswir1 | switch (asi) {
|
| 808 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
| 809 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
| 810 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
| 811 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
| 812 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
| 813 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 814 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 815 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
| 816 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
| 817 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 818 | 81ad8ba2 | blueswir1 | case 2: |
| 819 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
| 820 | e32664fb | blueswir1 | break;
|
| 821 | 81ad8ba2 | blueswir1 | case 4: |
| 822 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
| 823 | e32664fb | blueswir1 | break;
|
| 824 | 81ad8ba2 | blueswir1 | case 8: |
| 825 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
| 826 | e32664fb | blueswir1 | break;
|
| 827 | 81ad8ba2 | blueswir1 | default:
|
| 828 | 81ad8ba2 | blueswir1 | break;
|
| 829 | 81ad8ba2 | blueswir1 | } |
| 830 | 81ad8ba2 | blueswir1 | default:
|
| 831 | 81ad8ba2 | blueswir1 | break;
|
| 832 | 81ad8ba2 | blueswir1 | } |
| 833 | 81ad8ba2 | blueswir1 | |
| 834 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
| 835 | 81ad8ba2 | blueswir1 | if (sign) {
|
| 836 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 837 | 81ad8ba2 | blueswir1 | case 1: |
| 838 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
| 839 | e32664fb | blueswir1 | break;
|
| 840 | 81ad8ba2 | blueswir1 | case 2: |
| 841 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
| 842 | e32664fb | blueswir1 | break;
|
| 843 | 81ad8ba2 | blueswir1 | case 4: |
| 844 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
| 845 | e32664fb | blueswir1 | break;
|
| 846 | 81ad8ba2 | blueswir1 | default:
|
| 847 | 81ad8ba2 | blueswir1 | break;
|
| 848 | 81ad8ba2 | blueswir1 | } |
| 849 | 81ad8ba2 | blueswir1 | } |
| 850 | 3475187d | bellard | T1 = ret; |
| 851 | 3475187d | bellard | } |
| 852 | 3475187d | bellard | |
| 853 | 81ad8ba2 | blueswir1 | void helper_st_asi(int asi, int size) |
| 854 | 3475187d | bellard | {
|
| 855 | 3475187d | bellard | if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 856 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
| 857 | 3475187d | bellard | |
| 858 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
| 859 | 81ad8ba2 | blueswir1 | switch (asi) {
|
| 860 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
| 861 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
| 862 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
| 863 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
| 864 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
| 865 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
| 866 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 867 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
| 868 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 869 | 81ad8ba2 | blueswir1 | case 2: |
| 870 | 81ad8ba2 | blueswir1 | T0 = bswap16(T0); |
| 871 | e32664fb | blueswir1 | break;
|
| 872 | 81ad8ba2 | blueswir1 | case 4: |
| 873 | 81ad8ba2 | blueswir1 | T0 = bswap32(T0); |
| 874 | e32664fb | blueswir1 | break;
|
| 875 | 81ad8ba2 | blueswir1 | case 8: |
| 876 | 81ad8ba2 | blueswir1 | T0 = bswap64(T0); |
| 877 | e32664fb | blueswir1 | break;
|
| 878 | 81ad8ba2 | blueswir1 | default:
|
| 879 | 81ad8ba2 | blueswir1 | break;
|
| 880 | 81ad8ba2 | blueswir1 | } |
| 881 | 81ad8ba2 | blueswir1 | default:
|
| 882 | 81ad8ba2 | blueswir1 | break;
|
| 883 | 81ad8ba2 | blueswir1 | } |
| 884 | 81ad8ba2 | blueswir1 | |
| 885 | 3475187d | bellard | switch(asi) {
|
| 886 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
| 887 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
| 888 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
| 889 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
| 890 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
| 891 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 892 | 81ad8ba2 | blueswir1 | case 1: |
| 893 | 81ad8ba2 | blueswir1 | stb_kernel(T0, T1); |
| 894 | 81ad8ba2 | blueswir1 | break;
|
| 895 | 81ad8ba2 | blueswir1 | case 2: |
| 896 | 81ad8ba2 | blueswir1 | stw_kernel(T0 & ~1, T1);
|
| 897 | 81ad8ba2 | blueswir1 | break;
|
| 898 | 81ad8ba2 | blueswir1 | case 4: |
| 899 | 81ad8ba2 | blueswir1 | stl_kernel(T0 & ~3, T1);
|
| 900 | 81ad8ba2 | blueswir1 | break;
|
| 901 | 81ad8ba2 | blueswir1 | case 8: |
| 902 | 81ad8ba2 | blueswir1 | default:
|
| 903 | 81ad8ba2 | blueswir1 | stq_kernel(T0 & ~7, T1);
|
| 904 | 81ad8ba2 | blueswir1 | break;
|
| 905 | 81ad8ba2 | blueswir1 | } |
| 906 | 81ad8ba2 | blueswir1 | } else {
|
| 907 | 81ad8ba2 | blueswir1 | switch(size) {
|
| 908 | 81ad8ba2 | blueswir1 | case 1: |
| 909 | 81ad8ba2 | blueswir1 | stb_user(T0, T1); |
| 910 | 81ad8ba2 | blueswir1 | break;
|
| 911 | 81ad8ba2 | blueswir1 | case 2: |
| 912 | 81ad8ba2 | blueswir1 | stw_user(T0 & ~1, T1);
|
| 913 | 81ad8ba2 | blueswir1 | break;
|
| 914 | 81ad8ba2 | blueswir1 | case 4: |
| 915 | 81ad8ba2 | blueswir1 | stl_user(T0 & ~3, T1);
|
| 916 | 81ad8ba2 | blueswir1 | break;
|
| 917 | 81ad8ba2 | blueswir1 | case 8: |
| 918 | 81ad8ba2 | blueswir1 | default:
|
| 919 | 81ad8ba2 | blueswir1 | stq_user(T0 & ~7, T1);
|
| 920 | 81ad8ba2 | blueswir1 | break;
|
| 921 | 81ad8ba2 | blueswir1 | } |
| 922 | 81ad8ba2 | blueswir1 | } |
| 923 | 81ad8ba2 | blueswir1 | break;
|
| 924 | 3475187d | bellard | case 0x14: // Bypass |
| 925 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
| 926 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
| 927 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
| 928 | 0f8a249a | blueswir1 | {
|
| 929 | 02aab46a | bellard | switch(size) {
|
| 930 | 02aab46a | bellard | case 1: |
| 931 | 02aab46a | bellard | stb_phys(T0, T1); |
| 932 | 02aab46a | bellard | break;
|
| 933 | 02aab46a | bellard | case 2: |
| 934 | 02aab46a | bellard | stw_phys(T0 & ~1, T1);
|
| 935 | 02aab46a | bellard | break;
|
| 936 | 02aab46a | bellard | case 4: |
| 937 | 02aab46a | bellard | stl_phys(T0 & ~3, T1);
|
| 938 | 02aab46a | bellard | break;
|
| 939 | 02aab46a | bellard | case 8: |
| 940 | 02aab46a | bellard | default:
|
| 941 | 02aab46a | bellard | stq_phys(T0 & ~7, T1);
|
| 942 | 02aab46a | bellard | break;
|
| 943 | 02aab46a | bellard | } |
| 944 | 0f8a249a | blueswir1 | } |
| 945 | 0f8a249a | blueswir1 | return;
|
| 946 | 83469015 | bellard | case 0x04: // Nucleus |
| 947 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
| 948 | 83469015 | bellard | case 0x11: // As if user secondary |
| 949 | 83469015 | bellard | case 0x19: // As if user secondary LE |
| 950 | 83469015 | bellard | case 0x24: // Nucleus quad LDD 128 bit atomic |
| 951 | 83469015 | bellard | case 0x2c: // Nucleus quad LDD 128 bit atomic |
| 952 | 83469015 | bellard | case 0x4a: // UPA config |
| 953 | 83469015 | bellard | case 0x89: // Secondary LE |
| 954 | 0f8a249a | blueswir1 | // XXX
|
| 955 | 0f8a249a | blueswir1 | return;
|
| 956 | 3475187d | bellard | case 0x45: // LSU |
| 957 | 0f8a249a | blueswir1 | {
|
| 958 | 0f8a249a | blueswir1 | uint64_t oldreg; |
| 959 | 0f8a249a | blueswir1 | |
| 960 | 0f8a249a | blueswir1 | oldreg = env->lsu; |
| 961 | 0f8a249a | blueswir1 | env->lsu = T1 & (DMMU_E | IMMU_E); |
| 962 | 0f8a249a | blueswir1 | // Mappings generated during D/I MMU disabled mode are
|
| 963 | 0f8a249a | blueswir1 | // invalid in normal mode
|
| 964 | 0f8a249a | blueswir1 | if (oldreg != env->lsu) {
|
| 965 | 83469015 | bellard | #ifdef DEBUG_MMU
|
| 966 | 26a76461 | bellard | printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
| 967 | 0f8a249a | blueswir1 | dump_mmu(env); |
| 968 | 83469015 | bellard | #endif
|
| 969 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
| 970 | 0f8a249a | blueswir1 | } |
| 971 | 0f8a249a | blueswir1 | return;
|
| 972 | 0f8a249a | blueswir1 | } |
| 973 | 3475187d | bellard | case 0x50: // I-MMU regs |
| 974 | 0f8a249a | blueswir1 | {
|
| 975 | 0f8a249a | blueswir1 | int reg = (T0 >> 3) & 0xf; |
| 976 | 0f8a249a | blueswir1 | uint64_t oldreg; |
| 977 | 3b46e624 | ths | |
| 978 | 0f8a249a | blueswir1 | oldreg = env->immuregs[reg]; |
| 979 | 3475187d | bellard | switch(reg) {
|
| 980 | 3475187d | bellard | case 0: // RO |
| 981 | 3475187d | bellard | case 4: |
| 982 | 3475187d | bellard | return;
|
| 983 | 3475187d | bellard | case 1: // Not in I-MMU |
| 984 | 3475187d | bellard | case 2: |
| 985 | 3475187d | bellard | case 7: |
| 986 | 3475187d | bellard | case 8: |
| 987 | 3475187d | bellard | return;
|
| 988 | 3475187d | bellard | case 3: // SFSR |
| 989 | 0f8a249a | blueswir1 | if ((T1 & 1) == 0) |
| 990 | 0f8a249a | blueswir1 | T1 = 0; // Clear SFSR |
| 991 | 3475187d | bellard | break;
|
| 992 | 3475187d | bellard | case 5: // TSB access |
| 993 | 3475187d | bellard | case 6: // Tag access |
| 994 | 3475187d | bellard | default:
|
| 995 | 3475187d | bellard | break;
|
| 996 | 3475187d | bellard | } |
| 997 | 0f8a249a | blueswir1 | env->immuregs[reg] = T1; |
| 998 | 3475187d | bellard | #ifdef DEBUG_MMU
|
| 999 | 3475187d | bellard | if (oldreg != env->immuregs[reg]) {
|
| 1000 | 26a76461 | bellard | printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
| 1001 | 3475187d | bellard | } |
| 1002 | 0f8a249a | blueswir1 | dump_mmu(env); |
| 1003 | 3475187d | bellard | #endif
|
| 1004 | 0f8a249a | blueswir1 | return;
|
| 1005 | 0f8a249a | blueswir1 | } |
| 1006 | 3475187d | bellard | case 0x54: // I-MMU data in |
| 1007 | 0f8a249a | blueswir1 | {
|
| 1008 | 0f8a249a | blueswir1 | unsigned int i; |
| 1009 | 0f8a249a | blueswir1 | |
| 1010 | 0f8a249a | blueswir1 | // Try finding an invalid entry
|
| 1011 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 1012 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 1013 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
| 1014 | 0f8a249a | blueswir1 | env->itlb_tte[i] = T1; |
| 1015 | 0f8a249a | blueswir1 | return;
|
| 1016 | 0f8a249a | blueswir1 | } |
| 1017 | 0f8a249a | blueswir1 | } |
| 1018 | 0f8a249a | blueswir1 | // Try finding an unlocked entry
|
| 1019 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 1020 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x40) == 0) { |
| 1021 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
| 1022 | 0f8a249a | blueswir1 | env->itlb_tte[i] = T1; |
| 1023 | 0f8a249a | blueswir1 | return;
|
| 1024 | 0f8a249a | blueswir1 | } |
| 1025 | 0f8a249a | blueswir1 | } |
| 1026 | 0f8a249a | blueswir1 | // error state?
|
| 1027 | 0f8a249a | blueswir1 | return;
|
| 1028 | 0f8a249a | blueswir1 | } |
| 1029 | 3475187d | bellard | case 0x55: // I-MMU data access |
| 1030 | 0f8a249a | blueswir1 | {
|
| 1031 | 0f8a249a | blueswir1 | unsigned int i = (T0 >> 3) & 0x3f; |
| 1032 | 3475187d | bellard | |
| 1033 | 0f8a249a | blueswir1 | env->itlb_tag[i] = env->immuregs[6];
|
| 1034 | 0f8a249a | blueswir1 | env->itlb_tte[i] = T1; |
| 1035 | 0f8a249a | blueswir1 | return;
|
| 1036 | 0f8a249a | blueswir1 | } |
| 1037 | 3475187d | bellard | case 0x57: // I-MMU demap |
| 1038 | 0f8a249a | blueswir1 | // XXX
|
| 1039 | 0f8a249a | blueswir1 | return;
|
| 1040 | 3475187d | bellard | case 0x58: // D-MMU regs |
| 1041 | 0f8a249a | blueswir1 | {
|
| 1042 | 0f8a249a | blueswir1 | int reg = (T0 >> 3) & 0xf; |
| 1043 | 0f8a249a | blueswir1 | uint64_t oldreg; |
| 1044 | 3b46e624 | ths | |
| 1045 | 0f8a249a | blueswir1 | oldreg = env->dmmuregs[reg]; |
| 1046 | 3475187d | bellard | switch(reg) {
|
| 1047 | 3475187d | bellard | case 0: // RO |
| 1048 | 3475187d | bellard | case 4: |
| 1049 | 3475187d | bellard | return;
|
| 1050 | 3475187d | bellard | case 3: // SFSR |
| 1051 | 0f8a249a | blueswir1 | if ((T1 & 1) == 0) { |
| 1052 | 0f8a249a | blueswir1 | T1 = 0; // Clear SFSR, Fault address |
| 1053 | 0f8a249a | blueswir1 | env->dmmuregs[4] = 0; |
| 1054 | 0f8a249a | blueswir1 | } |
| 1055 | 0f8a249a | blueswir1 | env->dmmuregs[reg] = T1; |
| 1056 | 3475187d | bellard | break;
|
| 1057 | 3475187d | bellard | case 1: // Primary context |
| 1058 | 3475187d | bellard | case 2: // Secondary context |
| 1059 | 3475187d | bellard | case 5: // TSB access |
| 1060 | 3475187d | bellard | case 6: // Tag access |
| 1061 | 3475187d | bellard | case 7: // Virtual Watchpoint |
| 1062 | 3475187d | bellard | case 8: // Physical Watchpoint |
| 1063 | 3475187d | bellard | default:
|
| 1064 | 3475187d | bellard | break;
|
| 1065 | 3475187d | bellard | } |
| 1066 | 0f8a249a | blueswir1 | env->dmmuregs[reg] = T1; |
| 1067 | 3475187d | bellard | #ifdef DEBUG_MMU
|
| 1068 | 3475187d | bellard | if (oldreg != env->dmmuregs[reg]) {
|
| 1069 | 26a76461 | bellard | printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
| 1070 | 3475187d | bellard | } |
| 1071 | 0f8a249a | blueswir1 | dump_mmu(env); |
| 1072 | 3475187d | bellard | #endif
|
| 1073 | 0f8a249a | blueswir1 | return;
|
| 1074 | 0f8a249a | blueswir1 | } |
| 1075 | 3475187d | bellard | case 0x5c: // D-MMU data in |
| 1076 | 0f8a249a | blueswir1 | {
|
| 1077 | 0f8a249a | blueswir1 | unsigned int i; |
| 1078 | 0f8a249a | blueswir1 | |
| 1079 | 0f8a249a | blueswir1 | // Try finding an invalid entry
|
| 1080 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 1081 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 1082 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1083 | 0f8a249a | blueswir1 | env->dtlb_tte[i] = T1; |
| 1084 | 0f8a249a | blueswir1 | return;
|
| 1085 | 0f8a249a | blueswir1 | } |
| 1086 | 0f8a249a | blueswir1 | } |
| 1087 | 0f8a249a | blueswir1 | // Try finding an unlocked entry
|
| 1088 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
| 1089 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x40) == 0) { |
| 1090 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1091 | 0f8a249a | blueswir1 | env->dtlb_tte[i] = T1; |
| 1092 | 0f8a249a | blueswir1 | return;
|
| 1093 | 0f8a249a | blueswir1 | } |
| 1094 | 0f8a249a | blueswir1 | } |
| 1095 | 0f8a249a | blueswir1 | // error state?
|
| 1096 | 0f8a249a | blueswir1 | return;
|
| 1097 | 0f8a249a | blueswir1 | } |
| 1098 | 3475187d | bellard | case 0x5d: // D-MMU data access |
| 1099 | 0f8a249a | blueswir1 | {
|
| 1100 | 0f8a249a | blueswir1 | unsigned int i = (T0 >> 3) & 0x3f; |
| 1101 | 3475187d | bellard | |
| 1102 | 0f8a249a | blueswir1 | env->dtlb_tag[i] = env->dmmuregs[6];
|
| 1103 | 0f8a249a | blueswir1 | env->dtlb_tte[i] = T1; |
| 1104 | 0f8a249a | blueswir1 | return;
|
| 1105 | 0f8a249a | blueswir1 | } |
| 1106 | 3475187d | bellard | case 0x5f: // D-MMU demap |
| 1107 | 83469015 | bellard | case 0x49: // Interrupt data receive |
| 1108 | 0f8a249a | blueswir1 | // XXX
|
| 1109 | 0f8a249a | blueswir1 | return;
|
| 1110 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer, RO |
| 1111 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer, RO |
| 1112 | 3475187d | bellard | case 0x56: // I-MMU tag read, RO |
| 1113 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer, RO |
| 1114 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer, RO |
| 1115 | 3475187d | bellard | case 0x5b: // D-MMU data pointer, RO |
| 1116 | 3475187d | bellard | case 0x5e: // D-MMU tag read, RO |
| 1117 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
| 1118 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
| 1119 | 83469015 | bellard | case 0x82: // Primary no-fault, RO |
| 1120 | 83469015 | bellard | case 0x83: // Secondary no-fault, RO |
| 1121 | 83469015 | bellard | case 0x8a: // Primary no-fault LE, RO |
| 1122 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE, RO |
| 1123 | 3475187d | bellard | default:
|
| 1124 | 6c36d3fa | blueswir1 | do_unassigned_access(T0, 1, 0, 1); |
| 1125 | 0f8a249a | blueswir1 | return;
|
| 1126 | 3475187d | bellard | } |
| 1127 | 3475187d | bellard | } |
| 1128 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
| 1129 | 81ad8ba2 | blueswir1 | #endif /* TARGET_SPARC64 */ |
| 1130 | 3475187d | bellard | |
| 1131 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
| 1132 | a0c4cb4a | bellard | void helper_rett()
|
| 1133 | e8af50a3 | bellard | {
|
| 1134 | af7bf89b | bellard | unsigned int cwp; |
| 1135 | af7bf89b | bellard | |
| 1136 | d4218d99 | blueswir1 | if (env->psret == 1) |
| 1137 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
| 1138 | d4218d99 | blueswir1 | |
| 1139 | e8af50a3 | bellard | env->psret = 1;
|
| 1140 | 5fafdf24 | ths | cwp = (env->cwp + 1) & (NWINDOWS - 1); |
| 1141 | e8af50a3 | bellard | if (env->wim & (1 << cwp)) { |
| 1142 | e8af50a3 | bellard | raise_exception(TT_WIN_UNF); |
| 1143 | e8af50a3 | bellard | } |
| 1144 | e8af50a3 | bellard | set_cwp(cwp); |
| 1145 | e8af50a3 | bellard | env->psrs = env->psrps; |
| 1146 | e8af50a3 | bellard | } |
| 1147 | 3475187d | bellard | #endif
|
| 1148 | e8af50a3 | bellard | |
| 1149 | 8d5f07fa | bellard | void helper_ldfsr(void) |
| 1150 | e8af50a3 | bellard | {
|
| 1151 | 7a0e1f41 | bellard | int rnd_mode;
|
| 1152 | e8af50a3 | bellard | switch (env->fsr & FSR_RD_MASK) {
|
| 1153 | e8af50a3 | bellard | case FSR_RD_NEAREST:
|
| 1154 | 7a0e1f41 | bellard | rnd_mode = float_round_nearest_even; |
| 1155 | 0f8a249a | blueswir1 | break;
|
| 1156 | ed910241 | bellard | default:
|
| 1157 | e8af50a3 | bellard | case FSR_RD_ZERO:
|
| 1158 | 7a0e1f41 | bellard | rnd_mode = float_round_to_zero; |
| 1159 | 0f8a249a | blueswir1 | break;
|
| 1160 | e8af50a3 | bellard | case FSR_RD_POS:
|
| 1161 | 7a0e1f41 | bellard | rnd_mode = float_round_up; |
| 1162 | 0f8a249a | blueswir1 | break;
|
| 1163 | e8af50a3 | bellard | case FSR_RD_NEG:
|
| 1164 | 7a0e1f41 | bellard | rnd_mode = float_round_down; |
| 1165 | 0f8a249a | blueswir1 | break;
|
| 1166 | e8af50a3 | bellard | } |
| 1167 | 7a0e1f41 | bellard | set_float_rounding_mode(rnd_mode, &env->fp_status); |
| 1168 | e8af50a3 | bellard | } |
| 1169 | e80cfcfc | bellard | |
| 1170 | e80cfcfc | bellard | void helper_debug()
|
| 1171 | e80cfcfc | bellard | {
|
| 1172 | e80cfcfc | bellard | env->exception_index = EXCP_DEBUG; |
| 1173 | e80cfcfc | bellard | cpu_loop_exit(); |
| 1174 | e80cfcfc | bellard | } |
| 1175 | af7bf89b | bellard | |
| 1176 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
| 1177 | af7bf89b | bellard | void do_wrpsr()
|
| 1178 | af7bf89b | bellard | {
|
| 1179 | d4218d99 | blueswir1 | if ((T0 & PSR_CWP) >= NWINDOWS)
|
| 1180 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
| 1181 | d4218d99 | blueswir1 | else
|
| 1182 | d4218d99 | blueswir1 | PUT_PSR(env, T0); |
| 1183 | af7bf89b | bellard | } |
| 1184 | af7bf89b | bellard | |
| 1185 | af7bf89b | bellard | void do_rdpsr()
|
| 1186 | af7bf89b | bellard | {
|
| 1187 | af7bf89b | bellard | T0 = GET_PSR(env); |
| 1188 | af7bf89b | bellard | } |
| 1189 | 3475187d | bellard | |
| 1190 | 3475187d | bellard | #else
|
| 1191 | 3475187d | bellard | |
| 1192 | 3475187d | bellard | void do_popc()
|
| 1193 | 3475187d | bellard | {
|
| 1194 | 3475187d | bellard | T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); |
| 1195 | 3475187d | bellard | T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); |
| 1196 | 3475187d | bellard | T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); |
| 1197 | 3475187d | bellard | T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); |
| 1198 | 3475187d | bellard | T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); |
| 1199 | 3475187d | bellard | T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); |
| 1200 | 3475187d | bellard | } |
| 1201 | 83469015 | bellard | |
| 1202 | 83469015 | bellard | static inline uint64_t *get_gregset(uint64_t pstate) |
| 1203 | 83469015 | bellard | {
|
| 1204 | 83469015 | bellard | switch (pstate) {
|
| 1205 | 83469015 | bellard | default:
|
| 1206 | 83469015 | bellard | case 0: |
| 1207 | 0f8a249a | blueswir1 | return env->bgregs;
|
| 1208 | 83469015 | bellard | case PS_AG:
|
| 1209 | 0f8a249a | blueswir1 | return env->agregs;
|
| 1210 | 83469015 | bellard | case PS_MG:
|
| 1211 | 0f8a249a | blueswir1 | return env->mgregs;
|
| 1212 | 83469015 | bellard | case PS_IG:
|
| 1213 | 0f8a249a | blueswir1 | return env->igregs;
|
| 1214 | 83469015 | bellard | } |
| 1215 | 83469015 | bellard | } |
| 1216 | 83469015 | bellard | |
| 1217 | 8f1f22f6 | blueswir1 | static inline void change_pstate(uint64_t new_pstate) |
| 1218 | 83469015 | bellard | {
|
| 1219 | 8f1f22f6 | blueswir1 | uint64_t pstate_regs, new_pstate_regs; |
| 1220 | 83469015 | bellard | uint64_t *src, *dst; |
| 1221 | 83469015 | bellard | |
| 1222 | 83469015 | bellard | pstate_regs = env->pstate & 0xc01;
|
| 1223 | 83469015 | bellard | new_pstate_regs = new_pstate & 0xc01;
|
| 1224 | 83469015 | bellard | if (new_pstate_regs != pstate_regs) {
|
| 1225 | 0f8a249a | blueswir1 | // Switch global register bank
|
| 1226 | 0f8a249a | blueswir1 | src = get_gregset(new_pstate_regs); |
| 1227 | 0f8a249a | blueswir1 | dst = get_gregset(pstate_regs); |
| 1228 | 0f8a249a | blueswir1 | memcpy32(dst, env->gregs); |
| 1229 | 0f8a249a | blueswir1 | memcpy32(env->gregs, src); |
| 1230 | 83469015 | bellard | } |
| 1231 | 83469015 | bellard | env->pstate = new_pstate; |
| 1232 | 83469015 | bellard | } |
| 1233 | 83469015 | bellard | |
| 1234 | 8f1f22f6 | blueswir1 | void do_wrpstate(void) |
| 1235 | 8f1f22f6 | blueswir1 | {
|
| 1236 | 8f1f22f6 | blueswir1 | change_pstate(T0 & 0xf3f);
|
| 1237 | 8f1f22f6 | blueswir1 | } |
| 1238 | 8f1f22f6 | blueswir1 | |
| 1239 | 83469015 | bellard | void do_done(void) |
| 1240 | 83469015 | bellard | {
|
| 1241 | 83469015 | bellard | env->tl--; |
| 1242 | 83469015 | bellard | env->pc = env->tnpc[env->tl]; |
| 1243 | 83469015 | bellard | env->npc = env->tnpc[env->tl] + 4;
|
| 1244 | 83469015 | bellard | PUT_CCR(env, env->tstate[env->tl] >> 32);
|
| 1245 | 83469015 | bellard | env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
| 1246 | 8f1f22f6 | blueswir1 | change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
| 1247 | 17d996e1 | blueswir1 | PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
| 1248 | 83469015 | bellard | } |
| 1249 | 83469015 | bellard | |
| 1250 | 83469015 | bellard | void do_retry(void) |
| 1251 | 83469015 | bellard | {
|
| 1252 | 83469015 | bellard | env->tl--; |
| 1253 | 83469015 | bellard | env->pc = env->tpc[env->tl]; |
| 1254 | 83469015 | bellard | env->npc = env->tnpc[env->tl]; |
| 1255 | 83469015 | bellard | PUT_CCR(env, env->tstate[env->tl] >> 32);
|
| 1256 | 83469015 | bellard | env->asi = (env->tstate[env->tl] >> 24) & 0xff; |
| 1257 | 8f1f22f6 | blueswir1 | change_pstate((env->tstate[env->tl] >> 8) & 0xf3f); |
| 1258 | 17d996e1 | blueswir1 | PUT_CWP64(env, env->tstate[env->tl] & 0xff);
|
| 1259 | 83469015 | bellard | } |
| 1260 | 3475187d | bellard | #endif
|
| 1261 | ee5bbe38 | bellard | |
| 1262 | ee5bbe38 | bellard | void set_cwp(int new_cwp) |
| 1263 | ee5bbe38 | bellard | {
|
| 1264 | ee5bbe38 | bellard | /* put the modified wrap registers at their proper location */
|
| 1265 | ee5bbe38 | bellard | if (env->cwp == (NWINDOWS - 1)) |
| 1266 | ee5bbe38 | bellard | memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
| 1267 | ee5bbe38 | bellard | env->cwp = new_cwp; |
| 1268 | ee5bbe38 | bellard | /* put the wrap registers at their temporary location */
|
| 1269 | ee5bbe38 | bellard | if (new_cwp == (NWINDOWS - 1)) |
| 1270 | ee5bbe38 | bellard | memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
| 1271 | ee5bbe38 | bellard | env->regwptr = env->regbase + (new_cwp * 16);
|
| 1272 | ee5bbe38 | bellard | REGWPTR = env->regwptr; |
| 1273 | ee5bbe38 | bellard | } |
| 1274 | ee5bbe38 | bellard | |
| 1275 | ee5bbe38 | bellard | void cpu_set_cwp(CPUState *env1, int new_cwp) |
| 1276 | ee5bbe38 | bellard | {
|
| 1277 | ee5bbe38 | bellard | CPUState *saved_env; |
| 1278 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
| 1279 | ee5bbe38 | bellard | target_ulong *saved_regwptr; |
| 1280 | ee5bbe38 | bellard | #endif
|
| 1281 | ee5bbe38 | bellard | |
| 1282 | ee5bbe38 | bellard | saved_env = env; |
| 1283 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
| 1284 | ee5bbe38 | bellard | saved_regwptr = REGWPTR; |
| 1285 | ee5bbe38 | bellard | #endif
|
| 1286 | ee5bbe38 | bellard | env = env1; |
| 1287 | ee5bbe38 | bellard | set_cwp(new_cwp); |
| 1288 | ee5bbe38 | bellard | env = saved_env; |
| 1289 | ee5bbe38 | bellard | #ifdef reg_REGWPTR
|
| 1290 | ee5bbe38 | bellard | REGWPTR = saved_regwptr; |
| 1291 | ee5bbe38 | bellard | #endif
|
| 1292 | ee5bbe38 | bellard | } |
| 1293 | ee5bbe38 | bellard | |
| 1294 | ee5bbe38 | bellard | #ifdef TARGET_SPARC64
|
| 1295 | ee5bbe38 | bellard | void do_interrupt(int intno) |
| 1296 | ee5bbe38 | bellard | {
|
| 1297 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
| 1298 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
| 1299 | 0f8a249a | blueswir1 | static int count; |
| 1300 | 0f8a249a | blueswir1 | fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n", |
| 1301 | ee5bbe38 | bellard | count, intno, |
| 1302 | ee5bbe38 | bellard | env->pc, |
| 1303 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
| 1304 | 0f8a249a | blueswir1 | cpu_dump_state(env, logfile, fprintf, 0);
|
| 1305 | ee5bbe38 | bellard | #if 0
|
| 1306 | 0f8a249a | blueswir1 | {
|
| 1307 | 0f8a249a | blueswir1 | int i;
|
| 1308 | 0f8a249a | blueswir1 | uint8_t *ptr;
|
| 1309 | 0f8a249a | blueswir1 | |
| 1310 | 0f8a249a | blueswir1 | fprintf(logfile, " code=");
|
| 1311 | 0f8a249a | blueswir1 | ptr = (uint8_t *)env->pc;
|
| 1312 | 0f8a249a | blueswir1 | for(i = 0; i < 16; i++) {
|
| 1313 | 0f8a249a | blueswir1 | fprintf(logfile, " %02x", ldub(ptr + i));
|
| 1314 | 0f8a249a | blueswir1 | }
|
| 1315 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
| 1316 | 0f8a249a | blueswir1 | }
|
| 1317 | ee5bbe38 | bellard | #endif
|
| 1318 | 0f8a249a | blueswir1 | count++; |
| 1319 | ee5bbe38 | bellard | } |
| 1320 | ee5bbe38 | bellard | #endif
|
| 1321 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
| 1322 | 83469015 | bellard | if (env->tl == MAXTL) {
|
| 1323 | c68ea704 | bellard | cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
| 1324 | 0f8a249a | blueswir1 | return;
|
| 1325 | ee5bbe38 | bellard | } |
| 1326 | ee5bbe38 | bellard | #endif
|
| 1327 | ee5bbe38 | bellard | env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
| 1328 | 0f8a249a | blueswir1 | ((env->pstate & 0xf3f) << 8) | GET_CWP64(env); |
| 1329 | ee5bbe38 | bellard | env->tpc[env->tl] = env->pc; |
| 1330 | ee5bbe38 | bellard | env->tnpc[env->tl] = env->npc; |
| 1331 | ee5bbe38 | bellard | env->tt[env->tl] = intno; |
| 1332 | 8f1f22f6 | blueswir1 | change_pstate(PS_PEF | PS_PRIV | PS_AG); |
| 1333 | 8f1f22f6 | blueswir1 | |
| 1334 | 8f1f22f6 | blueswir1 | if (intno == TT_CLRWIN)
|
| 1335 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
| 1336 | 8f1f22f6 | blueswir1 | else if ((intno & 0x1c0) == TT_SPILL) |
| 1337 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
| 1338 | 8f1f22f6 | blueswir1 | else if ((intno & 0x1c0) == TT_FILL) |
| 1339 | 8f1f22f6 | blueswir1 | set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
| 1340 | 83469015 | bellard | env->tbr &= ~0x7fffULL;
|
| 1341 | 83469015 | bellard | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
| 1342 | 83469015 | bellard | if (env->tl < MAXTL - 1) { |
| 1343 | 0f8a249a | blueswir1 | env->tl++; |
| 1344 | 83469015 | bellard | } else {
|
| 1345 | 0f8a249a | blueswir1 | env->pstate |= PS_RED; |
| 1346 | 0f8a249a | blueswir1 | if (env->tl != MAXTL)
|
| 1347 | 0f8a249a | blueswir1 | env->tl++; |
| 1348 | 83469015 | bellard | } |
| 1349 | ee5bbe38 | bellard | env->pc = env->tbr; |
| 1350 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
| 1351 | ee5bbe38 | bellard | env->exception_index = 0;
|
| 1352 | ee5bbe38 | bellard | } |
| 1353 | ee5bbe38 | bellard | #else
|
| 1354 | ee5bbe38 | bellard | void do_interrupt(int intno) |
| 1355 | ee5bbe38 | bellard | {
|
| 1356 | ee5bbe38 | bellard | int cwp;
|
| 1357 | ee5bbe38 | bellard | |
| 1358 | ee5bbe38 | bellard | #ifdef DEBUG_PCALL
|
| 1359 | ee5bbe38 | bellard | if (loglevel & CPU_LOG_INT) {
|
| 1360 | 0f8a249a | blueswir1 | static int count; |
| 1361 | 0f8a249a | blueswir1 | fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
| 1362 | ee5bbe38 | bellard | count, intno, |
| 1363 | ee5bbe38 | bellard | env->pc, |
| 1364 | ee5bbe38 | bellard | env->npc, env->regwptr[6]);
|
| 1365 | 0f8a249a | blueswir1 | cpu_dump_state(env, logfile, fprintf, 0);
|
| 1366 | ee5bbe38 | bellard | #if 0
|
| 1367 | 0f8a249a | blueswir1 | {
|
| 1368 | 0f8a249a | blueswir1 | int i;
|
| 1369 | 0f8a249a | blueswir1 | uint8_t *ptr;
|
| 1370 | 0f8a249a | blueswir1 | |
| 1371 | 0f8a249a | blueswir1 | fprintf(logfile, " code=");
|
| 1372 | 0f8a249a | blueswir1 | ptr = (uint8_t *)env->pc;
|
| 1373 | 0f8a249a | blueswir1 | for(i = 0; i < 16; i++) {
|
| 1374 | 0f8a249a | blueswir1 | fprintf(logfile, " %02x", ldub(ptr + i));
|
| 1375 | 0f8a249a | blueswir1 | }
|
| 1376 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
| 1377 | 0f8a249a | blueswir1 | }
|
| 1378 | ee5bbe38 | bellard | #endif
|
| 1379 | 0f8a249a | blueswir1 | count++; |
| 1380 | ee5bbe38 | bellard | } |
| 1381 | ee5bbe38 | bellard | #endif
|
| 1382 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
| 1383 | ee5bbe38 | bellard | if (env->psret == 0) { |
| 1384 | c68ea704 | bellard | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
| 1385 | 0f8a249a | blueswir1 | return;
|
| 1386 | ee5bbe38 | bellard | } |
| 1387 | ee5bbe38 | bellard | #endif
|
| 1388 | ee5bbe38 | bellard | env->psret = 0;
|
| 1389 | 5fafdf24 | ths | cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 1390 | ee5bbe38 | bellard | set_cwp(cwp); |
| 1391 | ee5bbe38 | bellard | env->regwptr[9] = env->pc;
|
| 1392 | ee5bbe38 | bellard | env->regwptr[10] = env->npc;
|
| 1393 | ee5bbe38 | bellard | env->psrps = env->psrs; |
| 1394 | ee5bbe38 | bellard | env->psrs = 1;
|
| 1395 | ee5bbe38 | bellard | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
| 1396 | ee5bbe38 | bellard | env->pc = env->tbr; |
| 1397 | ee5bbe38 | bellard | env->npc = env->pc + 4;
|
| 1398 | ee5bbe38 | bellard | env->exception_index = 0;
|
| 1399 | ee5bbe38 | bellard | } |
| 1400 | ee5bbe38 | bellard | #endif
|
| 1401 | ee5bbe38 | bellard | |
| 1402 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
| 1403 | ee5bbe38 | bellard | |
| 1404 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
| 1405 | d2889a3e | blueswir1 | void *retaddr);
|
| 1406 | d2889a3e | blueswir1 | |
| 1407 | ee5bbe38 | bellard | #define MMUSUFFIX _mmu
|
| 1408 | d2889a3e | blueswir1 | #define ALIGNED_ONLY
|
| 1409 | ee5bbe38 | bellard | #define GETPC() (__builtin_return_address(0)) |
| 1410 | ee5bbe38 | bellard | |
| 1411 | ee5bbe38 | bellard | #define SHIFT 0 |
| 1412 | ee5bbe38 | bellard | #include "softmmu_template.h" |
| 1413 | ee5bbe38 | bellard | |
| 1414 | ee5bbe38 | bellard | #define SHIFT 1 |
| 1415 | ee5bbe38 | bellard | #include "softmmu_template.h" |
| 1416 | ee5bbe38 | bellard | |
| 1417 | ee5bbe38 | bellard | #define SHIFT 2 |
| 1418 | ee5bbe38 | bellard | #include "softmmu_template.h" |
| 1419 | ee5bbe38 | bellard | |
| 1420 | ee5bbe38 | bellard | #define SHIFT 3 |
| 1421 | ee5bbe38 | bellard | #include "softmmu_template.h" |
| 1422 | ee5bbe38 | bellard | |
| 1423 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
| 1424 | d2889a3e | blueswir1 | void *retaddr)
|
| 1425 | d2889a3e | blueswir1 | {
|
| 1426 | 94554550 | blueswir1 | #ifdef DEBUG_UNALIGNED
|
| 1427 | 94554550 | blueswir1 | printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
|
| 1428 | 94554550 | blueswir1 | #endif
|
| 1429 | 94554550 | blueswir1 | raise_exception(TT_UNALIGNED); |
| 1430 | d2889a3e | blueswir1 | } |
| 1431 | ee5bbe38 | bellard | |
| 1432 | ee5bbe38 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
| 1433 | ee5bbe38 | bellard | NULL, it means that the function was called in C code (i.e. not
|
| 1434 | ee5bbe38 | bellard | from generated code or from helper.c) */
|
| 1435 | ee5bbe38 | bellard | /* XXX: fix it to restore all registers */
|
| 1436 | ee5bbe38 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
| 1437 | ee5bbe38 | bellard | {
|
| 1438 | ee5bbe38 | bellard | TranslationBlock *tb; |
| 1439 | ee5bbe38 | bellard | int ret;
|
| 1440 | ee5bbe38 | bellard | unsigned long pc; |
| 1441 | ee5bbe38 | bellard | CPUState *saved_env; |
| 1442 | ee5bbe38 | bellard | |
| 1443 | ee5bbe38 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
| 1444 | ee5bbe38 | bellard | generated code */
|
| 1445 | ee5bbe38 | bellard | saved_env = env; |
| 1446 | ee5bbe38 | bellard | env = cpu_single_env; |
| 1447 | ee5bbe38 | bellard | |
| 1448 | ee5bbe38 | bellard | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
| 1449 | ee5bbe38 | bellard | if (ret) {
|
| 1450 | ee5bbe38 | bellard | if (retaddr) {
|
| 1451 | ee5bbe38 | bellard | /* now we have a real cpu fault */
|
| 1452 | ee5bbe38 | bellard | pc = (unsigned long)retaddr; |
| 1453 | ee5bbe38 | bellard | tb = tb_find_pc(pc); |
| 1454 | ee5bbe38 | bellard | if (tb) {
|
| 1455 | ee5bbe38 | bellard | /* the PC is inside the translated code. It means that we have
|
| 1456 | ee5bbe38 | bellard | a virtual CPU fault */
|
| 1457 | ee5bbe38 | bellard | cpu_restore_state(tb, env, pc, (void *)T2);
|
| 1458 | ee5bbe38 | bellard | } |
| 1459 | ee5bbe38 | bellard | } |
| 1460 | ee5bbe38 | bellard | cpu_loop_exit(); |
| 1461 | ee5bbe38 | bellard | } |
| 1462 | ee5bbe38 | bellard | env = saved_env; |
| 1463 | ee5bbe38 | bellard | } |
| 1464 | ee5bbe38 | bellard | |
| 1465 | ee5bbe38 | bellard | #endif
|
| 1466 | 6c36d3fa | blueswir1 | |
| 1467 | 6c36d3fa | blueswir1 | #ifndef TARGET_SPARC64
|
| 1468 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
| 1469 | 6c36d3fa | blueswir1 | int is_asi)
|
| 1470 | 6c36d3fa | blueswir1 | {
|
| 1471 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
| 1472 | 6c36d3fa | blueswir1 | |
| 1473 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
| 1474 | 6c36d3fa | blueswir1 | generated code */
|
| 1475 | 6c36d3fa | blueswir1 | saved_env = env; |
| 1476 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
| 1477 | 6c36d3fa | blueswir1 | if (env->mmuregs[3]) /* Fault status register */ |
| 1478 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
| 1479 | 6c36d3fa | blueswir1 | if (is_asi)
|
| 1480 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 16; |
| 1481 | 6c36d3fa | blueswir1 | if (env->psrs)
|
| 1482 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 5; |
| 1483 | 6c36d3fa | blueswir1 | if (is_exec)
|
| 1484 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 6; |
| 1485 | 6c36d3fa | blueswir1 | if (is_write)
|
| 1486 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= 1 << 7; |
| 1487 | 6c36d3fa | blueswir1 | env->mmuregs[3] |= (5 << 2) | 2; |
| 1488 | 6c36d3fa | blueswir1 | env->mmuregs[4] = addr; /* Fault address register */ |
| 1489 | 6c36d3fa | blueswir1 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
| 1490 | 6c36d3fa | blueswir1 | #ifdef DEBUG_UNASSIGNED
|
| 1491 | 5dcb6b91 | blueswir1 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
| 1492 | 6c36d3fa | blueswir1 | "\n", addr, env->pc);
|
| 1493 | 6c36d3fa | blueswir1 | #endif
|
| 1494 | 1b2e93c1 | blueswir1 | if (is_exec)
|
| 1495 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
| 1496 | 1b2e93c1 | blueswir1 | else
|
| 1497 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
| 1498 | 6c36d3fa | blueswir1 | } |
| 1499 | 6c36d3fa | blueswir1 | env = saved_env; |
| 1500 | 6c36d3fa | blueswir1 | } |
| 1501 | 6c36d3fa | blueswir1 | #else
|
| 1502 | 5dcb6b91 | blueswir1 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
| 1503 | 6c36d3fa | blueswir1 | int is_asi)
|
| 1504 | 6c36d3fa | blueswir1 | {
|
| 1505 | 6c36d3fa | blueswir1 | #ifdef DEBUG_UNASSIGNED
|
| 1506 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
| 1507 | 6c36d3fa | blueswir1 | |
| 1508 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
| 1509 | 6c36d3fa | blueswir1 | generated code */
|
| 1510 | 6c36d3fa | blueswir1 | saved_env = env; |
| 1511 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
| 1512 | 5dcb6b91 | blueswir1 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
| 1513 | 6c36d3fa | blueswir1 | addr, env->pc); |
| 1514 | 6c36d3fa | blueswir1 | env = saved_env; |
| 1515 | 6c36d3fa | blueswir1 | #endif
|
| 1516 | 1b2e93c1 | blueswir1 | if (is_exec)
|
| 1517 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
| 1518 | 1b2e93c1 | blueswir1 | else
|
| 1519 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
| 1520 | 6c36d3fa | blueswir1 | } |
| 1521 | 6c36d3fa | blueswir1 | #endif
|
| 1522 | 20c9f095 | blueswir1 | |
| 1523 | 20c9f095 | blueswir1 | #ifdef TARGET_SPARC64
|
| 1524 | 20c9f095 | blueswir1 | void do_tick_set_count(void *opaque, uint64_t count) |
| 1525 | 20c9f095 | blueswir1 | {
|
| 1526 | d8bdf5fa | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
| 1527 | 20c9f095 | blueswir1 | ptimer_set_count(opaque, -count); |
| 1528 | d8bdf5fa | blueswir1 | #endif
|
| 1529 | 20c9f095 | blueswir1 | } |
| 1530 | 20c9f095 | blueswir1 | |
| 1531 | 20c9f095 | blueswir1 | uint64_t do_tick_get_count(void *opaque)
|
| 1532 | 20c9f095 | blueswir1 | {
|
| 1533 | d8bdf5fa | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
| 1534 | 20c9f095 | blueswir1 | return -ptimer_get_count(opaque);
|
| 1535 | d8bdf5fa | blueswir1 | #else
|
| 1536 | d8bdf5fa | blueswir1 | return 0; |
| 1537 | d8bdf5fa | blueswir1 | #endif
|
| 1538 | 20c9f095 | blueswir1 | } |
| 1539 | 20c9f095 | blueswir1 | |
| 1540 | 20c9f095 | blueswir1 | void do_tick_set_limit(void *opaque, uint64_t limit) |
| 1541 | 20c9f095 | blueswir1 | {
|
| 1542 | d8bdf5fa | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
| 1543 | 20c9f095 | blueswir1 | ptimer_set_limit(opaque, -limit, 0);
|
| 1544 | d8bdf5fa | blueswir1 | #endif
|
| 1545 | 20c9f095 | blueswir1 | } |
| 1546 | 20c9f095 | blueswir1 | #endif |