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# Date Author Comment
ee0dc6d3 02/14/2010 09:23 am Blue Swirl

Fix incorrect exception_index use

env->exception_index should be cleared with -1, not 0.

See also 821b19fe923ac49a24cdb4af902584fdd019cee6.

Spotted by Igor Kovalenko.

Signed-off-by: Blue Swirl <>

5a25cc2b 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: separate execute and read/write permissions

On SH4, the ITLB and UTLB configurations are memory mapped, so loading
ITLB entries from UTLB has to be simulated correctly. For that the QEMU
TLB has to be handle the execute (ITLB) and read/write permissions...

0f3f1ec7 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: simplify call to tlb_set_page()

tlb_set_page() doesn't need addresses with offset, but simply the
page aligned addresses.

Signed-off-by: Aurelien Jarno <>

4d1e4ff6 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix ITLB priviledge check

There is an ITLB access violation if SR_MD=0 (user mode) while
the high bit of the protection key is 0 (priviledge mode).

Signed-off-by: Aurelien Jarno <>

628b61a0 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: optimize UTLB accesses

With the current code, the QEMU TLB is setup to match the read/write
mode of the MMU fault. This means when read access is done, the page
is setup in read-only mode. When the page is later accessed in write
mode, an MMU fault happened, and the page is switch in write-only...

55ff33a4 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: remove dead code

Signed-off-by: Aurelien Jarno <>

03e3b61e 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix store queue addresses

The store queues are located from 0xe0000000 to 0xe3ffffff.

Signed-off-by: Aurelien Jarno <>

e0bcb9ca 02/09/2010 10:07 pm Aurelien Jarno

sh7750: handle MMUCR TI bit

When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.

Signed-off-by: Aurelien Jarno <>

c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

55616505 05/13/2009 10:54 pm Paul Brook

Include assert.h from qemu-common.h

Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <>

679dee3c 04/03/2009 10:33 am edgar_igl

SH: Fix linux-user _is_cached typo.

Signed-off-by: Edgar E. Iglesias <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6970 c046a42c-6fe2-441c-8c8c-71466251a162

3c1adf12 04/03/2009 10:29 am edgar_igl

SH: Add cpu_sh4_is_cached for linux-user.

The entire U0 area is assumed to be cacheable.

Signed-off-by: Edgar E. Iglesias <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6969 c046a42c-6fe2-441c-8c8c-71466251a162

852d481f 04/02/2009 02:10 am edgar_igl

SH: Improve movca.l/ocbi emulation.

Author: Vladimir Prus <>

Fix movcal.l/ocbi emulation.
  • target-sh4/cpu.h (memory_content): New.
    (CPUSH4State): New fields movcal_backup and movcal_backup_tail.
  • target-sh4/helper.h (helper_movcal)...
927e3a4e 03/03/2009 11:14 am aurel32

SH4: Fixed last UTLB unused and URB/URC management

Signed-off-by: Lionel Landwerlin <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6675 c046a42c-6fe2-441c-8c8c-71466251a162

45f4d016 03/03/2009 08:14 am aurel32

SH4: Fixed last UTLB unused

Version 2 of the patch.

Signed-off-by: Lionel Landwerlin <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6672 c046a42c-6fe2-441c-8c8c-71466251a162

fb104582 03/03/2009 08:12 am aurel32

SH4: Fixed last UTLB unused

With my previous patch (the one monitoring tlb), I found that the last
TLB entry was never use. Here a little fix.

Signed-off-by: Lionel Landwerlin <>
Signed-off-by: Aurelien Jarno <>...

ef7ec1c1 03/03/2009 08:12 am aurel32

clean build: Fix remaining sh4 warnings

Signed-off-by: Jan Kiszka <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6668 c046a42c-6fe2-441c-8c8c-71466251a162

8fec2b8c 01/16/2009 12:36 am aliguori

global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)

These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

eeda6778 12/10/2008 07:31 pm aurel32

target-sh4: Add SH bit handling to TLB

This patch adds SH bit handling to sh4's TLB, which is a part of MMU
functionality that had not been implemented in qemu.

Additionally, increment_urc() call in cpu_load_tlb() is deleted, because
the specification explicitly says that URC is not incremented by an LDTLB...

5c16736a 12/07/2008 09:39 pm balrog

SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).

Main purpose of this is to delete
*physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers....

1e5459a3 12/07/2008 09:08 pm balrog

SH: On-chip PCI controller support (Takashi YOSHII).

This patch adds SuperH on-chip PCI controller(PCIC) support.

Signed-off-by: Takashi YOSHII <>
Signed-off-by: Andrzej Zaborowski <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162

cf7055bd 11/22/2008 12:33 am aurel32

target-sh4: fix TLB/MMU emulation

Based on a patch from Vladimir Prus and comments from Shin-ichiro KAWASAKI.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5770 c046a42c-6fe2-441c-8c8c-71466251a162

06afe2c8 08/22/2008 11:57 am aurel32

[sh4] MMU bug fix

Some bugs on SH4 MMU are fixed.

- When a TLB entry is overwritten or invalidated, tlb_flush_page() should be
invoked to invalidate old entry.
- When a ASID is changed, tlb_flush() should be invoke to invalidate entries
which have old ASID....

29e179bc 08/22/2008 11:57 am aurel32

[sh4] memory mapped TLB entries

SH4 MMU's memory mapped TLB feature is implemented.
SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry,
but does not to read it. So only memory write feature is implemented.
Work on memory read feature is left....

274a9e70 08/22/2008 11:57 am aurel32

[sh4] delay slot bug fix

Two bugs about delay slot handlings are fixed.

- After an exception occurred in delay slot, the branch instruction
before delay slot should be executed again. To judge such re-execution
is necessery or not, delay slot status is kept in SH4 CPU data structure....

833ed386 08/22/2008 11:57 am aurel32

[sh4] sleep instruction

This patch adds sleep instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162

ea2b542a 05/09/2008 09:45 pm aurel32

SH4 MMU improvements

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162

c3b5bc8a 12/02/2007 08:31 am ths

SH4: Signal handling for the user space emulator, by Magnus Damm.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3764 c046a42c-6fe2-441c-8c8c-71466251a162

e96e2044 12/02/2007 08:18 am ths

SH4: system emulator interrupt update, by Magnus Damm.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3762 c046a42c-6fe2-441c-8c8c-71466251a162

6ebbf390 10/14/2007 10:07 am j_mayer

Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions....

5fafdf24 09/17/2007 12:08 am ths

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162

9b3c35e0 04/07/2007 02:21 pm j_mayer

cpu_get_phys_page_debug should return target_phys_addr_t
instead of target_ulong to be consistent.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2633 c046a42c-6fe2-441c-8c8c-71466251a162

355fb23d 06/17/2006 10:58 pm pbrook

SH usermode fault handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1988 c046a42c-6fe2-441c-8c8c-71466251a162

fdf9b3e8 04/28/2006 12:07 am bellard

sh4 target (Samuel Tardieu)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162