root / target-alpha / helper.c @ ee0dc6d3
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/*
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* Alpha emulation cpu helpers for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "softfloat.h" |
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uint64_t cpu_alpha_load_fpcr (CPUState *env) |
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{
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uint64_t ret = 0;
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int flags, mask;
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flags = env->fp_status.float_exception_flags; |
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ret |= (uint64_t) flags << 52;
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if (flags)
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ret |= FPCR_SUM; |
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env->ipr[IPR_EXC_SUM] &= ~0x3E;
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env->ipr[IPR_EXC_SUM] |= flags << 1;
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mask = env->fp_status.float_exception_mask; |
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if (mask & float_flag_invalid)
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ret |= FPCR_INVD; |
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if (mask & float_flag_divbyzero)
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ret |= FPCR_DZED; |
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if (mask & float_flag_overflow)
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ret |= FPCR_OVFD; |
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if (mask & float_flag_underflow)
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ret |= FPCR_UNFD; |
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if (mask & float_flag_inexact)
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ret |= FPCR_INED; |
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switch (env->fp_status.float_rounding_mode) {
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case float_round_nearest_even:
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ret |= 2ULL << FPCR_DYN_SHIFT;
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break;
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case float_round_down:
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ret |= 1ULL << FPCR_DYN_SHIFT;
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break;
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case float_round_up:
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ret |= 3ULL << FPCR_DYN_SHIFT;
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break;
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case float_round_to_zero:
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break;
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} |
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return ret;
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} |
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void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
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{
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int round_mode, mask;
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set_float_exception_flags((val >> 52) & 0x3F, &env->fp_status); |
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mask = 0;
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if (val & FPCR_INVD)
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mask |= float_flag_invalid; |
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if (val & FPCR_DZED)
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mask |= float_flag_divbyzero; |
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if (val & FPCR_OVFD)
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mask |= float_flag_overflow; |
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if (val & FPCR_UNFD)
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mask |= float_flag_underflow; |
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if (val & FPCR_INED)
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mask |= float_flag_inexact; |
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env->fp_status.float_exception_mask = mask; |
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switch ((val >> FPCR_DYN_SHIFT) & 3) { |
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case 0: |
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round_mode = float_round_to_zero; |
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break;
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case 1: |
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round_mode = float_round_down; |
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break;
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case 2: |
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round_mode = float_round_nearest_even; |
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break;
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case 3: |
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default: /* this avoids a gcc (< 4.4) warning */ |
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round_mode = float_round_up; |
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break;
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} |
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set_float_rounding_mode(round_mode, &env->fp_status); |
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} |
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#if defined(CONFIG_USER_ONLY)
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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if (rw == 2) |
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env->exception_index = EXCP_ITB_MISS; |
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else
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env->exception_index = EXCP_DFAULT; |
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env->ipr[IPR_EXC_ADDR] = address; |
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return 1; |
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} |
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
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{
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return addr;
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} |
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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} |
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#else
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
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{
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return -1; |
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} |
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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uint32_t opc; |
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if (rw == 2) { |
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/* Instruction translation buffer miss */
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env->exception_index = EXCP_ITB_MISS; |
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} else {
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if (env->ipr[IPR_EXC_ADDR] & 1) |
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env->exception_index = EXCP_DTB_MISS_PAL; |
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else
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env->exception_index = EXCP_DTB_MISS_NATIVE; |
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opc = (ldl_code(env->pc) >> 21) << 4; |
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if (rw) {
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opc |= 0x9;
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} else {
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opc |= 0x4;
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} |
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env->ipr[IPR_MM_STAT] = opc; |
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} |
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return 1; |
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} |
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int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp) |
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{
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uint64_t hwpcb; |
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int ret = 0; |
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hwpcb = env->ipr[IPR_PCBB]; |
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switch (iprn) {
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case IPR_ASN:
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if (env->features & FEATURE_ASN)
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*valp = env->ipr[IPR_ASN]; |
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else
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*valp = 0;
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break;
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case IPR_ASTEN:
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*valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60; |
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break;
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case IPR_ASTSR:
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*valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60; |
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break;
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case IPR_DATFX:
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/* Write only */
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ret = -1;
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break;
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case IPR_ESP:
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if (env->features & FEATURE_SPS)
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*valp = env->ipr[IPR_ESP]; |
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else
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*valp = ldq_raw(hwpcb + 8);
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break;
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case IPR_FEN:
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*valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63; |
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break;
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case IPR_IPIR:
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/* Write-only */
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ret = -1;
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break;
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case IPR_IPL:
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*valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59; |
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break;
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case IPR_KSP:
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if (!(env->ipr[IPR_EXC_ADDR] & 1)) { |
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ret = -1;
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} else {
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if (env->features & FEATURE_SPS)
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*valp = env->ipr[IPR_KSP]; |
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else
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*valp = ldq_raw(hwpcb + 0);
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} |
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break;
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case IPR_MCES:
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*valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59; |
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break;
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case IPR_PERFMON:
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/* Implementation specific */
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*valp = 0;
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break;
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case IPR_PCBB:
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*valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16; |
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break;
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case IPR_PRBR:
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*valp = env->ipr[IPR_PRBR]; |
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break;
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case IPR_PTBR:
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*valp = env->ipr[IPR_PTBR]; |
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break;
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case IPR_SCBB:
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*valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]); |
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break;
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case IPR_SIRR:
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/* Write-only */
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ret = -1;
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break;
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case IPR_SISR:
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*valp = (int64_t)((int16_t)env->ipr[IPR_SISR]); |
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case IPR_SSP:
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if (env->features & FEATURE_SPS)
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*valp = env->ipr[IPR_SSP]; |
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else
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*valp = ldq_raw(hwpcb + 16);
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break;
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case IPR_SYSPTBR:
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if (env->features & FEATURE_VIRBND)
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*valp = env->ipr[IPR_SYSPTBR]; |
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else
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ret = -1;
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break;
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case IPR_TBCHK:
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if ((env->features & FEATURE_TBCHK)) {
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/* XXX: TODO */
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*valp = 0;
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ret = -1;
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} else {
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ret = -1;
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} |
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break;
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case IPR_TBIA:
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/* Write-only */
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ret = -1;
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break;
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case IPR_TBIAP:
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/* Write-only */
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ret = -1;
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break;
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case IPR_TBIS:
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/* Write-only */
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ret = -1;
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break;
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case IPR_TBISD:
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/* Write-only */
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ret = -1;
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break;
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case IPR_TBISI:
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/* Write-only */
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ret = -1;
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break;
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case IPR_USP:
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if (env->features & FEATURE_SPS)
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*valp = env->ipr[IPR_USP]; |
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else
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*valp = ldq_raw(hwpcb + 24);
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break;
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case IPR_VIRBND:
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if (env->features & FEATURE_VIRBND)
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*valp = env->ipr[IPR_VIRBND]; |
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else
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ret = -1;
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break;
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case IPR_VPTB:
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*valp = env->ipr[IPR_VPTB]; |
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break;
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case IPR_WHAMI:
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*valp = env->ipr[IPR_WHAMI]; |
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break;
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default:
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/* Invalid */
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ret = -1;
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break;
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} |
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return ret;
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} |
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int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp) |
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{
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uint64_t hwpcb, tmp64; |
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uint8_t tmp8; |
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int ret = 0; |
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hwpcb = env->ipr[IPR_PCBB]; |
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switch (iprn) {
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case IPR_ASN:
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/* Read-only */
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ret = -1;
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break;
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case IPR_ASTEN:
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tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4; |
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*oldvalp = tmp8; |
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tmp8 &= val & 0xF;
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tmp8 |= (val >> 4) & 0xF; |
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env->ipr[IPR_ASTEN] &= ~0xF;
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env->ipr[IPR_ASTEN] |= tmp8; |
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ret = 1;
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break;
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case IPR_ASTSR:
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tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4; |
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*oldvalp = tmp8; |
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tmp8 &= val & 0xF;
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tmp8 |= (val >> 4) & 0xF; |
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env->ipr[IPR_ASTSR] &= ~0xF;
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env->ipr[IPR_ASTSR] |= tmp8; |
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ret = 1;
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case IPR_DATFX:
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env->ipr[IPR_DATFX] &= ~0x1;
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env->ipr[IPR_DATFX] |= val & 1;
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tmp64 = ldq_raw(hwpcb + 56);
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tmp64 &= ~0x8000000000000000ULL;
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tmp64 |= (val & 1) << 63; |
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stq_raw(hwpcb + 56, tmp64);
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break;
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case IPR_ESP:
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if (env->features & FEATURE_SPS)
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env->ipr[IPR_ESP] = val; |
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else
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stq_raw(hwpcb + 8, val);
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break;
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case IPR_FEN:
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env->ipr[IPR_FEN] = val & 1;
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tmp64 = ldq_raw(hwpcb + 56);
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tmp64 &= ~1;
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tmp64 |= val & 1;
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stq_raw(hwpcb + 56, tmp64);
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break;
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case IPR_IPIR:
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/* XXX: TODO: Send IRQ to CPU #ir[16] */
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break;
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case IPR_IPL:
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*oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59; |
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env->ipr[IPR_IPL] &= ~0x1F;
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env->ipr[IPR_IPL] |= val & 0x1F;
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/* XXX: may issue an interrupt or ASR _now_ */
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ret = 1;
|
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break;
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case IPR_KSP:
|
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if (!(env->ipr[IPR_EXC_ADDR] & 1)) { |
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ret = -1;
|
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} else {
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if (env->features & FEATURE_SPS)
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env->ipr[IPR_KSP] = val; |
| 369 |
else
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stq_raw(hwpcb + 0, val);
|
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} |
| 372 |
break;
|
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case IPR_MCES:
|
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env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18); |
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env->ipr[IPR_MCES] |= val & 0x18;
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break;
|
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case IPR_PERFMON:
|
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/* Implementation specific */
|
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*oldvalp = 0;
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ret = 1;
|
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break;
|
| 382 |
case IPR_PCBB:
|
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/* Read-only */
|
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ret = -1;
|
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break;
|
| 386 |
case IPR_PRBR:
|
| 387 |
env->ipr[IPR_PRBR] = val; |
| 388 |
break;
|
| 389 |
case IPR_PTBR:
|
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/* Read-only */
|
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ret = -1;
|
| 392 |
break;
|
| 393 |
case IPR_SCBB:
|
| 394 |
env->ipr[IPR_SCBB] = (uint32_t)val; |
| 395 |
break;
|
| 396 |
case IPR_SIRR:
|
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if (val & 0xF) { |
| 398 |
env->ipr[IPR_SISR] |= 1 << (val & 0xF); |
| 399 |
/* XXX: request a software interrupt _now_ */
|
| 400 |
} |
| 401 |
break;
|
| 402 |
case IPR_SISR:
|
| 403 |
/* Read-only */
|
| 404 |
ret = -1;
|
| 405 |
break;
|
| 406 |
case IPR_SSP:
|
| 407 |
if (env->features & FEATURE_SPS)
|
| 408 |
env->ipr[IPR_SSP] = val; |
| 409 |
else
|
| 410 |
stq_raw(hwpcb + 16, val);
|
| 411 |
break;
|
| 412 |
case IPR_SYSPTBR:
|
| 413 |
if (env->features & FEATURE_VIRBND)
|
| 414 |
env->ipr[IPR_SYSPTBR] = val; |
| 415 |
else
|
| 416 |
ret = -1;
|
| 417 |
case IPR_TBCHK:
|
| 418 |
/* Read-only */
|
| 419 |
ret = -1;
|
| 420 |
break;
|
| 421 |
case IPR_TBIA:
|
| 422 |
tlb_flush(env, 1);
|
| 423 |
break;
|
| 424 |
case IPR_TBIAP:
|
| 425 |
tlb_flush(env, 1);
|
| 426 |
break;
|
| 427 |
case IPR_TBIS:
|
| 428 |
tlb_flush_page(env, val); |
| 429 |
break;
|
| 430 |
case IPR_TBISD:
|
| 431 |
tlb_flush_page(env, val); |
| 432 |
break;
|
| 433 |
case IPR_TBISI:
|
| 434 |
tlb_flush_page(env, val); |
| 435 |
break;
|
| 436 |
case IPR_USP:
|
| 437 |
if (env->features & FEATURE_SPS)
|
| 438 |
env->ipr[IPR_USP] = val; |
| 439 |
else
|
| 440 |
stq_raw(hwpcb + 24, val);
|
| 441 |
break;
|
| 442 |
case IPR_VIRBND:
|
| 443 |
if (env->features & FEATURE_VIRBND)
|
| 444 |
env->ipr[IPR_VIRBND] = val; |
| 445 |
else
|
| 446 |
ret = -1;
|
| 447 |
break;
|
| 448 |
case IPR_VPTB:
|
| 449 |
env->ipr[IPR_VPTB] = val; |
| 450 |
break;
|
| 451 |
case IPR_WHAMI:
|
| 452 |
/* Read-only */
|
| 453 |
ret = -1;
|
| 454 |
break;
|
| 455 |
default:
|
| 456 |
/* Invalid */
|
| 457 |
ret = -1;
|
| 458 |
break;
|
| 459 |
} |
| 460 |
|
| 461 |
return ret;
|
| 462 |
} |
| 463 |
|
| 464 |
void do_interrupt (CPUState *env)
|
| 465 |
{
|
| 466 |
int excp;
|
| 467 |
|
| 468 |
env->ipr[IPR_EXC_ADDR] = env->pc | 1;
|
| 469 |
excp = env->exception_index; |
| 470 |
env->exception_index = -1;
|
| 471 |
env->error_code = 0;
|
| 472 |
/* XXX: disable interrupts and memory mapping */
|
| 473 |
if (env->ipr[IPR_PAL_BASE] != -1ULL) { |
| 474 |
/* We use native PALcode */
|
| 475 |
env->pc = env->ipr[IPR_PAL_BASE] + excp; |
| 476 |
} else {
|
| 477 |
/* We use emulated PALcode */
|
| 478 |
call_pal(env); |
| 479 |
/* Emulate REI */
|
| 480 |
env->pc = env->ipr[IPR_EXC_ADDR] & ~7;
|
| 481 |
env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
|
| 482 |
/* XXX: re-enable interrupts and memory mapping */
|
| 483 |
} |
| 484 |
} |
| 485 |
#endif
|
| 486 |
|
| 487 |
void cpu_dump_state (CPUState *env, FILE *f,
|
| 488 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 489 |
int flags)
|
| 490 |
{
|
| 491 |
static const char *linux_reg_names[] = { |
| 492 |
"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ", |
| 493 |
"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ", |
| 494 |
"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", |
| 495 |
"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero", |
| 496 |
}; |
| 497 |
int i;
|
| 498 |
|
| 499 |
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS " TARGET_FMT_lx "\n", |
| 500 |
env->pc, env->ps); |
| 501 |
for (i = 0; i < 31; i++) { |
| 502 |
cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, |
| 503 |
linux_reg_names[i], env->ir[i]); |
| 504 |
if ((i % 3) == 2) |
| 505 |
cpu_fprintf(f, "\n");
|
| 506 |
} |
| 507 |
cpu_fprintf(f, "\n");
|
| 508 |
for (i = 0; i < 31; i++) { |
| 509 |
cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i, |
| 510 |
*((uint64_t *)(&env->fir[i]))); |
| 511 |
if ((i % 3) == 2) |
| 512 |
cpu_fprintf(f, "\n");
|
| 513 |
} |
| 514 |
cpu_fprintf(f, "\nlock " TARGET_FMT_lx "\n", env->lock); |
| 515 |
} |