root / target-sh4 / helper.c @ ee0dc6d3
History | View | Annotate | Download (17.1 kB)
| 1 |
/*
|
|---|---|
| 2 |
* SH4 emulation
|
| 3 |
*
|
| 4 |
* Copyright (c) 2005 Samuel Tardieu
|
| 5 |
*
|
| 6 |
* This library is free software; you can redistribute it and/or
|
| 7 |
* modify it under the terms of the GNU Lesser General Public
|
| 8 |
* License as published by the Free Software Foundation; either
|
| 9 |
* version 2 of the License, or (at your option) any later version.
|
| 10 |
*
|
| 11 |
* This library is distributed in the hope that it will be useful,
|
| 12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
| 14 |
* Lesser General Public License for more details.
|
| 15 |
*
|
| 16 |
* You should have received a copy of the GNU Lesser General Public
|
| 17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
| 18 |
*/
|
| 19 |
#include <stdarg.h> |
| 20 |
#include <stdlib.h> |
| 21 |
#include <stdio.h> |
| 22 |
#include <string.h> |
| 23 |
#include <inttypes.h> |
| 24 |
#include <signal.h> |
| 25 |
|
| 26 |
#include "cpu.h" |
| 27 |
#include "exec-all.h" |
| 28 |
#include "hw/sh_intc.h" |
| 29 |
|
| 30 |
#if defined(CONFIG_USER_ONLY)
|
| 31 |
|
| 32 |
void do_interrupt (CPUState *env)
|
| 33 |
{
|
| 34 |
env->exception_index = -1;
|
| 35 |
} |
| 36 |
|
| 37 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
| 38 |
int mmu_idx, int is_softmmu) |
| 39 |
{
|
| 40 |
env->tea = address; |
| 41 |
env->exception_index = -1;
|
| 42 |
switch (rw) {
|
| 43 |
case 0: |
| 44 |
env->exception_index = 0x0a0;
|
| 45 |
break;
|
| 46 |
case 1: |
| 47 |
env->exception_index = 0x0c0;
|
| 48 |
break;
|
| 49 |
case 2: |
| 50 |
env->exception_index = 0x0a0;
|
| 51 |
break;
|
| 52 |
} |
| 53 |
return 1; |
| 54 |
} |
| 55 |
|
| 56 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
| 57 |
{
|
| 58 |
return addr;
|
| 59 |
} |
| 60 |
|
| 61 |
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
| 62 |
{
|
| 63 |
/* For user mode, only U0 area is cachable. */
|
| 64 |
return !(addr & 0x80000000); |
| 65 |
} |
| 66 |
|
| 67 |
#else /* !CONFIG_USER_ONLY */ |
| 68 |
|
| 69 |
#define MMU_OK 0 |
| 70 |
#define MMU_ITLB_MISS (-1) |
| 71 |
#define MMU_ITLB_MULTIPLE (-2) |
| 72 |
#define MMU_ITLB_VIOLATION (-3) |
| 73 |
#define MMU_DTLB_MISS_READ (-4) |
| 74 |
#define MMU_DTLB_MISS_WRITE (-5) |
| 75 |
#define MMU_DTLB_INITIAL_WRITE (-6) |
| 76 |
#define MMU_DTLB_VIOLATION_READ (-7) |
| 77 |
#define MMU_DTLB_VIOLATION_WRITE (-8) |
| 78 |
#define MMU_DTLB_MULTIPLE (-9) |
| 79 |
#define MMU_DTLB_MISS (-10) |
| 80 |
#define MMU_IADDR_ERROR (-11) |
| 81 |
#define MMU_DADDR_ERROR_READ (-12) |
| 82 |
#define MMU_DADDR_ERROR_WRITE (-13) |
| 83 |
|
| 84 |
void do_interrupt(CPUState * env)
|
| 85 |
{
|
| 86 |
int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
|
| 87 |
int do_exp, irq_vector = env->exception_index;
|
| 88 |
|
| 89 |
/* prioritize exceptions over interrupts */
|
| 90 |
|
| 91 |
do_exp = env->exception_index != -1;
|
| 92 |
do_irq = do_irq && (env->exception_index == -1);
|
| 93 |
|
| 94 |
if (env->sr & SR_BL) {
|
| 95 |
if (do_exp && env->exception_index != 0x1e0) { |
| 96 |
env->exception_index = 0x000; /* masked exception -> reset */ |
| 97 |
} |
| 98 |
if (do_irq && !env->intr_at_halt) {
|
| 99 |
return; /* masked */ |
| 100 |
} |
| 101 |
env->intr_at_halt = 0;
|
| 102 |
} |
| 103 |
|
| 104 |
if (do_irq) {
|
| 105 |
irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
| 106 |
(env->sr >> 4) & 0xf); |
| 107 |
if (irq_vector == -1) { |
| 108 |
return; /* masked */ |
| 109 |
} |
| 110 |
} |
| 111 |
|
| 112 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
| 113 |
const char *expname; |
| 114 |
switch (env->exception_index) {
|
| 115 |
case 0x0e0: |
| 116 |
expname = "addr_error";
|
| 117 |
break;
|
| 118 |
case 0x040: |
| 119 |
expname = "tlb_miss";
|
| 120 |
break;
|
| 121 |
case 0x0a0: |
| 122 |
expname = "tlb_violation";
|
| 123 |
break;
|
| 124 |
case 0x180: |
| 125 |
expname = "illegal_instruction";
|
| 126 |
break;
|
| 127 |
case 0x1a0: |
| 128 |
expname = "slot_illegal_instruction";
|
| 129 |
break;
|
| 130 |
case 0x800: |
| 131 |
expname = "fpu_disable";
|
| 132 |
break;
|
| 133 |
case 0x820: |
| 134 |
expname = "slot_fpu";
|
| 135 |
break;
|
| 136 |
case 0x100: |
| 137 |
expname = "data_write";
|
| 138 |
break;
|
| 139 |
case 0x060: |
| 140 |
expname = "dtlb_miss_write";
|
| 141 |
break;
|
| 142 |
case 0x0c0: |
| 143 |
expname = "dtlb_violation_write";
|
| 144 |
break;
|
| 145 |
case 0x120: |
| 146 |
expname = "fpu_exception";
|
| 147 |
break;
|
| 148 |
case 0x080: |
| 149 |
expname = "initial_page_write";
|
| 150 |
break;
|
| 151 |
case 0x160: |
| 152 |
expname = "trapa";
|
| 153 |
break;
|
| 154 |
default:
|
| 155 |
expname = do_irq ? "interrupt" : "???"; |
| 156 |
break;
|
| 157 |
} |
| 158 |
qemu_log("exception 0x%03x [%s] raised\n",
|
| 159 |
irq_vector, expname); |
| 160 |
log_cpu_state(env, 0);
|
| 161 |
} |
| 162 |
|
| 163 |
env->ssr = env->sr; |
| 164 |
env->spc = env->pc; |
| 165 |
env->sgr = env->gregs[15];
|
| 166 |
env->sr |= SR_BL | SR_MD | SR_RB; |
| 167 |
|
| 168 |
if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
| 169 |
/* Branch instruction should be executed again before delay slot. */
|
| 170 |
env->spc -= 2;
|
| 171 |
/* Clear flags for exception/interrupt routine. */
|
| 172 |
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE); |
| 173 |
} |
| 174 |
if (env->flags & DELAY_SLOT_CLEARME)
|
| 175 |
env->flags = 0;
|
| 176 |
|
| 177 |
if (do_exp) {
|
| 178 |
env->expevt = env->exception_index; |
| 179 |
switch (env->exception_index) {
|
| 180 |
case 0x000: |
| 181 |
case 0x020: |
| 182 |
case 0x140: |
| 183 |
env->sr &= ~SR_FD; |
| 184 |
env->sr |= 0xf << 4; /* IMASK */ |
| 185 |
env->pc = 0xa0000000;
|
| 186 |
break;
|
| 187 |
case 0x040: |
| 188 |
case 0x060: |
| 189 |
env->pc = env->vbr + 0x400;
|
| 190 |
break;
|
| 191 |
case 0x160: |
| 192 |
env->spc += 2; /* special case for TRAPA */ |
| 193 |
/* fall through */
|
| 194 |
default:
|
| 195 |
env->pc = env->vbr + 0x100;
|
| 196 |
break;
|
| 197 |
} |
| 198 |
return;
|
| 199 |
} |
| 200 |
|
| 201 |
if (do_irq) {
|
| 202 |
env->intevt = irq_vector; |
| 203 |
env->pc = env->vbr + 0x600;
|
| 204 |
return;
|
| 205 |
} |
| 206 |
} |
| 207 |
|
| 208 |
static void update_itlb_use(CPUState * env, int itlbnb) |
| 209 |
{
|
| 210 |
uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
| 211 |
|
| 212 |
switch (itlbnb) {
|
| 213 |
case 0: |
| 214 |
and_mask = 0x1f;
|
| 215 |
break;
|
| 216 |
case 1: |
| 217 |
and_mask = 0xe7;
|
| 218 |
or_mask = 0x80;
|
| 219 |
break;
|
| 220 |
case 2: |
| 221 |
and_mask = 0xfb;
|
| 222 |
or_mask = 0x50;
|
| 223 |
break;
|
| 224 |
case 3: |
| 225 |
or_mask = 0x2c;
|
| 226 |
break;
|
| 227 |
} |
| 228 |
|
| 229 |
env->mmucr &= (and_mask << 24) | 0x00ffffff; |
| 230 |
env->mmucr |= (or_mask << 24);
|
| 231 |
} |
| 232 |
|
| 233 |
static int itlb_replacement(CPUState * env) |
| 234 |
{
|
| 235 |
if ((env->mmucr & 0xe0000000) == 0xe0000000) |
| 236 |
return 0; |
| 237 |
if ((env->mmucr & 0x98000000) == 0x18000000) |
| 238 |
return 1; |
| 239 |
if ((env->mmucr & 0x54000000) == 0x04000000) |
| 240 |
return 2; |
| 241 |
if ((env->mmucr & 0x2c000000) == 0x00000000) |
| 242 |
return 3; |
| 243 |
assert(0);
|
| 244 |
} |
| 245 |
|
| 246 |
/* Find the corresponding entry in the right TLB
|
| 247 |
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
|
| 248 |
*/
|
| 249 |
static int find_tlb_entry(CPUState * env, target_ulong address, |
| 250 |
tlb_t * entries, uint8_t nbtlb, int use_asid)
|
| 251 |
{
|
| 252 |
int match = MMU_DTLB_MISS;
|
| 253 |
uint32_t start, end; |
| 254 |
uint8_t asid; |
| 255 |
int i;
|
| 256 |
|
| 257 |
asid = env->pteh & 0xff;
|
| 258 |
|
| 259 |
for (i = 0; i < nbtlb; i++) { |
| 260 |
if (!entries[i].v)
|
| 261 |
continue; /* Invalid entry */ |
| 262 |
if (!entries[i].sh && use_asid && entries[i].asid != asid)
|
| 263 |
continue; /* Bad ASID */ |
| 264 |
start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
| 265 |
end = start + entries[i].size - 1;
|
| 266 |
if (address >= start && address <= end) { /* Match */ |
| 267 |
if (match != MMU_DTLB_MISS)
|
| 268 |
return MMU_DTLB_MULTIPLE; /* Multiple match */ |
| 269 |
match = i; |
| 270 |
} |
| 271 |
} |
| 272 |
return match;
|
| 273 |
} |
| 274 |
|
| 275 |
static void increment_urc(CPUState * env) |
| 276 |
{
|
| 277 |
uint8_t urb, urc; |
| 278 |
|
| 279 |
/* Increment URC */
|
| 280 |
urb = ((env->mmucr) >> 18) & 0x3f; |
| 281 |
urc = ((env->mmucr) >> 10) & 0x3f; |
| 282 |
urc++; |
| 283 |
if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
| 284 |
urc = 0;
|
| 285 |
env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
| 286 |
} |
| 287 |
|
| 288 |
/* Find itlb entry - update itlb from utlb if necessary and asked for
|
| 289 |
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
|
| 290 |
Update the itlb from utlb if update is not 0
|
| 291 |
*/
|
| 292 |
static int find_itlb_entry(CPUState * env, target_ulong address, |
| 293 |
int use_asid, int update) |
| 294 |
{
|
| 295 |
int e, n;
|
| 296 |
|
| 297 |
e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
| 298 |
if (e == MMU_DTLB_MULTIPLE)
|
| 299 |
e = MMU_ITLB_MULTIPLE; |
| 300 |
else if (e == MMU_DTLB_MISS && update) { |
| 301 |
e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
| 302 |
if (e >= 0) { |
| 303 |
tlb_t * ientry; |
| 304 |
n = itlb_replacement(env); |
| 305 |
ientry = &env->itlb[n]; |
| 306 |
if (ientry->v) {
|
| 307 |
tlb_flush_page(env, ientry->vpn << 10);
|
| 308 |
} |
| 309 |
*ientry = env->utlb[e]; |
| 310 |
e = n; |
| 311 |
} else if (e == MMU_DTLB_MISS) |
| 312 |
e = MMU_ITLB_MISS; |
| 313 |
} else if (e == MMU_DTLB_MISS) |
| 314 |
e = MMU_ITLB_MISS; |
| 315 |
if (e >= 0) |
| 316 |
update_itlb_use(env, e); |
| 317 |
return e;
|
| 318 |
} |
| 319 |
|
| 320 |
/* Find utlb entry
|
| 321 |
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
|
| 322 |
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
| 323 |
{
|
| 324 |
/* per utlb access */
|
| 325 |
increment_urc(env); |
| 326 |
|
| 327 |
/* Return entry */
|
| 328 |
return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
|
| 329 |
} |
| 330 |
|
| 331 |
/* Match address against MMU
|
| 332 |
Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
|
| 333 |
MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
|
| 334 |
MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
|
| 335 |
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
|
| 336 |
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
|
| 337 |
*/
|
| 338 |
static int get_mmu_address(CPUState * env, target_ulong * physical, |
| 339 |
int *prot, target_ulong address,
|
| 340 |
int rw, int access_type) |
| 341 |
{
|
| 342 |
int use_asid, n;
|
| 343 |
tlb_t *matching = NULL;
|
| 344 |
|
| 345 |
use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
| 346 |
|
| 347 |
if (rw == 2) { |
| 348 |
n = find_itlb_entry(env, address, use_asid, 1);
|
| 349 |
if (n >= 0) { |
| 350 |
matching = &env->itlb[n]; |
| 351 |
if (!(env->sr & SR_MD) && !(matching->pr & 2)) |
| 352 |
n = MMU_ITLB_VIOLATION; |
| 353 |
else
|
| 354 |
*prot = PAGE_EXEC; |
| 355 |
} |
| 356 |
} else {
|
| 357 |
n = find_utlb_entry(env, address, use_asid); |
| 358 |
if (n >= 0) { |
| 359 |
matching = &env->utlb[n]; |
| 360 |
if (!(env->sr & SR_MD) && !(matching->pr & 2)) { |
| 361 |
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
| 362 |
MMU_DTLB_VIOLATION_READ; |
| 363 |
} else if ((rw == 1) && !(matching->pr & 1)) { |
| 364 |
n = MMU_DTLB_VIOLATION_WRITE; |
| 365 |
} else if ((rw == 1) & !matching->d) { |
| 366 |
n = MMU_DTLB_INITIAL_WRITE; |
| 367 |
} else {
|
| 368 |
*prot = PAGE_READ; |
| 369 |
if ((matching->pr & 1) && matching->d) { |
| 370 |
*prot |= PAGE_WRITE; |
| 371 |
} |
| 372 |
} |
| 373 |
} else if (n == MMU_DTLB_MISS) { |
| 374 |
n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
| 375 |
MMU_DTLB_MISS_READ; |
| 376 |
} |
| 377 |
} |
| 378 |
if (n >= 0) { |
| 379 |
n = MMU_OK; |
| 380 |
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
| 381 |
(address & (matching->size - 1));
|
| 382 |
} |
| 383 |
return n;
|
| 384 |
} |
| 385 |
|
| 386 |
static int get_physical_address(CPUState * env, target_ulong * physical, |
| 387 |
int *prot, target_ulong address,
|
| 388 |
int rw, int access_type) |
| 389 |
{
|
| 390 |
/* P1, P2 and P4 areas do not use translation */
|
| 391 |
if ((address >= 0x80000000 && address < 0xc0000000) || |
| 392 |
address >= 0xe0000000) {
|
| 393 |
if (!(env->sr & SR_MD)
|
| 394 |
&& (address < 0xe0000000 || address >= 0xe4000000)) { |
| 395 |
/* Unauthorized access in user mode (only store queues are available) */
|
| 396 |
fprintf(stderr, "Unauthorized access\n");
|
| 397 |
if (rw == 0) |
| 398 |
return MMU_DADDR_ERROR_READ;
|
| 399 |
else if (rw == 1) |
| 400 |
return MMU_DADDR_ERROR_WRITE;
|
| 401 |
else
|
| 402 |
return MMU_IADDR_ERROR;
|
| 403 |
} |
| 404 |
if (address >= 0x80000000 && address < 0xc0000000) { |
| 405 |
/* Mask upper 3 bits for P1 and P2 areas */
|
| 406 |
*physical = address & 0x1fffffff;
|
| 407 |
} else {
|
| 408 |
*physical = address; |
| 409 |
} |
| 410 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 411 |
return MMU_OK;
|
| 412 |
} |
| 413 |
|
| 414 |
/* If MMU is disabled, return the corresponding physical page */
|
| 415 |
if (!env->mmucr & MMUCR_AT) {
|
| 416 |
*physical = address & 0x1FFFFFFF;
|
| 417 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 418 |
return MMU_OK;
|
| 419 |
} |
| 420 |
|
| 421 |
/* We need to resort to the MMU */
|
| 422 |
return get_mmu_address(env, physical, prot, address, rw, access_type);
|
| 423 |
} |
| 424 |
|
| 425 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
| 426 |
int mmu_idx, int is_softmmu) |
| 427 |
{
|
| 428 |
target_ulong physical; |
| 429 |
int prot, ret, access_type;
|
| 430 |
|
| 431 |
access_type = ACCESS_INT; |
| 432 |
ret = |
| 433 |
get_physical_address(env, &physical, &prot, address, rw, |
| 434 |
access_type); |
| 435 |
|
| 436 |
if (ret != MMU_OK) {
|
| 437 |
env->tea = address; |
| 438 |
switch (ret) {
|
| 439 |
case MMU_ITLB_MISS:
|
| 440 |
case MMU_DTLB_MISS_READ:
|
| 441 |
env->exception_index = 0x040;
|
| 442 |
break;
|
| 443 |
case MMU_DTLB_MULTIPLE:
|
| 444 |
case MMU_ITLB_MULTIPLE:
|
| 445 |
env->exception_index = 0x140;
|
| 446 |
break;
|
| 447 |
case MMU_ITLB_VIOLATION:
|
| 448 |
env->exception_index = 0x0a0;
|
| 449 |
break;
|
| 450 |
case MMU_DTLB_MISS_WRITE:
|
| 451 |
env->exception_index = 0x060;
|
| 452 |
break;
|
| 453 |
case MMU_DTLB_INITIAL_WRITE:
|
| 454 |
env->exception_index = 0x080;
|
| 455 |
break;
|
| 456 |
case MMU_DTLB_VIOLATION_READ:
|
| 457 |
env->exception_index = 0x0a0;
|
| 458 |
break;
|
| 459 |
case MMU_DTLB_VIOLATION_WRITE:
|
| 460 |
env->exception_index = 0x0c0;
|
| 461 |
break;
|
| 462 |
case MMU_IADDR_ERROR:
|
| 463 |
case MMU_DADDR_ERROR_READ:
|
| 464 |
env->exception_index = 0x0c0;
|
| 465 |
break;
|
| 466 |
case MMU_DADDR_ERROR_WRITE:
|
| 467 |
env->exception_index = 0x100;
|
| 468 |
break;
|
| 469 |
default:
|
| 470 |
assert(0);
|
| 471 |
} |
| 472 |
return 1; |
| 473 |
} |
| 474 |
|
| 475 |
address &= TARGET_PAGE_MASK; |
| 476 |
physical &= TARGET_PAGE_MASK; |
| 477 |
|
| 478 |
return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
|
| 479 |
} |
| 480 |
|
| 481 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
| 482 |
{
|
| 483 |
target_ulong physical; |
| 484 |
int prot;
|
| 485 |
|
| 486 |
get_physical_address(env, &physical, &prot, addr, 0, 0); |
| 487 |
return physical;
|
| 488 |
} |
| 489 |
|
| 490 |
void cpu_load_tlb(CPUSH4State * env)
|
| 491 |
{
|
| 492 |
int n = cpu_mmucr_urc(env->mmucr);
|
| 493 |
tlb_t * entry = &env->utlb[n]; |
| 494 |
|
| 495 |
if (entry->v) {
|
| 496 |
/* Overwriting valid entry in utlb. */
|
| 497 |
target_ulong address = entry->vpn << 10;
|
| 498 |
tlb_flush_page(env, address); |
| 499 |
} |
| 500 |
|
| 501 |
/* Take values into cpu status from registers. */
|
| 502 |
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
| 503 |
entry->vpn = cpu_pteh_vpn(env->pteh); |
| 504 |
entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
| 505 |
entry->ppn = cpu_ptel_ppn(env->ptel); |
| 506 |
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
| 507 |
switch (entry->sz) {
|
| 508 |
case 0: /* 00 */ |
| 509 |
entry->size = 1024; /* 1K */ |
| 510 |
break;
|
| 511 |
case 1: /* 01 */ |
| 512 |
entry->size = 1024 * 4; /* 4K */ |
| 513 |
break;
|
| 514 |
case 2: /* 10 */ |
| 515 |
entry->size = 1024 * 64; /* 64K */ |
| 516 |
break;
|
| 517 |
case 3: /* 11 */ |
| 518 |
entry->size = 1024 * 1024; /* 1M */ |
| 519 |
break;
|
| 520 |
default:
|
| 521 |
assert(0);
|
| 522 |
break;
|
| 523 |
} |
| 524 |
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
| 525 |
entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
| 526 |
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
| 527 |
entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
| 528 |
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
| 529 |
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
| 530 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
| 531 |
} |
| 532 |
|
| 533 |
void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
| 534 |
{
|
| 535 |
int i;
|
| 536 |
|
| 537 |
/* UTLB */
|
| 538 |
for (i = 0; i < UTLB_SIZE; i++) { |
| 539 |
tlb_t * entry = &s->utlb[i]; |
| 540 |
entry->v = 0;
|
| 541 |
} |
| 542 |
/* ITLB */
|
| 543 |
for (i = 0; i < UTLB_SIZE; i++) { |
| 544 |
tlb_t * entry = &s->utlb[i]; |
| 545 |
entry->v = 0;
|
| 546 |
} |
| 547 |
|
| 548 |
tlb_flush(s, 1);
|
| 549 |
} |
| 550 |
|
| 551 |
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
| 552 |
uint32_t mem_value) |
| 553 |
{
|
| 554 |
int associate = addr & 0x0000080; |
| 555 |
uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
| 556 |
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
| 557 |
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
| 558 |
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
| 559 |
int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0; |
| 560 |
|
| 561 |
if (associate) {
|
| 562 |
int i;
|
| 563 |
tlb_t * utlb_match_entry = NULL;
|
| 564 |
int needs_tlb_flush = 0; |
| 565 |
|
| 566 |
/* search UTLB */
|
| 567 |
for (i = 0; i < UTLB_SIZE; i++) { |
| 568 |
tlb_t * entry = &s->utlb[i]; |
| 569 |
if (!entry->v)
|
| 570 |
continue;
|
| 571 |
|
| 572 |
if (entry->vpn == vpn
|
| 573 |
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
| 574 |
if (utlb_match_entry) {
|
| 575 |
/* Multiple TLB Exception */
|
| 576 |
s->exception_index = 0x140;
|
| 577 |
s->tea = addr; |
| 578 |
break;
|
| 579 |
} |
| 580 |
if (entry->v && !v)
|
| 581 |
needs_tlb_flush = 1;
|
| 582 |
entry->v = v; |
| 583 |
entry->d = d; |
| 584 |
utlb_match_entry = entry; |
| 585 |
} |
| 586 |
increment_urc(s); /* per utlb access */
|
| 587 |
} |
| 588 |
|
| 589 |
/* search ITLB */
|
| 590 |
for (i = 0; i < ITLB_SIZE; i++) { |
| 591 |
tlb_t * entry = &s->itlb[i]; |
| 592 |
if (entry->vpn == vpn
|
| 593 |
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
| 594 |
if (entry->v && !v)
|
| 595 |
needs_tlb_flush = 1;
|
| 596 |
if (utlb_match_entry)
|
| 597 |
*entry = *utlb_match_entry; |
| 598 |
else
|
| 599 |
entry->v = v; |
| 600 |
break;
|
| 601 |
} |
| 602 |
} |
| 603 |
|
| 604 |
if (needs_tlb_flush)
|
| 605 |
tlb_flush_page(s, vpn << 10);
|
| 606 |
|
| 607 |
} else {
|
| 608 |
int index = (addr & 0x00003f00) >> 8; |
| 609 |
tlb_t * entry = &s->utlb[index]; |
| 610 |
if (entry->v) {
|
| 611 |
/* Overwriting valid entry in utlb. */
|
| 612 |
target_ulong address = entry->vpn << 10;
|
| 613 |
tlb_flush_page(s, address); |
| 614 |
} |
| 615 |
entry->asid = asid; |
| 616 |
entry->vpn = vpn; |
| 617 |
entry->d = d; |
| 618 |
entry->v = v; |
| 619 |
increment_urc(s); |
| 620 |
} |
| 621 |
} |
| 622 |
|
| 623 |
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
| 624 |
{
|
| 625 |
int n;
|
| 626 |
int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
| 627 |
|
| 628 |
/* check area */
|
| 629 |
if (env->sr & SR_MD) {
|
| 630 |
/* For previledged mode, P2 and P4 area is not cachable. */
|
| 631 |
if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
| 632 |
return 0; |
| 633 |
} else {
|
| 634 |
/* For user mode, only U0 area is cachable. */
|
| 635 |
if (0x80000000 <= addr) |
| 636 |
return 0; |
| 637 |
} |
| 638 |
|
| 639 |
/*
|
| 640 |
* TODO : Evaluate CCR and check if the cache is on or off.
|
| 641 |
* Now CCR is not in CPUSH4State, but in SH7750State.
|
| 642 |
* When you move the ccr inot CPUSH4State, the code will be
|
| 643 |
* as follows.
|
| 644 |
*/
|
| 645 |
#if 0
|
| 646 |
/* check if operand cache is enabled or not. */
|
| 647 |
if (!(env->ccr & 1))
|
| 648 |
return 0;
|
| 649 |
#endif
|
| 650 |
|
| 651 |
/* if MMU is off, no check for TLB. */
|
| 652 |
if (env->mmucr & MMUCR_AT)
|
| 653 |
return 1; |
| 654 |
|
| 655 |
/* check TLB */
|
| 656 |
n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
| 657 |
if (n >= 0) |
| 658 |
return env->itlb[n].c;
|
| 659 |
|
| 660 |
n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
| 661 |
if (n >= 0) |
| 662 |
return env->utlb[n].c;
|
| 663 |
|
| 664 |
return 0; |
| 665 |
} |
| 666 |
|
| 667 |
#endif
|