Revision ee6847d1
| b/Makefile | ||
|---|---|---|
| 108 | 108 |
obj-y += buffered_file.o migration.o migration-tcp.o net.o qemu-sockets.o |
| 109 | 109 |
obj-y += qemu-char.o aio.o net-checksum.o savevm.o cache-utils.o |
| 110 | 110 |
obj-y += msmouse.o ps2.o |
| 111 |
obj-y += qdev.o ssi.o |
|
| 111 |
obj-y += qdev.o qdev-properties.o ssi.o
|
|
| 112 | 112 |
|
| 113 | 113 |
obj-$(CONFIG_BRLAPI) += baum.o |
| 114 | 114 |
|
| b/Makefile.hw | ||
|---|---|---|
| 26 | 26 |
# SCSI layer |
| 27 | 27 |
obj-y += lsi53c895a.o esp.o |
| 28 | 28 |
|
| 29 |
obj-y += dma-helpers.o sysbus.o |
|
| 29 |
obj-y += dma-helpers.o sysbus.o qdev-addr.o
|
|
| 30 | 30 |
|
| 31 | 31 |
all: $(HWLIB) |
| 32 | 32 |
# Dummy command so that make thinks it has done something |
| b/hw/arm_sysctl.c | ||
|---|---|---|
| 194 | 194 |
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
| 195 | 195 |
int iomemtype; |
| 196 | 196 |
|
| 197 |
s->sys_id = qdev_get_prop_int(&dev->qdev, "sys_id", 0); |
|
| 198 | 197 |
/* The MPcore bootloader uses these flags to start secondary CPUs. |
| 199 | 198 |
We don't use a bootloader, so do this here. */ |
| 200 | 199 |
s->flags = 3; |
| ... | ... | |
| 210 | 209 |
DeviceState *dev; |
| 211 | 210 |
|
| 212 | 211 |
dev = qdev_create(NULL, "realview_sysctl"); |
| 213 |
qdev_set_prop_int(dev, "sys_id", sys_id);
|
|
| 212 |
qdev_prop_set_uint32(dev, "sys_id", sys_id);
|
|
| 214 | 213 |
qdev_init(dev); |
| 215 | 214 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
| 216 | 215 |
} |
| 217 | 216 |
|
| 217 |
static SysBusDeviceInfo arm_sysctl_info = {
|
|
| 218 |
.init = arm_sysctl_init1, |
|
| 219 |
.qdev.name = "realview_sysctl", |
|
| 220 |
.qdev.size = sizeof(arm_sysctl_state), |
|
| 221 |
.qdev.props = (Property[]) {
|
|
| 222 |
{
|
|
| 223 |
.name = "sys_id", |
|
| 224 |
.info = &qdev_prop_uint32, |
|
| 225 |
.offset = offsetof(arm_sysctl_state, sys_id), |
|
| 226 |
}, |
|
| 227 |
{/* end of list */}
|
|
| 228 |
} |
|
| 229 |
}; |
|
| 230 |
|
|
| 218 | 231 |
static void arm_sysctl_register_devices(void) |
| 219 | 232 |
{
|
| 220 |
sysbus_register_dev("realview_sysctl", sizeof(arm_sysctl_state),
|
|
| 221 |
arm_sysctl_init1); |
|
| 233 |
sysbus_register_withprop(&arm_sysctl_info); |
|
| 222 | 234 |
} |
| 223 | 235 |
|
| 224 | 236 |
device_init(arm_sysctl_register_devices) |
| b/hw/armv7m.c | ||
|---|---|---|
| 127 | 127 |
BitBandState *s = FROM_SYSBUS(BitBandState, dev); |
| 128 | 128 |
int iomemtype; |
| 129 | 129 |
|
| 130 |
s->base = qdev_get_prop_int(&dev->qdev, "base", 0); |
|
| 131 | 130 |
iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn, |
| 132 | 131 |
&s->base); |
| 133 | 132 |
sysbus_init_mmio(dev, 0x02000000, iomemtype); |
| ... | ... | |
| 138 | 137 |
DeviceState *dev; |
| 139 | 138 |
|
| 140 | 139 |
dev = qdev_create(NULL, "ARM,bitband-memory"); |
| 141 |
qdev_set_prop_int(dev, "base", 0x20000000);
|
|
| 140 |
qdev_prop_set_uint32(dev, "base", 0x20000000);
|
|
| 142 | 141 |
qdev_init(dev); |
| 143 | 142 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000); |
| 144 | 143 |
|
| 145 | 144 |
dev = qdev_create(NULL, "ARM,bitband-memory"); |
| 146 |
qdev_set_prop_int(dev, "base", 0x40000000);
|
|
| 145 |
qdev_prop_set_uint32(dev, "base", 0x40000000);
|
|
| 147 | 146 |
qdev_init(dev); |
| 148 | 147 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000); |
| 149 | 148 |
} |
| ... | ... | |
| 238 | 237 |
return pic; |
| 239 | 238 |
} |
| 240 | 239 |
|
| 240 |
static SysBusDeviceInfo bitband_info = {
|
|
| 241 |
.init = bitband_init, |
|
| 242 |
.qdev.name = "ARM,bitband-memory", |
|
| 243 |
.qdev.size = sizeof(BitBandState), |
|
| 244 |
.qdev.props = (Property[]) {
|
|
| 245 |
{
|
|
| 246 |
.name = "base", |
|
| 247 |
.info = &qdev_prop_hex32, |
|
| 248 |
.offset = offsetof(BitBandState, base), |
|
| 249 |
}, |
|
| 250 |
{/* end of list */}
|
|
| 251 |
} |
|
| 252 |
}; |
|
| 253 |
|
|
| 241 | 254 |
static void armv7m_register_devices(void) |
| 242 | 255 |
{
|
| 243 |
sysbus_register_dev("ARM,bitband-memory", sizeof(BitBandState),
|
|
| 244 |
bitband_init); |
|
| 256 |
sysbus_register_withprop(&bitband_info); |
|
| 245 | 257 |
} |
| 246 | 258 |
|
| 247 | 259 |
device_init(armv7m_register_devices) |
| b/hw/axis_dev88.c | ||
|---|---|---|
| 297 | 297 |
cpu_irq = cris_pic_init_cpu(env); |
| 298 | 298 |
dev = qdev_create(NULL, "etraxfs,pic"); |
| 299 | 299 |
/* FIXME: Is there a proper way to signal vectors to the CPU core? */ |
| 300 |
qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
|
|
| 300 |
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
|
|
| 301 | 301 |
qdev_init(dev); |
| 302 | 302 |
s = sysbus_from_qdev(dev); |
| 303 | 303 |
sysbus_mmio_map(s, 0, 0x3001c000); |
| b/hw/cs4231.c | ||
|---|---|---|
| 185 | 185 |
.init = cs4231_init1, |
| 186 | 186 |
.qdev.name = "SUNW,CS4231", |
| 187 | 187 |
.qdev.size = sizeof(CSState), |
| 188 |
.qdev.props = (DevicePropList[]) {
|
|
| 188 |
.qdev.props = (Property[]) {
|
|
| 189 | 189 |
{.name = NULL}
|
| 190 | 190 |
} |
| 191 | 191 |
}; |
| b/hw/eccmemctl.c | ||
|---|---|---|
| 321 | 321 |
ECCState *s = FROM_SYSBUS(ECCState, dev); |
| 322 | 322 |
|
| 323 | 323 |
sysbus_init_irq(dev, &s->irq); |
| 324 |
s->version = qdev_get_prop_int(&dev->qdev, "version", -1); |
|
| 325 | 324 |
s->regs[0] = s->version; |
| 326 | 325 |
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); |
| 327 | 326 |
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); |
| ... | ... | |
| 342 | 341 |
SysBusDevice *s; |
| 343 | 342 |
|
| 344 | 343 |
dev = qdev_create(NULL, "eccmemctl"); |
| 345 |
qdev_set_prop_int(dev, "version", version);
|
|
| 344 |
qdev_prop_set_uint32(dev, "version", version);
|
|
| 346 | 345 |
qdev_init(dev); |
| 347 | 346 |
s = sysbus_from_qdev(dev); |
| 348 | 347 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 352 | 351 |
} |
| 353 | 352 |
} |
| 354 | 353 |
|
| 354 |
static SysBusDeviceInfo ecc_info = {
|
|
| 355 |
.init = ecc_init1, |
|
| 356 |
.qdev.name = "eccmemctl", |
|
| 357 |
.qdev.size = sizeof(ECCState), |
|
| 358 |
.qdev.props = (Property[]) {
|
|
| 359 |
{
|
|
| 360 |
.name = "version", |
|
| 361 |
.info = &qdev_prop_uint32, |
|
| 362 |
.offset = offsetof(ECCState, version), |
|
| 363 |
.defval = (uint32_t[]) { -1 },
|
|
| 364 |
}, |
|
| 365 |
{/* end of list */}
|
|
| 366 |
} |
|
| 367 |
}; |
|
| 368 |
|
|
| 369 |
|
|
| 355 | 370 |
static void ecc_register_devices(void) |
| 356 | 371 |
{
|
| 357 |
sysbus_register_dev("eccmemctl", sizeof(ECCState), ecc_init1);
|
|
| 372 |
sysbus_register_withprop(&ecc_info);
|
|
| 358 | 373 |
} |
| 359 | 374 |
|
| 360 | 375 |
device_init(ecc_register_devices) |
| b/hw/escc.c | ||
|---|---|---|
| 120 | 120 |
struct ChannelState chn[2]; |
| 121 | 121 |
int it_shift; |
| 122 | 122 |
int mmio_index; |
| 123 |
uint32_t disabled; |
|
| 124 |
uint32_t frequency; |
|
| 123 | 125 |
}; |
| 124 | 126 |
|
| 125 | 127 |
#define SERIAL_CTRL 0 |
| ... | ... | |
| 732 | 734 |
SerialState *d; |
| 733 | 735 |
|
| 734 | 736 |
dev = qdev_create(NULL, "escc"); |
| 735 |
qdev_set_prop_int(dev, "disabled", 0);
|
|
| 736 |
qdev_set_prop_int(dev, "frequency", clock);
|
|
| 737 |
qdev_set_prop_int(dev, "it_shift", it_shift);
|
|
| 738 |
qdev_set_prop_ptr(dev, "chrB", chrB);
|
|
| 739 |
qdev_set_prop_ptr(dev, "chrA", chrA);
|
|
| 740 |
qdev_set_prop_int(dev, "chnBtype", ser);
|
|
| 741 |
qdev_set_prop_int(dev, "chnAtype", ser);
|
|
| 737 |
qdev_prop_set_uint32(dev, "disabled", 0);
|
|
| 738 |
qdev_prop_set_uint32(dev, "frequency", clock);
|
|
| 739 |
qdev_prop_set_uint32(dev, "it_shift", it_shift);
|
|
| 740 |
qdev_prop_set_ptr(dev, "chrB", chrB);
|
|
| 741 |
qdev_prop_set_ptr(dev, "chrA", chrA);
|
|
| 742 |
qdev_prop_set_uint32(dev, "chnBtype", ser);
|
|
| 743 |
qdev_prop_set_uint32(dev, "chnAtype", ser);
|
|
| 742 | 744 |
qdev_init(dev); |
| 743 | 745 |
s = sysbus_from_qdev(dev); |
| 744 | 746 |
sysbus_connect_irq(s, 0, irqA); |
| ... | ... | |
| 895 | 897 |
SysBusDevice *s; |
| 896 | 898 |
|
| 897 | 899 |
dev = qdev_create(NULL, "escc"); |
| 898 |
qdev_set_prop_int(dev, "disabled", disabled);
|
|
| 899 |
qdev_set_prop_int(dev, "frequency", clock);
|
|
| 900 |
qdev_set_prop_int(dev, "it_shift", it_shift);
|
|
| 901 |
qdev_set_prop_ptr(dev, "chrB", NULL);
|
|
| 902 |
qdev_set_prop_ptr(dev, "chrA", NULL);
|
|
| 903 |
qdev_set_prop_int(dev, "chnBtype", mouse);
|
|
| 904 |
qdev_set_prop_int(dev, "chnAtype", kbd);
|
|
| 900 |
qdev_prop_set_uint32(dev, "disabled", disabled);
|
|
| 901 |
qdev_prop_set_uint32(dev, "frequency", clock);
|
|
| 902 |
qdev_prop_set_uint32(dev, "it_shift", it_shift);
|
|
| 903 |
qdev_prop_set_ptr(dev, "chrB", NULL);
|
|
| 904 |
qdev_prop_set_ptr(dev, "chrA", NULL);
|
|
| 905 |
qdev_prop_set_uint32(dev, "chnBtype", mouse);
|
|
| 906 |
qdev_prop_set_uint32(dev, "chnAtype", kbd);
|
|
| 905 | 907 |
qdev_init(dev); |
| 906 | 908 |
s = sysbus_from_qdev(dev); |
| 907 | 909 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 914 | 916 |
SerialState *s = FROM_SYSBUS(SerialState, dev); |
| 915 | 917 |
int io; |
| 916 | 918 |
unsigned int i; |
| 917 |
uint32_t clock, disabled; |
|
| 918 |
|
|
| 919 |
s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", 0); |
|
| 920 |
clock = qdev_get_prop_int(&dev->qdev, "frequency", 0); |
|
| 921 |
s->chn[0].chr = qdev_get_prop_ptr(&dev->qdev, "chrB"); |
|
| 922 |
s->chn[1].chr = qdev_get_prop_ptr(&dev->qdev, "chrA"); |
|
| 923 |
disabled = qdev_get_prop_int(&dev->qdev, "disabled", 0); |
|
| 924 |
s->chn[0].disabled = disabled; |
|
| 925 |
s->chn[1].disabled = disabled; |
|
| 919 |
|
|
| 920 |
s->chn[0].disabled = s->disabled; |
|
| 921 |
s->chn[1].disabled = s->disabled; |
|
| 926 | 922 |
for (i = 0; i < 2; i++) {
|
| 927 | 923 |
sysbus_init_irq(dev, &s->chn[i].irq); |
| 928 | 924 |
s->chn[i].chn = 1 - i; |
| 929 |
s->chn[i].clock = clock / 2;
|
|
| 925 |
s->chn[i].clock = s->frequency / 2;
|
|
| 930 | 926 |
if (s->chn[i].chr) {
|
| 931 | 927 |
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, |
| 932 | 928 |
serial_receive1, serial_event, &s->chn[i]); |
| ... | ... | |
| 934 | 930 |
} |
| 935 | 931 |
s->chn[0].otherchn = &s->chn[1]; |
| 936 | 932 |
s->chn[1].otherchn = &s->chn[0]; |
| 937 |
s->chn[0].type = qdev_get_prop_int(&dev->qdev, "chnBtype", 0); |
|
| 938 |
s->chn[1].type = qdev_get_prop_int(&dev->qdev, "chnAtype", 0); |
|
| 939 | 933 |
|
| 940 | 934 |
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s); |
| 941 | 935 |
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io); |
| ... | ... | |
| 957 | 951 |
.init = escc_init1, |
| 958 | 952 |
.qdev.name = "escc", |
| 959 | 953 |
.qdev.size = sizeof(SerialState), |
| 960 |
.qdev.props = (DevicePropList[]) {
|
|
| 961 |
{.name = "frequency", .type = PROP_TYPE_INT},
|
|
| 962 |
{.name = "it_shift", .type = PROP_TYPE_INT},
|
|
| 963 |
{.name = "disabled", .type = PROP_TYPE_INT},
|
|
| 964 |
{.name = "chrB", .type = PROP_TYPE_PTR},
|
|
| 965 |
{.name = "chrA", .type = PROP_TYPE_PTR},
|
|
| 966 |
{.name = "chnBtype", .type = PROP_TYPE_INT},
|
|
| 967 |
{.name = "chnAtype", .type = PROP_TYPE_INT},
|
|
| 968 |
{.name = NULL}
|
|
| 954 |
.qdev.props = (Property[]) {
|
|
| 955 |
{
|
|
| 956 |
.name = "frequency", |
|
| 957 |
.info = &qdev_prop_uint32, |
|
| 958 |
.offset = offsetof(SerialState, frequency), |
|
| 959 |
}, |
|
| 960 |
{
|
|
| 961 |
.name = "it_shift", |
|
| 962 |
.info = &qdev_prop_uint32, |
|
| 963 |
.offset = offsetof(SerialState, it_shift), |
|
| 964 |
}, |
|
| 965 |
{
|
|
| 966 |
.name = "disabled", |
|
| 967 |
.info = &qdev_prop_uint32, |
|
| 968 |
.offset = offsetof(SerialState, disabled), |
|
| 969 |
}, |
|
| 970 |
{
|
|
| 971 |
.name = "chrB", |
|
| 972 |
.info = &qdev_prop_ptr, |
|
| 973 |
.offset = offsetof(SerialState, chn[1].chr), |
|
| 974 |
}, |
|
| 975 |
{
|
|
| 976 |
.name = "chrA", |
|
| 977 |
.info = &qdev_prop_ptr, |
|
| 978 |
.offset = offsetof(SerialState, chn[0].chr), |
|
| 979 |
}, |
|
| 980 |
{
|
|
| 981 |
.name = "chnBtype", |
|
| 982 |
.info = &qdev_prop_uint32, |
|
| 983 |
.offset = offsetof(SerialState, chn[1].type), |
|
| 984 |
}, |
|
| 985 |
{
|
|
| 986 |
.name = "chnAtype", |
|
| 987 |
.info = &qdev_prop_uint32, |
|
| 988 |
.offset = offsetof(SerialState, chn[0].type), |
|
| 989 |
}, |
|
| 990 |
{/* end of list */}
|
|
| 969 | 991 |
} |
| 970 | 992 |
}; |
| 971 | 993 |
|
| b/hw/esp.c | ||
|---|---|---|
| 650 | 650 |
{
|
| 651 | 651 |
DeviceState *dev; |
| 652 | 652 |
SysBusDevice *s; |
| 653 |
ESPState *esp; |
|
| 653 | 654 |
|
| 654 | 655 |
dev = qdev_create(NULL, "esp"); |
| 655 |
qdev_set_prop_ptr(dev, "dma_memory_read", dma_memory_read); |
|
| 656 |
qdev_set_prop_ptr(dev, "dma_memory_write", dma_memory_write); |
|
| 657 |
qdev_set_prop_ptr(dev, "dma_opaque", dma_opaque); |
|
| 658 |
qdev_set_prop_int(dev, "it_shift", it_shift); |
|
| 656 |
esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
|
| 657 |
esp->dma_memory_read = dma_memory_read; |
|
| 658 |
esp->dma_memory_write = dma_memory_write; |
|
| 659 |
esp->dma_opaque = dma_opaque; |
|
| 660 |
esp->it_shift = it_shift; |
|
| 659 | 661 |
qdev_init(dev); |
| 660 | 662 |
s = sysbus_from_qdev(dev); |
| 661 | 663 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 668 | 670 |
int esp_io_memory; |
| 669 | 671 |
|
| 670 | 672 |
sysbus_init_irq(dev, &s->irq); |
| 671 |
s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", -1); |
|
| 672 | 673 |
assert(s->it_shift != -1); |
| 673 |
s->dma_memory_read = qdev_get_prop_ptr(&dev->qdev, "dma_memory_read"); |
|
| 674 |
s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write"); |
|
| 675 |
s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque"); |
|
| 676 | 674 |
|
| 677 | 675 |
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
| 678 | 676 |
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
| b/hw/etraxfs.c | ||
|---|---|---|
| 88 | 88 |
cpu_irq = cris_pic_init_cpu(env); |
| 89 | 89 |
dev = qdev_create(NULL, "etraxfs,pic"); |
| 90 | 90 |
/* FIXME: Is there a proper way to signal vectors to the CPU core? */ |
| 91 |
qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
|
|
| 91 |
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
|
|
| 92 | 92 |
qdev_init(dev); |
| 93 | 93 |
s = sysbus_from_qdev(dev); |
| 94 | 94 |
sysbus_mmio_map(s, 0, 0x3001c000); |
| b/hw/etraxfs_pic.c | ||
|---|---|---|
| 140 | 140 |
struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev); |
| 141 | 141 |
int intr_vect_regs; |
| 142 | 142 |
|
| 143 |
s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector"); |
|
| 144 | 143 |
qdev_init_gpio_in(&dev->qdev, irq_handler, 32); |
| 145 | 144 |
sysbus_init_irq(dev, &s->parent_irq); |
| 146 | 145 |
sysbus_init_irq(dev, &s->parent_nmi); |
| ... | ... | |
| 149 | 148 |
sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs); |
| 150 | 149 |
} |
| 151 | 150 |
|
| 151 |
static SysBusDeviceInfo etraxfs_pic_info = {
|
|
| 152 |
.init = etraxfs_pic_init, |
|
| 153 |
.qdev.name = "etraxfs,pic", |
|
| 154 |
.qdev.size = sizeof(struct etrax_pic), |
|
| 155 |
.qdev.props = (Property[]) {
|
|
| 156 |
{
|
|
| 157 |
.name = "interrupt_vector", |
|
| 158 |
.info = &qdev_prop_ptr, |
|
| 159 |
.offset = offsetof(struct etrax_pic, interrupt_vector), |
|
| 160 |
}, |
|
| 161 |
{/* end of list */}
|
|
| 162 |
} |
|
| 163 |
}; |
|
| 164 |
|
|
| 152 | 165 |
static void etraxfs_pic_register(void) |
| 153 | 166 |
{
|
| 154 |
sysbus_register_dev("etraxfs,pic", sizeof (struct etrax_pic),
|
|
| 155 |
etraxfs_pic_init); |
|
| 167 |
sysbus_register_withprop(&etraxfs_pic_info); |
|
| 156 | 168 |
} |
| 157 | 169 |
|
| 158 | 170 |
device_init(etraxfs_pic_register) |
| b/hw/fdc.c | ||
|---|---|---|
| 511 | 511 |
/* Floppy drives */ |
| 512 | 512 |
fdrive_t drives[MAX_FD]; |
| 513 | 513 |
int reset_sensei; |
| 514 |
uint32_t strict_io; |
|
| 515 |
uint32_t mem_mapped; |
|
| 514 | 516 |
}; |
| 515 | 517 |
|
| 516 | 518 |
static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
| ... | ... | |
| 1898 | 1900 |
fdctrl_t *fdctrl; |
| 1899 | 1901 |
|
| 1900 | 1902 |
dev = qdev_create(NULL, "fdc"); |
| 1901 |
qdev_set_prop_int(dev, "strict_io", 0);
|
|
| 1902 |
qdev_set_prop_int(dev, "mem_mapped", mem_mapped);
|
|
| 1903 |
qdev_set_prop_int(dev, "sun4m", 0);
|
|
| 1903 |
qdev_prop_set_uint32(dev, "strict_io", 0);
|
|
| 1904 |
qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped);
|
|
| 1905 |
qdev_prop_set_uint32(dev, "sun4m", 0);
|
|
| 1904 | 1906 |
qdev_init(dev); |
| 1905 | 1907 |
s = sysbus_from_qdev(dev); |
| 1906 | 1908 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 1931 | 1933 |
fdctrl_t *fdctrl; |
| 1932 | 1934 |
|
| 1933 | 1935 |
dev = qdev_create(NULL, "fdc"); |
| 1934 |
qdev_set_prop_int(dev, "strict_io", 1);
|
|
| 1935 |
qdev_set_prop_int(dev, "mem_mapped", 1);
|
|
| 1936 |
qdev_set_prop_int(dev, "sun4m", 1);
|
|
| 1936 |
qdev_prop_set_uint32(dev, "strict_io", 1);
|
|
| 1937 |
qdev_prop_set_uint32(dev, "mem_mapped", 1);
|
|
| 1938 |
qdev_prop_set_uint32(dev, "sun4m", 1);
|
|
| 1937 | 1939 |
qdev_init(dev); |
| 1938 | 1940 |
s = sysbus_from_qdev(dev); |
| 1939 | 1941 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 1953 | 1955 |
|
| 1954 | 1956 |
sysbus_init_irq(dev, &s->irq); |
| 1955 | 1957 |
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); |
| 1956 |
if (qdev_get_prop_int(&dev->qdev, "strict_io", 0)) {
|
|
| 1958 |
if (s->strict_io) {
|
|
| 1957 | 1959 |
io = cpu_register_io_memory(fdctrl_mem_read_strict, |
| 1958 | 1960 |
fdctrl_mem_write_strict, s); |
| 1959 | 1961 |
} else {
|
| ... | ... | |
| 1967 | 1969 |
.init = fdc_init1, |
| 1968 | 1970 |
.qdev.name = "fdc", |
| 1969 | 1971 |
.qdev.size = sizeof(fdctrl_t), |
| 1970 |
.qdev.props = (DevicePropList[]) {
|
|
| 1971 |
{.name = "io_base", .type = PROP_TYPE_INT},
|
|
| 1972 |
{.name = "strict_io", .type = PROP_TYPE_INT},
|
|
| 1973 |
{.name = "mem_mapped", .type = PROP_TYPE_INT},
|
|
| 1974 |
{.name = "sun4m", .type = PROP_TYPE_INT},
|
|
| 1975 |
{.name = NULL}
|
|
| 1972 |
.qdev.props = (Property[]) {
|
|
| 1973 |
{
|
|
| 1974 |
.name = "io_base", |
|
| 1975 |
.info = &qdev_prop_uint32, |
|
| 1976 |
.offset = offsetof(fdctrl_t, io_base), |
|
| 1977 |
}, |
|
| 1978 |
{
|
|
| 1979 |
.name = "strict_io", |
|
| 1980 |
.info = &qdev_prop_uint32, |
|
| 1981 |
.offset = offsetof(fdctrl_t, strict_io), |
|
| 1982 |
}, |
|
| 1983 |
{
|
|
| 1984 |
.name = "mem_mapped", |
|
| 1985 |
.info = &qdev_prop_uint32, |
|
| 1986 |
.offset = offsetof(fdctrl_t, mem_mapped), |
|
| 1987 |
}, |
|
| 1988 |
{
|
|
| 1989 |
.name = "sun4m", |
|
| 1990 |
.info = &qdev_prop_uint32, |
|
| 1991 |
.offset = offsetof(fdctrl_t, sun4m), |
|
| 1992 |
}, |
|
| 1993 |
{/* end of properties */}
|
|
| 1976 | 1994 |
} |
| 1977 | 1995 |
}; |
| 1978 | 1996 |
|
| b/hw/i2c.c | ||
|---|---|---|
| 20 | 20 |
static struct BusInfo i2c_bus_info = {
|
| 21 | 21 |
.name = "I2C", |
| 22 | 22 |
.size = sizeof(i2c_bus), |
| 23 |
.props = (Property[]) {
|
|
| 24 |
{
|
|
| 25 |
.name = "address", |
|
| 26 |
.info = &qdev_prop_uint32, |
|
| 27 |
.offset = offsetof(struct i2c_slave, address), |
|
| 28 |
}, |
|
| 29 |
{/* end of list */}
|
|
| 30 |
} |
|
| 23 | 31 |
}; |
| 24 | 32 |
|
| 25 | 33 |
static void i2c_bus_save(QEMUFile *f, void *opaque) |
| ... | ... | |
| 151 | 159 |
i2c_slave *s = I2C_SLAVE_FROM_QDEV(dev); |
| 152 | 160 |
|
| 153 | 161 |
s->info = info; |
| 154 |
s->address = qdev_get_prop_int(dev, "address", 0); |
|
| 155 | 162 |
|
| 156 | 163 |
info->init(s); |
| 157 | 164 |
} |
| ... | ... | |
| 169 | 176 |
DeviceState *dev; |
| 170 | 177 |
|
| 171 | 178 |
dev = qdev_create(&bus->qbus, name); |
| 172 |
qdev_set_prop_int(dev, "address", addr);
|
|
| 179 |
qdev_prop_set_uint32(dev, "address", addr);
|
|
| 173 | 180 |
qdev_init(dev); |
| 174 | 181 |
return dev; |
| 175 | 182 |
} |
| b/hw/i2c.h | ||
|---|---|---|
| 40 | 40 |
I2CSlaveInfo *info; |
| 41 | 41 |
|
| 42 | 42 |
/* Remaining fields for internal use by the I2C code. */ |
| 43 |
int address;
|
|
| 43 |
uint32_t address;
|
|
| 44 | 44 |
}; |
| 45 | 45 |
|
| 46 | 46 |
i2c_bus *i2c_init_bus(DeviceState *parent, const char *name); |
| b/hw/integratorcp.c | ||
|---|---|---|
| 17 | 17 |
|
| 18 | 18 |
typedef struct {
|
| 19 | 19 |
SysBusDevice busdev; |
| 20 |
uint32_t memsz; |
|
| 20 | 21 |
uint32_t flash_offset; |
| 21 | 22 |
uint32_t cm_osc; |
| 22 | 23 |
uint32_t cm_ctrl; |
| ... | ... | |
| 230 | 231 |
{
|
| 231 | 232 |
int iomemtype; |
| 232 | 233 |
integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev); |
| 233 |
int memsz; |
|
| 234 | 234 |
|
| 235 |
memsz = qdev_get_prop_int(&dev->qdev, "memsz", 0); |
|
| 236 | 235 |
s->cm_osc = 0x01000048; |
| 237 | 236 |
/* ??? What should the high bits of this value be? */ |
| 238 | 237 |
s->cm_auxosc = 0x0007feff; |
| 239 | 238 |
s->cm_sdram = 0x00011122; |
| 240 |
if (memsz >= 256) {
|
|
| 239 |
if (s->memsz >= 256) {
|
|
| 241 | 240 |
integrator_spd[31] = 64; |
| 242 | 241 |
s->cm_sdram |= 0x10; |
| 243 |
} else if (memsz >= 128) {
|
|
| 242 |
} else if (s->memsz >= 128) {
|
|
| 244 | 243 |
integrator_spd[31] = 32; |
| 245 | 244 |
s->cm_sdram |= 0x0c; |
| 246 |
} else if (memsz >= 64) {
|
|
| 245 |
} else if (s->memsz >= 64) {
|
|
| 247 | 246 |
integrator_spd[31] = 16; |
| 248 | 247 |
s->cm_sdram |= 0x08; |
| 249 |
} else if (memsz >= 32) {
|
|
| 248 |
} else if (s->memsz >= 32) {
|
|
| 250 | 249 |
integrator_spd[31] = 4; |
| 251 | 250 |
s->cm_sdram |= 0x04; |
| 252 | 251 |
} else {
|
| ... | ... | |
| 475 | 474 |
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM); |
| 476 | 475 |
|
| 477 | 476 |
dev = qdev_create(NULL, "integrator_core"); |
| 478 |
qdev_set_prop_int(dev, "memsz", ram_size >> 20);
|
|
| 477 |
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
|
|
| 479 | 478 |
qdev_init(dev); |
| 480 | 479 |
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
| 481 | 480 |
|
| ... | ... | |
| 522 | 521 |
|
| 523 | 522 |
machine_init(integratorcp_machine_init); |
| 524 | 523 |
|
| 524 |
static SysBusDeviceInfo core_info = {
|
|
| 525 |
.init = integratorcm_init, |
|
| 526 |
.qdev.name = "integrator_core", |
|
| 527 |
.qdev.size = sizeof(integratorcm_state), |
|
| 528 |
.qdev.props = (Property[]) {
|
|
| 529 |
{
|
|
| 530 |
.name = "memsz", |
|
| 531 |
.info = &qdev_prop_uint32, |
|
| 532 |
.offset = offsetof(integratorcm_state, memsz), |
|
| 533 |
}, |
|
| 534 |
{/* end of list */}
|
|
| 535 |
} |
|
| 536 |
}; |
|
| 537 |
|
|
| 525 | 538 |
static void integratorcp_register_devices(void) |
| 526 | 539 |
{
|
| 527 | 540 |
sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
|
| 528 |
sysbus_register_dev("integrator_core", sizeof(integratorcm_state),
|
|
| 529 |
integratorcm_init); |
|
| 541 |
sysbus_register_withprop(&core_info); |
|
| 530 | 542 |
} |
| 531 | 543 |
|
| 532 | 544 |
device_init(integratorcp_register_devices) |
| b/hw/iommu.c | ||
|---|---|---|
| 373 | 373 |
IOMMUState *d; |
| 374 | 374 |
|
| 375 | 375 |
dev = qdev_create(NULL, "iommu"); |
| 376 |
qdev_set_prop_int(dev, "version", version);
|
|
| 376 |
qdev_prop_set_uint32(dev, "version", version);
|
|
| 377 | 377 |
qdev_init(dev); |
| 378 | 378 |
s = sysbus_from_qdev(dev); |
| 379 | 379 |
sysbus_connect_irq(s, 0, irq); |
| ... | ... | |
| 391 | 391 |
|
| 392 | 392 |
sysbus_init_irq(dev, &s->irq); |
| 393 | 393 |
|
| 394 |
s->version = qdev_get_prop_int(&dev->qdev, "version", 0); |
|
| 395 |
|
|
| 396 | 394 |
io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); |
| 397 | 395 |
sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); |
| 398 | 396 |
|
| ... | ... | |
| 405 | 403 |
.init = iommu_init1, |
| 406 | 404 |
.qdev.name = "iommu", |
| 407 | 405 |
.qdev.size = sizeof(IOMMUState), |
| 408 |
.qdev.props = (DevicePropList[]) {
|
|
| 409 |
{.name = "version", .type = PROP_TYPE_INT},
|
|
| 410 |
{.name = NULL}
|
|
| 406 |
.qdev.props = (Property[]) {
|
|
| 407 |
{
|
|
| 408 |
.name = "version", |
|
| 409 |
.info = &qdev_prop_uint32, |
|
| 410 |
.offset = offsetof(IOMMUState, version), |
|
| 411 |
}, |
|
| 412 |
{/* end of property list */}
|
|
| 411 | 413 |
} |
| 412 | 414 |
}; |
| 413 | 415 |
|
| b/hw/m48t59.c | ||
|---|---|---|
| 43 | 43 |
struct m48t59_t {
|
| 44 | 44 |
SysBusDevice busdev; |
| 45 | 45 |
/* Model parameters */ |
| 46 |
int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
|
|
| 46 |
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
|
|
| 47 | 47 |
/* Hardware parameters */ |
| 48 | 48 |
qemu_irq IRQ; |
| 49 | 49 |
uint32_t io_base; |
| 50 |
uint16_t size;
|
|
| 50 |
uint32_t size;
|
|
| 51 | 51 |
/* RTC management */ |
| 52 | 52 |
time_t time_offset; |
| 53 | 53 |
time_t stop_time; |
| ... | ... | |
| 623 | 623 |
m48t59_t *d; |
| 624 | 624 |
|
| 625 | 625 |
dev = qdev_create(NULL, "m48t59"); |
| 626 |
qdev_set_prop_int(dev, "type", type);
|
|
| 627 |
qdev_set_prop_int(dev, "size", size);
|
|
| 628 |
qdev_set_prop_int(dev, "io_base", io_base);
|
|
| 626 |
qdev_prop_set_uint32(dev, "type", type);
|
|
| 627 |
qdev_prop_set_uint32(dev, "size", size);
|
|
| 628 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
|
| 629 | 629 |
qdev_init(dev); |
| 630 | 630 |
s = sysbus_from_qdev(dev); |
| 631 | 631 |
sysbus_connect_irq(s, 0, IRQ); |
| ... | ... | |
| 647 | 647 |
m48t59_t *s = FROM_SYSBUS(m48t59_t, dev); |
| 648 | 648 |
int mem_index; |
| 649 | 649 |
|
| 650 |
s->size = qdev_get_prop_int(&dev->qdev, "size", -1); |
|
| 651 | 650 |
s->buffer = qemu_mallocz(s->size); |
| 652 | 651 |
sysbus_init_irq(dev, &s->IRQ); |
| 653 |
s->io_base = qdev_get_prop_int(&dev->qdev, "io_base", 0); |
|
| 654 |
s->type = qdev_get_prop_int(&dev->qdev, "type", -1); |
|
| 655 | 652 |
|
| 656 | 653 |
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s); |
| 657 | 654 |
sysbus_init_mmio(dev, s->size, mem_index); |
| ... | ... | |
| 666 | 663 |
register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
|
| 667 | 664 |
} |
| 668 | 665 |
|
| 666 |
static SysBusDeviceInfo m48t59_info = {
|
|
| 667 |
.init = m48t59_init1, |
|
| 668 |
.qdev.name = "m48t59", |
|
| 669 |
.qdev.size = sizeof(m48t59_t), |
|
| 670 |
.qdev.props = (Property[]) {
|
|
| 671 |
{
|
|
| 672 |
.name = "size", |
|
| 673 |
.info = &qdev_prop_uint32, |
|
| 674 |
.offset = offsetof(m48t59_t, size), |
|
| 675 |
.defval = (uint32_t[]) { -1 },
|
|
| 676 |
},{
|
|
| 677 |
.name = "type", |
|
| 678 |
.info = &qdev_prop_uint32, |
|
| 679 |
.offset = offsetof(m48t59_t, type), |
|
| 680 |
.defval = (uint32_t[]) { -1 },
|
|
| 681 |
},{
|
|
| 682 |
.name = "io_base", |
|
| 683 |
.info = &qdev_prop_hex32, |
|
| 684 |
.offset = offsetof(m48t59_t, io_base), |
|
| 685 |
}, |
|
| 686 |
{/* end of list */}
|
|
| 687 |
} |
|
| 688 |
}; |
|
| 689 |
|
|
| 669 | 690 |
static void m48t59_register_devices(void) |
| 670 | 691 |
{
|
| 671 |
sysbus_register_dev("m48t59", sizeof(m48t59_t), m48t59_init1);
|
|
| 692 |
sysbus_register_withprop(&m48t59_info);
|
|
| 672 | 693 |
} |
| 673 | 694 |
|
| 674 | 695 |
device_init(m48t59_register_devices) |
| b/hw/mips_malta.c | ||
|---|---|---|
| 914 | 914 |
/* TODO: Populate SPD eeprom data. */ |
| 915 | 915 |
DeviceState *eeprom; |
| 916 | 916 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
| 917 |
qdev_set_prop_int(eeprom, "address", 0x50 + i);
|
|
| 918 |
qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
|
|
| 917 |
qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
|
|
| 918 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
|
|
| 919 | 919 |
qdev_init(eeprom); |
| 920 | 920 |
} |
| 921 | 921 |
pit = pit_init(0x40, i8259[0]); |
| b/hw/musicpal.c | ||
|---|---|---|
| 1578 | 1578 |
|
| 1579 | 1579 |
qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
| 1580 | 1580 |
dev = qdev_create(NULL, "mv88w8618_eth"); |
| 1581 |
qdev_set_netdev(dev, &nd_table[0]);
|
|
| 1581 |
dev->nd = &nd_table[0];
|
|
| 1582 | 1582 |
qdev_init(dev); |
| 1583 | 1583 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE); |
| 1584 | 1584 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]); |
| b/hw/pc.c | ||
|---|---|---|
| 1402 | 1402 |
for (i = 0; i < 8; i++) {
|
| 1403 | 1403 |
DeviceState *eeprom; |
| 1404 | 1404 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
| 1405 |
qdev_set_prop_int(eeprom, "address", 0x50 + i);
|
|
| 1406 |
qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
|
|
| 1405 |
qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
|
|
| 1406 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
|
|
| 1407 | 1407 |
qdev_init(eeprom); |
| 1408 | 1408 |
} |
| 1409 | 1409 |
} |
| b/hw/pci.c | ||
|---|---|---|
| 59 | 59 |
.name = "PCI", |
| 60 | 60 |
.size = sizeof(PCIBus), |
| 61 | 61 |
.print_dev = pcibus_dev_print, |
| 62 |
.props = (Property[]) {
|
|
| 63 |
{
|
|
| 64 |
.name = "devfn", |
|
| 65 |
.info = &qdev_prop_uint32, |
|
| 66 |
.offset = offsetof(PCIDevice, devfn), |
|
| 67 |
.defval = (uint32_t[]) { -1 },
|
|
| 68 |
}, |
|
| 69 |
{/* end of list */}
|
|
| 70 |
} |
|
| 62 | 71 |
}; |
| 63 | 72 |
|
| 64 | 73 |
static void pci_update_mappings(PCIDevice *d); |
| ... | ... | |
| 770 | 779 |
} |
| 771 | 780 |
|
| 772 | 781 |
dev = qdev_create(&bus->qbus, name); |
| 773 |
qdev_set_prop_int(dev, "devfn", devfn);
|
|
| 782 |
qdev_prop_set_uint32(dev, "devfn", devfn);
|
|
| 774 | 783 |
return (PCIDevice *)dev; |
| 775 | 784 |
} |
| 776 | 785 |
|
| ... | ... | |
| 813 | 822 |
if (strcmp(nd->model, pci_nic_models[i]) == 0) {
|
| 814 | 823 |
pci_dev = pci_create(pci_nic_names[i], devaddr); |
| 815 | 824 |
dev = &pci_dev->qdev; |
| 816 |
qdev_set_netdev(dev, nd);
|
|
| 825 |
dev->nd = nd;
|
|
| 817 | 826 |
qdev_init(dev); |
| 818 | 827 |
nd->private = dev; |
| 819 | 828 |
return pci_dev; |
| ... | ... | |
| 891 | 900 |
int devfn; |
| 892 | 901 |
|
| 893 | 902 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
| 894 |
devfn = qdev_get_prop_int(qdev, "devfn", -1);
|
|
| 903 |
devfn = pci_dev->devfn;
|
|
| 895 | 904 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
| 896 | 905 |
info->config_read, info->config_write); |
| 897 | 906 |
assert(pci_dev); |
| ... | ... | |
| 918 | 927 |
DeviceState *dev; |
| 919 | 928 |
|
| 920 | 929 |
dev = qdev_create(&bus->qbus, name); |
| 921 |
qdev_set_prop_int(dev, "devfn", devfn);
|
|
| 930 |
qdev_prop_set_uint32(dev, "devfn", devfn);
|
|
| 922 | 931 |
qdev_init(dev); |
| 923 | 932 |
|
| 924 | 933 |
return (PCIDevice *)dev; |
| b/hw/pcnet.c | ||
|---|---|---|
| 2128 | 2128 |
s->mmio_index = |
| 2129 | 2129 |
cpu_register_io_memory(lance_mem_read, lance_mem_write, d); |
| 2130 | 2130 |
|
| 2131 |
s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma"); |
|
| 2132 |
|
|
| 2133 | 2131 |
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); |
| 2134 | 2132 |
|
| 2135 | 2133 |
sysbus_init_mmio(dev, 4, s->mmio_index); |
| ... | ... | |
| 2141 | 2139 |
|
| 2142 | 2140 |
pcnet_common_init(&dev->qdev, s, lance_cleanup); |
| 2143 | 2141 |
} |
| 2142 |
|
|
| 2143 |
static SysBusDeviceInfo lance_info = {
|
|
| 2144 |
.init = lance_init, |
|
| 2145 |
.qdev.name = "lance", |
|
| 2146 |
.qdev.size = sizeof(SysBusPCNetState), |
|
| 2147 |
.qdev.props = (Property[]) {
|
|
| 2148 |
{
|
|
| 2149 |
.name = "dma", |
|
| 2150 |
.info = &qdev_prop_ptr, |
|
| 2151 |
.offset = offsetof(SysBusPCNetState, state.dma_opaque), |
|
| 2152 |
}, |
|
| 2153 |
{/* end of list */}
|
|
| 2154 |
} |
|
| 2155 |
}; |
|
| 2156 |
|
|
| 2144 | 2157 |
#endif /* TARGET_SPARC */ |
| 2145 | 2158 |
|
| 2146 | 2159 |
static PCIDeviceInfo pcnet_info = {
|
| ... | ... | |
| 2153 | 2166 |
{
|
| 2154 | 2167 |
pci_qdev_register(&pcnet_info); |
| 2155 | 2168 |
#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) |
| 2156 |
sysbus_register_dev("lance", sizeof(SysBusPCNetState), lance_init);
|
|
| 2169 |
sysbus_register_withprop(&lance_info);
|
|
| 2157 | 2170 |
#endif |
| 2158 | 2171 |
} |
| 2159 | 2172 |
|
| b/hw/qdev-addr.c | ||
|---|---|---|
| 1 |
#include "qdev.h" |
|
| 2 |
#include "qdev-addr.h" |
|
| 3 |
#include "targphys.h" |
|
| 4 |
|
|
| 5 |
/* --- target physical address --- */ |
|
| 6 |
|
|
| 7 |
static int parse_taddr(DeviceState *dev, Property *prop, const char *str) |
|
| 8 |
{
|
|
| 9 |
target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 10 |
|
|
| 11 |
*ptr = strtoull(str, NULL, 16); |
|
| 12 |
return 0; |
|
| 13 |
} |
|
| 14 |
|
|
| 15 |
static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 16 |
{
|
|
| 17 |
target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 18 |
return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr); |
|
| 19 |
} |
|
| 20 |
|
|
| 21 |
PropertyInfo qdev_prop_taddr = {
|
|
| 22 |
.name = "taddr", |
|
| 23 |
.type = PROP_TYPE_TADDR, |
|
| 24 |
.size = sizeof(target_phys_addr_t), |
|
| 25 |
.parse = parse_taddr, |
|
| 26 |
.print = print_taddr, |
|
| 27 |
}; |
|
| 28 |
|
|
| 29 |
void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value) |
|
| 30 |
{
|
|
| 31 |
qdev_prop_set(dev, name, &value, PROP_TYPE_TADDR); |
|
| 32 |
} |
|
| b/hw/qdev-addr.h | ||
|---|---|---|
| 1 |
extern PropertyInfo qdev_prop_taddr; |
|
| 2 |
void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value); |
|
| b/hw/qdev-properties.c | ||
|---|---|---|
| 1 |
#include "qdev.h" |
|
| 2 |
|
|
| 3 |
void *qdev_get_prop_ptr(DeviceState *dev, Property *prop) |
|
| 4 |
{
|
|
| 5 |
void *ptr = dev; |
|
| 6 |
ptr += prop->offset; |
|
| 7 |
return ptr; |
|
| 8 |
} |
|
| 9 |
|
|
| 10 |
/* --- 16bit integer --- */ |
|
| 11 |
|
|
| 12 |
static int parse_uint16(DeviceState *dev, Property *prop, const char *str) |
|
| 13 |
{
|
|
| 14 |
uint16_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 15 |
const char *fmt; |
|
| 16 |
|
|
| 17 |
/* accept both hex and decimal */ |
|
| 18 |
fmt = strncasecmp(str, "0x",2) == 0 ? "%" PRIx16 : "%" PRIu16; |
|
| 19 |
if (sscanf(str, fmt, ptr) != 1) |
|
| 20 |
return -1; |
|
| 21 |
return 0; |
|
| 22 |
} |
|
| 23 |
|
|
| 24 |
static int print_uint16(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 25 |
{
|
|
| 26 |
uint16_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 27 |
return snprintf(dest, len, "%" PRIu16, *ptr); |
|
| 28 |
} |
|
| 29 |
|
|
| 30 |
PropertyInfo qdev_prop_uint16 = {
|
|
| 31 |
.name = "uint16", |
|
| 32 |
.type = PROP_TYPE_UINT16, |
|
| 33 |
.size = sizeof(uint16_t), |
|
| 34 |
.parse = parse_uint16, |
|
| 35 |
.print = print_uint16, |
|
| 36 |
}; |
|
| 37 |
|
|
| 38 |
/* --- 32bit integer --- */ |
|
| 39 |
|
|
| 40 |
static int parse_uint32(DeviceState *dev, Property *prop, const char *str) |
|
| 41 |
{
|
|
| 42 |
uint32_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 43 |
const char *fmt; |
|
| 44 |
|
|
| 45 |
/* accept both hex and decimal */ |
|
| 46 |
fmt = strncasecmp(str, "0x",2) == 0 ? "%" PRIx32 : "%" PRIu32; |
|
| 47 |
if (sscanf(str, fmt, ptr) != 1) |
|
| 48 |
return -1; |
|
| 49 |
return 0; |
|
| 50 |
} |
|
| 51 |
|
|
| 52 |
static int print_uint32(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 53 |
{
|
|
| 54 |
uint32_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 55 |
return snprintf(dest, len, "%" PRIu32, *ptr); |
|
| 56 |
} |
|
| 57 |
|
|
| 58 |
PropertyInfo qdev_prop_uint32 = {
|
|
| 59 |
.name = "uint32", |
|
| 60 |
.type = PROP_TYPE_UINT32, |
|
| 61 |
.size = sizeof(uint32_t), |
|
| 62 |
.parse = parse_uint32, |
|
| 63 |
.print = print_uint32, |
|
| 64 |
}; |
|
| 65 |
|
|
| 66 |
/* --- 32bit hex value --- */ |
|
| 67 |
|
|
| 68 |
static int parse_hex32(DeviceState *dev, Property *prop, const char *str) |
|
| 69 |
{
|
|
| 70 |
uint32_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 71 |
|
|
| 72 |
if (sscanf(str, "%" PRIx32, ptr) != 1) |
|
| 73 |
return -1; |
|
| 74 |
return 0; |
|
| 75 |
} |
|
| 76 |
|
|
| 77 |
static int print_hex32(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 78 |
{
|
|
| 79 |
uint32_t *ptr = qdev_get_prop_ptr(dev, prop); |
|
| 80 |
return snprintf(dest, len, "0x%" PRIx32, *ptr); |
|
| 81 |
} |
|
| 82 |
|
|
| 83 |
PropertyInfo qdev_prop_hex32 = {
|
|
| 84 |
.name = "hex32", |
|
| 85 |
.type = PROP_TYPE_UINT32, |
|
| 86 |
.size = sizeof(uint32_t), |
|
| 87 |
.parse = parse_hex32, |
|
| 88 |
.print = print_hex32, |
|
| 89 |
}; |
|
| 90 |
|
|
| 91 |
/* --- pointer --- */ |
|
| 92 |
|
|
| 93 |
static int print_ptr(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 94 |
{
|
|
| 95 |
void **ptr = qdev_get_prop_ptr(dev, prop); |
|
| 96 |
return snprintf(dest, len, "<%p>", *ptr); |
|
| 97 |
} |
|
| 98 |
|
|
| 99 |
PropertyInfo qdev_prop_ptr = {
|
|
| 100 |
.name = "ptr", |
|
| 101 |
.type = PROP_TYPE_PTR, |
|
| 102 |
.size = sizeof(void*), |
|
| 103 |
.print = print_ptr, |
|
| 104 |
}; |
|
| 105 |
|
|
| 106 |
/* --- mac address --- */ |
|
| 107 |
|
|
| 108 |
/* |
|
| 109 |
* accepted syntax versions: |
|
| 110 |
* 01:02:03:04:05:06 |
|
| 111 |
* 01-02-03-04-05-06 |
|
| 112 |
*/ |
|
| 113 |
static int parse_mac(DeviceState *dev, Property *prop, const char *str) |
|
| 114 |
{
|
|
| 115 |
uint8_t *mac = qdev_get_prop_ptr(dev, prop); |
|
| 116 |
int i, pos; |
|
| 117 |
char *p; |
|
| 118 |
|
|
| 119 |
for (i = 0, pos = 0; i < 6; i++, pos += 3) {
|
|
| 120 |
if (!isxdigit(str[pos])) |
|
| 121 |
return -1; |
|
| 122 |
if (!isxdigit(str[pos+1])) |
|
| 123 |
return -1; |
|
| 124 |
if (i == 5 && str[pos+2] != '\0') |
|
| 125 |
return -1; |
|
| 126 |
if (str[pos+2] != ':' && str[pos+2] != '-') |
|
| 127 |
return -1; |
|
| 128 |
mac[i] = strtol(str+pos, &p, 16); |
|
| 129 |
} |
|
| 130 |
return 0; |
|
| 131 |
} |
|
| 132 |
|
|
| 133 |
static int print_mac(DeviceState *dev, Property *prop, char *dest, size_t len) |
|
| 134 |
{
|
|
| 135 |
uint8_t *mac = qdev_get_prop_ptr(dev, prop); |
|
| 136 |
return snprintf(dest, len, "%02x:%02x:%02x:%02x:%02x:%02x", |
|
| 137 |
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
|
| 138 |
} |
|
| 139 |
|
|
| 140 |
PropertyInfo qdev_prop_macaddr = {
|
|
| 141 |
.name = "mac-addr", |
|
| 142 |
.type = PROP_TYPE_MACADDR, |
|
| 143 |
.size = 6, |
|
| 144 |
.parse = parse_mac, |
|
| 145 |
.print = print_mac, |
|
| 146 |
}; |
|
| 147 |
|
|
| 148 |
/* --- public helpers --- */ |
|
| 149 |
|
|
| 150 |
static Property *qdev_prop_walk(Property *props, const char *name) |
|
| 151 |
{
|
|
| 152 |
if (!props) |
|
| 153 |
return NULL; |
|
| 154 |
while (props->name) {
|
|
| 155 |
if (strcmp(props->name, name) == 0) |
|
| 156 |
return props; |
|
| 157 |
props++; |
|
| 158 |
} |
|
| 159 |
return NULL; |
|
| 160 |
} |
|
| 161 |
|
|
| 162 |
static Property *qdev_prop_find(DeviceState *dev, const char *name) |
|
| 163 |
{
|
|
| 164 |
Property *prop; |
|
| 165 |
|
|
| 166 |
/* device properties */ |
|
| 167 |
prop = qdev_prop_walk(dev->info->props, name); |
|
| 168 |
if (prop) |
|
| 169 |
return prop; |
|
| 170 |
|
|
| 171 |
/* bus properties */ |
|
| 172 |
prop = qdev_prop_walk(dev->parent_bus->info->props, name); |
|
| 173 |
if (prop) |
|
| 174 |
return prop; |
|
| 175 |
|
|
| 176 |
return NULL; |
|
| 177 |
} |
|
| 178 |
|
|
| 179 |
int qdev_prop_parse(DeviceState *dev, const char *name, const char *value) |
|
| 180 |
{
|
|
| 181 |
Property *prop; |
|
| 182 |
|
|
| 183 |
prop = qdev_prop_find(dev, name); |
|
| 184 |
if (!prop) {
|
|
| 185 |
fprintf(stderr, "property \"%s.%s\" not found\n", |
|
| 186 |
dev->info->name, name); |
|
| 187 |
return -1; |
|
| 188 |
} |
|
| 189 |
if (!prop->info->parse) {
|
|
| 190 |
fprintf(stderr, "property \"%s.%s\" has no parser\n", |
|
| 191 |
dev->info->name, name); |
|
| 192 |
return -1; |
|
| 193 |
} |
|
| 194 |
return prop->info->parse(dev, prop, value); |
|
| 195 |
} |
|
| 196 |
|
|
| 197 |
void qdev_prop_set(DeviceState *dev, const char *name, void *src, enum PropertyType type) |
|
| 198 |
{
|
|
| 199 |
Property *prop; |
|
| 200 |
void *dst; |
|
| 201 |
|
|
| 202 |
prop = qdev_prop_find(dev, name); |
|
| 203 |
if (!prop) {
|
|
| 204 |
fprintf(stderr, "%s: property \"%s.%s\" not found\n", |
|
| 205 |
__FUNCTION__, dev->info->name, name); |
|
| 206 |
abort(); |
|
| 207 |
} |
|
| 208 |
if (prop->info->type != type) {
|
|
| 209 |
fprintf(stderr, "%s: property \"%s.%s\" type mismatch\n", |
|
| 210 |
__FUNCTION__, dev->info->name, name); |
|
| 211 |
abort(); |
|
| 212 |
} |
|
| 213 |
dst = qdev_get_prop_ptr(dev, prop); |
|
| 214 |
memcpy(dst, src, prop->info->size); |
|
| 215 |
} |
|
| 216 |
|
|
| 217 |
void qdev_prop_set_uint16(DeviceState *dev, const char *name, uint16_t value) |
|
| 218 |
{
|
|
| 219 |
qdev_prop_set(dev, name, &value, PROP_TYPE_UINT16); |
|
| 220 |
} |
|
| 221 |
|
|
| 222 |
void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value) |
|
| 223 |
{
|
|
| 224 |
qdev_prop_set(dev, name, &value, PROP_TYPE_UINT32); |
|
| 225 |
} |
|
| 226 |
|
|
| 227 |
void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value) |
|
| 228 |
{
|
|
| 229 |
qdev_prop_set(dev, name, &value, PROP_TYPE_PTR); |
|
| 230 |
} |
|
| 231 |
|
|
| 232 |
void qdev_prop_set_defaults(DeviceState *dev, Property *props) |
|
| 233 |
{
|
|
| 234 |
char *dst; |
|
| 235 |
|
|
| 236 |
if (!props) |
|
| 237 |
return; |
|
| 238 |
while (props->name) {
|
|
| 239 |
if (props->defval) {
|
|
| 240 |
dst = qdev_get_prop_ptr(dev, props); |
|
| 241 |
memcpy(dst, props->defval, props->info->size); |
|
| 242 |
} |
|
| 243 |
props++; |
|
| 244 |
} |
|
| 245 |
} |
|
| 246 |
|
|
| b/hw/qdev.c | ||
|---|---|---|
| 30 | 30 |
#include "sysemu.h" |
| 31 | 31 |
#include "monitor.h" |
| 32 | 32 |
|
| 33 |
struct DeviceProperty {
|
|
| 34 |
const char *name; |
|
| 35 |
DevicePropType type; |
|
| 36 |
union {
|
|
| 37 |
uint64_t i; |
|
| 38 |
void *ptr; |
|
| 39 |
} value; |
|
| 40 |
DeviceProperty *next; |
|
| 41 |
}; |
|
| 42 |
|
|
| 43 | 33 |
/* This is a nasty hack to allow passing a NULL bus to qdev_create. */ |
| 44 | 34 |
static BusState *main_system_bus; |
| 45 | 35 |
extern struct BusInfo system_bus_info; |
| ... | ... | |
| 85 | 75 |
dev = qemu_mallocz(info->size); |
| 86 | 76 |
dev->info = info; |
| 87 | 77 |
dev->parent_bus = bus; |
| 78 |
qdev_prop_set_defaults(dev, dev->info->props); |
|
| 79 |
qdev_prop_set_defaults(dev, dev->parent_bus->info->props); |
|
| 88 | 80 |
LIST_INSERT_HEAD(&bus->children, dev, sibling); |
| 89 | 81 |
return dev; |
| 90 | 82 |
} |
| ... | ... | |
| 104 | 96 |
free(dev); |
| 105 | 97 |
} |
| 106 | 98 |
|
| 107 |
static DeviceProperty *create_prop(DeviceState *dev, const char *name, |
|
| 108 |
DevicePropType type) |
|
| 109 |
{
|
|
| 110 |
DeviceProperty *prop; |
|
| 111 |
|
|
| 112 |
/* TODO: Check for duplicate properties. */ |
|
| 113 |
prop = qemu_mallocz(sizeof(*prop)); |
|
| 114 |
prop->name = qemu_strdup(name); |
|
| 115 |
prop->type = type; |
|
| 116 |
prop->next = dev->props; |
|
| 117 |
dev->props = prop; |
|
| 118 |
|
|
| 119 |
return prop; |
|
| 120 |
} |
|
| 121 |
|
|
| 122 |
void qdev_set_prop_int(DeviceState *dev, const char *name, uint64_t value) |
|
| 123 |
{
|
|
| 124 |
DeviceProperty *prop; |
|
| 125 |
|
|
| 126 |
prop = create_prop(dev, name, PROP_TYPE_INT); |
|
| 127 |
prop->value.i = value; |
|
| 128 |
} |
|
| 129 |
|
|
| 130 |
void qdev_set_prop_dev(DeviceState *dev, const char *name, DeviceState *value) |
|
| 131 |
{
|
|
| 132 |
DeviceProperty *prop; |
|
| 133 |
|
|
| 134 |
prop = create_prop(dev, name, PROP_TYPE_DEV); |
|
| 135 |
prop->value.ptr = value; |
|
| 136 |
} |
|
| 137 |
|
|
| 138 |
void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value) |
|
| 139 |
{
|
|
| 140 |
DeviceProperty *prop; |
|
| 141 |
|
|
| 142 |
prop = create_prop(dev, name, PROP_TYPE_PTR); |
|
| 143 |
prop->value.ptr = value; |
|
| 144 |
} |
|
| 145 |
|
|
| 146 |
void qdev_set_netdev(DeviceState *dev, NICInfo *nd) |
|
| 147 |
{
|
|
| 148 |
assert(!dev->nd); |
|
| 149 |
dev->nd = nd; |
|
| 150 |
} |
|
| 151 |
|
|
| 152 |
|
|
| 153 | 99 |
/* Get a character (serial) device interface. */ |
| 154 | 100 |
CharDriverState *qdev_init_chardev(DeviceState *dev) |
| 155 | 101 |
{
|
| ... | ... | |
| 168 | 114 |
return dev->parent_bus; |
| 169 | 115 |
} |
| 170 | 116 |
|
| 171 |
static DeviceProperty *find_prop(DeviceState *dev, const char *name, |
|
| 172 |
DevicePropType type) |
|
| 173 |
{
|
|
| 174 |
DeviceProperty *prop; |
|
| 175 |
|
|
| 176 |
for (prop = dev->props; prop; prop = prop->next) {
|
|
| 177 |
if (strcmp(prop->name, name) == 0) {
|
|
| 178 |
assert (prop->type == type); |
|
| 179 |
return prop; |
|
| 180 |
} |
|
| 181 |
} |
|
| 182 |
return NULL; |
|
| 183 |
} |
|
| 184 |
|
|
| 185 |
uint64_t qdev_get_prop_int(DeviceState *dev, const char *name, uint64_t def) |
|
| 186 |
{
|
|
| 187 |
DeviceProperty *prop; |
|
| 188 |
|
|
| 189 |
prop = find_prop(dev, name, PROP_TYPE_INT); |
|
| 190 |
if (!prop) {
|
|
| 191 |
return def; |
|
| 192 |
} |
|
| 193 |
|
|
| 194 |
return prop->value.i; |
|
| 195 |
} |
|
| 196 |
|
|
| 197 |
void *qdev_get_prop_ptr(DeviceState *dev, const char *name) |
|
| 198 |
{
|
|
| 199 |
DeviceProperty *prop; |
|
| 200 |
|
|
| 201 |
prop = find_prop(dev, name, PROP_TYPE_PTR); |
|
| 202 |
assert(prop); |
|
| 203 |
return prop->value.ptr; |
|
| 204 |
} |
|
| 205 |
|
|
| 206 |
DeviceState *qdev_get_prop_dev(DeviceState *dev, const char *name) |
|
| 207 |
{
|
|
| 208 |
DeviceProperty *prop; |
|
| 209 |
|
|
| 210 |
prop = find_prop(dev, name, PROP_TYPE_DEV); |
|
| 211 |
if (!prop) {
|
|
| 212 |
return NULL; |
|
| 213 |
} |
|
| 214 |
return prop->value.ptr; |
|
| 215 |
} |
|
| 216 |
|
|
| 217 | 117 |
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) |
| 218 | 118 |
{
|
| 219 | 119 |
assert(dev->num_gpio_in == 0); |
| ... | ... | |
| 326 | 226 |
#define qdev_printf(fmt, ...) monitor_printf(mon, "%*s" fmt, indent, "", ## __VA_ARGS__) |
| 327 | 227 |
static void qbus_print(Monitor *mon, BusState *bus, int indent); |
| 328 | 228 |
|
| 229 |
static void qdev_print_props(Monitor *mon, DeviceState *dev, Property *props, |
|
| 230 |
const char *prefix, int indent) |
|
| 231 |
{
|
|
| 232 |
char buf[64]; |
|
| 233 |
|
|
| 234 |
if (!props) |
|
| 235 |
return; |
|
| 236 |
while (props->name) {
|
|
| 237 |
if (props->info->print) {
|
|
| 238 |
props->info->print(dev, props, buf, sizeof(buf)); |
|
| 239 |
qdev_printf("%s-prop: %s = %s\n", prefix, props->name, buf);
|
|
| 240 |
} |
|
| 241 |
props++; |
|
| 242 |
} |
|
| 243 |
} |
|
| 244 |
|
|
| 329 | 245 |
static void qdev_print(Monitor *mon, DeviceState *dev, int indent) |
| 330 | 246 |
{
|
| 331 |
DeviceProperty *prop; |
|
| 332 | 247 |
BusState *child; |
| 333 | 248 |
qdev_printf("dev: %s\n", dev->info->name);
|
| 334 | 249 |
indent += 2; |
| ... | ... | |
| 338 | 253 |
if (dev->num_gpio_out) {
|
| 339 | 254 |
qdev_printf("gpio-out %d\n", dev->num_gpio_out);
|
| 340 | 255 |
} |
| 341 |
for (prop = dev->props; prop; prop = prop->next) {
|
|
| 342 |
switch (prop->type) {
|
|
| 343 |
case PROP_TYPE_INT: |
|
| 344 |
qdev_printf("prop-int %s 0x%" PRIx64 "\n", prop->name,
|
|
| 345 |
prop->value.i); |
|
| 346 |
break; |
|
| 347 |
case PROP_TYPE_PTR: |
|
| 348 |
qdev_printf("prop-ptr %s\n", prop->name);
|
|
| 349 |
break; |
|
| 350 |
case PROP_TYPE_DEV: |
|
| 351 |
qdev_printf("prop-dev %s %s\n", prop->name,
|
|
| 352 |
((DeviceState *)prop->value.ptr)->info->name); |
|
| 353 |
break; |
|
| 354 |
default: |
|
| 355 |
qdev_printf("prop-unknown%d %s\n", prop->type, prop->name);
|
|
| 356 |
break; |
|
| 357 |
} |
|
| 358 |
} |
|
| 256 |
qdev_print_props(mon, dev, dev->info->props, "dev", indent); |
|
| 257 |
qdev_print_props(mon, dev, dev->parent_bus->info->props, "bus", indent); |
|
| 359 | 258 |
if (dev->parent_bus->info->print_dev) |
| 360 | 259 |
dev->parent_bus->info->print_dev(mon, dev, indent); |
| 361 | 260 |
LIST_FOREACH(child, &dev->child_bus, sibling) {
|
| b/hw/qdev.h | ||
|---|---|---|
| 4 | 4 |
#include "hw.h" |
| 5 | 5 |
#include "sys-queue.h" |
| 6 | 6 |
|
| 7 |
typedef struct DeviceInfo DeviceInfo; |
|
| 7 |
typedef struct Property Property; |
|
| 8 |
|
|
| 9 |
typedef struct PropertyInfo PropertyInfo; |
|
| 8 | 10 |
|
| 9 |
typedef struct DeviceProperty DeviceProperty;
|
|
| 11 |
typedef struct DeviceInfo DeviceInfo;
|
|
| 10 | 12 |
|
| 11 | 13 |
typedef struct BusState BusState; |
| 12 | 14 |
|
| ... | ... | |
| 17 | 19 |
struct DeviceState {
|
| 18 | 20 |
DeviceInfo *info; |
| 19 | 21 |
BusState *parent_bus; |
| 20 |
DeviceProperty *props; |
|
| 21 | 22 |
int num_gpio_out; |
| 22 | 23 |
qemu_irq *gpio_out; |
| 23 | 24 |
int num_gpio_in; |
| ... | ... | |
| 32 | 33 |
const char *name; |
| 33 | 34 |
size_t size; |
| 34 | 35 |
bus_dev_printfn print_dev; |
| 36 |
Property *props; |
|
| 35 | 37 |
}; |
| 36 | 38 |
|
| 37 | 39 |
struct BusState {
|
| ... | ... | |
| 42 | 44 |
LIST_ENTRY(BusState) sibling; |
| 43 | 45 |
}; |
| 44 | 46 |
|
| 47 |
struct Property {
|
|
| 48 |
const char *name; |
|
| 49 |
PropertyInfo *info; |
|
| 50 |
int offset; |
|
| 51 |
void *defval; |
|
| 52 |
}; |
|
| 53 |
|
|
| 54 |
enum PropertyType {
|
|
| 55 |
PROP_TYPE_UNSPEC = 0, |
|
| 56 |
PROP_TYPE_UINT16, |
|
| 57 |
PROP_TYPE_UINT32, |
|
| 58 |
PROP_TYPE_TADDR, |
|
| 59 |
PROP_TYPE_MACADDR, |
|
| 60 |
PROP_TYPE_PTR, |
|
| 61 |
}; |
|
| 62 |
|
|
| 63 |
struct PropertyInfo {
|
|
| 64 |
const char *name; |
|
| 65 |
size_t size; |
|
| 66 |
enum PropertyType type; |
|
| 67 |
int (*parse)(DeviceState *dev, Property *prop, const char *str); |
|
| 68 |
int (*print)(DeviceState *dev, Property *prop, char *dest, size_t len); |
|
| 69 |
}; |
|
| 70 |
|
|
| 45 | 71 |
/*** Board API. This should go away once we have a machine config file. ***/ |
| 46 | 72 |
|
| 47 | 73 |
DeviceState *qdev_create(BusState *bus, const char *name); |
| 48 | 74 |
void qdev_init(DeviceState *dev); |
| 49 | 75 |
void qdev_free(DeviceState *dev); |
| 50 | 76 |
|
| 51 |
/* Set properties between creation and init. */ |
|
| 52 |
void qdev_set_prop_int(DeviceState *dev, const char *name, uint64_t value); |
|
| 53 |
void qdev_set_prop_dev(DeviceState *dev, const char *name, DeviceState *value); |
|
| 54 |
void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value); |
|
| 55 |
void qdev_set_netdev(DeviceState *dev, NICInfo *nd); |
|
| 56 |
|
|
| 57 | 77 |
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); |
| 58 | 78 |
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); |
| 59 | 79 |
|
| ... | ... | |
| 61 | 81 |
|
| 62 | 82 |
/*** Device API. ***/ |
| 63 | 83 |
|
| 64 |
typedef enum {
|
|
| 65 |
PROP_TYPE_INT, |
|
| 66 |
PROP_TYPE_PTR, |
|
| 67 |
PROP_TYPE_DEV |
|
| 68 |
} DevicePropType; |
|
| 69 |
|
|
| 70 |
typedef struct {
|
|
| 71 |
const char *name; |
|
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