root / hw / slavio_misc.c @ ee6847d1
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/*
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* QEMU Sparc SLAVIO aux io port emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sun4m.h" |
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#include "sysemu.h" |
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#include "sysbus.h" |
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/* debug misc */
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//#define DEBUG_MISC
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/*
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* This is the auxio port, chip control and system control part of
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* chip STP2001 (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* This also includes the PMC CPU idle controller.
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*/
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#ifdef DEBUG_MISC
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#define MISC_DPRINTF(fmt, ...) \
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do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define MISC_DPRINTF(fmt, ...)
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#endif
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typedef struct MiscState { |
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SysBusDevice busdev; |
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qemu_irq irq; |
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uint8_t config; |
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uint8_t aux1, aux2; |
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uint8_t diag, mctrl; |
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uint32_t sysctrl; |
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uint16_t leds; |
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qemu_irq fdc_tc; |
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} MiscState; |
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typedef struct APCState { |
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SysBusDevice busdev; |
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qemu_irq cpu_halt; |
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} APCState; |
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|
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#define MISC_SIZE 1 |
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#define SYSCTRL_SIZE 4 |
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#define MISC_LEDS 0x01600000 |
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#define MISC_CFG 0x01800000 |
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#define MISC_DIAG 0x01a00000 |
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#define MISC_MDM 0x01b00000 |
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#define MISC_SYS 0x01f00000 |
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#define AUX1_TC 0x02 |
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#define AUX2_PWROFF 0x01 |
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#define AUX2_PWRINTCLR 0x02 |
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#define AUX2_PWRFAIL 0x20 |
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#define CFG_PWRINTEN 0x08 |
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#define SYS_RESET 0x01 |
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#define SYS_RESETSTAT 0x02 |
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static void slavio_misc_update_irq(void *opaque) |
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{ |
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MiscState *s = opaque; |
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if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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MISC_DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq); |
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} else {
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MISC_DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq); |
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} |
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} |
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static void slavio_misc_reset(void *opaque) |
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{ |
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MiscState *s = opaque; |
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// Diagnostic and system control registers not cleared in reset
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s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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} |
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void slavio_set_power_fail(void *opaque, int power_failing) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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if (power_failing && (s->config & CFG_PWRINTEN)) {
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s->aux2 |= AUX2_PWRFAIL; |
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} else {
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s->aux2 &= ~AUX2_PWRFAIL; |
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} |
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slavio_misc_update_irq(s); |
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} |
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static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
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s->config = val & 0xff;
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slavio_misc_update_irq(s); |
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} |
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static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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ret = s->config; |
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MISC_DPRINTF("Read config %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = { |
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slavio_cfg_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = { |
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slavio_cfg_mem_writeb, |
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NULL,
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NULL,
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}; |
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static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
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s->diag = val & 0xff;
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} |
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static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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ret = s->diag; |
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MISC_DPRINTF("Read diag %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *slavio_diag_mem_read[3] = { |
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slavio_diag_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = { |
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slavio_diag_mem_writeb, |
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NULL,
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NULL,
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}; |
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static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
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s->mctrl = val & 0xff;
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} |
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static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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ret = s->mctrl; |
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MISC_DPRINTF("Read modem control %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = { |
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slavio_mdm_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = { |
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slavio_mdm_mem_writeb, |
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NULL,
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NULL,
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}; |
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static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
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if (val & AUX1_TC) {
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// Send a pulse to floppy terminal count line
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if (s->fdc_tc) {
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qemu_irq_raise(s->fdc_tc); |
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qemu_irq_lower(s->fdc_tc); |
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} |
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val &= ~AUX1_TC; |
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} |
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s->aux1 = val & 0xff;
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} |
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static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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ret = s->aux1; |
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MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = { |
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slavio_aux1_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = { |
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slavio_aux1_mem_writeb, |
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NULL,
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NULL,
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}; |
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static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
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MISC_DPRINTF("Write aux2 %2.2x\n", val);
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val |= s->aux2 & AUX2_PWRFAIL; |
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if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
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val &= AUX2_PWROFF; |
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s->aux2 = val; |
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if (val & AUX2_PWROFF)
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qemu_system_shutdown_request(); |
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slavio_misc_update_irq(s); |
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} |
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static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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ret = s->aux2; |
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MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = { |
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slavio_aux2_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = { |
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slavio_aux2_mem_writeb, |
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NULL,
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NULL,
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}; |
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static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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APCState *s = opaque; |
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
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qemu_irq_raise(s->cpu_halt); |
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} |
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static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret = 0;
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MISC_DPRINTF("Read power management %2.2x\n", ret);
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return ret;
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} |
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static CPUReadMemoryFunc *apc_mem_read[3] = { |
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apc_mem_readb, |
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NULL,
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NULL,
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}; |
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static CPUWriteMemoryFunc *apc_mem_write[3] = { |
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apc_mem_writeb, |
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NULL,
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NULL,
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}; |
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static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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switch (addr) {
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case 0: |
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ret = s->sysctrl; |
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break;
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default:
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break;
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} |
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MISC_DPRINTF("Read system control %08x\n", ret);
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return ret;
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} |
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static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write system control %08x\n", val);
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switch (addr) {
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case 0: |
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if (val & SYS_RESET) {
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s->sysctrl = SYS_RESETSTAT; |
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qemu_system_reset_request(); |
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} |
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break;
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default:
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break;
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} |
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} |
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static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = { |
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NULL,
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NULL,
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slavio_sysctrl_mem_readl, |
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}; |
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static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { |
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NULL,
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NULL,
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slavio_sysctrl_mem_writel, |
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}; |
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static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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MiscState *s = opaque; |
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uint32_t ret = 0;
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switch (addr) {
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case 0: |
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ret = s->leds; |
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break;
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default:
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break;
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} |
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MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
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return ret;
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} |
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static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MiscState *s = opaque; |
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MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff); |
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switch (addr) {
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case 0: |
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s->leds = val; |
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break;
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default:
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break;
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} |
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} |
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static CPUReadMemoryFunc *slavio_led_mem_read[3] = { |
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NULL,
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slavio_led_mem_readw, |
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NULL,
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}; |
400 |
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static CPUWriteMemoryFunc *slavio_led_mem_write[3] = { |
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NULL,
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slavio_led_mem_writew, |
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NULL,
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}; |
406 |
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static void slavio_misc_save(QEMUFile *f, void *opaque) |
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{ |
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MiscState *s = opaque; |
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uint32_t tmp = 0;
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uint8_t tmp8; |
412 |
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qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
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qemu_put_8s(f, &s->config); |
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qemu_put_8s(f, &s->aux1); |
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qemu_put_8s(f, &s->aux2); |
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qemu_put_8s(f, &s->diag); |
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qemu_put_8s(f, &s->mctrl); |
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tmp8 = s->sysctrl & 0xff;
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qemu_put_8s(f, &tmp8); |
421 |
} |
422 |
|
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static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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MiscState *s = opaque; |
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uint32_t tmp; |
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uint8_t tmp8; |
428 |
|
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if (version_id != 1) |
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return -EINVAL;
|
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|
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qemu_get_be32s(f, &tmp); |
433 |
qemu_get_8s(f, &s->config); |
434 |
qemu_get_8s(f, &s->aux1); |
435 |
qemu_get_8s(f, &s->aux2); |
436 |
qemu_get_8s(f, &s->diag); |
437 |
qemu_get_8s(f, &s->mctrl); |
438 |
qemu_get_8s(f, &tmp8); |
439 |
s->sysctrl = (uint32_t)tmp8; |
440 |
return 0; |
441 |
} |
442 |
|
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void *slavio_misc_init(target_phys_addr_t base,
|
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target_phys_addr_t aux1_base, |
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target_phys_addr_t aux2_base, qemu_irq irq, |
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qemu_irq fdc_tc) |
447 |
{ |
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DeviceState *dev; |
449 |
SysBusDevice *s; |
450 |
MiscState *d; |
451 |
|
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dev = qdev_create(NULL, "slavio_misc"); |
453 |
qdev_init(dev); |
454 |
s = sysbus_from_qdev(dev); |
455 |
if (base) {
|
456 |
/* 8 bit registers */
|
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/* Slavio control */
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sysbus_mmio_map(s, 0, base + MISC_CFG);
|
459 |
/* Diagnostics */
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460 |
sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
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/* Modem control */
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sysbus_mmio_map(s, 2, base + MISC_MDM);
|
463 |
/* 16 bit registers */
|
464 |
/* ss600mp diag LEDs */
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465 |
sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
466 |
/* 32 bit registers */
|
467 |
/* System control */
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sysbus_mmio_map(s, 4, base + MISC_SYS);
|
469 |
} |
470 |
if (aux1_base) {
|
471 |
/* AUX 1 (Misc System Functions) */
|
472 |
sysbus_mmio_map(s, 5, aux1_base);
|
473 |
} |
474 |
if (aux2_base) {
|
475 |
/* AUX 2 (Software Powerdown Control) */
|
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sysbus_mmio_map(s, 6, aux2_base);
|
477 |
} |
478 |
sysbus_connect_irq(s, 0, irq);
|
479 |
sysbus_connect_irq(s, 1, fdc_tc);
|
480 |
|
481 |
d = FROM_SYSBUS(MiscState, s); |
482 |
|
483 |
return d;
|
484 |
} |
485 |
|
486 |
static void apc_init1(SysBusDevice *dev) |
487 |
{ |
488 |
APCState *s = FROM_SYSBUS(APCState, dev); |
489 |
int io;
|
490 |
|
491 |
sysbus_init_irq(dev, &s->cpu_halt); |
492 |
|
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/* Power management (APC) XXX: not a Slavio device */
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io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); |
495 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
496 |
} |
497 |
|
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void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
|
499 |
{ |
500 |
DeviceState *dev; |
501 |
SysBusDevice *s; |
502 |
|
503 |
dev = qdev_create(NULL, "apc"); |
504 |
qdev_init(dev); |
505 |
s = sysbus_from_qdev(dev); |
506 |
/* Power management (APC) XXX: not a Slavio device */
|
507 |
sysbus_mmio_map(s, 0, power_base);
|
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sysbus_connect_irq(s, 0, cpu_halt);
|
509 |
} |
510 |
|
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static void slavio_misc_init1(SysBusDevice *dev) |
512 |
{ |
513 |
MiscState *s = FROM_SYSBUS(MiscState, dev); |
514 |
int io;
|
515 |
|
516 |
sysbus_init_irq(dev, &s->irq); |
517 |
sysbus_init_irq(dev, &s->fdc_tc); |
518 |
|
519 |
/* 8 bit registers */
|
520 |
/* Slavio control */
|
521 |
io = cpu_register_io_memory(slavio_cfg_mem_read, |
522 |
slavio_cfg_mem_write, s); |
523 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
524 |
|
525 |
/* Diagnostics */
|
526 |
io = cpu_register_io_memory(slavio_diag_mem_read, |
527 |
slavio_diag_mem_write, s); |
528 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
529 |
|
530 |
/* Modem control */
|
531 |
io = cpu_register_io_memory(slavio_mdm_mem_read, |
532 |
slavio_mdm_mem_write, s); |
533 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
534 |
|
535 |
/* 16 bit registers */
|
536 |
/* ss600mp diag LEDs */
|
537 |
io = cpu_register_io_memory(slavio_led_mem_read, |
538 |
slavio_led_mem_write, s); |
539 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
540 |
|
541 |
/* 32 bit registers */
|
542 |
/* System control */
|
543 |
io = cpu_register_io_memory(slavio_sysctrl_mem_read, |
544 |
slavio_sysctrl_mem_write, s); |
545 |
sysbus_init_mmio(dev, SYSCTRL_SIZE, io); |
546 |
|
547 |
/* AUX 1 (Misc System Functions) */
|
548 |
io = cpu_register_io_memory(slavio_aux1_mem_read, |
549 |
slavio_aux1_mem_write, s); |
550 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
551 |
|
552 |
/* AUX 2 (Software Powerdown Control) */
|
553 |
io = cpu_register_io_memory(slavio_aux2_mem_read, |
554 |
slavio_aux2_mem_write, s); |
555 |
sysbus_init_mmio(dev, MISC_SIZE, io); |
556 |
|
557 |
register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load, |
558 |
s); |
559 |
qemu_register_reset(slavio_misc_reset, s); |
560 |
slavio_misc_reset(s); |
561 |
} |
562 |
|
563 |
static SysBusDeviceInfo slavio_misc_info = {
|
564 |
.init = slavio_misc_init1, |
565 |
.qdev.name = "slavio_misc",
|
566 |
.qdev.size = sizeof(MiscState),
|
567 |
}; |
568 |
|
569 |
static SysBusDeviceInfo apc_info = {
|
570 |
.init = apc_init1, |
571 |
.qdev.name = "apc",
|
572 |
.qdev.size = sizeof(MiscState),
|
573 |
}; |
574 |
|
575 |
static void slavio_misc_register_devices(void) |
576 |
{ |
577 |
sysbus_register_withprop(&slavio_misc_info); |
578 |
sysbus_register_withprop(&apc_info); |
579 |
} |
580 |
|
581 |
device_init(slavio_misc_register_devices) |