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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 79aceca5 | bellard | */
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19 | fdabc366 | bellard | #include <stdarg.h> |
20 | fdabc366 | bellard | #include <stdlib.h> |
21 | fdabc366 | bellard | #include <stdio.h> |
22 | fdabc366 | bellard | #include <string.h> |
23 | fdabc366 | bellard | #include <inttypes.h> |
24 | fdabc366 | bellard | #include <signal.h> |
25 | fdabc366 | bellard | |
26 | fdabc366 | bellard | #include "cpu.h" |
27 | fdabc366 | bellard | #include "exec-all.h" |
28 | 0411a972 | j_mayer | #include "helper_regs.h" |
29 | ca10f867 | aurel32 | #include "qemu-common.h" |
30 | d76d1650 | aurel32 | #include "kvm.h" |
31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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33 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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34 | 6b542af7 | j_mayer | //#define DEBUG_SLB
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35 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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36 | 0411a972 | j_mayer | //#define DUMP_PAGE_TABLES
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37 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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38 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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39 | 9a64fbe4 | bellard | |
40 | d12d51d5 | aliguori | #ifdef DEBUG_MMU
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41 | 93fcfe39 | aliguori | # define LOG_MMU(...) qemu_log(__VA_ARGS__)
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42 | 93fcfe39 | aliguori | # define LOG_MMU_STATE(env) log_cpu_state((env), 0) |
43 | d12d51d5 | aliguori | #else
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44 | d12d51d5 | aliguori | # define LOG_MMU(...) do { } while (0) |
45 | d12d51d5 | aliguori | # define LOG_MMU_STATE(...) do { } while (0) |
46 | d12d51d5 | aliguori | #endif
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47 | d12d51d5 | aliguori | |
48 | d12d51d5 | aliguori | |
49 | d12d51d5 | aliguori | #ifdef DEBUG_SOFTWARE_TLB
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50 | 93fcfe39 | aliguori | # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
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51 | d12d51d5 | aliguori | #else
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52 | d12d51d5 | aliguori | # define LOG_SWTLB(...) do { } while (0) |
53 | d12d51d5 | aliguori | #endif
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54 | d12d51d5 | aliguori | |
55 | d12d51d5 | aliguori | #ifdef DEBUG_BATS
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56 | 93fcfe39 | aliguori | # define LOG_BATS(...) qemu_log(__VA_ARGS__)
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57 | d12d51d5 | aliguori | #else
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58 | d12d51d5 | aliguori | # define LOG_BATS(...) do { } while (0) |
59 | d12d51d5 | aliguori | #endif
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60 | d12d51d5 | aliguori | |
61 | d12d51d5 | aliguori | #ifdef DEBUG_SLB
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62 | 93fcfe39 | aliguori | # define LOG_SLB(...) qemu_log(__VA_ARGS__)
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63 | d12d51d5 | aliguori | #else
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64 | d12d51d5 | aliguori | # define LOG_SLB(...) do { } while (0) |
65 | d12d51d5 | aliguori | #endif
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66 | d12d51d5 | aliguori | |
67 | d12d51d5 | aliguori | #ifdef DEBUG_EXCEPTIONS
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68 | 93fcfe39 | aliguori | # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
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69 | d12d51d5 | aliguori | #else
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70 | d12d51d5 | aliguori | # define LOG_EXCP(...) do { } while (0) |
71 | d12d51d5 | aliguori | #endif
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72 | d12d51d5 | aliguori | |
73 | d569956e | David Gibson | /*****************************************************************************/
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74 | d569956e | David Gibson | /* PowerPC Hypercall emulation */
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75 | d569956e | David Gibson | |
76 | d569956e | David Gibson | void (*cpu_ppc_hypercall)(CPUState *);
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77 | d12d51d5 | aliguori | |
78 | 9a64fbe4 | bellard | /*****************************************************************************/
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79 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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80 | a541f297 | bellard | |
81 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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82 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
83 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
84 | 24741ef3 | bellard | { |
85 | 24741ef3 | bellard | int exception, error_code;
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86 | d9bce9d9 | j_mayer | |
87 | 24741ef3 | bellard | if (rw == 2) { |
88 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
89 | 8f793433 | j_mayer | error_code = 0x40000000;
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90 | 24741ef3 | bellard | } else {
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91 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
92 | 8f793433 | j_mayer | error_code = 0x40000000;
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93 | 24741ef3 | bellard | if (rw)
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94 | 24741ef3 | bellard | error_code |= 0x02000000;
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95 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
96 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
97 | 24741ef3 | bellard | } |
98 | 24741ef3 | bellard | env->exception_index = exception; |
99 | 24741ef3 | bellard | env->error_code = error_code; |
100 | 76a66253 | j_mayer | |
101 | 24741ef3 | bellard | return 1; |
102 | 24741ef3 | bellard | } |
103 | 76a66253 | j_mayer | |
104 | 24741ef3 | bellard | #else
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105 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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106 | 636aa200 | Blue Swirl | static inline int pte_is_valid(target_ulong pte0) |
107 | 76a66253 | j_mayer | { |
108 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
109 | 76a66253 | j_mayer | } |
110 | 76a66253 | j_mayer | |
111 | 636aa200 | Blue Swirl | static inline void pte_invalidate(target_ulong *pte0) |
112 | 76a66253 | j_mayer | { |
113 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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114 | 76a66253 | j_mayer | } |
115 | 76a66253 | j_mayer | |
116 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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117 | 636aa200 | Blue Swirl | static inline int pte64_is_valid(target_ulong pte0) |
118 | caa4039c | j_mayer | { |
119 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
120 | caa4039c | j_mayer | } |
121 | caa4039c | j_mayer | |
122 | 636aa200 | Blue Swirl | static inline void pte64_invalidate(target_ulong *pte0) |
123 | caa4039c | j_mayer | { |
124 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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125 | caa4039c | j_mayer | } |
126 | caa4039c | j_mayer | #endif
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127 | caa4039c | j_mayer | |
128 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
129 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
130 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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131 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
132 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
133 | caa4039c | j_mayer | #endif
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134 | 76a66253 | j_mayer | |
135 | 636aa200 | Blue Swirl | static inline int pp_check(int key, int pp, int nx) |
136 | b227a8e9 | j_mayer | { |
137 | b227a8e9 | j_mayer | int access;
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138 | b227a8e9 | j_mayer | |
139 | b227a8e9 | j_mayer | /* Compute access rights */
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140 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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141 | b227a8e9 | j_mayer | access = 0;
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142 | b227a8e9 | j_mayer | if (key == 0) { |
143 | b227a8e9 | j_mayer | switch (pp) {
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144 | b227a8e9 | j_mayer | case 0x0: |
145 | b227a8e9 | j_mayer | case 0x1: |
146 | b227a8e9 | j_mayer | case 0x2: |
147 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
148 | b227a8e9 | j_mayer | /* No break here */
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149 | b227a8e9 | j_mayer | case 0x3: |
150 | b227a8e9 | j_mayer | case 0x6: |
151 | b227a8e9 | j_mayer | access |= PAGE_READ; |
152 | b227a8e9 | j_mayer | break;
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153 | b227a8e9 | j_mayer | } |
154 | b227a8e9 | j_mayer | } else {
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155 | b227a8e9 | j_mayer | switch (pp) {
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156 | b227a8e9 | j_mayer | case 0x0: |
157 | b227a8e9 | j_mayer | case 0x6: |
158 | b227a8e9 | j_mayer | access = 0;
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159 | b227a8e9 | j_mayer | break;
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160 | b227a8e9 | j_mayer | case 0x1: |
161 | b227a8e9 | j_mayer | case 0x3: |
162 | b227a8e9 | j_mayer | access = PAGE_READ; |
163 | b227a8e9 | j_mayer | break;
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164 | b227a8e9 | j_mayer | case 0x2: |
165 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
166 | b227a8e9 | j_mayer | break;
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167 | b227a8e9 | j_mayer | } |
168 | b227a8e9 | j_mayer | } |
169 | b227a8e9 | j_mayer | if (nx == 0) |
170 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
171 | b227a8e9 | j_mayer | |
172 | b227a8e9 | j_mayer | return access;
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173 | b227a8e9 | j_mayer | } |
174 | b227a8e9 | j_mayer | |
175 | 636aa200 | Blue Swirl | static inline int check_prot(int prot, int rw, int access_type) |
176 | b227a8e9 | j_mayer | { |
177 | b227a8e9 | j_mayer | int ret;
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178 | b227a8e9 | j_mayer | |
179 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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180 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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181 | b227a8e9 | j_mayer | ret = 0;
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182 | b227a8e9 | j_mayer | else
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183 | b227a8e9 | j_mayer | ret = -2;
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184 | b227a8e9 | j_mayer | } else if (rw) { |
185 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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186 | b227a8e9 | j_mayer | ret = 0;
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187 | b227a8e9 | j_mayer | else
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188 | b227a8e9 | j_mayer | ret = -2;
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189 | b227a8e9 | j_mayer | } else {
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190 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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191 | b227a8e9 | j_mayer | ret = 0;
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192 | b227a8e9 | j_mayer | else
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193 | b227a8e9 | j_mayer | ret = -2;
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194 | b227a8e9 | j_mayer | } |
195 | b227a8e9 | j_mayer | |
196 | b227a8e9 | j_mayer | return ret;
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197 | b227a8e9 | j_mayer | } |
198 | b227a8e9 | j_mayer | |
199 | c227f099 | Anthony Liguori | static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, |
200 | 636aa200 | Blue Swirl | target_ulong pte1, int h, int rw, int type) |
201 | 76a66253 | j_mayer | { |
202 | caa4039c | j_mayer | target_ulong ptem, mmask; |
203 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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204 | 76a66253 | j_mayer | |
205 | 76a66253 | j_mayer | ret = -1;
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206 | 76a66253 | j_mayer | /* Check validity and table match */
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207 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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208 | caa4039c | j_mayer | if (is_64b) {
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209 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
210 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
211 | caa4039c | j_mayer | } else
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212 | caa4039c | j_mayer | #endif
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213 | caa4039c | j_mayer | { |
214 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
215 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
216 | caa4039c | j_mayer | } |
217 | caa4039c | j_mayer | if (ptev && h == pteh) {
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218 | 76a66253 | j_mayer | /* Check vsid & api */
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219 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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220 | caa4039c | j_mayer | if (is_64b) {
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221 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
222 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
223 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
224 | 29c8ca6f | blueswir1 | ctx->nx = (pte1 >> 2) & 1; /* No execute bit */ |
225 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
226 | caa4039c | j_mayer | } else
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227 | caa4039c | j_mayer | #endif
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228 | caa4039c | j_mayer | { |
229 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
230 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
231 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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232 | caa4039c | j_mayer | } |
233 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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234 | c227f099 | Anthony Liguori | if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
235 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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236 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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237 | 93fcfe39 | aliguori | qemu_log("Bad RPN/WIMG/PP\n");
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238 | 76a66253 | j_mayer | return -3; |
239 | 76a66253 | j_mayer | } |
240 | 76a66253 | j_mayer | } |
241 | 76a66253 | j_mayer | /* Compute access rights */
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242 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
243 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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244 | 76a66253 | j_mayer | ctx->raddr = pte1; |
245 | 76a66253 | j_mayer | ctx->prot = access; |
246 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
247 | b227a8e9 | j_mayer | if (ret == 0) { |
248 | 76a66253 | j_mayer | /* Access granted */
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249 | d12d51d5 | aliguori | LOG_MMU("PTE access granted !\n");
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250 | 76a66253 | j_mayer | } else {
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251 | 76a66253 | j_mayer | /* Access right violation */
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252 | d12d51d5 | aliguori | LOG_MMU("PTE access rejected\n");
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253 | 76a66253 | j_mayer | } |
254 | 76a66253 | j_mayer | } |
255 | 76a66253 | j_mayer | } |
256 | 76a66253 | j_mayer | |
257 | 76a66253 | j_mayer | return ret;
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258 | 76a66253 | j_mayer | } |
259 | 76a66253 | j_mayer | |
260 | c227f099 | Anthony Liguori | static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0, |
261 | 636aa200 | Blue Swirl | target_ulong pte1, int h, int rw, int type) |
262 | caa4039c | j_mayer | { |
263 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
264 | caa4039c | j_mayer | } |
265 | caa4039c | j_mayer | |
266 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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267 | c227f099 | Anthony Liguori | static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0, |
268 | 636aa200 | Blue Swirl | target_ulong pte1, int h, int rw, int type) |
269 | caa4039c | j_mayer | { |
270 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
271 | caa4039c | j_mayer | } |
272 | caa4039c | j_mayer | #endif
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273 | caa4039c | j_mayer | |
274 | c227f099 | Anthony Liguori | static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, |
275 | 636aa200 | Blue Swirl | int ret, int rw) |
276 | 76a66253 | j_mayer | { |
277 | 76a66253 | j_mayer | int store = 0; |
278 | 76a66253 | j_mayer | |
279 | 76a66253 | j_mayer | /* Update page flags */
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280 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
281 | 76a66253 | j_mayer | /* Update accessed flag */
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282 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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283 | 76a66253 | j_mayer | store = 1;
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284 | 76a66253 | j_mayer | } |
285 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
286 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
287 | 76a66253 | j_mayer | /* Update changed flag */
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288 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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289 | 76a66253 | j_mayer | store = 1;
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290 | 76a66253 | j_mayer | } else {
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291 | 76a66253 | j_mayer | /* Force page fault for first write access */
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292 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
293 | 76a66253 | j_mayer | } |
294 | 76a66253 | j_mayer | } |
295 | 76a66253 | j_mayer | |
296 | 76a66253 | j_mayer | return store;
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297 | 76a66253 | j_mayer | } |
298 | 76a66253 | j_mayer | |
299 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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300 | 636aa200 | Blue Swirl | static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way, |
301 | 636aa200 | Blue Swirl | int is_code)
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302 | 76a66253 | j_mayer | { |
303 | 76a66253 | j_mayer | int nr;
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304 | 76a66253 | j_mayer | |
305 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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306 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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307 | 76a66253 | j_mayer | /* Select TLB way */
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308 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
309 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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310 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
311 | 76a66253 | j_mayer | nr += env->nb_tlb; |
312 | 76a66253 | j_mayer | |
313 | 76a66253 | j_mayer | return nr;
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314 | 76a66253 | j_mayer | } |
315 | 76a66253 | j_mayer | |
316 | 636aa200 | Blue Swirl | static inline void ppc6xx_tlb_invalidate_all(CPUState *env) |
317 | 76a66253 | j_mayer | { |
318 | c227f099 | Anthony Liguori | ppc6xx_tlb_t *tlb; |
319 | 76a66253 | j_mayer | int nr, max;
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320 | 76a66253 | j_mayer | |
321 | d12d51d5 | aliguori | //LOG_SWTLB("Invalidate all TLBs\n");
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322 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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323 | 76a66253 | j_mayer | max = env->nb_tlb; |
324 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
325 | 76a66253 | j_mayer | max *= 2;
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326 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
327 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
328 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
329 | 76a66253 | j_mayer | } |
330 | 76a66253 | j_mayer | tlb_flush(env, 1);
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331 | 76a66253 | j_mayer | } |
332 | 76a66253 | j_mayer | |
333 | 636aa200 | Blue Swirl | static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, |
334 | 636aa200 | Blue Swirl | target_ulong eaddr, |
335 | 636aa200 | Blue Swirl | int is_code, int match_epn) |
336 | 76a66253 | j_mayer | { |
337 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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338 | c227f099 | Anthony Liguori | ppc6xx_tlb_t *tlb; |
339 | 76a66253 | j_mayer | int way, nr;
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340 | 76a66253 | j_mayer | |
341 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
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342 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
343 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
344 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
345 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
346 | 90e189ec | Blue Swirl | LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, |
347 | 90e189ec | Blue Swirl | env->nb_tlb, eaddr); |
348 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
349 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
350 | 76a66253 | j_mayer | } |
351 | 76a66253 | j_mayer | } |
352 | 76a66253 | j_mayer | #else
|
353 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
|
354 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
355 | 76a66253 | j_mayer | #endif
|
356 | 76a66253 | j_mayer | } |
357 | 76a66253 | j_mayer | |
358 | 636aa200 | Blue Swirl | static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, |
359 | 636aa200 | Blue Swirl | target_ulong eaddr, int is_code)
|
360 | 76a66253 | j_mayer | { |
361 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
362 | 76a66253 | j_mayer | } |
363 | 76a66253 | j_mayer | |
364 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
365 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
366 | 76a66253 | j_mayer | { |
367 | c227f099 | Anthony Liguori | ppc6xx_tlb_t *tlb; |
368 | 76a66253 | j_mayer | int nr;
|
369 | 76a66253 | j_mayer | |
370 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
371 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
372 | 90e189ec | Blue Swirl | LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx |
373 | 90e189ec | Blue Swirl | " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
374 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
375 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
376 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
377 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
378 | 76a66253 | j_mayer | tlb->EPN = EPN; |
379 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
380 | 76a66253 | j_mayer | env->last_way = way; |
381 | 76a66253 | j_mayer | } |
382 | 76a66253 | j_mayer | |
383 | c227f099 | Anthony Liguori | static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, |
384 | 636aa200 | Blue Swirl | target_ulong eaddr, int rw, int access_type) |
385 | 76a66253 | j_mayer | { |
386 | c227f099 | Anthony Liguori | ppc6xx_tlb_t *tlb; |
387 | 76a66253 | j_mayer | int nr, best, way;
|
388 | 76a66253 | j_mayer | int ret;
|
389 | d9bce9d9 | j_mayer | |
390 | 76a66253 | j_mayer | best = -1;
|
391 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
392 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
393 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
394 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
395 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
396 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
397 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
398 | 90e189ec | Blue Swirl | LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx |
399 | 90e189ec | Blue Swirl | "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb, |
400 | 90e189ec | Blue Swirl | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
401 | 90e189ec | Blue Swirl | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
402 | 76a66253 | j_mayer | continue;
|
403 | 76a66253 | j_mayer | } |
404 | 90e189ec | Blue Swirl | LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " " |
405 | 90e189ec | Blue Swirl | TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
|
406 | 90e189ec | Blue Swirl | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
407 | 90e189ec | Blue Swirl | tlb->EPN, eaddr, tlb->pte1, |
408 | 90e189ec | Blue Swirl | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
409 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
410 | 76a66253 | j_mayer | case -3: |
411 | 76a66253 | j_mayer | /* TLB inconsistency */
|
412 | 76a66253 | j_mayer | return -1; |
413 | 76a66253 | j_mayer | case -2: |
414 | 76a66253 | j_mayer | /* Access violation */
|
415 | 76a66253 | j_mayer | ret = -2;
|
416 | 76a66253 | j_mayer | best = nr; |
417 | 76a66253 | j_mayer | break;
|
418 | 76a66253 | j_mayer | case -1: |
419 | 76a66253 | j_mayer | default:
|
420 | 76a66253 | j_mayer | /* No match */
|
421 | 76a66253 | j_mayer | break;
|
422 | 76a66253 | j_mayer | case 0: |
423 | 76a66253 | j_mayer | /* access granted */
|
424 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
425 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
426 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
427 | 76a66253 | j_mayer | */
|
428 | 76a66253 | j_mayer | ret = 0;
|
429 | 76a66253 | j_mayer | best = nr; |
430 | 76a66253 | j_mayer | goto done;
|
431 | 76a66253 | j_mayer | } |
432 | 76a66253 | j_mayer | } |
433 | 76a66253 | j_mayer | if (best != -1) { |
434 | 76a66253 | j_mayer | done:
|
435 | 90e189ec | Blue Swirl | LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n", |
436 | 90e189ec | Blue Swirl | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
437 | 76a66253 | j_mayer | /* Update page flags */
|
438 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
439 | 76a66253 | j_mayer | } |
440 | 76a66253 | j_mayer | |
441 | 76a66253 | j_mayer | return ret;
|
442 | 76a66253 | j_mayer | } |
443 | 76a66253 | j_mayer | |
444 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
445 | 636aa200 | Blue Swirl | static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp, |
446 | 636aa200 | Blue Swirl | int *protp, target_ulong *BATu,
|
447 | 636aa200 | Blue Swirl | target_ulong *BATl) |
448 | faadf50e | j_mayer | { |
449 | faadf50e | j_mayer | target_ulong bl; |
450 | faadf50e | j_mayer | int pp, valid, prot;
|
451 | faadf50e | j_mayer | |
452 | faadf50e | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
453 | faadf50e | j_mayer | valid = 0;
|
454 | faadf50e | j_mayer | prot = 0;
|
455 | faadf50e | j_mayer | if (((msr_pr == 0) && (*BATu & 0x00000002)) || |
456 | faadf50e | j_mayer | ((msr_pr != 0) && (*BATu & 0x00000001))) { |
457 | faadf50e | j_mayer | valid = 1;
|
458 | faadf50e | j_mayer | pp = *BATl & 0x00000003;
|
459 | faadf50e | j_mayer | if (pp != 0) { |
460 | faadf50e | j_mayer | prot = PAGE_READ | PAGE_EXEC; |
461 | faadf50e | j_mayer | if (pp == 0x2) |
462 | faadf50e | j_mayer | prot |= PAGE_WRITE; |
463 | faadf50e | j_mayer | } |
464 | faadf50e | j_mayer | } |
465 | faadf50e | j_mayer | *blp = bl; |
466 | faadf50e | j_mayer | *validp = valid; |
467 | faadf50e | j_mayer | *protp = prot; |
468 | faadf50e | j_mayer | } |
469 | faadf50e | j_mayer | |
470 | 636aa200 | Blue Swirl | static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, |
471 | 636aa200 | Blue Swirl | int *validp, int *protp, |
472 | 636aa200 | Blue Swirl | target_ulong *BATu, target_ulong *BATl) |
473 | faadf50e | j_mayer | { |
474 | faadf50e | j_mayer | target_ulong bl; |
475 | faadf50e | j_mayer | int key, pp, valid, prot;
|
476 | faadf50e | j_mayer | |
477 | faadf50e | j_mayer | bl = (*BATl & 0x0000003F) << 17; |
478 | 90e189ec | Blue Swirl | LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n", |
479 | 90e189ec | Blue Swirl | (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
480 | faadf50e | j_mayer | prot = 0;
|
481 | faadf50e | j_mayer | valid = (*BATl >> 6) & 1; |
482 | faadf50e | j_mayer | if (valid) {
|
483 | faadf50e | j_mayer | pp = *BATu & 0x00000003;
|
484 | faadf50e | j_mayer | if (msr_pr == 0) |
485 | faadf50e | j_mayer | key = (*BATu >> 3) & 1; |
486 | faadf50e | j_mayer | else
|
487 | faadf50e | j_mayer | key = (*BATu >> 2) & 1; |
488 | faadf50e | j_mayer | prot = pp_check(key, pp, 0);
|
489 | faadf50e | j_mayer | } |
490 | faadf50e | j_mayer | *blp = bl; |
491 | faadf50e | j_mayer | *validp = valid; |
492 | faadf50e | j_mayer | *protp = prot; |
493 | faadf50e | j_mayer | } |
494 | faadf50e | j_mayer | |
495 | c227f099 | Anthony Liguori | static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual, |
496 | 636aa200 | Blue Swirl | int rw, int type) |
497 | 9a64fbe4 | bellard | { |
498 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
499 | 05f92404 | Blue Swirl | target_ulong BEPIl, BEPIu, bl; |
500 | faadf50e | j_mayer | int i, valid, prot;
|
501 | 9a64fbe4 | bellard | int ret = -1; |
502 | 9a64fbe4 | bellard | |
503 | 90e189ec | Blue Swirl | LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, |
504 | 90e189ec | Blue Swirl | type == ACCESS_CODE ? 'I' : 'D', virtual); |
505 | 9a64fbe4 | bellard | switch (type) {
|
506 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
507 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
508 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
509 | 9a64fbe4 | bellard | break;
|
510 | 9a64fbe4 | bellard | default:
|
511 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
512 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
513 | 9a64fbe4 | bellard | break;
|
514 | 9a64fbe4 | bellard | } |
515 | faadf50e | j_mayer | for (i = 0; i < env->nb_BATs; i++) { |
516 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
517 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
518 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
519 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
520 | faadf50e | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
|
521 | faadf50e | j_mayer | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
522 | faadf50e | j_mayer | } else {
|
523 | faadf50e | j_mayer | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
524 | faadf50e | j_mayer | } |
525 | 90e189ec | Blue Swirl | LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
526 | 90e189ec | Blue Swirl | " BATl " TARGET_FMT_lx "\n", __func__, |
527 | 90e189ec | Blue Swirl | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
528 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
529 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
530 | 9a64fbe4 | bellard | /* BAT matches */
|
531 | faadf50e | j_mayer | if (valid != 0) { |
532 | 9a64fbe4 | bellard | /* Get physical address */
|
533 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
534 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
535 | a541f297 | bellard | (virtual & 0x0001F000);
|
536 | b227a8e9 | j_mayer | /* Compute access rights */
|
537 | faadf50e | j_mayer | ctx->prot = prot; |
538 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
539 | d12d51d5 | aliguori | if (ret == 0) |
540 | 90e189ec | Blue Swirl | LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", |
541 | d12d51d5 | aliguori | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
542 | d12d51d5 | aliguori | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
543 | 9a64fbe4 | bellard | break;
|
544 | 9a64fbe4 | bellard | } |
545 | 9a64fbe4 | bellard | } |
546 | 9a64fbe4 | bellard | } |
547 | 9a64fbe4 | bellard | if (ret < 0) { |
548 | d12d51d5 | aliguori | #if defined(DEBUG_BATS)
|
549 | 0bf9e31a | Blue Swirl | if (qemu_log_enabled()) {
|
550 | 90e189ec | Blue Swirl | LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual); |
551 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
552 | 4a057712 | j_mayer | BATu = &BATut[i]; |
553 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
554 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
555 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
556 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
557 | 90e189ec | Blue Swirl | LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
558 | 90e189ec | Blue Swirl | " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " " |
559 | 90e189ec | Blue Swirl | TARGET_FMT_lx " " TARGET_FMT_lx "\n", |
560 | 0bf9e31a | Blue Swirl | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
561 | 0bf9e31a | Blue Swirl | *BATu, *BATl, BEPIu, BEPIl, bl); |
562 | 4a057712 | j_mayer | } |
563 | 9a64fbe4 | bellard | } |
564 | 9a64fbe4 | bellard | #endif
|
565 | 9a64fbe4 | bellard | } |
566 | 9a64fbe4 | bellard | /* No hit */
|
567 | 9a64fbe4 | bellard | return ret;
|
568 | 9a64fbe4 | bellard | } |
569 | 9a64fbe4 | bellard | |
570 | 9a64fbe4 | bellard | /* PTE table lookup */
|
571 | c227f099 | Anthony Liguori | static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, |
572 | 636aa200 | Blue Swirl | int type, int target_page_bits) |
573 | 9a64fbe4 | bellard | { |
574 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
575 | 76a66253 | j_mayer | int i, good = -1; |
576 | caa4039c | j_mayer | int ret, r;
|
577 | 9a64fbe4 | bellard | |
578 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
579 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
580 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
581 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
582 | caa4039c | j_mayer | if (is_64b) {
|
583 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
584 | 5b5aba4f | blueswir1 | pte1 = ldq_phys(base + (i * 16) + 8); |
585 | 5b5aba4f | blueswir1 | |
586 | 5b5aba4f | blueswir1 | /* We have a TLB that saves 4K pages, so let's
|
587 | 5b5aba4f | blueswir1 | * split a huge page to 4k chunks */
|
588 | 5b5aba4f | blueswir1 | if (target_page_bits != TARGET_PAGE_BITS)
|
589 | 5b5aba4f | blueswir1 | pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1)) |
590 | 5b5aba4f | blueswir1 | & TARGET_PAGE_MASK; |
591 | 5b5aba4f | blueswir1 | |
592 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
593 | 90e189ec | Blue Swirl | LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
594 | 90e189ec | Blue Swirl | TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
595 | 90e189ec | Blue Swirl | base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, |
596 | 90e189ec | Blue Swirl | (int)((pte0 >> 1) & 1), ctx->ptem); |
597 | caa4039c | j_mayer | } else
|
598 | caa4039c | j_mayer | #endif
|
599 | caa4039c | j_mayer | { |
600 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
601 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
602 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
603 | 90e189ec | Blue Swirl | LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
604 | 90e189ec | Blue Swirl | TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
605 | 90e189ec | Blue Swirl | base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, |
606 | 90e189ec | Blue Swirl | (int)((pte0 >> 6) & 1), ctx->ptem); |
607 | 12de9a39 | j_mayer | } |
608 | caa4039c | j_mayer | switch (r) {
|
609 | 76a66253 | j_mayer | case -3: |
610 | 76a66253 | j_mayer | /* PTE inconsistency */
|
611 | 76a66253 | j_mayer | return -1; |
612 | 76a66253 | j_mayer | case -2: |
613 | 76a66253 | j_mayer | /* Access violation */
|
614 | 76a66253 | j_mayer | ret = -2;
|
615 | 76a66253 | j_mayer | good = i; |
616 | 76a66253 | j_mayer | break;
|
617 | 76a66253 | j_mayer | case -1: |
618 | 76a66253 | j_mayer | default:
|
619 | 76a66253 | j_mayer | /* No PTE match */
|
620 | 76a66253 | j_mayer | break;
|
621 | 76a66253 | j_mayer | case 0: |
622 | 76a66253 | j_mayer | /* access granted */
|
623 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
624 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
625 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
626 | 76a66253 | j_mayer | */
|
627 | 76a66253 | j_mayer | ret = 0;
|
628 | 76a66253 | j_mayer | good = i; |
629 | 76a66253 | j_mayer | goto done;
|
630 | 9a64fbe4 | bellard | } |
631 | 9a64fbe4 | bellard | } |
632 | 9a64fbe4 | bellard | if (good != -1) { |
633 | 76a66253 | j_mayer | done:
|
634 | 90e189ec | Blue Swirl | LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n", |
635 | 90e189ec | Blue Swirl | ctx->raddr, ctx->prot, ret); |
636 | 9a64fbe4 | bellard | /* Update page flags */
|
637 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
638 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
639 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
640 | caa4039c | j_mayer | if (is_64b) {
|
641 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
642 | caa4039c | j_mayer | } else
|
643 | caa4039c | j_mayer | #endif
|
644 | caa4039c | j_mayer | { |
645 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
646 | caa4039c | j_mayer | } |
647 | caa4039c | j_mayer | } |
648 | 9a64fbe4 | bellard | } |
649 | 9a64fbe4 | bellard | |
650 | 9a64fbe4 | bellard | return ret;
|
651 | 79aceca5 | bellard | } |
652 | 79aceca5 | bellard | |
653 | c227f099 | Anthony Liguori | static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type, |
654 | 636aa200 | Blue Swirl | int target_page_bits)
|
655 | caa4039c | j_mayer | { |
656 | 5b5aba4f | blueswir1 | return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
657 | caa4039c | j_mayer | } |
658 | caa4039c | j_mayer | |
659 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
660 | c227f099 | Anthony Liguori | static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type, |
661 | 636aa200 | Blue Swirl | int target_page_bits)
|
662 | caa4039c | j_mayer | { |
663 | 5b5aba4f | blueswir1 | return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
664 | caa4039c | j_mayer | } |
665 | caa4039c | j_mayer | #endif
|
666 | caa4039c | j_mayer | |
667 | c227f099 | Anthony Liguori | static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, |
668 | 636aa200 | Blue Swirl | int type, int target_page_bits) |
669 | caa4039c | j_mayer | { |
670 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
671 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64)
|
672 | 5b5aba4f | blueswir1 | return find_pte64(ctx, h, rw, type, target_page_bits);
|
673 | caa4039c | j_mayer | #endif
|
674 | caa4039c | j_mayer | |
675 | 5b5aba4f | blueswir1 | return find_pte32(ctx, h, rw, type, target_page_bits);
|
676 | caa4039c | j_mayer | } |
677 | caa4039c | j_mayer | |
678 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
679 | 636aa200 | Blue Swirl | static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, |
680 | 636aa200 | Blue Swirl | target_ulong *vsid, target_ulong *page_mask, |
681 | 636aa200 | Blue Swirl | int *attr, int *target_page_bits) |
682 | caa4039c | j_mayer | { |
683 | 81762d6d | David Gibson | uint64_t esid; |
684 | 81762d6d | David Gibson | int n;
|
685 | caa4039c | j_mayer | |
686 | 90e189ec | Blue Swirl | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); |
687 | 81762d6d | David Gibson | |
688 | 81762d6d | David Gibson | esid = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; |
689 | 81762d6d | David Gibson | |
690 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
691 | 81762d6d | David Gibson | ppc_slb_t *slb = &env->slb[n]; |
692 | 81762d6d | David Gibson | |
693 | 81762d6d | David Gibson | LOG_SLB("%s: slot %d %016" PRIx64 " %016" |
694 | 81762d6d | David Gibson | PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
|
695 | 81762d6d | David Gibson | if (slb->esid == esid) {
|
696 | 81762d6d | David Gibson | *vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; |
697 | 81762d6d | David Gibson | *page_mask = ~SEGMENT_MASK_256M; |
698 | 81762d6d | David Gibson | *attr = slb->vsid & SLB_VSID_ATTR; |
699 | 81762d6d | David Gibson | if (target_page_bits) {
|
700 | 81762d6d | David Gibson | *target_page_bits = (slb->vsid & SLB_VSID_L) |
701 | 81762d6d | David Gibson | ? TARGET_PAGE_BITS_16M |
702 | 81762d6d | David Gibson | : TARGET_PAGE_BITS; |
703 | caa4039c | j_mayer | } |
704 | 81762d6d | David Gibson | return n;
|
705 | caa4039c | j_mayer | } |
706 | caa4039c | j_mayer | } |
707 | caa4039c | j_mayer | |
708 | 81762d6d | David Gibson | return -5; |
709 | 79aceca5 | bellard | } |
710 | 12de9a39 | j_mayer | |
711 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
712 | eacc3249 | j_mayer | { |
713 | eacc3249 | j_mayer | int n, do_invalidate;
|
714 | eacc3249 | j_mayer | |
715 | eacc3249 | j_mayer | do_invalidate = 0;
|
716 | 2c1ee068 | j_mayer | /* XXX: Warning: slbia never invalidates the first segment */
|
717 | 2c1ee068 | j_mayer | for (n = 1; n < env->slb_nr; n++) { |
718 | 81762d6d | David Gibson | ppc_slb_t *slb = &env->slb[n]; |
719 | 8eee0af9 | blueswir1 | |
720 | 81762d6d | David Gibson | if (slb->esid & SLB_ESID_V) {
|
721 | 81762d6d | David Gibson | slb->esid &= ~SLB_ESID_V; |
722 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
723 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
724 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
725 | eacc3249 | j_mayer | */
|
726 | eacc3249 | j_mayer | do_invalidate = 1;
|
727 | eacc3249 | j_mayer | } |
728 | eacc3249 | j_mayer | } |
729 | eacc3249 | j_mayer | if (do_invalidate)
|
730 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
731 | eacc3249 | j_mayer | } |
732 | eacc3249 | j_mayer | |
733 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
734 | eacc3249 | j_mayer | { |
735 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
736 | eacc3249 | j_mayer | int attr;
|
737 | eacc3249 | j_mayer | int n;
|
738 | 81762d6d | David Gibson | ppc_slb_t *slb; |
739 | eacc3249 | j_mayer | |
740 | 5b5aba4f | blueswir1 | n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
|
741 | 81762d6d | David Gibson | if (n < 0) { |
742 | 81762d6d | David Gibson | return;
|
743 | eacc3249 | j_mayer | } |
744 | eacc3249 | j_mayer | |
745 | 81762d6d | David Gibson | slb = &env->slb[n]; |
746 | 81762d6d | David Gibson | |
747 | 81762d6d | David Gibson | if (slb->esid & SLB_ESID_V) {
|
748 | 81762d6d | David Gibson | slb->esid &= ~SLB_ESID_V; |
749 | 12de9a39 | j_mayer | |
750 | 81762d6d | David Gibson | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
751 | 81762d6d | David Gibson | * and we still don't have a tlb_flush_mask(env, n, mask)
|
752 | 81762d6d | David Gibson | * in Qemu, we just invalidate all TLBs
|
753 | 81762d6d | David Gibson | */
|
754 | 81762d6d | David Gibson | tlb_flush(env, 1);
|
755 | 81762d6d | David Gibson | } |
756 | 12de9a39 | j_mayer | } |
757 | 12de9a39 | j_mayer | |
758 | 81762d6d | David Gibson | int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
|
759 | 12de9a39 | j_mayer | { |
760 | 81762d6d | David Gibson | int slot = rb & 0xfff; |
761 | 81762d6d | David Gibson | uint64_t esid = rb & ~0xfff;
|
762 | 81762d6d | David Gibson | ppc_slb_t *slb = &env->slb[slot]; |
763 | f6b868fc | blueswir1 | |
764 | 81762d6d | David Gibson | if (slot >= env->slb_nr) {
|
765 | 81762d6d | David Gibson | return -1; |
766 | 81762d6d | David Gibson | } |
767 | f6b868fc | blueswir1 | |
768 | 81762d6d | David Gibson | slb->esid = esid; |
769 | 81762d6d | David Gibson | slb->vsid = rs; |
770 | f6b868fc | blueswir1 | |
771 | 90e189ec | Blue Swirl | LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 |
772 | 81762d6d | David Gibson | " %016" PRIx64 "\n", __func__, slot, rb, rs, |
773 | 81762d6d | David Gibson | slb->esid, slb->vsid); |
774 | f6b868fc | blueswir1 | |
775 | 81762d6d | David Gibson | return 0; |
776 | 12de9a39 | j_mayer | } |
777 | efdef95f | David Gibson | |
778 | efdef95f | David Gibson | int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
|
779 | efdef95f | David Gibson | { |
780 | efdef95f | David Gibson | int slot = rb & 0xfff; |
781 | efdef95f | David Gibson | ppc_slb_t *slb = &env->slb[slot]; |
782 | efdef95f | David Gibson | |
783 | efdef95f | David Gibson | if (slot >= env->slb_nr) {
|
784 | efdef95f | David Gibson | return -1; |
785 | efdef95f | David Gibson | } |
786 | efdef95f | David Gibson | |
787 | efdef95f | David Gibson | *rt = slb->esid; |
788 | efdef95f | David Gibson | return 0; |
789 | efdef95f | David Gibson | } |
790 | efdef95f | David Gibson | |
791 | efdef95f | David Gibson | int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
|
792 | efdef95f | David Gibson | { |
793 | efdef95f | David Gibson | int slot = rb & 0xfff; |
794 | efdef95f | David Gibson | ppc_slb_t *slb = &env->slb[slot]; |
795 | efdef95f | David Gibson | |
796 | efdef95f | David Gibson | if (slot >= env->slb_nr) {
|
797 | efdef95f | David Gibson | return -1; |
798 | efdef95f | David Gibson | } |
799 | efdef95f | David Gibson | |
800 | efdef95f | David Gibson | *rt = slb->vsid; |
801 | efdef95f | David Gibson | return 0; |
802 | efdef95f | David Gibson | } |
803 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
804 | 79aceca5 | bellard | |
805 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
806 | c227f099 | Anthony Liguori | static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1, |
807 | 636aa200 | Blue Swirl | int sdr_sh,
|
808 | c227f099 | Anthony Liguori | target_phys_addr_t hash, |
809 | c227f099 | Anthony Liguori | target_phys_addr_t mask) |
810 | 12de9a39 | j_mayer | { |
811 | c227f099 | Anthony Liguori | return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
812 | 12de9a39 | j_mayer | } |
813 | 12de9a39 | j_mayer | |
814 | c227f099 | Anthony Liguori | static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, |
815 | 636aa200 | Blue Swirl | target_ulong eaddr, int rw, int type) |
816 | 79aceca5 | bellard | { |
817 | c227f099 | Anthony Liguori | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
818 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
819 | 5b5aba4f | blueswir1 | int ds, vsid_sh, sdr_sh, pr, target_page_bits;
|
820 | caa4039c | j_mayer | int ret, ret2;
|
821 | caa4039c | j_mayer | |
822 | 0411a972 | j_mayer | pr = msr_pr; |
823 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
824 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
825 | 81762d6d | David Gibson | int attr;
|
826 | 81762d6d | David Gibson | |
827 | d12d51d5 | aliguori | LOG_MMU("Check SLBs\n");
|
828 | 5b5aba4f | blueswir1 | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, |
829 | 5b5aba4f | blueswir1 | &target_page_bits); |
830 | caa4039c | j_mayer | if (ret < 0) |
831 | caa4039c | j_mayer | return ret;
|
832 | 81762d6d | David Gibson | ctx->key = !!(pr ? (attr & SLB_VSID_KP) : (attr & SLB_VSID_KS)); |
833 | caa4039c | j_mayer | ds = 0;
|
834 | 81762d6d | David Gibson | ctx->nx = !!(attr & SLB_VSID_N); |
835 | 5b5aba4f | blueswir1 | ctx->eaddr = eaddr; |
836 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
837 | caa4039c | j_mayer | vsid_sh = 7;
|
838 | caa4039c | j_mayer | sdr_sh = 18;
|
839 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
840 | caa4039c | j_mayer | } else
|
841 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
842 | caa4039c | j_mayer | { |
843 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
844 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
845 | 0411a972 | j_mayer | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
846 | 0411a972 | j_mayer | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
847 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
848 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
849 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
850 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
851 | caa4039c | j_mayer | vsid_sh = 6;
|
852 | caa4039c | j_mayer | sdr_sh = 16;
|
853 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
854 | 5b5aba4f | blueswir1 | target_page_bits = TARGET_PAGE_BITS; |
855 | 90e189ec | Blue Swirl | LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" |
856 | 90e189ec | Blue Swirl | TARGET_FMT_lx " lr=" TARGET_FMT_lx
|
857 | 90e189ec | Blue Swirl | " ir=%d dr=%d pr=%d %d t=%d\n",
|
858 | 90e189ec | Blue Swirl | eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, |
859 | 90e189ec | Blue Swirl | (int)msr_dr, pr != 0 ? 1 : 0, rw, type); |
860 | caa4039c | j_mayer | } |
861 | 90e189ec | Blue Swirl | LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", |
862 | 90e189ec | Blue Swirl | ctx->key, ds, ctx->nx, vsid); |
863 | caa4039c | j_mayer | ret = -1;
|
864 | caa4039c | j_mayer | if (!ds) {
|
865 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
866 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
867 | 9a64fbe4 | bellard | /* Page address translation */
|
868 | 76a66253 | j_mayer | /* Primary table address */
|
869 | 76a66253 | j_mayer | sdr = env->sdr1; |
870 | 5b5aba4f | blueswir1 | pgidx = (eaddr & page_mask) >> target_page_bits; |
871 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
872 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
873 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
874 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
875 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
876 | 12de9a39 | j_mayer | } else
|
877 | 12de9a39 | j_mayer | #endif
|
878 | 12de9a39 | j_mayer | { |
879 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
880 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
881 | 12de9a39 | j_mayer | } |
882 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
883 | 90e189ec | Blue Swirl | LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
884 | 90e189ec | Blue Swirl | " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
885 | 90e189ec | Blue Swirl | sdr, sdr_sh, hash, mask, page_mask); |
886 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
887 | 76a66253 | j_mayer | /* Secondary table address */
|
888 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
889 | 90e189ec | Blue Swirl | LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
890 | 90e189ec | Blue Swirl | " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask); |
891 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
892 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
893 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
894 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
895 | 5b5aba4f | blueswir1 | if (target_page_bits > 23) { |
896 | 5b5aba4f | blueswir1 | ctx->ptem = (vsid << 12) |
|
897 | 5b5aba4f | blueswir1 | ((pgidx << (target_page_bits - 16)) & 0xF80); |
898 | 5b5aba4f | blueswir1 | } else {
|
899 | 5b5aba4f | blueswir1 | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
900 | 5b5aba4f | blueswir1 | } |
901 | caa4039c | j_mayer | } else
|
902 | caa4039c | j_mayer | #endif
|
903 | caa4039c | j_mayer | { |
904 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
905 | caa4039c | j_mayer | } |
906 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
907 | c227f099 | Anthony Liguori | ctx->raddr = (target_phys_addr_t)-1ULL;
|
908 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
909 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
910 | 76a66253 | j_mayer | /* Software TLB search */
|
911 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
912 | 76a66253 | j_mayer | } else {
|
913 | 90e189ec | Blue Swirl | LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
914 | 90e189ec | Blue Swirl | "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx |
915 | 90e189ec | Blue Swirl | " pg_addr=" TARGET_FMT_plx "\n", |
916 | 90e189ec | Blue Swirl | sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
917 | 76a66253 | j_mayer | /* Primary table lookup */
|
918 | 5b5aba4f | blueswir1 | ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
|
919 | 76a66253 | j_mayer | if (ret < 0) { |
920 | 76a66253 | j_mayer | /* Secondary table lookup */
|
921 | d12d51d5 | aliguori | if (eaddr != 0xEFFFFFFF) |
922 | 90e189ec | Blue Swirl | LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
923 | 90e189ec | Blue Swirl | "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx |
924 | 90e189ec | Blue Swirl | " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid, |
925 | 90e189ec | Blue Swirl | pgidx, hash, ctx->pg_addr[1]);
|
926 | 5b5aba4f | blueswir1 | ret2 = find_pte(env, ctx, 1, rw, type,
|
927 | 5b5aba4f | blueswir1 | target_page_bits); |
928 | 76a66253 | j_mayer | if (ret2 != -1) |
929 | 76a66253 | j_mayer | ret = ret2; |
930 | 76a66253 | j_mayer | } |
931 | 9a64fbe4 | bellard | } |
932 | 0411a972 | j_mayer | #if defined (DUMP_PAGE_TABLES)
|
933 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
934 | c227f099 | Anthony Liguori | target_phys_addr_t curaddr; |
935 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
936 | 90e189ec | Blue Swirl | qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx |
937 | 90e189ec | Blue Swirl | "\n", sdr, mask + 0x80); |
938 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
939 | b33c17e1 | j_mayer | curaddr += 16) {
|
940 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
941 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
942 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
943 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
944 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
945 | 90e189ec | Blue Swirl | qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
|
946 | 90e189ec | Blue Swirl | curaddr, a0, a1, a2, a3); |
947 | 12de9a39 | j_mayer | } |
948 | b33c17e1 | j_mayer | } |
949 | b33c17e1 | j_mayer | } |
950 | 12de9a39 | j_mayer | #endif
|
951 | 9a64fbe4 | bellard | } else {
|
952 | d12d51d5 | aliguori | LOG_MMU("No access allowed\n");
|
953 | 76a66253 | j_mayer | ret = -3;
|
954 | 9a64fbe4 | bellard | } |
955 | 9a64fbe4 | bellard | } else {
|
956 | d12d51d5 | aliguori | LOG_MMU("direct store...\n");
|
957 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
958 | 9a64fbe4 | bellard | switch (type) {
|
959 | 9a64fbe4 | bellard | case ACCESS_INT:
|
960 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
961 | 9a64fbe4 | bellard | break;
|
962 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
963 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
964 | 9a64fbe4 | bellard | return -4; |
965 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
966 | 9a64fbe4 | bellard | /* Floating point load/store */
|
967 | 9a64fbe4 | bellard | return -4; |
968 | 9a64fbe4 | bellard | case ACCESS_RES:
|
969 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
970 | 9a64fbe4 | bellard | return -4; |
971 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
972 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
973 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
974 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
975 | 9a64fbe4 | bellard | */
|
976 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
977 | 9a64fbe4 | bellard | return 0; |
978 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
979 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
980 | 9a64fbe4 | bellard | return -4; |
981 | 9a64fbe4 | bellard | default:
|
982 | 93fcfe39 | aliguori | qemu_log("ERROR: instruction should not need "
|
983 | 9a64fbe4 | bellard | "address translation\n");
|
984 | 9a64fbe4 | bellard | return -4; |
985 | 9a64fbe4 | bellard | } |
986 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
987 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
988 | 9a64fbe4 | bellard | ret = 2;
|
989 | 9a64fbe4 | bellard | } else {
|
990 | 9a64fbe4 | bellard | ret = -2;
|
991 | 9a64fbe4 | bellard | } |
992 | 79aceca5 | bellard | } |
993 | 9a64fbe4 | bellard | |
994 | 9a64fbe4 | bellard | return ret;
|
995 | 79aceca5 | bellard | } |
996 | 79aceca5 | bellard | |
997 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
998 | c227f099 | Anthony Liguori | static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, |
999 | c227f099 | Anthony Liguori | target_phys_addr_t *raddrp, |
1000 | 636aa200 | Blue Swirl | target_ulong address, uint32_t pid, int ext,
|
1001 | 636aa200 | Blue Swirl | int i)
|
1002 | c294fc58 | j_mayer | { |
1003 | c294fc58 | j_mayer | target_ulong mask; |
1004 | c294fc58 | j_mayer | |
1005 | c294fc58 | j_mayer | /* Check valid flag */
|
1006 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1007 | c294fc58 | j_mayer | return -1; |
1008 | c294fc58 | j_mayer | } |
1009 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1010 | 90e189ec | Blue Swirl | LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx |
1011 | 90e189ec | Blue Swirl | " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN, |
1012 | 90e189ec | Blue Swirl | mask, (uint32_t)tlb->PID); |
1013 | c294fc58 | j_mayer | /* Check PID */
|
1014 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1015 | c294fc58 | j_mayer | return -1; |
1016 | c294fc58 | j_mayer | /* Check effective address */
|
1017 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1018 | c294fc58 | j_mayer | return -1; |
1019 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1020 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1021 | 36081602 | j_mayer | if (ext) {
|
1022 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1023 | c227f099 | Anthony Liguori | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1024 | 36081602 | j_mayer | } |
1025 | 9706285b | j_mayer | #endif
|
1026 | c294fc58 | j_mayer | |
1027 | c294fc58 | j_mayer | return 0; |
1028 | c294fc58 | j_mayer | } |
1029 | c294fc58 | j_mayer | |
1030 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1031 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1032 | c294fc58 | j_mayer | { |
1033 | c227f099 | Anthony Liguori | ppcemb_tlb_t *tlb; |
1034 | c227f099 | Anthony Liguori | target_phys_addr_t raddr; |
1035 | c294fc58 | j_mayer | int i, ret;
|
1036 | c294fc58 | j_mayer | |
1037 | c294fc58 | j_mayer | /* Default return value is no match */
|
1038 | c294fc58 | j_mayer | ret = -1;
|
1039 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1040 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1041 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1042 | c294fc58 | j_mayer | ret = i; |
1043 | c294fc58 | j_mayer | break;
|
1044 | c294fc58 | j_mayer | } |
1045 | c294fc58 | j_mayer | } |
1046 | c294fc58 | j_mayer | |
1047 | c294fc58 | j_mayer | return ret;
|
1048 | c294fc58 | j_mayer | } |
1049 | c294fc58 | j_mayer | |
1050 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1051 | 636aa200 | Blue Swirl | static inline void ppc4xx_tlb_invalidate_all(CPUState *env) |
1052 | a750fc0b | j_mayer | { |
1053 | c227f099 | Anthony Liguori | ppcemb_tlb_t *tlb; |
1054 | a750fc0b | j_mayer | int i;
|
1055 | a750fc0b | j_mayer | |
1056 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1057 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1058 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1059 | a750fc0b | j_mayer | } |
1060 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1061 | a750fc0b | j_mayer | } |
1062 | a750fc0b | j_mayer | |
1063 | 636aa200 | Blue Swirl | static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, |
1064 | 636aa200 | Blue Swirl | target_ulong eaddr, uint32_t pid) |
1065 | 0a032cbe | j_mayer | { |
1066 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1067 | c227f099 | Anthony Liguori | ppcemb_tlb_t *tlb; |
1068 | c227f099 | Anthony Liguori | target_phys_addr_t raddr; |
1069 | daf4f96e | j_mayer | target_ulong page, end; |
1070 | 0a032cbe | j_mayer | int i;
|
1071 | 0a032cbe | j_mayer | |
1072 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1073 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1074 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1075 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1076 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1077 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1078 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1079 | daf4f96e | j_mayer | break;
|
1080 | 0a032cbe | j_mayer | } |
1081 | 0a032cbe | j_mayer | } |
1082 | daf4f96e | j_mayer | #else
|
1083 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1084 | daf4f96e | j_mayer | #endif
|
1085 | 0a032cbe | j_mayer | } |
1086 | 0a032cbe | j_mayer | |
1087 | c227f099 | Anthony Liguori | static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1088 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1089 | a8dea12f | j_mayer | { |
1090 | c227f099 | Anthony Liguori | ppcemb_tlb_t *tlb; |
1091 | c227f099 | Anthony Liguori | target_phys_addr_t raddr; |
1092 | 0411a972 | j_mayer | int i, ret, zsel, zpr, pr;
|
1093 | 3b46e624 | ths | |
1094 | c55e9aef | j_mayer | ret = -1;
|
1095 | c227f099 | Anthony Liguori | raddr = (target_phys_addr_t)-1ULL;
|
1096 | 0411a972 | j_mayer | pr = msr_pr; |
1097 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1098 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1099 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1100 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1101 | a8dea12f | j_mayer | continue;
|
1102 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1103 | ec5c3e48 | Edgar E. Iglesias | zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3; |
1104 | d12d51d5 | aliguori | LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1105 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1106 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1107 | b227a8e9 | j_mayer | switch (zpr) {
|
1108 | b227a8e9 | j_mayer | case 0x2: |
1109 | 0411a972 | j_mayer | if (pr != 0) |
1110 | b227a8e9 | j_mayer | goto check_perms;
|
1111 | b227a8e9 | j_mayer | /* No break here */
|
1112 | b227a8e9 | j_mayer | case 0x3: |
1113 | b227a8e9 | j_mayer | /* All accesses granted */
|
1114 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1115 | b227a8e9 | j_mayer | ret = 0;
|
1116 | b227a8e9 | j_mayer | break;
|
1117 | b227a8e9 | j_mayer | case 0x0: |
1118 | 0411a972 | j_mayer | if (pr != 0) { |
1119 | dcbc9a70 | Edgar E. Iglesias | /* Raise Zone protection fault. */
|
1120 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_40x_ESR] = 1 << 22; |
1121 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1122 | b227a8e9 | j_mayer | ret = -2;
|
1123 | a8dea12f | j_mayer | break;
|
1124 | a8dea12f | j_mayer | } |
1125 | b227a8e9 | j_mayer | /* No break here */
|
1126 | b227a8e9 | j_mayer | case 0x1: |
1127 | b227a8e9 | j_mayer | check_perms:
|
1128 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1129 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1130 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1131 | dcbc9a70 | Edgar E. Iglesias | if (ret == -2) |
1132 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_40x_ESR] = 0;
|
1133 | b227a8e9 | j_mayer | break;
|
1134 | a8dea12f | j_mayer | } |
1135 | a8dea12f | j_mayer | if (ret >= 0) { |
1136 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1137 | 90e189ec | Blue Swirl | LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx |
1138 | 90e189ec | Blue Swirl | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1139 | 90e189ec | Blue Swirl | ret); |
1140 | c55e9aef | j_mayer | return 0; |
1141 | a8dea12f | j_mayer | } |
1142 | a8dea12f | j_mayer | } |
1143 | 90e189ec | Blue Swirl | LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx |
1144 | 90e189ec | Blue Swirl | " %d %d\n", __func__, address, raddr, ctx->prot, ret);
|
1145 | 3b46e624 | ths | |
1146 | a8dea12f | j_mayer | return ret;
|
1147 | a8dea12f | j_mayer | } |
1148 | a8dea12f | j_mayer | |
1149 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1150 | c294fc58 | j_mayer | { |
1151 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1152 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1153 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1154 | c294fc58 | j_mayer | } |
1155 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1156 | c294fc58 | j_mayer | } |
1157 | c294fc58 | j_mayer | |
1158 | c227f099 | Anthony Liguori | static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1159 | 93220573 | aurel32 | target_ulong address, int rw,
|
1160 | 93220573 | aurel32 | int access_type)
|
1161 | 5eb7995e | j_mayer | { |
1162 | c227f099 | Anthony Liguori | ppcemb_tlb_t *tlb; |
1163 | c227f099 | Anthony Liguori | target_phys_addr_t raddr; |
1164 | 5eb7995e | j_mayer | int i, prot, ret;
|
1165 | 5eb7995e | j_mayer | |
1166 | 5eb7995e | j_mayer | ret = -1;
|
1167 | c227f099 | Anthony Liguori | raddr = (target_phys_addr_t)-1ULL;
|
1168 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1169 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1170 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1171 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1172 | 5eb7995e | j_mayer | continue;
|
1173 | 0411a972 | j_mayer | if (msr_pr != 0) |
1174 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1175 | 5eb7995e | j_mayer | else
|
1176 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1177 | 5eb7995e | j_mayer | /* Check the address space */
|
1178 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1179 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1180 | 5eb7995e | j_mayer | continue;
|
1181 | 5eb7995e | j_mayer | ctx->prot = prot; |
1182 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1183 | 5eb7995e | j_mayer | ret = 0;
|
1184 | 5eb7995e | j_mayer | break;
|
1185 | 5eb7995e | j_mayer | } |
1186 | 5eb7995e | j_mayer | ret = -3;
|
1187 | 5eb7995e | j_mayer | } else {
|
1188 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1189 | 5eb7995e | j_mayer | continue;
|
1190 | 5eb7995e | j_mayer | ctx->prot = prot; |
1191 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1192 | 5eb7995e | j_mayer | ret = 0;
|
1193 | 5eb7995e | j_mayer | break;
|
1194 | 5eb7995e | j_mayer | } |
1195 | 5eb7995e | j_mayer | ret = -2;
|
1196 | 5eb7995e | j_mayer | } |
1197 | 5eb7995e | j_mayer | } |
1198 | 5eb7995e | j_mayer | if (ret >= 0) |
1199 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1200 | 5eb7995e | j_mayer | |
1201 | 5eb7995e | j_mayer | return ret;
|
1202 | 5eb7995e | j_mayer | } |
1203 | 5eb7995e | j_mayer | |
1204 | c227f099 | Anthony Liguori | static inline int check_physical(CPUState *env, mmu_ctx_t *ctx, |
1205 | 636aa200 | Blue Swirl | target_ulong eaddr, int rw)
|
1206 | 76a66253 | j_mayer | { |
1207 | 76a66253 | j_mayer | int in_plb, ret;
|
1208 | 3b46e624 | ths | |
1209 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1210 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1211 | 76a66253 | j_mayer | ret = 0;
|
1212 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1213 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1214 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1215 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1216 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1217 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1218 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1219 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1220 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1221 | caa4039c | j_mayer | break;
|
1222 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1223 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1224 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1225 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1226 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1227 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1228 | caa4039c | j_mayer | break;
|
1229 | 9706285b | j_mayer | #endif
|
1230 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1231 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1232 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1233 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1234 | caa4039c | j_mayer | */
|
1235 | caa4039c | j_mayer | in_plb = |
1236 | caa4039c | j_mayer | /* Check PLB validity */
|
1237 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1238 | caa4039c | j_mayer | /* and address in plb area */
|
1239 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1240 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1241 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1242 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1243 | caa4039c | j_mayer | /* Access in protected area */
|
1244 | caa4039c | j_mayer | if (rw == 1) { |
1245 | caa4039c | j_mayer | /* Access is not allowed */
|
1246 | caa4039c | j_mayer | ret = -2;
|
1247 | caa4039c | j_mayer | } |
1248 | caa4039c | j_mayer | } else {
|
1249 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1250 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1251 | 76a66253 | j_mayer | } |
1252 | 76a66253 | j_mayer | } |
1253 | e1833e1f | j_mayer | break;
|
1254 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1255 | b4095fed | j_mayer | /* XXX: TODO */
|
1256 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1257 | b4095fed | j_mayer | break;
|
1258 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1259 | caa4039c | j_mayer | /* XXX: TODO */
|
1260 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1261 | caa4039c | j_mayer | break;
|
1262 | caa4039c | j_mayer | default:
|
1263 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1264 | caa4039c | j_mayer | return -1; |
1265 | 76a66253 | j_mayer | } |
1266 | 76a66253 | j_mayer | |
1267 | 76a66253 | j_mayer | return ret;
|
1268 | 76a66253 | j_mayer | } |
1269 | 76a66253 | j_mayer | |
1270 | c227f099 | Anthony Liguori | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1271 | faadf50e | j_mayer | int rw, int access_type) |
1272 | 9a64fbe4 | bellard | { |
1273 | 9a64fbe4 | bellard | int ret;
|
1274 | 0411a972 | j_mayer | |
1275 | 514fb8c1 | bellard | #if 0
|
1276 | 93fcfe39 | aliguori | qemu_log("%s\n", __func__);
|
1277 | d9bce9d9 | j_mayer | #endif
|
1278 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1279 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1280 | a586e548 | Edgar E. Iglesias | if (env->mmu_model == POWERPC_MMU_BOOKE) {
|
1281 | a586e548 | Edgar E. Iglesias | /* The BookE MMU always performs address translation. The
|
1282 | a586e548 | Edgar E. Iglesias | IS and DS bits only affect the address space. */
|
1283 | a586e548 | Edgar E. Iglesias | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1284 | a586e548 | Edgar E. Iglesias | rw, access_type); |
1285 | a586e548 | Edgar E. Iglesias | } else {
|
1286 | a586e548 | Edgar E. Iglesias | /* No address translation. */
|
1287 | a586e548 | Edgar E. Iglesias | ret = check_physical(env, ctx, eaddr, rw); |
1288 | a586e548 | Edgar E. Iglesias | } |
1289 | 9a64fbe4 | bellard | } else {
|
1290 | c55e9aef | j_mayer | ret = -1;
|
1291 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1292 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1293 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1294 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1295 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1296 | 94855937 | blueswir1 | /* Try to find a BAT */
|
1297 | 94855937 | blueswir1 | if (env->nb_BATs != 0) |
1298 | 94855937 | blueswir1 | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1299 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1300 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1301 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1302 | c55e9aef | j_mayer | #endif
|
1303 | a8dea12f | j_mayer | if (ret < 0) { |
1304 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1305 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1306 | a8dea12f | j_mayer | } |
1307 | a8dea12f | j_mayer | break;
|
1308 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1309 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1310 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1311 | a8dea12f | j_mayer | rw, access_type); |
1312 | a8dea12f | j_mayer | break;
|
1313 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1314 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1315 | 5eb7995e | j_mayer | rw, access_type); |
1316 | 5eb7995e | j_mayer | break;
|
1317 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1318 | b4095fed | j_mayer | /* XXX: TODO */
|
1319 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1320 | b4095fed | j_mayer | break;
|
1321 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1322 | c55e9aef | j_mayer | /* XXX: TODO */
|
1323 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1324 | c55e9aef | j_mayer | return -1; |
1325 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1326 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode do not do any translation\n");
|
1327 | 2662a059 | j_mayer | return -1; |
1328 | c55e9aef | j_mayer | default:
|
1329 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1330 | a8dea12f | j_mayer | return -1; |
1331 | 9a64fbe4 | bellard | } |
1332 | 9a64fbe4 | bellard | } |
1333 | 514fb8c1 | bellard | #if 0
|
1334 | 90e189ec | Blue Swirl | qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
|
1335 | 90e189ec | Blue Swirl | __func__, eaddr, ret, ctx->raddr);
|
1336 | 76a66253 | j_mayer | #endif
|
1337 | d9bce9d9 | j_mayer | |
1338 | 9a64fbe4 | bellard | return ret;
|
1339 | 9a64fbe4 | bellard | } |
1340 | 9a64fbe4 | bellard | |
1341 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1342 | a6b025d3 | bellard | { |
1343 | c227f099 | Anthony Liguori | mmu_ctx_t ctx; |
1344 | a6b025d3 | bellard | |
1345 | faadf50e | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
1346 | a6b025d3 | bellard | return -1; |
1347 | 76a66253 | j_mayer | |
1348 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1349 | a6b025d3 | bellard | } |
1350 | 9a64fbe4 | bellard | |
1351 | 9a64fbe4 | bellard | /* Perform address translation */
|
1352 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1353 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1354 | 9a64fbe4 | bellard | { |
1355 | c227f099 | Anthony Liguori | mmu_ctx_t ctx; |
1356 | a541f297 | bellard | int access_type;
|
1357 | 9a64fbe4 | bellard | int ret = 0; |
1358 | d9bce9d9 | j_mayer | |
1359 | b769d8fe | bellard | if (rw == 2) { |
1360 | b769d8fe | bellard | /* code access */
|
1361 | b769d8fe | bellard | rw = 0;
|
1362 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1363 | b769d8fe | bellard | } else {
|
1364 | b769d8fe | bellard | /* data access */
|
1365 | b4cec7b4 | aurel32 | access_type = env->access_type; |
1366 | b769d8fe | bellard | } |
1367 | faadf50e | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type); |
1368 | 9a64fbe4 | bellard | if (ret == 0) { |
1369 | d4c430a8 | Paul Brook | tlb_set_page(env, address & TARGET_PAGE_MASK, |
1370 | d4c430a8 | Paul Brook | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1371 | d4c430a8 | Paul Brook | mmu_idx, TARGET_PAGE_SIZE); |
1372 | d4c430a8 | Paul Brook | ret = 0;
|
1373 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1374 | d12d51d5 | aliguori | LOG_MMU_STATE(env); |
1375 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1376 | 9a64fbe4 | bellard | switch (ret) {
|
1377 | 9a64fbe4 | bellard | case -1: |
1378 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1379 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1380 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1381 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1382 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1383 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1384 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1385 | 76a66253 | j_mayer | goto tlb_miss;
|
1386 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1387 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1388 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1389 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1390 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1391 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1392 | 8f793433 | j_mayer | env->error_code = 0;
|
1393 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1394 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1395 | c55e9aef | j_mayer | break;
|
1396 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1397 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1398 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1399 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1400 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1401 | c55e9aef | j_mayer | #endif
|
1402 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1403 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1404 | 8f793433 | j_mayer | break;
|
1405 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1406 | a586e548 | Edgar E. Iglesias | env->exception_index = POWERPC_EXCP_ITLB; |
1407 | a586e548 | Edgar E. Iglesias | env->error_code = 0;
|
1408 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_DEAR] = address; |
1409 | c55e9aef | j_mayer | return -1; |
1410 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1411 | c55e9aef | j_mayer | /* XXX: TODO */
|
1412 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1413 | c55e9aef | j_mayer | return -1; |
1414 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1415 | b4095fed | j_mayer | /* XXX: TODO */
|
1416 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1417 | b4095fed | j_mayer | break;
|
1418 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1419 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1420 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1421 | 2662a059 | j_mayer | return -1; |
1422 | c55e9aef | j_mayer | default:
|
1423 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1424 | c55e9aef | j_mayer | return -1; |
1425 | 76a66253 | j_mayer | } |
1426 | 9a64fbe4 | bellard | break;
|
1427 | 9a64fbe4 | bellard | case -2: |
1428 | 9a64fbe4 | bellard | /* Access rights violation */
|
1429 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1430 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1431 | 9a64fbe4 | bellard | break;
|
1432 | 9a64fbe4 | bellard | case -3: |
1433 | 76a66253 | j_mayer | /* No execute protection violation */
|
1434 | a586e548 | Edgar E. Iglesias | if (env->mmu_model == POWERPC_MMU_BOOKE) {
|
1435 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_ESR] = 0x00000000;
|
1436 | a586e548 | Edgar E. Iglesias | } |
1437 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1438 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1439 | 9a64fbe4 | bellard | break;
|
1440 | 9a64fbe4 | bellard | case -4: |
1441 | 9a64fbe4 | bellard | /* Direct store exception */
|
1442 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1443 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1444 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1445 | 2be0071f | bellard | break;
|
1446 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1447 | 2be0071f | bellard | case -5: |
1448 | 2be0071f | bellard | /* No match in segment table */
|
1449 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1450 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1451 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1452 | add78955 | j_mayer | env->error_code = 0x40000000;
|
1453 | add78955 | j_mayer | } else {
|
1454 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1455 | add78955 | j_mayer | env->error_code = 0;
|
1456 | add78955 | j_mayer | } |
1457 | 9a64fbe4 | bellard | break;
|
1458 | e1833e1f | j_mayer | #endif
|
1459 | 9a64fbe4 | bellard | } |
1460 | 9a64fbe4 | bellard | } else {
|
1461 | 9a64fbe4 | bellard | switch (ret) {
|
1462 | 9a64fbe4 | bellard | case -1: |
1463 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1464 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1465 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1466 | 76a66253 | j_mayer | if (rw == 1) { |
1467 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1468 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1469 | 76a66253 | j_mayer | } else {
|
1470 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1471 | 8f793433 | j_mayer | env->error_code = 0;
|
1472 | 76a66253 | j_mayer | } |
1473 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1474 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1475 | 76a66253 | j_mayer | tlb_miss:
|
1476 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1477 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1478 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1479 | 8f793433 | j_mayer | break;
|
1480 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1481 | 7dbe11ac | j_mayer | if (rw == 1) { |
1482 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1483 | 7dbe11ac | j_mayer | } else {
|
1484 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1485 | 7dbe11ac | j_mayer | } |
1486 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1487 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1488 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1489 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1490 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1491 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1492 | 7dbe11ac | j_mayer | break;
|
1493 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1494 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1495 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1496 | 8f793433 | j_mayer | env->error_code = 0;
|
1497 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1498 | a8dea12f | j_mayer | if (rw)
|
1499 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1500 | a8dea12f | j_mayer | else
|
1501 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1502 | c55e9aef | j_mayer | break;
|
1503 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1504 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1505 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1506 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1507 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1508 | c55e9aef | j_mayer | #endif
|
1509 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1510 | 8f793433 | j_mayer | env->error_code = 0;
|
1511 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1512 | 8f793433 | j_mayer | if (rw == 1) |
1513 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1514 | 8f793433 | j_mayer | else
|
1515 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1516 | 8f793433 | j_mayer | break;
|
1517 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1518 | b4095fed | j_mayer | /* XXX: TODO */
|
1519 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1520 | b4095fed | j_mayer | break;
|
1521 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1522 | a586e548 | Edgar E. Iglesias | env->exception_index = POWERPC_EXCP_DTLB; |
1523 | a586e548 | Edgar E. Iglesias | env->error_code = 0;
|
1524 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_DEAR] = address; |
1525 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; |
1526 | c55e9aef | j_mayer | return -1; |
1527 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1528 | c55e9aef | j_mayer | /* XXX: TODO */
|
1529 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1530 | c55e9aef | j_mayer | return -1; |
1531 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1532 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1533 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1534 | 2662a059 | j_mayer | return -1; |
1535 | c55e9aef | j_mayer | default:
|
1536 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1537 | c55e9aef | j_mayer | return -1; |
1538 | 76a66253 | j_mayer | } |
1539 | 9a64fbe4 | bellard | break;
|
1540 | 9a64fbe4 | bellard | case -2: |
1541 | 9a64fbe4 | bellard | /* Access rights violation */
|
1542 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1543 | 8f793433 | j_mayer | env->error_code = 0;
|
1544 | dcbc9a70 | Edgar E. Iglesias | if (env->mmu_model == POWERPC_MMU_SOFT_4xx
|
1545 | dcbc9a70 | Edgar E. Iglesias | || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { |
1546 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_40x_DEAR] = address; |
1547 | dcbc9a70 | Edgar E. Iglesias | if (rw) {
|
1548 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_40x_ESR] |= 0x00800000;
|
1549 | dcbc9a70 | Edgar E. Iglesias | } |
1550 | a586e548 | Edgar E. Iglesias | } else if (env->mmu_model == POWERPC_MMU_BOOKE) { |
1551 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_DEAR] = address; |
1552 | a586e548 | Edgar E. Iglesias | env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; |
1553 | dcbc9a70 | Edgar E. Iglesias | } else {
|
1554 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_DAR] = address; |
1555 | dcbc9a70 | Edgar E. Iglesias | if (rw == 1) { |
1556 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_DSISR] = 0x0A000000;
|
1557 | dcbc9a70 | Edgar E. Iglesias | } else {
|
1558 | dcbc9a70 | Edgar E. Iglesias | env->spr[SPR_DSISR] = 0x08000000;
|
1559 | dcbc9a70 | Edgar E. Iglesias | } |
1560 | dcbc9a70 | Edgar E. Iglesias | } |
1561 | 9a64fbe4 | bellard | break;
|
1562 | 9a64fbe4 | bellard | case -4: |
1563 | 9a64fbe4 | bellard | /* Direct store exception */
|
1564 | 9a64fbe4 | bellard | switch (access_type) {
|
1565 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1566 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1567 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1568 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1569 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1570 | 9a64fbe4 | bellard | break;
|
1571 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1572 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1573 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1574 | 8f793433 | j_mayer | env->error_code = 0;
|
1575 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1576 | 8f793433 | j_mayer | if (rw == 1) |
1577 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1578 | 8f793433 | j_mayer | else
|
1579 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1580 | 9a64fbe4 | bellard | break;
|
1581 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1582 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1583 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1584 | 8f793433 | j_mayer | env->error_code = 0;
|
1585 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1586 | 8f793433 | j_mayer | if (rw == 1) |
1587 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1588 | 8f793433 | j_mayer | else
|
1589 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1590 | 9a64fbe4 | bellard | break;
|
1591 | 9a64fbe4 | bellard | default:
|
1592 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1593 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1594 | 8f793433 | j_mayer | env->error_code = |
1595 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1596 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1597 | 9a64fbe4 | bellard | break;
|
1598 | 9a64fbe4 | bellard | } |
1599 | fdabc366 | bellard | break;
|
1600 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1601 | 2be0071f | bellard | case -5: |
1602 | 2be0071f | bellard | /* No match in segment table */
|
1603 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1604 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1605 | add78955 | j_mayer | env->error_code = 0;
|
1606 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1607 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1608 | add78955 | j_mayer | if (rw == 1) |
1609 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1610 | add78955 | j_mayer | else
|
1611 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1612 | add78955 | j_mayer | } else {
|
1613 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1614 | add78955 | j_mayer | env->error_code = 0;
|
1615 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1616 | add78955 | j_mayer | } |
1617 | 2be0071f | bellard | break;
|
1618 | e1833e1f | j_mayer | #endif
|
1619 | 9a64fbe4 | bellard | } |
1620 | 9a64fbe4 | bellard | } |
1621 | 9a64fbe4 | bellard | #if 0
|
1622 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1623 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1624 | 9a64fbe4 | bellard | #endif
|
1625 | 9a64fbe4 | bellard | ret = 1;
|
1626 | 9a64fbe4 | bellard | } |
1627 | 76a66253 | j_mayer | |
1628 | 9a64fbe4 | bellard | return ret;
|
1629 | 9a64fbe4 | bellard | } |
1630 | 9a64fbe4 | bellard | |
1631 | 3fc6c082 | bellard | /*****************************************************************************/
|
1632 | 3fc6c082 | bellard | /* BATs management */
|
1633 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1634 | 636aa200 | Blue Swirl | static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, |
1635 | 636aa200 | Blue Swirl | target_ulong mask) |
1636 | 3fc6c082 | bellard | { |
1637 | 3fc6c082 | bellard | target_ulong base, end, page; |
1638 | 76a66253 | j_mayer | |
1639 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1640 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1641 | 90e189ec | Blue Swirl | LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" |
1642 | 90e189ec | Blue Swirl | TARGET_FMT_lx ")\n", base, end, mask);
|
1643 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1644 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1645 | d12d51d5 | aliguori | LOG_BATS("Flush done\n");
|
1646 | 3fc6c082 | bellard | } |
1647 | 3fc6c082 | bellard | #endif
|
1648 | 3fc6c082 | bellard | |
1649 | 636aa200 | Blue Swirl | static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr, |
1650 | 636aa200 | Blue Swirl | target_ulong value) |
1651 | 3fc6c082 | bellard | { |
1652 | 90e189ec | Blue Swirl | LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID, |
1653 | 90e189ec | Blue Swirl | nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1654 | 3fc6c082 | bellard | } |
1655 | 3fc6c082 | bellard | |
1656 | 45d827d2 | aurel32 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1657 | 3fc6c082 | bellard | { |
1658 | 3fc6c082 | bellard | target_ulong mask; |
1659 | 3fc6c082 | bellard | |
1660 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1661 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1662 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1663 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1664 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1665 | 3fc6c082 | bellard | #endif
|
1666 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1667 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1668 | 3fc6c082 | bellard | */
|
1669 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1670 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1671 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1672 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1673 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1674 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1675 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1676 | 76a66253 | j_mayer | #else
|
1677 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1678 | 3fc6c082 | bellard | #endif
|
1679 | 3fc6c082 | bellard | } |
1680 | 3fc6c082 | bellard | } |
1681 | 3fc6c082 | bellard | |
1682 | 45d827d2 | aurel32 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1683 | 3fc6c082 | bellard | { |
1684 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1685 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1686 | 3fc6c082 | bellard | } |
1687 | 3fc6c082 | bellard | |
1688 | 45d827d2 | aurel32 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1689 | 3fc6c082 | bellard | { |
1690 | 3fc6c082 | bellard | target_ulong mask; |
1691 | 3fc6c082 | bellard | |
1692 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1693 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1694 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1695 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1696 | 3fc6c082 | bellard | */
|
1697 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1698 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1699 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1700 | 3fc6c082 | bellard | #endif
|
1701 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1702 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1703 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1704 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1705 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1706 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1707 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1708 | 3fc6c082 | bellard | #else
|
1709 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1710 | 3fc6c082 | bellard | #endif
|
1711 | 3fc6c082 | bellard | } |
1712 | 3fc6c082 | bellard | } |
1713 | 3fc6c082 | bellard | |
1714 | 45d827d2 | aurel32 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1715 | 3fc6c082 | bellard | { |
1716 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1717 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1718 | 3fc6c082 | bellard | } |
1719 | 3fc6c082 | bellard | |
1720 | 45d827d2 | aurel32 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
1721 | 056401ea | j_mayer | { |
1722 | 056401ea | j_mayer | target_ulong mask; |
1723 | 05f92404 | Blue Swirl | #if defined(FLUSH_ALL_TLBS)
|
1724 | 056401ea | j_mayer | int do_inval;
|
1725 | 05f92404 | Blue Swirl | #endif
|
1726 | 056401ea | j_mayer | |
1727 | 056401ea | j_mayer | dump_store_bat(env, 'I', 0, nr, value); |
1728 | 056401ea | j_mayer | if (env->IBAT[0][nr] != value) { |
1729 | 05f92404 | Blue Swirl | #if defined(FLUSH_ALL_TLBS)
|
1730 | 056401ea | j_mayer | do_inval = 0;
|
1731 | 05f92404 | Blue Swirl | #endif
|
1732 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1733 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1734 | 056401ea | j_mayer | /* Invalidate BAT only if it is valid */
|
1735 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1736 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1737 | 056401ea | j_mayer | #else
|
1738 | 056401ea | j_mayer | do_inval = 1;
|
1739 | 056401ea | j_mayer | #endif
|
1740 | 056401ea | j_mayer | } |
1741 | 056401ea | j_mayer | /* When storing valid upper BAT, mask BEPI and BRPN
|
1742 | 056401ea | j_mayer | * and invalidate all TLBs covered by this BAT
|
1743 | 056401ea | j_mayer | */
|
1744 | 056401ea | j_mayer | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1745 | 056401ea | j_mayer | (value & ~0x0001FFFFUL & ~mask);
|
1746 | 056401ea | j_mayer | env->DBAT[0][nr] = env->IBAT[0][nr]; |
1747 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1748 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1749 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1750 | 056401ea | j_mayer | #else
|
1751 | 056401ea | j_mayer | do_inval = 1;
|
1752 | 056401ea | j_mayer | #endif
|
1753 | 056401ea | j_mayer | } |
1754 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1755 | 056401ea | j_mayer | if (do_inval)
|
1756 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1757 | 056401ea | j_mayer | #endif
|
1758 | 056401ea | j_mayer | } |
1759 | 056401ea | j_mayer | } |
1760 | 056401ea | j_mayer | |
1761 | 45d827d2 | aurel32 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
1762 | 056401ea | j_mayer | { |
1763 | 056401ea | j_mayer | target_ulong mask; |
1764 | 05f92404 | Blue Swirl | #if defined(FLUSH_ALL_TLBS)
|
1765 | 056401ea | j_mayer | int do_inval;
|
1766 | 05f92404 | Blue Swirl | #endif
|
1767 | 056401ea | j_mayer | |
1768 | 056401ea | j_mayer | dump_store_bat(env, 'I', 1, nr, value); |
1769 | 056401ea | j_mayer | if (env->IBAT[1][nr] != value) { |
1770 | 05f92404 | Blue Swirl | #if defined(FLUSH_ALL_TLBS)
|
1771 | 056401ea | j_mayer | do_inval = 0;
|
1772 | 05f92404 | Blue Swirl | #endif
|
1773 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1774 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1775 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1776 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1777 | 056401ea | j_mayer | #else
|
1778 | 056401ea | j_mayer | do_inval = 1;
|
1779 | 056401ea | j_mayer | #endif
|
1780 | 056401ea | j_mayer | } |
1781 | 056401ea | j_mayer | if (value & 0x40) { |
1782 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1783 | 056401ea | j_mayer | mask = (value << 17) & 0x0FFE0000UL; |
1784 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1785 | 056401ea | j_mayer | #else
|
1786 | 056401ea | j_mayer | do_inval = 1;
|
1787 | 056401ea | j_mayer | #endif
|
1788 | 056401ea | j_mayer | } |
1789 | 056401ea | j_mayer | env->IBAT[1][nr] = value;
|
1790 | 056401ea | j_mayer | env->DBAT[1][nr] = value;
|
1791 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1792 | 056401ea | j_mayer | if (do_inval)
|
1793 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1794 | 056401ea | j_mayer | #endif
|
1795 | 056401ea | j_mayer | } |
1796 | 056401ea | j_mayer | } |
1797 | 056401ea | j_mayer | |
1798 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1799 | 0a032cbe | j_mayer | /* TLB management */
|
1800 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1801 | 0a032cbe | j_mayer | { |
1802 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1803 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1804 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1805 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1806 | daf4f96e | j_mayer | break;
|
1807 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1808 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1809 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1810 | daf4f96e | j_mayer | break;
|
1811 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1812 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1813 | 7dbe11ac | j_mayer | break;
|
1814 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1815 | b4095fed | j_mayer | /* XXX: TODO */
|
1816 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1817 | b4095fed | j_mayer | break;
|
1818 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1819 | a586e548 | Edgar E. Iglesias | tlb_flush(env, 1);
|
1820 | 7dbe11ac | j_mayer | break;
|
1821 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1822 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1823 | da07cf59 | aliguori | if (!kvm_enabled())
|
1824 | da07cf59 | aliguori | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1825 | 7dbe11ac | j_mayer | break;
|
1826 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1827 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1828 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1829 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1830 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1831 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1832 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1833 | daf4f96e | j_mayer | break;
|
1834 | 00af685f | j_mayer | default:
|
1835 | 00af685f | j_mayer | /* XXX: TODO */
|
1836 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1837 | 00af685f | j_mayer | break;
|
1838 | 0a032cbe | j_mayer | } |
1839 | 0a032cbe | j_mayer | } |
1840 | 0a032cbe | j_mayer | |
1841 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1842 | daf4f96e | j_mayer | { |
1843 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1844 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1845 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1846 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1847 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1848 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1849 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1850 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1851 | daf4f96e | j_mayer | break;
|
1852 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1853 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1854 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1855 | daf4f96e | j_mayer | break;
|
1856 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1857 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1858 | 7dbe11ac | j_mayer | break;
|
1859 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1860 | b4095fed | j_mayer | /* XXX: TODO */
|
1861 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1862 | b4095fed | j_mayer | break;
|
1863 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1864 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1865 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1866 | 7dbe11ac | j_mayer | break;
|
1867 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1868 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1869 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1870 | 7dbe11ac | j_mayer | break;
|
1871 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1872 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1873 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1874 | 6f2d8978 | j_mayer | addr &= ~((target_ulong)-1ULL << 28); |
1875 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
1876 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
1877 | daf4f96e | j_mayer | */
|
1878 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
1879 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
1880 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
1881 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
1882 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
1883 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
1884 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
1885 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
1886 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
1887 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
1888 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
1889 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
1890 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
1891 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
1892 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
1893 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
1894 | 7dbe11ac | j_mayer | break;
|
1895 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1896 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1897 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1898 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1899 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
1900 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
1901 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
1902 | 7dbe11ac | j_mayer | */
|
1903 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
1904 | 7dbe11ac | j_mayer | break;
|
1905 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1906 | 00af685f | j_mayer | default:
|
1907 | 00af685f | j_mayer | /* XXX: TODO */
|
1908 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1909 | 00af685f | j_mayer | break;
|
1910 | daf4f96e | j_mayer | } |
1911 | daf4f96e | j_mayer | #else
|
1912 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
1913 | daf4f96e | j_mayer | #endif
|
1914 | daf4f96e | j_mayer | } |
1915 | daf4f96e | j_mayer | |
1916 | 3fc6c082 | bellard | /*****************************************************************************/
|
1917 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1918 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1919 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1920 | d9bce9d9 | j_mayer | { |
1921 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1922 | d9bce9d9 | j_mayer | env->asr = value; |
1923 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1924 | d9bce9d9 | j_mayer | } |
1925 | d9bce9d9 | j_mayer | } |
1926 | d9bce9d9 | j_mayer | #endif
|
1927 | d9bce9d9 | j_mayer | |
1928 | 45d827d2 | aurel32 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1929 | 3fc6c082 | bellard | { |
1930 | 90e189ec | Blue Swirl | LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); |
1931 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1932 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
1933 | 12de9a39 | j_mayer | * is <= 28
|
1934 | 12de9a39 | j_mayer | */
|
1935 | 3fc6c082 | bellard | env->sdr1 = value; |
1936 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1937 | 3fc6c082 | bellard | } |
1938 | 3fc6c082 | bellard | } |
1939 | 3fc6c082 | bellard | |
1940 | f6b868fc | blueswir1 | #if defined(TARGET_PPC64)
|
1941 | f6b868fc | blueswir1 | target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
|
1942 | f6b868fc | blueswir1 | { |
1943 | f6b868fc | blueswir1 | // XXX
|
1944 | f6b868fc | blueswir1 | return 0; |
1945 | f6b868fc | blueswir1 | } |
1946 | f6b868fc | blueswir1 | #endif
|
1947 | f6b868fc | blueswir1 | |
1948 | 45d827d2 | aurel32 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1949 | 3fc6c082 | bellard | { |
1950 | 90e189ec | Blue Swirl | LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, |
1951 | 90e189ec | Blue Swirl | srnum, value, env->sr[srnum]); |
1952 | f6b868fc | blueswir1 | #if defined(TARGET_PPC64)
|
1953 | f6b868fc | blueswir1 | if (env->mmu_model & POWERPC_MMU_64) {
|
1954 | f6b868fc | blueswir1 | uint64_t rb = 0, rs = 0; |
1955 | f6b868fc | blueswir1 | |
1956 | f6b868fc | blueswir1 | /* ESID = srnum */
|
1957 | f6b868fc | blueswir1 | rb |= ((uint32_t)srnum & 0xf) << 28; |
1958 | f6b868fc | blueswir1 | /* Set the valid bit */
|
1959 | f6b868fc | blueswir1 | rb |= 1 << 27; |
1960 | f6b868fc | blueswir1 | /* Index = ESID */
|
1961 | f6b868fc | blueswir1 | rb |= (uint32_t)srnum; |
1962 | f6b868fc | blueswir1 | |
1963 | f6b868fc | blueswir1 | /* VSID = VSID */
|
1964 | f6b868fc | blueswir1 | rs |= (value & 0xfffffff) << 12; |
1965 | f6b868fc | blueswir1 | /* flags = flags */
|
1966 | f6b868fc | blueswir1 | rs |= ((value >> 27) & 0xf) << 9; |
1967 | f6b868fc | blueswir1 | |
1968 | f6b868fc | blueswir1 | ppc_store_slb(env, rb, rs); |
1969 | f6b868fc | blueswir1 | } else
|
1970 | f6b868fc | blueswir1 | #endif
|
1971 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
1972 | 3fc6c082 | bellard | env->sr[srnum] = value; |
1973 | bf1752ef | aurel32 | /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
|
1974 | bf1752ef | aurel32 | flusing the whole TLB. */
|
1975 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
1976 | 3fc6c082 | bellard | { |
1977 | 3fc6c082 | bellard | target_ulong page, end; |
1978 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
1979 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
1980 | 3fc6c082 | bellard | end = page + (16 << 20); |
1981 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
1982 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1983 | 3fc6c082 | bellard | } |
1984 | 3fc6c082 | bellard | #else
|
1985 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1986 | 3fc6c082 | bellard | #endif
|
1987 | 3fc6c082 | bellard | } |
1988 | 3fc6c082 | bellard | } |
1989 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
1990 | 3fc6c082 | bellard | |
1991 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
1992 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
1993 | 3fc6c082 | bellard | { |
1994 | a4f30719 | j_mayer | hreg_store_msr(env, value, 0);
|
1995 | 3fc6c082 | bellard | } |
1996 | 3fc6c082 | bellard | |
1997 | 3fc6c082 | bellard | /*****************************************************************************/
|
1998 | 3fc6c082 | bellard | /* Exception processing */
|
1999 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
2000 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
2001 | 79aceca5 | bellard | { |
2002 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2003 | e1833e1f | j_mayer | env->error_code = 0;
|
2004 | 18fba28c | bellard | } |
2005 | 47103572 | j_mayer | |
2006 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
2007 | 47103572 | j_mayer | { |
2008 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2009 | e1833e1f | j_mayer | env->error_code = 0;
|
2010 | 47103572 | j_mayer | } |
2011 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
2012 | 636aa200 | Blue Swirl | static inline void dump_syscall(CPUState *env) |
2013 | d094807b | bellard | { |
2014 | b11ebf64 | Blue Swirl | qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 |
2015 | b11ebf64 | Blue Swirl | " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 |
2016 | b11ebf64 | Blue Swirl | " nip=" TARGET_FMT_lx "\n", |
2017 | 90e189ec | Blue Swirl | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), |
2018 | 90e189ec | Blue Swirl | ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), |
2019 | 90e189ec | Blue Swirl | ppc_dump_gpr(env, 6), env->nip);
|
2020 | d094807b | bellard | } |
2021 | d094807b | bellard | |
2022 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2023 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2024 | e1833e1f | j_mayer | */
|
2025 | 636aa200 | Blue Swirl | static inline void powerpc_excp(CPUState *env, int excp_model, int excp) |
2026 | 18fba28c | bellard | { |
2027 | 0411a972 | j_mayer | target_ulong msr, new_msr, vector; |
2028 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2029 | a4f30719 | j_mayer | int lpes0, lpes1, lev;
|
2030 | 79aceca5 | bellard | |
2031 | b172c56a | j_mayer | if (0) { |
2032 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2033 | b172c56a | j_mayer | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
2034 | b172c56a | j_mayer | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
2035 | b172c56a | j_mayer | } else {
|
2036 | b172c56a | j_mayer | /* Those values ensure we won't enter the hypervisor mode */
|
2037 | b172c56a | j_mayer | lpes0 = 0;
|
2038 | b172c56a | j_mayer | lpes1 = 1;
|
2039 | b172c56a | j_mayer | } |
2040 | b172c56a | j_mayer | |
2041 | 90e189ec | Blue Swirl | qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
|
2042 | 90e189ec | Blue Swirl | " => %08x (%02x)\n", env->nip, excp, env->error_code);
|
2043 | 41557447 | Alexander Graf | |
2044 | 41557447 | Alexander Graf | /* new srr1 value excluding must-be-zero bits */
|
2045 | 41557447 | Alexander Graf | msr = env->msr & ~0x783f0000ULL;
|
2046 | 41557447 | Alexander Graf | |
2047 | 41557447 | Alexander Graf | /* new interrupt handler msr */
|
2048 | 41557447 | Alexander Graf | new_msr = env->msr & ((target_ulong)1 << MSR_ME);
|
2049 | 41557447 | Alexander Graf | |
2050 | 41557447 | Alexander Graf | /* target registers */
|
2051 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2052 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2053 | e1833e1f | j_mayer | asrr0 = -1;
|
2054 | e1833e1f | j_mayer | asrr1 = -1;
|
2055 | 41557447 | Alexander Graf | |
2056 | 9a64fbe4 | bellard | switch (excp) {
|
2057 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2058 | e1833e1f | j_mayer | /* Should never happen */
|
2059 | e1833e1f | j_mayer | return;
|
2060 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2061 | e1833e1f | j_mayer | switch (excp_model) {
|
2062 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2063 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2064 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2065 | c62db105 | j_mayer | break;
|
2066 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2067 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2068 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2069 | c62db105 | j_mayer | break;
|
2070 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2071 | c62db105 | j_mayer | break;
|
2072 | e1833e1f | j_mayer | default:
|
2073 | e1833e1f | j_mayer | goto excp_invalid;
|
2074 | 2be0071f | bellard | } |
2075 | 9a64fbe4 | bellard | goto store_next;
|
2076 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2077 | e1833e1f | j_mayer | if (msr_me == 0) { |
2078 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2079 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2080 | e63ecc6f | j_mayer | */
|
2081 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2082 | 93fcfe39 | aliguori | qemu_log("Machine check while not allowed. "
|
2083 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2084 | e63ecc6f | j_mayer | } else {
|
2085 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2086 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2087 | e63ecc6f | j_mayer | } |
2088 | e63ecc6f | j_mayer | env->halted = 1;
|
2089 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2090 | e1833e1f | j_mayer | } |
2091 | b172c56a | j_mayer | if (0) { |
2092 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2093 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2094 | b172c56a | j_mayer | } |
2095 | 41557447 | Alexander Graf | |
2096 | 41557447 | Alexander Graf | /* machine check exceptions don't have ME set */
|
2097 | 41557447 | Alexander Graf | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2098 | 41557447 | Alexander Graf | |
2099 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2100 | e1833e1f | j_mayer | switch (excp_model) {
|
2101 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2102 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2103 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2104 | c62db105 | j_mayer | break;
|
2105 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2106 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2107 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2108 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2109 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2110 | c62db105 | j_mayer | break;
|
2111 | c62db105 | j_mayer | default:
|
2112 | c62db105 | j_mayer | break;
|
2113 | 2be0071f | bellard | } |
2114 | e1833e1f | j_mayer | goto store_next;
|
2115 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2116 | 90e189ec | Blue Swirl | LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx |
2117 | 90e189ec | Blue Swirl | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
2118 | e1833e1f | j_mayer | if (lpes1 == 0) |
2119 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2120 | a541f297 | bellard | goto store_next;
|
2121 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2122 | 90e189ec | Blue Swirl | LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx |
2123 | 90e189ec | Blue Swirl | "\n", msr, env->nip);
|
2124 | e1833e1f | j_mayer | if (lpes1 == 0) |
2125 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2126 | e1833e1f | j_mayer | msr |= env->error_code; |
2127 | 9a64fbe4 | bellard | goto store_next;
|
2128 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2129 | e1833e1f | j_mayer | if (lpes0 == 1) |
2130 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2131 | 9a64fbe4 | bellard | goto store_next;
|
2132 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2133 | e1833e1f | j_mayer | if (lpes1 == 0) |
2134 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2135 | e1833e1f | j_mayer | /* XXX: this is false */
|
2136 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2137 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2138 | 9a64fbe4 | bellard | goto store_current;
|
2139 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2140 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2141 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2142 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2143 | d12d51d5 | aliguori | LOG_EXCP("Ignore floating point exception\n");
|
2144 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2145 | 7c58044c | j_mayer | env->error_code = 0;
|
2146 | 9a64fbe4 | bellard | return;
|
2147 | 76a66253 | j_mayer | } |
2148 | e1833e1f | j_mayer | if (lpes1 == 0) |
2149 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2150 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2151 | 5b52b991 | j_mayer | if (msr_fe0 == msr_fe1)
|
2152 | 5b52b991 | j_mayer | goto store_next;
|
2153 | 5b52b991 | j_mayer | msr |= 0x00010000;
|
2154 | 76a66253 | j_mayer | break;
|
2155 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2156 | 90e189ec | Blue Swirl | LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); |
2157 | e1833e1f | j_mayer | if (lpes1 == 0) |
2158 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2159 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2160 | 76a66253 | j_mayer | break;
|
2161 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2162 | e1833e1f | j_mayer | if (lpes1 == 0) |
2163 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2164 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2165 | 76a66253 | j_mayer | break;
|
2166 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2167 | e1833e1f | j_mayer | if (lpes1 == 0) |
2168 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2169 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2170 | 9a64fbe4 | bellard | break;
|
2171 | 9a64fbe4 | bellard | default:
|
2172 | 9a64fbe4 | bellard | /* Should never occur */
|
2173 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2174 | e1833e1f | j_mayer | env->error_code); |
2175 | 76a66253 | j_mayer | break;
|
2176 | 76a66253 | j_mayer | } |
2177 | 5b52b991 | j_mayer | goto store_current;
|
2178 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2179 | e1833e1f | j_mayer | if (lpes1 == 0) |
2180 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2181 | e1833e1f | j_mayer | goto store_current;
|
2182 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2183 | 93fcfe39 | aliguori | dump_syscall(env); |
2184 | f9fdea6b | j_mayer | lev = env->error_code; |
2185 | d569956e | David Gibson | if ((lev == 1) && cpu_ppc_hypercall) { |
2186 | d569956e | David Gibson | cpu_ppc_hypercall(env); |
2187 | d569956e | David Gibson | return;
|
2188 | d569956e | David Gibson | } |
2189 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2190 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2191 | e1833e1f | j_mayer | goto store_next;
|
2192 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2193 | e1833e1f | j_mayer | goto store_current;
|
2194 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2195 | e1833e1f | j_mayer | if (lpes1 == 0) |
2196 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2197 | e1833e1f | j_mayer | goto store_next;
|
2198 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2199 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2200 | d12d51d5 | aliguori | LOG_EXCP("FIT exception\n");
|
2201 | 9a64fbe4 | bellard | goto store_next;
|
2202 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2203 | d12d51d5 | aliguori | LOG_EXCP("WDT exception\n");
|
2204 | e1833e1f | j_mayer | switch (excp_model) {
|
2205 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2206 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2207 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2208 | e1833e1f | j_mayer | break;
|
2209 | e1833e1f | j_mayer | default:
|
2210 | e1833e1f | j_mayer | break;
|
2211 | e1833e1f | j_mayer | } |
2212 | 2be0071f | bellard | goto store_next;
|
2213 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2214 | e1833e1f | j_mayer | goto store_next;
|
2215 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2216 | e1833e1f | j_mayer | goto store_next;
|
2217 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2218 | e1833e1f | j_mayer | switch (excp_model) {
|
2219 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2220 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2221 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2222 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2223 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2224 | e1833e1f | j_mayer | break;
|
2225 | e1833e1f | j_mayer | default:
|
2226 | e1833e1f | j_mayer | break;
|
2227 | e1833e1f | j_mayer | } |
2228 | 2be0071f | bellard | /* XXX: TODO */
|
2229 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2230 | 2be0071f | bellard | goto store_next;
|
2231 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2232 | e1833e1f | j_mayer | goto store_current;
|
2233 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2234 | 2be0071f | bellard | /* XXX: TODO */
|
2235 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2236 | 2be0071f | bellard | "is not implemented yet !\n");
|
2237 | 2be0071f | bellard | goto store_next;
|
2238 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2239 | 2be0071f | bellard | /* XXX: TODO */
|
2240 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2241 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2242 | 9a64fbe4 | bellard | goto store_next;
|
2243 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2244 | 2be0071f | bellard | /* XXX: TODO */
|
2245 | 2be0071f | bellard | cpu_abort(env, |
2246 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2247 | 9a64fbe4 | bellard | goto store_next;
|
2248 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2249 | 76a66253 | j_mayer | /* XXX: TODO */
|
2250 | e1833e1f | j_mayer | cpu_abort(env, |
2251 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2252 | 2be0071f | bellard | goto store_next;
|
2253 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2254 | e1833e1f | j_mayer | switch (excp_model) {
|
2255 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2256 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2257 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2258 | a750fc0b | j_mayer | break;
|
2259 | 2be0071f | bellard | default:
|
2260 | 2be0071f | bellard | break;
|
2261 | 2be0071f | bellard | } |
2262 | e1833e1f | j_mayer | /* XXX: TODO */
|
2263 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2264 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2265 | e1833e1f | j_mayer | goto store_next;
|
2266 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2267 | 41557447 | Alexander Graf | if (msr_pow) {
|
2268 | 41557447 | Alexander Graf | /* indicate that we resumed from power save mode */
|
2269 | 41557447 | Alexander Graf | msr |= 0x10000;
|
2270 | 41557447 | Alexander Graf | } else {
|
2271 | 41557447 | Alexander Graf | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2272 | 41557447 | Alexander Graf | } |
2273 | 41557447 | Alexander Graf | |
2274 | a4f30719 | j_mayer | if (0) { |
2275 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2276 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2277 | a4f30719 | j_mayer | } |
2278 | e1833e1f | j_mayer | goto store_next;
|
2279 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2280 | e1833e1f | j_mayer | if (lpes1 == 0) |
2281 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2282 | e1833e1f | j_mayer | goto store_next;
|
2283 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2284 | e1833e1f | j_mayer | if (lpes1 == 0) |
2285 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2286 | e1833e1f | j_mayer | goto store_next;
|
2287 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2288 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2289 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2290 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2291 | 41557447 | Alexander Graf | new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
2292 | b172c56a | j_mayer | goto store_next;
|
2293 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2294 | e1833e1f | j_mayer | if (lpes1 == 0) |
2295 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2296 | e1833e1f | j_mayer | goto store_next;
|
2297 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2298 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2299 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2300 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2301 | 41557447 | Alexander Graf | new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
2302 | e1833e1f | j_mayer | goto store_next;
|
2303 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2304 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2305 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2306 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2307 | 41557447 | Alexander Graf | new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
2308 | e1833e1f | j_mayer | goto store_next;
|
2309 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2310 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2311 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2312 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2313 | 41557447 | Alexander Graf | new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
2314 | e1833e1f | j_mayer | goto store_next;
|
2315 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2316 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2317 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2318 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2319 | 41557447 | Alexander Graf | new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
2320 | e1833e1f | j_mayer | goto store_next;
|
2321 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2322 | e1833e1f | j_mayer | if (lpes1 == 0) |
2323 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2324 | e1833e1f | j_mayer | goto store_current;
|
2325 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2326 | d12d51d5 | aliguori | LOG_EXCP("PIT exception\n");
|
2327 | e1833e1f | j_mayer | goto store_next;
|
2328 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2329 | e1833e1f | j_mayer | /* XXX: TODO */
|
2330 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2331 | e1833e1f | j_mayer | goto store_next;
|
2332 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2333 | e1833e1f | j_mayer | /* XXX: TODO */
|
2334 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2335 | e1833e1f | j_mayer | goto store_next;
|
2336 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2337 | e1833e1f | j_mayer | /* XXX: TODO */
|
2338 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2339 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2340 | e1833e1f | j_mayer | goto store_next;
|
2341 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2342 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2343 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2344 | e1833e1f | j_mayer | switch (excp_model) {
|
2345 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2346 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2347 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2348 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2349 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2350 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2351 | 76a66253 | j_mayer | goto tlb_miss;
|
2352 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2353 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2354 | 2be0071f | bellard | default:
|
2355 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2356 | 2be0071f | bellard | break;
|
2357 | 2be0071f | bellard | } |
2358 | e1833e1f | j_mayer | break;
|
2359 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2360 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2361 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2362 | e1833e1f | j_mayer | switch (excp_model) {
|
2363 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2364 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2365 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2366 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2367 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2368 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2369 | 76a66253 | j_mayer | goto tlb_miss;
|
2370 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2371 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2372 | 2be0071f | bellard | default:
|
2373 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2374 | 2be0071f | bellard | break;
|
2375 | 2be0071f | bellard | } |
2376 | e1833e1f | j_mayer | break;
|
2377 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2378 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2379 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2380 | e1833e1f | j_mayer | switch (excp_model) {
|
2381 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2382 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2383 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2384 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2385 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2386 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2387 | 0411a972 | j_mayer | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2388 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_TGPR;
|
2389 | 0411a972 | j_mayer | hreg_swap_gpr_tgpr(env); |
2390 | 0411a972 | j_mayer | } |
2391 | e1833e1f | j_mayer | goto tlb_miss;
|
2392 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2393 | e1833e1f | j_mayer | tlb_miss:
|
2394 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2395 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2396 | 0bf9e31a | Blue Swirl | const char *es; |
2397 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2398 | 76a66253 | j_mayer | int en;
|
2399 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2400 | 76a66253 | j_mayer | es = "I";
|
2401 | 76a66253 | j_mayer | en = 'I';
|
2402 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2403 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2404 | 76a66253 | j_mayer | } else {
|
2405 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2406 | 76a66253 | j_mayer | es = "DL";
|
2407 | 76a66253 | j_mayer | else
|
2408 | 76a66253 | j_mayer | es = "DS";
|
2409 | 76a66253 | j_mayer | en = 'D';
|
2410 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2411 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2412 | 76a66253 | j_mayer | } |
2413 | 90e189ec | Blue Swirl | qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
2414 | 90e189ec | Blue Swirl | TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " |
2415 | 90e189ec | Blue Swirl | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
2416 | 90e189ec | Blue Swirl | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2417 | 90e189ec | Blue Swirl | env->error_code); |
2418 | 2be0071f | bellard | } |
2419 | 9a64fbe4 | bellard | #endif
|
2420 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2421 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2422 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2423 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2424 | c62db105 | j_mayer | break;
|
2425 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2426 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2427 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2428 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
2429 | 0bf9e31a | Blue Swirl | const char *es; |
2430 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2431 | 7dbe11ac | j_mayer | int en;
|
2432 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2433 | 7dbe11ac | j_mayer | es = "I";
|
2434 | 7dbe11ac | j_mayer | en = 'I';
|
2435 | 0411a972 | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2436 | 0411a972 | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2437 | 7dbe11ac | j_mayer | } else {
|
2438 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2439 | 7dbe11ac | j_mayer | es = "DL";
|
2440 | 7dbe11ac | j_mayer | else
|
2441 | 7dbe11ac | j_mayer | es = "DS";
|
2442 | 7dbe11ac | j_mayer | en = 'D';
|
2443 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2444 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2445 | 7dbe11ac | j_mayer | } |
2446 | 90e189ec | Blue Swirl | qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
2447 | 90e189ec | Blue Swirl | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
2448 | 90e189ec | Blue Swirl | env->error_code); |
2449 | 7dbe11ac | j_mayer | } |
2450 | 7dbe11ac | j_mayer | #endif
|
2451 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2452 | 7dbe11ac | j_mayer | break;
|
2453 | 2be0071f | bellard | default:
|
2454 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2455 | 2be0071f | bellard | break;
|
2456 | 2be0071f | bellard | } |
2457 | e1833e1f | j_mayer | goto store_next;
|
2458 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2459 | e1833e1f | j_mayer | /* XXX: TODO */
|
2460 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2461 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2462 | e1833e1f | j_mayer | goto store_next;
|
2463 | b4095fed | j_mayer | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2464 | b4095fed | j_mayer | /* XXX: TODO */
|
2465 | b4095fed | j_mayer | cpu_abort(env, "DABR exception is not implemented yet !\n");
|
2466 | b4095fed | j_mayer | goto store_next;
|
2467 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2468 | e1833e1f | j_mayer | /* XXX: TODO */
|
2469 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2470 | e1833e1f | j_mayer | goto store_next;
|
2471 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2472 | e1833e1f | j_mayer | /* XXX: TODO */
|
2473 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2474 | e1833e1f | j_mayer | goto store_next;
|
2475 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2476 | e1833e1f | j_mayer | /* XXX: TODO */
|
2477 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2478 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2479 | e1833e1f | j_mayer | goto store_next;
|
2480 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2481 | e1833e1f | j_mayer | if (lpes1 == 0) |
2482 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2483 | e1833e1f | j_mayer | /* XXX: TODO */
|
2484 | e1833e1f | j_mayer | cpu_abort(env, |
2485 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2486 | e1833e1f | j_mayer | goto store_next;
|
2487 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2488 | e1833e1f | j_mayer | /* XXX: TODO */
|
2489 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2490 | e1833e1f | j_mayer | goto store_next;
|
2491 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2492 | e1833e1f | j_mayer | /* XXX: TODO */
|
2493 | e1833e1f | j_mayer | cpu_abort(env, |
2494 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2495 | e1833e1f | j_mayer | goto store_next;
|
2496 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2497 | e1833e1f | j_mayer | /* XXX: TODO */
|
2498 | e1833e1f | j_mayer | cpu_abort(env, |
2499 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2500 | e1833e1f | j_mayer | goto store_next;
|
2501 | b4095fed | j_mayer | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2502 | b4095fed | j_mayer | /* XXX: TODO */
|
2503 | b4095fed | j_mayer | cpu_abort(env, "Maskable external exception "
|
2504 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2505 | b4095fed | j_mayer | goto store_next;
|
2506 | b4095fed | j_mayer | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
2507 | b4095fed | j_mayer | /* XXX: TODO */
|
2508 | b4095fed | j_mayer | cpu_abort(env, "Non maskable external exception "
|
2509 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2510 | b4095fed | j_mayer | goto store_next;
|
2511 | 2be0071f | bellard | default:
|
2512 | e1833e1f | j_mayer | excp_invalid:
|
2513 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2514 | e1833e1f | j_mayer | break;
|
2515 | 9a64fbe4 | bellard | store_current:
|
2516 | 2be0071f | bellard | /* save current instruction location */
|
2517 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2518 | 9a64fbe4 | bellard | break;
|
2519 | 9a64fbe4 | bellard | store_next:
|
2520 | 2be0071f | bellard | /* save next instruction location */
|
2521 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2522 | 9a64fbe4 | bellard | break;
|
2523 | 9a64fbe4 | bellard | } |
2524 | e1833e1f | j_mayer | /* Save MSR */
|
2525 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2526 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2527 | e1833e1f | j_mayer | if (asrr0 != -1) |
2528 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2529 | e1833e1f | j_mayer | if (asrr1 != -1) |
2530 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2531 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2532 | 0411a972 | j_mayer | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2533 | 2be0071f | bellard | tlb_flush(env, 1);
|
2534 | 41557447 | Alexander Graf | |
2535 | 41557447 | Alexander Graf | if (msr_ile) {
|
2536 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_LE;
|
2537 | 41557447 | Alexander Graf | } |
2538 | 41557447 | Alexander Graf | |
2539 | e1833e1f | j_mayer | /* Jump to handler */
|
2540 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2541 | 6f2d8978 | j_mayer | if (vector == (target_ulong)-1ULL) { |
2542 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2543 | e1833e1f | j_mayer | excp); |
2544 | e1833e1f | j_mayer | } |
2545 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2546 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2547 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2548 | 0411a972 | j_mayer | if (!msr_icm) {
|
2549 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2550 | 0411a972 | j_mayer | } else {
|
2551 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_CM;
|
2552 | 0411a972 | j_mayer | } |
2553 | c62db105 | j_mayer | } else {
|
2554 | 6ce0ca12 | blueswir1 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
|
2555 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2556 | 0411a972 | j_mayer | } else {
|
2557 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_SF;
|
2558 | 0411a972 | j_mayer | } |
2559 | c62db105 | j_mayer | } |
2560 | e1833e1f | j_mayer | #endif
|
2561 | 0411a972 | j_mayer | /* XXX: we don't use hreg_store_msr here as already have treated
|
2562 | 0411a972 | j_mayer | * any special case that could occur. Just store MSR and update hflags
|
2563 | 0411a972 | j_mayer | */
|
2564 | a4f30719 | j_mayer | env->msr = new_msr & env->msr_mask; |
2565 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2566 | e1833e1f | j_mayer | env->nip = vector; |
2567 | e1833e1f | j_mayer | /* Reset exception state */
|
2568 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2569 | e1833e1f | j_mayer | env->error_code = 0;
|
2570 | a586e548 | Edgar E. Iglesias | |
2571 | a586e548 | Edgar E. Iglesias | if (env->mmu_model == POWERPC_MMU_BOOKE) {
|
2572 | a586e548 | Edgar E. Iglesias | /* XXX: The BookE changes address space when switching modes,
|
2573 | a586e548 | Edgar E. Iglesias | we should probably implement that as different MMU indexes,
|
2574 | a586e548 | Edgar E. Iglesias | but for the moment we do it the slow way and flush all. */
|
2575 | a586e548 | Edgar E. Iglesias | tlb_flush(env, 1);
|
2576 | a586e548 | Edgar E. Iglesias | } |
2577 | fb0eaffc | bellard | } |
2578 | 47103572 | j_mayer | |
2579 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2580 | 47103572 | j_mayer | { |
2581 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2582 | e1833e1f | j_mayer | } |
2583 | 47103572 | j_mayer | |
2584 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2585 | e1833e1f | j_mayer | { |
2586 | f9fdea6b | j_mayer | int hdice;
|
2587 | f9fdea6b | j_mayer | |
2588 | 0411a972 | j_mayer | #if 0
|
2589 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2590 | a496775f | j_mayer | __func__, env, env->pending_interrupts,
|
2591 | 0411a972 | j_mayer | env->interrupt_request, (int)msr_me, (int)msr_ee);
|
2592 | 47103572 | j_mayer | #endif
|
2593 | e1833e1f | j_mayer | /* External reset */
|
2594 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2595 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2596 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2597 | e1833e1f | j_mayer | return;
|
2598 | e1833e1f | j_mayer | } |
2599 | e1833e1f | j_mayer | /* Machine check exception */
|
2600 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2601 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2602 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2603 | e1833e1f | j_mayer | return;
|
2604 | 47103572 | j_mayer | } |
2605 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2606 | e1833e1f | j_mayer | /* External debug exception */
|
2607 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2608 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2609 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2610 | e1833e1f | j_mayer | return;
|
2611 | e1833e1f | j_mayer | }
|
2612 | e1833e1f | j_mayer | #endif
|
2613 | b172c56a | j_mayer | if (0) { |
2614 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2615 | b172c56a | j_mayer | hdice = env->spr[SPR_LPCR] & 1;
|
2616 | b172c56a | j_mayer | } else {
|
2617 | b172c56a | j_mayer | hdice = 0;
|
2618 | b172c56a | j_mayer | } |
2619 | f9fdea6b | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
2620 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2621 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2622 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2623 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2624 | e1833e1f | j_mayer | return;
|
2625 | e1833e1f | j_mayer | } |
2626 | e1833e1f | j_mayer | } |
2627 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2628 | e1833e1f | j_mayer | /* External critical interrupt */
|
2629 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2630 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2631 | e1833e1f | j_mayer | * critical interrupt status
|
2632 | e1833e1f | j_mayer | */
|
2633 | e1833e1f | j_mayer | #if 0
|
2634 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2635 | 47103572 | j_mayer | #endif
|
2636 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2637 | e1833e1f | j_mayer | return;
|
2638 | e1833e1f | j_mayer | } |
2639 | e1833e1f | j_mayer | } |
2640 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2641 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2642 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2643 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2644 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2645 | e1833e1f | j_mayer | return;
|
2646 | e1833e1f | j_mayer | } |
2647 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2648 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2649 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2650 | e1833e1f | j_mayer | return;
|
2651 | e1833e1f | j_mayer | } |
2652 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2653 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2654 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2655 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2656 | e1833e1f | j_mayer | return;
|
2657 | e1833e1f | j_mayer | } |
2658 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2659 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2660 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2661 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2662 | e1833e1f | j_mayer | return;
|
2663 | e1833e1f | j_mayer | } |
2664 | 47103572 | j_mayer | /* Decrementer exception */
|
2665 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2666 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2667 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2668 | e1833e1f | j_mayer | return;
|
2669 | e1833e1f | j_mayer | } |
2670 | 47103572 | j_mayer | /* External interrupt */
|
2671 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2672 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2673 | e9df014c | j_mayer | * interrupt status
|
2674 | e9df014c | j_mayer | */
|
2675 | e9df014c | j_mayer | #if 0
|
2676 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2677 | e9df014c | j_mayer | #endif
|
2678 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2679 | e1833e1f | j_mayer | return;
|
2680 | e1833e1f | j_mayer | } |
2681 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2682 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2683 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2684 | e1833e1f | j_mayer | return;
|
2685 | 47103572 | j_mayer | } |
2686 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2687 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2688 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2689 | e1833e1f | j_mayer | return;
|
2690 | e1833e1f | j_mayer | } |
2691 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2692 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2693 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2694 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2695 | e1833e1f | j_mayer | return;
|
2696 | e1833e1f | j_mayer | } |
2697 | 47103572 | j_mayer | } |
2698 | 47103572 | j_mayer | } |
2699 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2700 | a496775f | j_mayer | |
2701 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2702 | 4a057712 | j_mayer | { |
2703 | 90e189ec | Blue Swirl | qemu_log("Return from exception at " TARGET_FMT_lx " with flags " |
2704 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", RA, msr);
|
2705 | a496775f | j_mayer | } |
2706 | a496775f | j_mayer | |
2707 | d84bda46 | Blue Swirl | void cpu_reset(CPUPPCState *env)
|
2708 | 0a032cbe | j_mayer | { |
2709 | 0411a972 | j_mayer | target_ulong msr; |
2710 | 0a032cbe | j_mayer | |
2711 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
2712 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
2713 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
|
2714 | eca1bdf4 | aliguori | } |
2715 | eca1bdf4 | aliguori | |
2716 | 0411a972 | j_mayer | msr = (target_ulong)0;
|
2717 | a4f30719 | j_mayer | if (0) { |
2718 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2719 | a4f30719 | j_mayer | msr |= (target_ulong)MSR_HVB; |
2720 | a4f30719 | j_mayer | } |
2721 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2722 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
2723 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_EP;
|
2724 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2725 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2726 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_SE;
|
2727 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_BE;
|
2728 | 0a032cbe | j_mayer | #endif
|
2729 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2730 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2731 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
2732 | 4c2ab988 | aurel32 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
2733 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_PR;
|
2734 | 0a032cbe | j_mayer | #else
|
2735 | fc1c67bc | Blue Swirl | env->excp_prefix = env->hreset_excp_prefix; |
2736 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2737 | b4095fed | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL)
|
2738 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2739 | 0a032cbe | j_mayer | #endif
|
2740 | 07c485ce | blueswir1 | env->msr = msr & env->msr_mask; |
2741 | 6ce0ca12 | blueswir1 | #if defined(TARGET_PPC64)
|
2742 | 6ce0ca12 | blueswir1 | if (env->mmu_model & POWERPC_MMU_64)
|
2743 | 6ce0ca12 | blueswir1 | env->msr |= (1ULL << MSR_SF);
|
2744 | 6ce0ca12 | blueswir1 | #endif
|
2745 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2746 | 18b21a2f | Nathan Froyd | env->reserve_addr = (target_ulong)-1ULL;
|
2747 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2748 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2749 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2750 | e1833e1f | j_mayer | env->error_code = 0;
|
2751 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2752 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2753 | 0a032cbe | j_mayer | } |
2754 | 0a032cbe | j_mayer | |
2755 | aaed909a | bellard | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
2756 | 0a032cbe | j_mayer | { |
2757 | 0a032cbe | j_mayer | CPUPPCState *env; |
2758 | c227f099 | Anthony Liguori | const ppc_def_t *def;
|
2759 | aaed909a | bellard | |
2760 | aaed909a | bellard | def = cpu_ppc_find_by_name(cpu_model); |
2761 | aaed909a | bellard | if (!def)
|
2762 | aaed909a | bellard | return NULL; |
2763 | 0a032cbe | j_mayer | |
2764 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2765 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2766 | 2e70f6ef | pbrook | ppc_translate_init(); |
2767 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
2768 | aaed909a | bellard | cpu_ppc_register_internal(env, def); |
2769 | d76d1650 | aurel32 | |
2770 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
2771 | d76d1650 | aurel32 | |
2772 | 0a032cbe | j_mayer | return env;
|
2773 | 0a032cbe | j_mayer | } |
2774 | 0a032cbe | j_mayer | |
2775 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2776 | 0a032cbe | j_mayer | { |
2777 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2778 | aaed909a | bellard | qemu_free(env); |
2779 | 0a032cbe | j_mayer | } |