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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation for qemu: main translation routines.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 79aceca5 | bellard | */
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19 | c6a1c22b | bellard | #include <stdarg.h> |
20 | c6a1c22b | bellard | #include <stdlib.h> |
21 | c6a1c22b | bellard | #include <stdio.h> |
22 | c6a1c22b | bellard | #include <string.h> |
23 | c6a1c22b | bellard | #include <inttypes.h> |
24 | c6a1c22b | bellard | |
25 | 79aceca5 | bellard | #include "cpu.h" |
26 | c6a1c22b | bellard | #include "exec-all.h" |
27 | 79aceca5 | bellard | #include "disas.h" |
28 | 57fec1fe | bellard | #include "tcg-op.h" |
29 | ca10f867 | aurel32 | #include "qemu-common.h" |
30 | 0cfe11ea | aurel32 | #include "host-utils.h" |
31 | 79aceca5 | bellard | |
32 | a7812ae4 | pbrook | #include "helper.h" |
33 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
34 | a7812ae4 | pbrook | #include "helper.h" |
35 | a7812ae4 | pbrook | |
36 | 8cbcb4fa | aurel32 | #define CPU_SINGLE_STEP 0x1 |
37 | 8cbcb4fa | aurel32 | #define CPU_BRANCH_STEP 0x2 |
38 | 8cbcb4fa | aurel32 | #define GDBSTUB_SINGLE_STEP 0x4 |
39 | 8cbcb4fa | aurel32 | |
40 | a750fc0b | j_mayer | /* Include definitions for instructions classes and implementations flags */
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41 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
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42 | 76a66253 | j_mayer | //#define DO_PPC_STATISTICS
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43 | 79aceca5 | bellard | |
44 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_DISAS
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45 | 93fcfe39 | aliguori | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
46 | d12d51d5 | aliguori | #else
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47 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
48 | d12d51d5 | aliguori | #endif
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49 | a750fc0b | j_mayer | /*****************************************************************************/
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50 | a750fc0b | j_mayer | /* Code translation helpers */
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51 | c53be334 | bellard | |
52 | f78fb44e | aurel32 | /* global register indexes */
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53 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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54 | 1d542695 | aurel32 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
55 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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56 | 1d542695 | aurel32 | + 10*4 + 22*5 /* SPE GPRh */ |
57 | f78fb44e | aurel32 | #endif
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58 | a5e26afa | aurel32 | + 10*4 + 22*5 /* FPR */ |
59 | 47e4661c | aurel32 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
60 | 47e4661c | aurel32 | + 8*5 /* CRF */]; |
61 | f78fb44e | aurel32 | static TCGv cpu_gpr[32]; |
62 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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63 | f78fb44e | aurel32 | static TCGv cpu_gprh[32]; |
64 | f78fb44e | aurel32 | #endif
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65 | a7812ae4 | pbrook | static TCGv_i64 cpu_fpr[32]; |
66 | a7812ae4 | pbrook | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
67 | a7812ae4 | pbrook | static TCGv_i32 cpu_crf[8]; |
68 | bd568f18 | aurel32 | static TCGv cpu_nip;
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69 | 6527f6ea | aurel32 | static TCGv cpu_msr;
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70 | cfdcd37a | aurel32 | static TCGv cpu_ctr;
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71 | cfdcd37a | aurel32 | static TCGv cpu_lr;
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72 | 3d7b417e | aurel32 | static TCGv cpu_xer;
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73 | cf360a32 | aurel32 | static TCGv cpu_reserve;
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74 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpscr;
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75 | a7859e89 | aurel32 | static TCGv_i32 cpu_access_type;
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76 | f78fb44e | aurel32 | |
77 | 2e70f6ef | pbrook | #include "gen-icount.h" |
78 | 2e70f6ef | pbrook | |
79 | 2e70f6ef | pbrook | void ppc_translate_init(void) |
80 | 2e70f6ef | pbrook | { |
81 | f78fb44e | aurel32 | int i;
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82 | f78fb44e | aurel32 | char* p;
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83 | 2dc766da | blueswir1 | size_t cpu_reg_names_size; |
84 | b2437bf2 | pbrook | static int done_init = 0; |
85 | f78fb44e | aurel32 | |
86 | 2e70f6ef | pbrook | if (done_init)
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87 | 2e70f6ef | pbrook | return;
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88 | f78fb44e | aurel32 | |
89 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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90 | a7812ae4 | pbrook | |
91 | f78fb44e | aurel32 | p = cpu_reg_names; |
92 | 2dc766da | blueswir1 | cpu_reg_names_size = sizeof(cpu_reg_names);
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93 | 47e4661c | aurel32 | |
94 | 47e4661c | aurel32 | for (i = 0; i < 8; i++) { |
95 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "crf%d", i);
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96 | a7812ae4 | pbrook | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
97 | a7812ae4 | pbrook | offsetof(CPUState, crf[i]), p); |
98 | 47e4661c | aurel32 | p += 5;
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99 | 2dc766da | blueswir1 | cpu_reg_names_size -= 5;
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100 | 47e4661c | aurel32 | } |
101 | 47e4661c | aurel32 | |
102 | f78fb44e | aurel32 | for (i = 0; i < 32; i++) { |
103 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%d", i);
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104 | a7812ae4 | pbrook | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
105 | f78fb44e | aurel32 | offsetof(CPUState, gpr[i]), p); |
106 | f78fb44e | aurel32 | p += (i < 10) ? 3 : 4; |
107 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
108 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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109 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%dH", i);
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110 | a7812ae4 | pbrook | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
111 | a7812ae4 | pbrook | offsetof(CPUState, gprh[i]), p); |
112 | f78fb44e | aurel32 | p += (i < 10) ? 4 : 5; |
113 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
114 | f78fb44e | aurel32 | #endif
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115 | 1d542695 | aurel32 | |
116 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "fp%d", i);
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117 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
118 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), p); |
119 | ec1ac72d | aurel32 | p += (i < 10) ? 4 : 5; |
120 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
121 | a5e26afa | aurel32 | |
122 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dH", i);
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123 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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124 | fe1e5c53 | aurel32 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
125 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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126 | fe1e5c53 | aurel32 | #else
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127 | a7812ae4 | pbrook | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
128 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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129 | fe1e5c53 | aurel32 | #endif
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130 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
131 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
132 | ec1ac72d | aurel32 | |
133 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dL", i);
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134 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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135 | fe1e5c53 | aurel32 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
136 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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137 | fe1e5c53 | aurel32 | #else
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138 | a7812ae4 | pbrook | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
139 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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140 | fe1e5c53 | aurel32 | #endif
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141 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
142 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
143 | f78fb44e | aurel32 | } |
144 | f10dc08e | aurel32 | |
145 | a7812ae4 | pbrook | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
146 | bd568f18 | aurel32 | offsetof(CPUState, nip), "nip");
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147 | bd568f18 | aurel32 | |
148 | 6527f6ea | aurel32 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
149 | 6527f6ea | aurel32 | offsetof(CPUState, msr), "msr");
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150 | 6527f6ea | aurel32 | |
151 | a7812ae4 | pbrook | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
152 | cfdcd37a | aurel32 | offsetof(CPUState, ctr), "ctr");
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153 | cfdcd37a | aurel32 | |
154 | a7812ae4 | pbrook | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
155 | cfdcd37a | aurel32 | offsetof(CPUState, lr), "lr");
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156 | cfdcd37a | aurel32 | |
157 | a7812ae4 | pbrook | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
158 | 3d7b417e | aurel32 | offsetof(CPUState, xer), "xer");
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159 | 3d7b417e | aurel32 | |
160 | cf360a32 | aurel32 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
161 | 18b21a2f | Nathan Froyd | offsetof(CPUState, reserve_addr), |
162 | 18b21a2f | Nathan Froyd | "reserve_addr");
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163 | cf360a32 | aurel32 | |
164 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
165 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "fpscr");
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166 | e1571908 | aurel32 | |
167 | a7859e89 | aurel32 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
168 | a7859e89 | aurel32 | offsetof(CPUState, access_type), "access_type");
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169 | a7859e89 | aurel32 | |
170 | f10dc08e | aurel32 | /* register helpers */
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171 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
172 | f10dc08e | aurel32 | #include "helper.h" |
173 | f10dc08e | aurel32 | |
174 | 2e70f6ef | pbrook | done_init = 1;
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175 | 2e70f6ef | pbrook | } |
176 | 2e70f6ef | pbrook | |
177 | 79aceca5 | bellard | /* internal defines */
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178 | 79aceca5 | bellard | typedef struct DisasContext { |
179 | 79aceca5 | bellard | struct TranslationBlock *tb;
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180 | 0fa85d43 | bellard | target_ulong nip; |
181 | 79aceca5 | bellard | uint32_t opcode; |
182 | 9a64fbe4 | bellard | uint32_t exception; |
183 | 3cc62370 | bellard | /* Routine used to access memory */
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184 | 3cc62370 | bellard | int mem_idx;
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185 | 76db3ba4 | aurel32 | int access_type;
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186 | 3cc62370 | bellard | /* Translation flags */
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187 | 76db3ba4 | aurel32 | int le_mode;
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188 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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189 | d9bce9d9 | j_mayer | int sf_mode;
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190 | d9bce9d9 | j_mayer | #endif
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191 | 3cc62370 | bellard | int fpu_enabled;
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192 | a9d9eb8f | j_mayer | int altivec_enabled;
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193 | 0487d6a8 | j_mayer | int spe_enabled;
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194 | c227f099 | Anthony Liguori | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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195 | ea4e754f | bellard | int singlestep_enabled;
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196 | 79aceca5 | bellard | } DisasContext; |
197 | 79aceca5 | bellard | |
198 | c227f099 | Anthony Liguori | struct opc_handler_t {
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199 | 79aceca5 | bellard | /* invalid bits */
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200 | 79aceca5 | bellard | uint32_t inval; |
201 | 9a64fbe4 | bellard | /* instruction type */
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202 | 0487d6a8 | j_mayer | uint64_t type; |
203 | 79aceca5 | bellard | /* handler */
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204 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
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205 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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206 | b55266b5 | blueswir1 | const char *oname; |
207 | a750fc0b | j_mayer | #endif
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208 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS)
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209 | 76a66253 | j_mayer | uint64_t count; |
210 | 76a66253 | j_mayer | #endif
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211 | 3fc6c082 | bellard | }; |
212 | 79aceca5 | bellard | |
213 | 636aa200 | Blue Swirl | static inline void gen_reset_fpstatus(void) |
214 | 7c58044c | j_mayer | { |
215 | 7c58044c | j_mayer | #ifdef CONFIG_SOFTFLOAT
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216 | a44d2ce1 | aurel32 | gen_helper_reset_fpstatus(); |
217 | 7c58044c | j_mayer | #endif
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218 | 7c58044c | j_mayer | } |
219 | 7c58044c | j_mayer | |
220 | 636aa200 | Blue Swirl | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
221 | 7c58044c | j_mayer | { |
222 | 0f2f39c2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
223 | af12906f | aurel32 | |
224 | 7c58044c | j_mayer | if (set_fprf != 0) { |
225 | 7c58044c | j_mayer | /* This case might be optimized later */
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226 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 1);
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227 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
228 | a7812ae4 | pbrook | if (unlikely(set_rc)) {
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229 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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230 | a7812ae4 | pbrook | } |
231 | af12906f | aurel32 | gen_helper_float_check_status(); |
232 | 7c58044c | j_mayer | } else if (unlikely(set_rc)) { |
233 | 7c58044c | j_mayer | /* We always need to compute fpcc */
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234 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 0);
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235 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
236 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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237 | 7c58044c | j_mayer | } |
238 | af12906f | aurel32 | |
239 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
240 | 7c58044c | j_mayer | } |
241 | 7c58044c | j_mayer | |
242 | 636aa200 | Blue Swirl | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
243 | a7859e89 | aurel32 | { |
244 | 76db3ba4 | aurel32 | if (ctx->access_type != access_type) {
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245 | 76db3ba4 | aurel32 | tcg_gen_movi_i32(cpu_access_type, access_type); |
246 | 76db3ba4 | aurel32 | ctx->access_type = access_type; |
247 | 76db3ba4 | aurel32 | } |
248 | a7859e89 | aurel32 | } |
249 | a7859e89 | aurel32 | |
250 | 636aa200 | Blue Swirl | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
251 | d9bce9d9 | j_mayer | { |
252 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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253 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
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254 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, nip); |
255 | d9bce9d9 | j_mayer | else
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256 | d9bce9d9 | j_mayer | #endif
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257 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
258 | d9bce9d9 | j_mayer | } |
259 | d9bce9d9 | j_mayer | |
260 | 636aa200 | Blue Swirl | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
261 | e06fcd75 | aurel32 | { |
262 | e06fcd75 | aurel32 | TCGv_i32 t0, t1; |
263 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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264 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
265 | e06fcd75 | aurel32 | } |
266 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
267 | e06fcd75 | aurel32 | t1 = tcg_const_i32(error); |
268 | e06fcd75 | aurel32 | gen_helper_raise_exception_err(t0, t1); |
269 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
270 | e06fcd75 | aurel32 | tcg_temp_free_i32(t1); |
271 | e06fcd75 | aurel32 | ctx->exception = (excp); |
272 | e06fcd75 | aurel32 | } |
273 | e1833e1f | j_mayer | |
274 | 636aa200 | Blue Swirl | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
275 | e06fcd75 | aurel32 | { |
276 | e06fcd75 | aurel32 | TCGv_i32 t0; |
277 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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278 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
279 | e06fcd75 | aurel32 | } |
280 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
281 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
282 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
283 | e06fcd75 | aurel32 | ctx->exception = (excp); |
284 | e06fcd75 | aurel32 | } |
285 | e1833e1f | j_mayer | |
286 | 636aa200 | Blue Swirl | static inline void gen_debug_exception(DisasContext *ctx) |
287 | e06fcd75 | aurel32 | { |
288 | e06fcd75 | aurel32 | TCGv_i32 t0; |
289 | 5518f3a6 | blueswir1 | |
290 | 5518f3a6 | blueswir1 | if (ctx->exception != POWERPC_EXCP_BRANCH)
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291 | 5518f3a6 | blueswir1 | gen_update_nip(ctx, ctx->nip); |
292 | e06fcd75 | aurel32 | t0 = tcg_const_i32(EXCP_DEBUG); |
293 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
294 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
295 | e06fcd75 | aurel32 | } |
296 | 9a64fbe4 | bellard | |
297 | 636aa200 | Blue Swirl | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
298 | e06fcd75 | aurel32 | { |
299 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
300 | e06fcd75 | aurel32 | } |
301 | a9d9eb8f | j_mayer | |
302 | f24e5695 | bellard | /* Stop translation */
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303 | 636aa200 | Blue Swirl | static inline void gen_stop_exception(DisasContext *ctx) |
304 | 3fc6c082 | bellard | { |
305 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
306 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
307 | 3fc6c082 | bellard | } |
308 | 3fc6c082 | bellard | |
309 | f24e5695 | bellard | /* No need to update nip here, as execution flow will change */
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310 | 636aa200 | Blue Swirl | static inline void gen_sync_exception(DisasContext *ctx) |
311 | 2be0071f | bellard | { |
312 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_SYNC; |
313 | 2be0071f | bellard | } |
314 | 2be0071f | bellard | |
315 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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316 | 5c55ff99 | Blue Swirl | GEN_OPCODE(name, opc1, opc2, opc3, inval, type) |
317 | 79aceca5 | bellard | |
318 | c7697e1f | j_mayer | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
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319 | 5c55ff99 | Blue Swirl | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type) |
320 | c7697e1f | j_mayer | |
321 | c227f099 | Anthony Liguori | typedef struct opcode_t { |
322 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
323 | 1235fc06 | ths | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
324 | 18fba28c | bellard | unsigned char pad[5]; |
325 | 18fba28c | bellard | #else
|
326 | 18fba28c | bellard | unsigned char pad[1]; |
327 | 18fba28c | bellard | #endif
|
328 | c227f099 | Anthony Liguori | opc_handler_t handler; |
329 | b55266b5 | blueswir1 | const char *oname; |
330 | c227f099 | Anthony Liguori | } opcode_t; |
331 | 79aceca5 | bellard | |
332 | a750fc0b | j_mayer | /*****************************************************************************/
|
333 | 79aceca5 | bellard | /*** Instruction decoding ***/
|
334 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
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335 | 636aa200 | Blue Swirl | static inline uint32_t name(uint32_t opcode) \ |
336 | 79aceca5 | bellard | { \ |
337 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
338 | 79aceca5 | bellard | } |
339 | 79aceca5 | bellard | |
340 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
|
341 | 636aa200 | Blue Swirl | static inline int32_t name(uint32_t opcode) \ |
342 | 79aceca5 | bellard | { \ |
343 | 18fba28c | bellard | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
344 | 79aceca5 | bellard | } |
345 | 79aceca5 | bellard | |
346 | 79aceca5 | bellard | /* Opcode part 1 */
|
347 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
348 | 79aceca5 | bellard | /* Opcode part 2 */
|
349 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
350 | 79aceca5 | bellard | /* Opcode part 3 */
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351 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
352 | 79aceca5 | bellard | /* Update Cr0 flags */
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353 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
354 | 79aceca5 | bellard | /* Destination */
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355 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
356 | 79aceca5 | bellard | /* Source */
|
357 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
358 | 79aceca5 | bellard | /* First operand */
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359 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
360 | 79aceca5 | bellard | /* Second operand */
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361 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
362 | 79aceca5 | bellard | /* Third operand */
|
363 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
364 | 79aceca5 | bellard | /*** Get CRn ***/
|
365 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
366 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
367 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
368 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
369 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
370 | 79aceca5 | bellard | /* SPR / TBL */
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371 | 3fc6c082 | bellard | EXTRACT_HELPER(_SPR, 11, 10); |
372 | 636aa200 | Blue Swirl | static inline uint32_t SPR(uint32_t opcode) |
373 | 3fc6c082 | bellard | { |
374 | 3fc6c082 | bellard | uint32_t sprn = _SPR(opcode); |
375 | 3fc6c082 | bellard | |
376 | 3fc6c082 | bellard | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
377 | 3fc6c082 | bellard | } |
378 | 79aceca5 | bellard | /*** Get constants ***/
|
379 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
380 | 79aceca5 | bellard | /* 16 bits signed immediate value */
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381 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
382 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
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383 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
384 | 21d21583 | aurel32 | /* 5 bits signed immediate value */
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385 | 21d21583 | aurel32 | EXTRACT_HELPER(SIMM5, 16, 5); |
386 | 27a4edb3 | aurel32 | /* 5 bits signed immediate value */
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387 | 27a4edb3 | aurel32 | EXTRACT_HELPER(UIMM5, 16, 5); |
388 | 79aceca5 | bellard | /* Bit count */
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389 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
390 | 79aceca5 | bellard | /* Shift count */
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391 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
392 | cd633b10 | aurel32 | /* Vector shift count */
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393 | cd633b10 | aurel32 | EXTRACT_HELPER(VSH, 6, 4); |
394 | 79aceca5 | bellard | /* Mask start */
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395 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
396 | 79aceca5 | bellard | /* Mask end */
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397 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
398 | fb0eaffc | bellard | /* Trap operand */
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399 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
400 | 79aceca5 | bellard | |
401 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
402 | 79aceca5 | bellard | EXTRACT_HELPER(FM, 17, 8); |
403 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
404 | e4bb997e | aurel32 | EXTRACT_HELPER(FPIMM, 12, 4); |
405 | fb0eaffc | bellard | |
406 | 79aceca5 | bellard | /*** Jump target decoding ***/
|
407 | 79aceca5 | bellard | /* Displacement */
|
408 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
409 | 79aceca5 | bellard | /* Immediate address */
|
410 | 636aa200 | Blue Swirl | static inline target_ulong LI(uint32_t opcode) |
411 | 79aceca5 | bellard | { |
412 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
413 | 79aceca5 | bellard | } |
414 | 79aceca5 | bellard | |
415 | 636aa200 | Blue Swirl | static inline uint32_t BD(uint32_t opcode) |
416 | 79aceca5 | bellard | { |
417 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
418 | 79aceca5 | bellard | } |
419 | 79aceca5 | bellard | |
420 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
421 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
422 | 79aceca5 | bellard | /* Absolute/relative address */
|
423 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
424 | 79aceca5 | bellard | /* Link */
|
425 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
426 | 79aceca5 | bellard | |
427 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
|
428 | 636aa200 | Blue Swirl | static inline target_ulong MASK(uint32_t start, uint32_t end) |
429 | 79aceca5 | bellard | { |
430 | 76a66253 | j_mayer | target_ulong ret; |
431 | 79aceca5 | bellard | |
432 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
433 | 76a66253 | j_mayer | if (likely(start == 0)) { |
434 | 6f2d8978 | j_mayer | ret = UINT64_MAX << (63 - end);
|
435 | 76a66253 | j_mayer | } else if (likely(end == 63)) { |
436 | 6f2d8978 | j_mayer | ret = UINT64_MAX >> start; |
437 | 76a66253 | j_mayer | } |
438 | 76a66253 | j_mayer | #else
|
439 | 76a66253 | j_mayer | if (likely(start == 0)) { |
440 | 6f2d8978 | j_mayer | ret = UINT32_MAX << (31 - end);
|
441 | 76a66253 | j_mayer | } else if (likely(end == 31)) { |
442 | 6f2d8978 | j_mayer | ret = UINT32_MAX >> start; |
443 | 76a66253 | j_mayer | } |
444 | 76a66253 | j_mayer | #endif
|
445 | 76a66253 | j_mayer | else {
|
446 | 76a66253 | j_mayer | ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
447 | 76a66253 | j_mayer | (((target_ulong)(-1ULL) >> (end)) >> 1); |
448 | 76a66253 | j_mayer | if (unlikely(start > end))
|
449 | 76a66253 | j_mayer | return ~ret;
|
450 | 76a66253 | j_mayer | } |
451 | 79aceca5 | bellard | |
452 | 79aceca5 | bellard | return ret;
|
453 | 79aceca5 | bellard | } |
454 | 79aceca5 | bellard | |
455 | a750fc0b | j_mayer | /*****************************************************************************/
|
456 | a750fc0b | j_mayer | /* PowerPC instructions table */
|
457 | 933dc6eb | bellard | |
458 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
459 | 79aceca5 | bellard | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
460 | 5c55ff99 | Blue Swirl | { \ |
461 | 79aceca5 | bellard | .opc1 = op1, \ |
462 | 79aceca5 | bellard | .opc2 = op2, \ |
463 | 79aceca5 | bellard | .opc3 = op3, \ |
464 | 18fba28c | bellard | .pad = { 0, }, \
|
465 | 79aceca5 | bellard | .handler = { \ |
466 | 79aceca5 | bellard | .inval = invl, \ |
467 | 9a64fbe4 | bellard | .type = _typ, \ |
468 | 79aceca5 | bellard | .handler = &gen_##name, \ |
469 | 76a66253 | j_mayer | .oname = stringify(name), \ |
470 | 79aceca5 | bellard | }, \ |
471 | 3fc6c082 | bellard | .oname = stringify(name), \ |
472 | 79aceca5 | bellard | } |
473 | c7697e1f | j_mayer | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
474 | 5c55ff99 | Blue Swirl | { \ |
475 | c7697e1f | j_mayer | .opc1 = op1, \ |
476 | c7697e1f | j_mayer | .opc2 = op2, \ |
477 | c7697e1f | j_mayer | .opc3 = op3, \ |
478 | c7697e1f | j_mayer | .pad = { 0, }, \
|
479 | c7697e1f | j_mayer | .handler = { \ |
480 | c7697e1f | j_mayer | .inval = invl, \ |
481 | c7697e1f | j_mayer | .type = _typ, \ |
482 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
483 | c7697e1f | j_mayer | .oname = onam, \ |
484 | c7697e1f | j_mayer | }, \ |
485 | c7697e1f | j_mayer | .oname = onam, \ |
486 | c7697e1f | j_mayer | } |
487 | 76a66253 | j_mayer | #else
|
488 | 76a66253 | j_mayer | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
|
489 | 5c55ff99 | Blue Swirl | { \ |
490 | c7697e1f | j_mayer | .opc1 = op1, \ |
491 | c7697e1f | j_mayer | .opc2 = op2, \ |
492 | c7697e1f | j_mayer | .opc3 = op3, \ |
493 | c7697e1f | j_mayer | .pad = { 0, }, \
|
494 | c7697e1f | j_mayer | .handler = { \ |
495 | c7697e1f | j_mayer | .inval = invl, \ |
496 | c7697e1f | j_mayer | .type = _typ, \ |
497 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
498 | 5c55ff99 | Blue Swirl | }, \ |
499 | 5c55ff99 | Blue Swirl | .oname = stringify(name), \ |
500 | 5c55ff99 | Blue Swirl | } |
501 | 5c55ff99 | Blue Swirl | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
|
502 | 5c55ff99 | Blue Swirl | { \ |
503 | 5c55ff99 | Blue Swirl | .opc1 = op1, \ |
504 | 5c55ff99 | Blue Swirl | .opc2 = op2, \ |
505 | 5c55ff99 | Blue Swirl | .opc3 = op3, \ |
506 | 5c55ff99 | Blue Swirl | .pad = { 0, }, \
|
507 | 5c55ff99 | Blue Swirl | .handler = { \ |
508 | 5c55ff99 | Blue Swirl | .inval = invl, \ |
509 | 5c55ff99 | Blue Swirl | .type = _typ, \ |
510 | 5c55ff99 | Blue Swirl | .handler = &gen_##name, \ |
511 | 5c55ff99 | Blue Swirl | }, \ |
512 | 5c55ff99 | Blue Swirl | .oname = onam, \ |
513 | 5c55ff99 | Blue Swirl | } |
514 | 5c55ff99 | Blue Swirl | #endif
|
515 | 2e610050 | Blue Swirl | |
516 | 5c55ff99 | Blue Swirl | /* SPR load/store helpers */
|
517 | 636aa200 | Blue Swirl | static inline void gen_load_spr(TCGv t, int reg) |
518 | 5c55ff99 | Blue Swirl | { |
519 | 5c55ff99 | Blue Swirl | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
520 | 5c55ff99 | Blue Swirl | } |
521 | 2e610050 | Blue Swirl | |
522 | 636aa200 | Blue Swirl | static inline void gen_store_spr(int reg, TCGv t) |
523 | 5c55ff99 | Blue Swirl | { |
524 | 5c55ff99 | Blue Swirl | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
525 | 5c55ff99 | Blue Swirl | } |
526 | 2e610050 | Blue Swirl | |
527 | 54623277 | Blue Swirl | /* Invalid instruction */
|
528 | 99e300ef | Blue Swirl | static void gen_invalid(DisasContext *ctx) |
529 | 9a64fbe4 | bellard | { |
530 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
531 | 9a64fbe4 | bellard | } |
532 | 9a64fbe4 | bellard | |
533 | c227f099 | Anthony Liguori | static opc_handler_t invalid_handler = {
|
534 | 79aceca5 | bellard | .inval = 0xFFFFFFFF,
|
535 | 9a64fbe4 | bellard | .type = PPC_NONE, |
536 | 79aceca5 | bellard | .handler = gen_invalid, |
537 | 79aceca5 | bellard | }; |
538 | 79aceca5 | bellard | |
539 | e1571908 | aurel32 | /*** Integer comparison ***/
|
540 | e1571908 | aurel32 | |
541 | 636aa200 | Blue Swirl | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
542 | e1571908 | aurel32 | { |
543 | e1571908 | aurel32 | int l1, l2, l3;
|
544 | e1571908 | aurel32 | |
545 | 269f3e95 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
546 | 269f3e95 | aurel32 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); |
547 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
|
548 | e1571908 | aurel32 | |
549 | e1571908 | aurel32 | l1 = gen_new_label(); |
550 | e1571908 | aurel32 | l2 = gen_new_label(); |
551 | e1571908 | aurel32 | l3 = gen_new_label(); |
552 | e1571908 | aurel32 | if (s) {
|
553 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
554 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); |
555 | e1571908 | aurel32 | } else {
|
556 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
557 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); |
558 | e1571908 | aurel32 | } |
559 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
|
560 | e1571908 | aurel32 | tcg_gen_br(l3); |
561 | e1571908 | aurel32 | gen_set_label(l1); |
562 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
|
563 | e1571908 | aurel32 | tcg_gen_br(l3); |
564 | e1571908 | aurel32 | gen_set_label(l2); |
565 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
|
566 | e1571908 | aurel32 | gen_set_label(l3); |
567 | e1571908 | aurel32 | } |
568 | e1571908 | aurel32 | |
569 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
570 | e1571908 | aurel32 | { |
571 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
572 | ea363694 | aurel32 | gen_op_cmp(arg0, t0, s, crf); |
573 | ea363694 | aurel32 | tcg_temp_free(t0); |
574 | e1571908 | aurel32 | } |
575 | e1571908 | aurel32 | |
576 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
577 | 636aa200 | Blue Swirl | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
578 | e1571908 | aurel32 | { |
579 | ea363694 | aurel32 | TCGv t0, t1; |
580 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
581 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
582 | e1571908 | aurel32 | if (s) {
|
583 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t0, arg0); |
584 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t1, arg1); |
585 | e1571908 | aurel32 | } else {
|
586 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t0, arg0); |
587 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t1, arg1); |
588 | e1571908 | aurel32 | } |
589 | ea363694 | aurel32 | gen_op_cmp(t0, t1, s, crf); |
590 | ea363694 | aurel32 | tcg_temp_free(t1); |
591 | ea363694 | aurel32 | tcg_temp_free(t0); |
592 | e1571908 | aurel32 | } |
593 | e1571908 | aurel32 | |
594 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
595 | e1571908 | aurel32 | { |
596 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
597 | ea363694 | aurel32 | gen_op_cmp32(arg0, t0, s, crf); |
598 | ea363694 | aurel32 | tcg_temp_free(t0); |
599 | e1571908 | aurel32 | } |
600 | e1571908 | aurel32 | #endif
|
601 | e1571908 | aurel32 | |
602 | 636aa200 | Blue Swirl | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
603 | e1571908 | aurel32 | { |
604 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
605 | e1571908 | aurel32 | if (!(ctx->sf_mode))
|
606 | e1571908 | aurel32 | gen_op_cmpi32(reg, 0, 1, 0); |
607 | e1571908 | aurel32 | else
|
608 | e1571908 | aurel32 | #endif
|
609 | e1571908 | aurel32 | gen_op_cmpi(reg, 0, 1, 0); |
610 | e1571908 | aurel32 | } |
611 | e1571908 | aurel32 | |
612 | e1571908 | aurel32 | /* cmp */
|
613 | 99e300ef | Blue Swirl | static void gen_cmp(DisasContext *ctx) |
614 | e1571908 | aurel32 | { |
615 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
616 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
617 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
618 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
619 | e1571908 | aurel32 | else
|
620 | e1571908 | aurel32 | #endif
|
621 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
622 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
623 | e1571908 | aurel32 | } |
624 | e1571908 | aurel32 | |
625 | e1571908 | aurel32 | /* cmpi */
|
626 | 99e300ef | Blue Swirl | static void gen_cmpi(DisasContext *ctx) |
627 | e1571908 | aurel32 | { |
628 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
629 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
630 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
631 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
632 | e1571908 | aurel32 | else
|
633 | e1571908 | aurel32 | #endif
|
634 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
635 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
636 | e1571908 | aurel32 | } |
637 | e1571908 | aurel32 | |
638 | e1571908 | aurel32 | /* cmpl */
|
639 | 99e300ef | Blue Swirl | static void gen_cmpl(DisasContext *ctx) |
640 | e1571908 | aurel32 | { |
641 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
642 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
643 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
644 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
645 | e1571908 | aurel32 | else
|
646 | e1571908 | aurel32 | #endif
|
647 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
648 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
649 | e1571908 | aurel32 | } |
650 | e1571908 | aurel32 | |
651 | e1571908 | aurel32 | /* cmpli */
|
652 | 99e300ef | Blue Swirl | static void gen_cmpli(DisasContext *ctx) |
653 | e1571908 | aurel32 | { |
654 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
655 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
656 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
657 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
658 | e1571908 | aurel32 | else
|
659 | e1571908 | aurel32 | #endif
|
660 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
661 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
662 | e1571908 | aurel32 | } |
663 | e1571908 | aurel32 | |
664 | e1571908 | aurel32 | /* isel (PowerPC 2.03 specification) */
|
665 | 99e300ef | Blue Swirl | static void gen_isel(DisasContext *ctx) |
666 | e1571908 | aurel32 | { |
667 | e1571908 | aurel32 | int l1, l2;
|
668 | e1571908 | aurel32 | uint32_t bi = rC(ctx->opcode); |
669 | e1571908 | aurel32 | uint32_t mask; |
670 | a7812ae4 | pbrook | TCGv_i32 t0; |
671 | e1571908 | aurel32 | |
672 | e1571908 | aurel32 | l1 = gen_new_label(); |
673 | e1571908 | aurel32 | l2 = gen_new_label(); |
674 | e1571908 | aurel32 | |
675 | e1571908 | aurel32 | mask = 1 << (3 - (bi & 0x03)); |
676 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
677 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
|
678 | fea0c503 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
679 | e1571908 | aurel32 | if (rA(ctx->opcode) == 0) |
680 | e1571908 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
681 | e1571908 | aurel32 | else
|
682 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
683 | e1571908 | aurel32 | tcg_gen_br(l2); |
684 | e1571908 | aurel32 | gen_set_label(l1); |
685 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
686 | e1571908 | aurel32 | gen_set_label(l2); |
687 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
688 | e1571908 | aurel32 | } |
689 | e1571908 | aurel32 | |
690 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
691 | 79aceca5 | bellard | |
692 | 636aa200 | Blue Swirl | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
693 | 636aa200 | Blue Swirl | TCGv arg1, TCGv arg2, int sub)
|
694 | 74637406 | aurel32 | { |
695 | 74637406 | aurel32 | int l1;
|
696 | 74637406 | aurel32 | TCGv t0; |
697 | 79aceca5 | bellard | |
698 | 74637406 | aurel32 | l1 = gen_new_label(); |
699 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
700 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
701 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
702 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg0, arg1); |
703 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
704 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
705 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
706 | 74637406 | aurel32 | #endif
|
707 | 74637406 | aurel32 | if (sub)
|
708 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
709 | 74637406 | aurel32 | else
|
710 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
711 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg1, arg2); |
712 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
713 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
714 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
715 | 74637406 | aurel32 | #endif
|
716 | 74637406 | aurel32 | if (sub)
|
717 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
718 | 74637406 | aurel32 | else
|
719 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
720 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
721 | 74637406 | aurel32 | gen_set_label(l1); |
722 | 74637406 | aurel32 | tcg_temp_free(t0); |
723 | 79aceca5 | bellard | } |
724 | 79aceca5 | bellard | |
725 | 636aa200 | Blue Swirl | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
726 | 636aa200 | Blue Swirl | TCGv arg2, int sub)
|
727 | 74637406 | aurel32 | { |
728 | 74637406 | aurel32 | int l1 = gen_new_label();
|
729 | d9bce9d9 | j_mayer | |
730 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
731 | 74637406 | aurel32 | if (!(ctx->sf_mode)) {
|
732 | 74637406 | aurel32 | TCGv t0, t1; |
733 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
734 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
735 | d9bce9d9 | j_mayer | |
736 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
737 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t1, arg2); |
738 | 74637406 | aurel32 | if (sub) {
|
739 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); |
740 | bdc4e053 | aurel32 | } else {
|
741 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
742 | 74637406 | aurel32 | } |
743 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
744 | a9730017 | aurel32 | gen_set_label(l1); |
745 | a9730017 | aurel32 | tcg_temp_free(t0); |
746 | a9730017 | aurel32 | tcg_temp_free(t1); |
747 | 74637406 | aurel32 | } else
|
748 | 74637406 | aurel32 | #endif
|
749 | a9730017 | aurel32 | { |
750 | a9730017 | aurel32 | if (sub) {
|
751 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); |
752 | a9730017 | aurel32 | } else {
|
753 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); |
754 | a9730017 | aurel32 | } |
755 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
756 | a9730017 | aurel32 | gen_set_label(l1); |
757 | 74637406 | aurel32 | } |
758 | d9bce9d9 | j_mayer | } |
759 | d9bce9d9 | j_mayer | |
760 | 74637406 | aurel32 | /* Common add function */
|
761 | 636aa200 | Blue Swirl | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
762 | 636aa200 | Blue Swirl | TCGv arg2, int add_ca, int compute_ca, |
763 | 636aa200 | Blue Swirl | int compute_ov)
|
764 | 74637406 | aurel32 | { |
765 | 74637406 | aurel32 | TCGv t0, t1; |
766 | d9bce9d9 | j_mayer | |
767 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
768 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
769 | 74637406 | aurel32 | t0 = ret; |
770 | 74637406 | aurel32 | } else {
|
771 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
772 | 74637406 | aurel32 | } |
773 | 79aceca5 | bellard | |
774 | 74637406 | aurel32 | if (add_ca) {
|
775 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
776 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
777 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
778 | d2e9fd8f | malc | } else {
|
779 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
780 | 74637406 | aurel32 | } |
781 | 79aceca5 | bellard | |
782 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
783 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
784 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
785 | 74637406 | aurel32 | } else if (compute_ca) { |
786 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
787 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
788 | 74637406 | aurel32 | } else if (compute_ov) { |
789 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
790 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
791 | 74637406 | aurel32 | } |
792 | 79aceca5 | bellard | |
793 | 74637406 | aurel32 | tcg_gen_add_tl(t0, arg1, arg2); |
794 | 74637406 | aurel32 | |
795 | 74637406 | aurel32 | if (compute_ca) {
|
796 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
797 | 74637406 | aurel32 | } |
798 | 74637406 | aurel32 | if (add_ca) {
|
799 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
800 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
801 | 74637406 | aurel32 | tcg_temp_free(t1); |
802 | 74637406 | aurel32 | } |
803 | 74637406 | aurel32 | if (compute_ov) {
|
804 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
|
805 | 74637406 | aurel32 | } |
806 | 74637406 | aurel32 | |
807 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
808 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
809 | 74637406 | aurel32 | |
810 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
811 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
812 | 74637406 | aurel32 | tcg_temp_free(t0); |
813 | 74637406 | aurel32 | } |
814 | 39dd32ee | aurel32 | } |
815 | 74637406 | aurel32 | /* Add functions with two operands */
|
816 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
817 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
818 | 74637406 | aurel32 | { \ |
819 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
820 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
821 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
822 | 74637406 | aurel32 | } |
823 | 74637406 | aurel32 | /* Add functions with one operand and one immediate */
|
824 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
825 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
826 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
827 | 74637406 | aurel32 | { \ |
828 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
829 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
830 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
831 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
832 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
833 | 74637406 | aurel32 | } |
834 | 74637406 | aurel32 | |
835 | 74637406 | aurel32 | /* add add. addo addo. */
|
836 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
837 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
838 | 74637406 | aurel32 | /* addc addc. addco addco. */
|
839 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
840 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
841 | 74637406 | aurel32 | /* adde adde. addeo addeo. */
|
842 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
843 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
844 | 74637406 | aurel32 | /* addme addme. addmeo addmeo. */
|
845 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
846 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
847 | 74637406 | aurel32 | /* addze addze. addzeo addzeo.*/
|
848 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
849 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
850 | 74637406 | aurel32 | /* addi */
|
851 | 99e300ef | Blue Swirl | static void gen_addi(DisasContext *ctx) |
852 | d9bce9d9 | j_mayer | { |
853 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
854 | 74637406 | aurel32 | |
855 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
856 | 74637406 | aurel32 | /* li case */
|
857 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
858 | 74637406 | aurel32 | } else {
|
859 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); |
860 | 74637406 | aurel32 | } |
861 | d9bce9d9 | j_mayer | } |
862 | 74637406 | aurel32 | /* addic addic.*/
|
863 | 636aa200 | Blue Swirl | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
864 | 636aa200 | Blue Swirl | int compute_Rc0)
|
865 | d9bce9d9 | j_mayer | { |
866 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
867 | 74637406 | aurel32 | |
868 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
869 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
870 | 74637406 | aurel32 | |
871 | 74637406 | aurel32 | if (likely(simm != 0)) { |
872 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
873 | 74637406 | aurel32 | tcg_gen_addi_tl(t0, arg1, simm); |
874 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
875 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
876 | 74637406 | aurel32 | tcg_temp_free(t0); |
877 | 74637406 | aurel32 | } else {
|
878 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, arg1); |
879 | 74637406 | aurel32 | } |
880 | 74637406 | aurel32 | if (compute_Rc0) {
|
881 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
882 | 74637406 | aurel32 | } |
883 | d9bce9d9 | j_mayer | } |
884 | 99e300ef | Blue Swirl | |
885 | 99e300ef | Blue Swirl | static void gen_addic(DisasContext *ctx) |
886 | d9bce9d9 | j_mayer | { |
887 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
888 | d9bce9d9 | j_mayer | } |
889 | e8eaa2c0 | Blue Swirl | |
890 | e8eaa2c0 | Blue Swirl | static void gen_addic_(DisasContext *ctx) |
891 | d9bce9d9 | j_mayer | { |
892 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
893 | d9bce9d9 | j_mayer | } |
894 | 99e300ef | Blue Swirl | |
895 | 54623277 | Blue Swirl | /* addis */
|
896 | 99e300ef | Blue Swirl | static void gen_addis(DisasContext *ctx) |
897 | d9bce9d9 | j_mayer | { |
898 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
899 | 74637406 | aurel32 | |
900 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
901 | 74637406 | aurel32 | /* lis case */
|
902 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
|
903 | 74637406 | aurel32 | } else {
|
904 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
|
905 | 74637406 | aurel32 | } |
906 | d9bce9d9 | j_mayer | } |
907 | 74637406 | aurel32 | |
908 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
909 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
910 | d9bce9d9 | j_mayer | { |
911 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
912 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
913 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
914 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); |
915 | 74637406 | aurel32 | |
916 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t0, arg1); |
917 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t1, arg2); |
918 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
|
919 | 74637406 | aurel32 | if (sign) {
|
920 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
921 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
|
922 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); |
923 | 74637406 | aurel32 | gen_set_label(l3); |
924 | 2ef1b120 | aurel32 | tcg_gen_div_i32(t0, t0, t1); |
925 | 74637406 | aurel32 | } else {
|
926 | 2ef1b120 | aurel32 | tcg_gen_divu_i32(t0, t0, t1); |
927 | 74637406 | aurel32 | } |
928 | 74637406 | aurel32 | if (compute_ov) {
|
929 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
930 | 74637406 | aurel32 | } |
931 | 74637406 | aurel32 | tcg_gen_br(l2); |
932 | 74637406 | aurel32 | gen_set_label(l1); |
933 | 74637406 | aurel32 | if (sign) {
|
934 | 2ef1b120 | aurel32 | tcg_gen_sari_i32(t0, t0, 31);
|
935 | 74637406 | aurel32 | } else {
|
936 | 74637406 | aurel32 | tcg_gen_movi_i32(t0, 0);
|
937 | 74637406 | aurel32 | } |
938 | 74637406 | aurel32 | if (compute_ov) {
|
939 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
940 | 74637406 | aurel32 | } |
941 | 74637406 | aurel32 | gen_set_label(l2); |
942 | 2ef1b120 | aurel32 | tcg_gen_extu_i32_tl(ret, t0); |
943 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
944 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
945 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
946 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
947 | d9bce9d9 | j_mayer | } |
948 | 74637406 | aurel32 | /* Div functions */
|
949 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
950 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
951 | 74637406 | aurel32 | { \ |
952 | 74637406 | aurel32 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
953 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
954 | 74637406 | aurel32 | sign, compute_ov); \ |
955 | 74637406 | aurel32 | } |
956 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
957 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
958 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
959 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
960 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
961 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
962 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
963 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
964 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
965 | d9bce9d9 | j_mayer | { |
966 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
967 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
968 | 74637406 | aurel32 | |
969 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
|
970 | 74637406 | aurel32 | if (sign) {
|
971 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
972 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
|
973 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); |
974 | 74637406 | aurel32 | gen_set_label(l3); |
975 | 74637406 | aurel32 | tcg_gen_div_i64(ret, arg1, arg2); |
976 | 74637406 | aurel32 | } else {
|
977 | 74637406 | aurel32 | tcg_gen_divu_i64(ret, arg1, arg2); |
978 | 74637406 | aurel32 | } |
979 | 74637406 | aurel32 | if (compute_ov) {
|
980 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
981 | 74637406 | aurel32 | } |
982 | 74637406 | aurel32 | tcg_gen_br(l2); |
983 | 74637406 | aurel32 | gen_set_label(l1); |
984 | 74637406 | aurel32 | if (sign) {
|
985 | 74637406 | aurel32 | tcg_gen_sari_i64(ret, arg1, 63);
|
986 | 74637406 | aurel32 | } else {
|
987 | 74637406 | aurel32 | tcg_gen_movi_i64(ret, 0);
|
988 | 74637406 | aurel32 | } |
989 | 74637406 | aurel32 | if (compute_ov) {
|
990 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
991 | 74637406 | aurel32 | } |
992 | 74637406 | aurel32 | gen_set_label(l2); |
993 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
994 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
995 | d9bce9d9 | j_mayer | } |
996 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
997 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
998 | 74637406 | aurel32 | { \ |
999 | 2ef1b120 | aurel32 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1000 | 2ef1b120 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1001 | 2ef1b120 | aurel32 | sign, compute_ov); \ |
1002 | 74637406 | aurel32 | } |
1003 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
1004 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1005 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
1006 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
1007 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1008 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
1009 | d9bce9d9 | j_mayer | #endif
|
1010 | 74637406 | aurel32 | |
1011 | 74637406 | aurel32 | /* mulhw mulhw. */
|
1012 | 99e300ef | Blue Swirl | static void gen_mulhw(DisasContext *ctx) |
1013 | d9bce9d9 | j_mayer | { |
1014 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1015 | 74637406 | aurel32 | |
1016 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1017 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1018 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1019 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
1020 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
1021 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1022 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1023 | 74637406 | aurel32 | #else
|
1024 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1025 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1026 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1027 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1028 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1029 | 74637406 | aurel32 | #endif
|
1030 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1031 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1032 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1033 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1034 | d9bce9d9 | j_mayer | } |
1035 | 99e300ef | Blue Swirl | |
1036 | 54623277 | Blue Swirl | /* mulhwu mulhwu. */
|
1037 | 99e300ef | Blue Swirl | static void gen_mulhwu(DisasContext *ctx) |
1038 | d9bce9d9 | j_mayer | { |
1039 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1040 | 74637406 | aurel32 | |
1041 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1042 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1043 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1044 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1045 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1046 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1047 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1048 | 74637406 | aurel32 | #else
|
1049 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1050 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1051 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1052 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1053 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1054 | 74637406 | aurel32 | #endif
|
1055 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1056 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1057 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1058 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1059 | d9bce9d9 | j_mayer | } |
1060 | 99e300ef | Blue Swirl | |
1061 | 54623277 | Blue Swirl | /* mullw mullw. */
|
1062 | 99e300ef | Blue Swirl | static void gen_mullw(DisasContext *ctx) |
1063 | d9bce9d9 | j_mayer | { |
1064 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1065 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1066 | 1e4c090f | aurel32 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
1067 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1068 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1069 | d9bce9d9 | j_mayer | } |
1070 | 99e300ef | Blue Swirl | |
1071 | 54623277 | Blue Swirl | /* mullwo mullwo. */
|
1072 | 99e300ef | Blue Swirl | static void gen_mullwo(DisasContext *ctx) |
1073 | d9bce9d9 | j_mayer | { |
1074 | 74637406 | aurel32 | int l1;
|
1075 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1076 | 74637406 | aurel32 | |
1077 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1078 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1079 | 74637406 | aurel32 | l1 = gen_new_label(); |
1080 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1081 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1082 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1083 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1084 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1085 | 74637406 | aurel32 | #else
|
1086 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1087 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1088 | d9bce9d9 | j_mayer | #endif
|
1089 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1090 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1091 | 74637406 | aurel32 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); |
1092 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); |
1093 | 74637406 | aurel32 | #else
|
1094 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1095 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
1096 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
1097 | 74637406 | aurel32 | #endif
|
1098 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1099 | 74637406 | aurel32 | gen_set_label(l1); |
1100 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1101 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1102 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1103 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1104 | d9bce9d9 | j_mayer | } |
1105 | 99e300ef | Blue Swirl | |
1106 | 54623277 | Blue Swirl | /* mulli */
|
1107 | 99e300ef | Blue Swirl | static void gen_mulli(DisasContext *ctx) |
1108 | d9bce9d9 | j_mayer | { |
1109 | 74637406 | aurel32 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1110 | 74637406 | aurel32 | SIMM(ctx->opcode)); |
1111 | d9bce9d9 | j_mayer | } |
1112 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1113 | 74637406 | aurel32 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
1114 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1115 | 74637406 | aurel32 | { \ |
1116 | a7812ae4 | pbrook | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
1117 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1118 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1119 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
1120 | d9bce9d9 | j_mayer | } |
1121 | 74637406 | aurel32 | /* mulhd mulhd. */
|
1122 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
|
1123 | 74637406 | aurel32 | /* mulhdu mulhdu. */
|
1124 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
|
1125 | 99e300ef | Blue Swirl | |
1126 | 54623277 | Blue Swirl | /* mulld mulld. */
|
1127 | 99e300ef | Blue Swirl | static void gen_mulld(DisasContext *ctx) |
1128 | d9bce9d9 | j_mayer | { |
1129 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1130 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1131 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1132 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1133 | d9bce9d9 | j_mayer | } |
1134 | 74637406 | aurel32 | /* mulldo mulldo. */
|
1135 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
|
1136 | d9bce9d9 | j_mayer | #endif
|
1137 | 74637406 | aurel32 | |
1138 | 74637406 | aurel32 | /* neg neg. nego nego. */
|
1139 | 636aa200 | Blue Swirl | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1140 | 636aa200 | Blue Swirl | int ov_check)
|
1141 | d9bce9d9 | j_mayer | { |
1142 | ec6469a3 | aurel32 | int l1 = gen_new_label();
|
1143 | ec6469a3 | aurel32 | int l2 = gen_new_label();
|
1144 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1145 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1146 | 74637406 | aurel32 | if (ctx->sf_mode) {
|
1147 | 741a7444 | aurel32 | tcg_gen_mov_tl(t0, arg1); |
1148 | ec6469a3 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1149 | ec6469a3 | aurel32 | } else
|
1150 | ec6469a3 | aurel32 | #endif
|
1151 | ec6469a3 | aurel32 | { |
1152 | ec6469a3 | aurel32 | tcg_gen_ext32s_tl(t0, arg1); |
1153 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1154 | 74637406 | aurel32 | } |
1155 | 74637406 | aurel32 | tcg_gen_neg_tl(ret, arg1); |
1156 | 74637406 | aurel32 | if (ov_check) {
|
1157 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1158 | 74637406 | aurel32 | } |
1159 | 74637406 | aurel32 | tcg_gen_br(l2); |
1160 | 74637406 | aurel32 | gen_set_label(l1); |
1161 | ec6469a3 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1162 | 74637406 | aurel32 | if (ov_check) {
|
1163 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1164 | 74637406 | aurel32 | } |
1165 | 74637406 | aurel32 | gen_set_label(l2); |
1166 | ec6469a3 | aurel32 | tcg_temp_free(t0); |
1167 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1168 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
1169 | 74637406 | aurel32 | } |
1170 | 99e300ef | Blue Swirl | |
1171 | 99e300ef | Blue Swirl | static void gen_neg(DisasContext *ctx) |
1172 | d9bce9d9 | j_mayer | { |
1173 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
1174 | d9bce9d9 | j_mayer | } |
1175 | 99e300ef | Blue Swirl | |
1176 | 99e300ef | Blue Swirl | static void gen_nego(DisasContext *ctx) |
1177 | 79aceca5 | bellard | { |
1178 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
1179 | 79aceca5 | bellard | } |
1180 | 74637406 | aurel32 | |
1181 | 74637406 | aurel32 | /* Common subf function */
|
1182 | 636aa200 | Blue Swirl | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1183 | 636aa200 | Blue Swirl | TCGv arg2, int add_ca, int compute_ca, |
1184 | 636aa200 | Blue Swirl | int compute_ov)
|
1185 | 79aceca5 | bellard | { |
1186 | 74637406 | aurel32 | TCGv t0, t1; |
1187 | 76a66253 | j_mayer | |
1188 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
1189 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
1190 | 74637406 | aurel32 | t0 = ret; |
1191 | e864cabd | j_mayer | } else {
|
1192 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1193 | d9bce9d9 | j_mayer | } |
1194 | 76a66253 | j_mayer | |
1195 | 74637406 | aurel32 | if (add_ca) {
|
1196 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1197 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
1198 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
1199 | d2e9fd8f | malc | } else {
|
1200 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
1201 | d9bce9d9 | j_mayer | } |
1202 | 79aceca5 | bellard | |
1203 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
1204 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1205 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
1206 | 74637406 | aurel32 | } else if (compute_ca) { |
1207 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
1208 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1209 | 74637406 | aurel32 | } else if (compute_ov) { |
1210 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1211 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1212 | 74637406 | aurel32 | } |
1213 | 74637406 | aurel32 | |
1214 | 74637406 | aurel32 | if (add_ca) {
|
1215 | 74637406 | aurel32 | tcg_gen_not_tl(t0, arg1); |
1216 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, arg2); |
1217 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 0);
|
1218 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
1219 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
1220 | 74637406 | aurel32 | tcg_temp_free(t1); |
1221 | 79aceca5 | bellard | } else {
|
1222 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, arg2, arg1); |
1223 | 74637406 | aurel32 | if (compute_ca) {
|
1224 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 1);
|
1225 | 74637406 | aurel32 | } |
1226 | 74637406 | aurel32 | } |
1227 | 74637406 | aurel32 | if (compute_ov) {
|
1228 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
|
1229 | 74637406 | aurel32 | } |
1230 | 74637406 | aurel32 | |
1231 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1232 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
1233 | 74637406 | aurel32 | |
1234 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
1235 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1236 | 74637406 | aurel32 | tcg_temp_free(t0); |
1237 | 79aceca5 | bellard | } |
1238 | 79aceca5 | bellard | } |
1239 | 74637406 | aurel32 | /* Sub functions with Two operands functions */
|
1240 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
1241 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1242 | 74637406 | aurel32 | { \ |
1243 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1244 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1245 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1246 | 74637406 | aurel32 | } |
1247 | 74637406 | aurel32 | /* Sub functions with one operand and one immediate */
|
1248 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
1249 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
1250 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1251 | 74637406 | aurel32 | { \ |
1252 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
1253 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1254 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
1255 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1256 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
1257 | 74637406 | aurel32 | } |
1258 | 74637406 | aurel32 | /* subf subf. subfo subfo. */
|
1259 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
1260 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
1261 | 74637406 | aurel32 | /* subfc subfc. subfco subfco. */
|
1262 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
1263 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
1264 | 74637406 | aurel32 | /* subfe subfe. subfeo subfo. */
|
1265 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
1266 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
1267 | 74637406 | aurel32 | /* subfme subfme. subfmeo subfmeo. */
|
1268 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
1269 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
1270 | 74637406 | aurel32 | /* subfze subfze. subfzeo subfzeo.*/
|
1271 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
1272 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
1273 | 99e300ef | Blue Swirl | |
1274 | 54623277 | Blue Swirl | /* subfic */
|
1275 | 99e300ef | Blue Swirl | static void gen_subfic(DisasContext *ctx) |
1276 | 79aceca5 | bellard | { |
1277 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1278 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1279 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1280 | 74637406 | aurel32 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1281 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); |
1282 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 1);
|
1283 | 74637406 | aurel32 | tcg_temp_free(t1); |
1284 | 74637406 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1285 | 74637406 | aurel32 | tcg_temp_free(t0); |
1286 | 79aceca5 | bellard | } |
1287 | 79aceca5 | bellard | |
1288 | 79aceca5 | bellard | /*** Integer logical ***/
|
1289 | 26d67362 | aurel32 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
1290 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1291 | 79aceca5 | bellard | { \ |
1292 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1293 | 26d67362 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
1294 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1295 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1296 | 79aceca5 | bellard | } |
1297 | 79aceca5 | bellard | |
1298 | 26d67362 | aurel32 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
1299 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1300 | 79aceca5 | bellard | { \ |
1301 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
1302 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1303 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1304 | 79aceca5 | bellard | } |
1305 | 79aceca5 | bellard | |
1306 | 79aceca5 | bellard | /* and & and. */
|
1307 | 26d67362 | aurel32 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
|
1308 | 79aceca5 | bellard | /* andc & andc. */
|
1309 | 26d67362 | aurel32 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
|
1310 | e8eaa2c0 | Blue Swirl | |
1311 | 54623277 | Blue Swirl | /* andi. */
|
1312 | e8eaa2c0 | Blue Swirl | static void gen_andi_(DisasContext *ctx) |
1313 | 79aceca5 | bellard | { |
1314 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1315 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1316 | 79aceca5 | bellard | } |
1317 | e8eaa2c0 | Blue Swirl | |
1318 | 54623277 | Blue Swirl | /* andis. */
|
1319 | e8eaa2c0 | Blue Swirl | static void gen_andis_(DisasContext *ctx) |
1320 | 79aceca5 | bellard | { |
1321 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
|
1322 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1323 | 79aceca5 | bellard | } |
1324 | 99e300ef | Blue Swirl | |
1325 | 54623277 | Blue Swirl | /* cntlzw */
|
1326 | 99e300ef | Blue Swirl | static void gen_cntlzw(DisasContext *ctx) |
1327 | 26d67362 | aurel32 | { |
1328 | a7812ae4 | pbrook | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1329 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1330 | 2e31f5d3 | pbrook | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1331 | 26d67362 | aurel32 | } |
1332 | 79aceca5 | bellard | /* eqv & eqv. */
|
1333 | 26d67362 | aurel32 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
|
1334 | 79aceca5 | bellard | /* extsb & extsb. */
|
1335 | 26d67362 | aurel32 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
|
1336 | 79aceca5 | bellard | /* extsh & extsh. */
|
1337 | 26d67362 | aurel32 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
|
1338 | 79aceca5 | bellard | /* nand & nand. */
|
1339 | 26d67362 | aurel32 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
|
1340 | 79aceca5 | bellard | /* nor & nor. */
|
1341 | 26d67362 | aurel32 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
|
1342 | 99e300ef | Blue Swirl | |
1343 | 54623277 | Blue Swirl | /* or & or. */
|
1344 | 99e300ef | Blue Swirl | static void gen_or(DisasContext *ctx) |
1345 | 9a64fbe4 | bellard | { |
1346 | 76a66253 | j_mayer | int rs, ra, rb;
|
1347 | 76a66253 | j_mayer | |
1348 | 76a66253 | j_mayer | rs = rS(ctx->opcode); |
1349 | 76a66253 | j_mayer | ra = rA(ctx->opcode); |
1350 | 76a66253 | j_mayer | rb = rB(ctx->opcode); |
1351 | 76a66253 | j_mayer | /* Optimisation for mr. ri case */
|
1352 | 76a66253 | j_mayer | if (rs != ra || rs != rb) {
|
1353 | 26d67362 | aurel32 | if (rs != rb)
|
1354 | 26d67362 | aurel32 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
1355 | 26d67362 | aurel32 | else
|
1356 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
1357 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1358 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
1359 | 76a66253 | j_mayer | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1360 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
1361 | c80f84e3 | j_mayer | #if defined(TARGET_PPC64)
|
1362 | c80f84e3 | j_mayer | } else {
|
1363 | 26d67362 | aurel32 | int prio = 0; |
1364 | 26d67362 | aurel32 | |
1365 | c80f84e3 | j_mayer | switch (rs) {
|
1366 | c80f84e3 | j_mayer | case 1: |
1367 | c80f84e3 | j_mayer | /* Set process priority to low */
|
1368 | 26d67362 | aurel32 | prio = 2;
|
1369 | c80f84e3 | j_mayer | break;
|
1370 | c80f84e3 | j_mayer | case 6: |
1371 | c80f84e3 | j_mayer | /* Set process priority to medium-low */
|
1372 | 26d67362 | aurel32 | prio = 3;
|
1373 | c80f84e3 | j_mayer | break;
|
1374 | c80f84e3 | j_mayer | case 2: |
1375 | c80f84e3 | j_mayer | /* Set process priority to normal */
|
1376 | 26d67362 | aurel32 | prio = 4;
|
1377 | c80f84e3 | j_mayer | break;
|
1378 | be147d08 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
1379 | be147d08 | j_mayer | case 31: |
1380 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1381 | be147d08 | j_mayer | /* Set process priority to very low */
|
1382 | 26d67362 | aurel32 | prio = 1;
|
1383 | be147d08 | j_mayer | } |
1384 | be147d08 | j_mayer | break;
|
1385 | be147d08 | j_mayer | case 5: |
1386 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1387 | be147d08 | j_mayer | /* Set process priority to medium-hight */
|
1388 | 26d67362 | aurel32 | prio = 5;
|
1389 | be147d08 | j_mayer | } |
1390 | be147d08 | j_mayer | break;
|
1391 | be147d08 | j_mayer | case 3: |
1392 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1393 | be147d08 | j_mayer | /* Set process priority to high */
|
1394 | 26d67362 | aurel32 | prio = 6;
|
1395 | be147d08 | j_mayer | } |
1396 | be147d08 | j_mayer | break;
|
1397 | be147d08 | j_mayer | case 7: |
1398 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 1) { |
1399 | be147d08 | j_mayer | /* Set process priority to very high */
|
1400 | 26d67362 | aurel32 | prio = 7;
|
1401 | be147d08 | j_mayer | } |
1402 | be147d08 | j_mayer | break;
|
1403 | be147d08 | j_mayer | #endif
|
1404 | c80f84e3 | j_mayer | default:
|
1405 | c80f84e3 | j_mayer | /* nop */
|
1406 | c80f84e3 | j_mayer | break;
|
1407 | c80f84e3 | j_mayer | } |
1408 | 26d67362 | aurel32 | if (prio) {
|
1409 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1410 | 54cdcae6 | aurel32 | gen_load_spr(t0, SPR_PPR); |
1411 | ea363694 | aurel32 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
|
1412 | ea363694 | aurel32 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
|
1413 | 54cdcae6 | aurel32 | gen_store_spr(SPR_PPR, t0); |
1414 | ea363694 | aurel32 | tcg_temp_free(t0); |
1415 | 26d67362 | aurel32 | } |
1416 | c80f84e3 | j_mayer | #endif
|
1417 | 9a64fbe4 | bellard | } |
1418 | 9a64fbe4 | bellard | } |
1419 | 79aceca5 | bellard | /* orc & orc. */
|
1420 | 26d67362 | aurel32 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
|
1421 | 99e300ef | Blue Swirl | |
1422 | 54623277 | Blue Swirl | /* xor & xor. */
|
1423 | 99e300ef | Blue Swirl | static void gen_xor(DisasContext *ctx) |
1424 | 9a64fbe4 | bellard | { |
1425 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
1426 | 26d67362 | aurel32 | if (rS(ctx->opcode) != rB(ctx->opcode))
|
1427 | 312179c4 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1428 | 26d67362 | aurel32 | else
|
1429 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1430 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1431 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1432 | 9a64fbe4 | bellard | } |
1433 | 99e300ef | Blue Swirl | |
1434 | 54623277 | Blue Swirl | /* ori */
|
1435 | 99e300ef | Blue Swirl | static void gen_ori(DisasContext *ctx) |
1436 | 79aceca5 | bellard | { |
1437 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1438 | 79aceca5 | bellard | |
1439 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1440 | 9a64fbe4 | bellard | /* NOP */
|
1441 | 76a66253 | j_mayer | /* XXX: should handle special NOPs for POWER series */
|
1442 | 9a64fbe4 | bellard | return;
|
1443 | 76a66253 | j_mayer | } |
1444 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1445 | 79aceca5 | bellard | } |
1446 | 99e300ef | Blue Swirl | |
1447 | 54623277 | Blue Swirl | /* oris */
|
1448 | 99e300ef | Blue Swirl | static void gen_oris(DisasContext *ctx) |
1449 | 79aceca5 | bellard | { |
1450 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1451 | 79aceca5 | bellard | |
1452 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1453 | 9a64fbe4 | bellard | /* NOP */
|
1454 | 9a64fbe4 | bellard | return;
|
1455 | 76a66253 | j_mayer | } |
1456 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1457 | 79aceca5 | bellard | } |
1458 | 99e300ef | Blue Swirl | |
1459 | 54623277 | Blue Swirl | /* xori */
|
1460 | 99e300ef | Blue Swirl | static void gen_xori(DisasContext *ctx) |
1461 | 79aceca5 | bellard | { |
1462 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1463 | 9a64fbe4 | bellard | |
1464 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1465 | 9a64fbe4 | bellard | /* NOP */
|
1466 | 9a64fbe4 | bellard | return;
|
1467 | 9a64fbe4 | bellard | } |
1468 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1469 | 79aceca5 | bellard | } |
1470 | 99e300ef | Blue Swirl | |
1471 | 54623277 | Blue Swirl | /* xoris */
|
1472 | 99e300ef | Blue Swirl | static void gen_xoris(DisasContext *ctx) |
1473 | 79aceca5 | bellard | { |
1474 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1475 | 9a64fbe4 | bellard | |
1476 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1477 | 9a64fbe4 | bellard | /* NOP */
|
1478 | 9a64fbe4 | bellard | return;
|
1479 | 9a64fbe4 | bellard | } |
1480 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1481 | 79aceca5 | bellard | } |
1482 | 99e300ef | Blue Swirl | |
1483 | 54623277 | Blue Swirl | /* popcntb : PowerPC 2.03 specification */
|
1484 | 99e300ef | Blue Swirl | static void gen_popcntb(DisasContext *ctx) |
1485 | d9bce9d9 | j_mayer | { |
1486 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1487 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
1488 | a7812ae4 | pbrook | gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1489 | d9bce9d9 | j_mayer | else
|
1490 | d9bce9d9 | j_mayer | #endif
|
1491 | a7812ae4 | pbrook | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1492 | d9bce9d9 | j_mayer | } |
1493 | d9bce9d9 | j_mayer | |
1494 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1495 | d9bce9d9 | j_mayer | /* extsw & extsw. */
|
1496 | 26d67362 | aurel32 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
|
1497 | 99e300ef | Blue Swirl | |
1498 | 54623277 | Blue Swirl | /* cntlzd */
|
1499 | 99e300ef | Blue Swirl | static void gen_cntlzd(DisasContext *ctx) |
1500 | 26d67362 | aurel32 | { |
1501 | a7812ae4 | pbrook | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1502 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1503 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1504 | 26d67362 | aurel32 | } |
1505 | d9bce9d9 | j_mayer | #endif
|
1506 | d9bce9d9 | j_mayer | |
1507 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1508 | 99e300ef | Blue Swirl | |
1509 | 54623277 | Blue Swirl | /* rlwimi & rlwimi. */
|
1510 | 99e300ef | Blue Swirl | static void gen_rlwimi(DisasContext *ctx) |
1511 | 79aceca5 | bellard | { |
1512 | 76a66253 | j_mayer | uint32_t mb, me, sh; |
1513 | 79aceca5 | bellard | |
1514 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1515 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1516 | 76a66253 | j_mayer | sh = SH(ctx->opcode); |
1517 | d03ef511 | aurel32 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1518 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1519 | d03ef511 | aurel32 | } else {
|
1520 | d03ef511 | aurel32 | target_ulong mask; |
1521 | a7812ae4 | pbrook | TCGv t1; |
1522 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1523 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1524 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_new_i32(); |
1525 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); |
1526 | a7812ae4 | pbrook | tcg_gen_rotli_i32(t2, t2, sh); |
1527 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(t0, t2); |
1528 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1529 | 54843a58 | aurel32 | #else
|
1530 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1531 | 54843a58 | aurel32 | #endif
|
1532 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1533 | d03ef511 | aurel32 | mb += 32;
|
1534 | d03ef511 | aurel32 | me += 32;
|
1535 | 76a66253 | j_mayer | #endif
|
1536 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1537 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1538 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1539 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1540 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1541 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1542 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1543 | d03ef511 | aurel32 | } |
1544 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1545 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1546 | 79aceca5 | bellard | } |
1547 | 99e300ef | Blue Swirl | |
1548 | 54623277 | Blue Swirl | /* rlwinm & rlwinm. */
|
1549 | 99e300ef | Blue Swirl | static void gen_rlwinm(DisasContext *ctx) |
1550 | 79aceca5 | bellard | { |
1551 | 79aceca5 | bellard | uint32_t mb, me, sh; |
1552 | 3b46e624 | ths | |
1553 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
1554 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1555 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1556 | d03ef511 | aurel32 | |
1557 | d03ef511 | aurel32 | if (likely(mb == 0 && me == (31 - sh))) { |
1558 | d03ef511 | aurel32 | if (likely(sh == 0)) { |
1559 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1560 | d03ef511 | aurel32 | } else {
|
1561 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1562 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1563 | d03ef511 | aurel32 | tcg_gen_shli_tl(t0, t0, sh); |
1564 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1565 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1566 | 79aceca5 | bellard | } |
1567 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
1568 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1569 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1570 | d03ef511 | aurel32 | tcg_gen_shri_tl(t0, t0, mb); |
1571 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1572 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1573 | d03ef511 | aurel32 | } else {
|
1574 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1575 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1576 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_new_i32(); |
1577 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1578 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t1, t1, sh); |
1579 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1580 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1581 | 54843a58 | aurel32 | #else
|
1582 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1583 | 54843a58 | aurel32 | #endif
|
1584 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1585 | d03ef511 | aurel32 | mb += 32;
|
1586 | d03ef511 | aurel32 | me += 32;
|
1587 | 76a66253 | j_mayer | #endif
|
1588 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1589 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1590 | d03ef511 | aurel32 | } |
1591 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1592 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1593 | 79aceca5 | bellard | } |
1594 | 99e300ef | Blue Swirl | |
1595 | 54623277 | Blue Swirl | /* rlwnm & rlwnm. */
|
1596 | 99e300ef | Blue Swirl | static void gen_rlwnm(DisasContext *ctx) |
1597 | 79aceca5 | bellard | { |
1598 | 79aceca5 | bellard | uint32_t mb, me; |
1599 | 54843a58 | aurel32 | TCGv t0; |
1600 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1601 | a7812ae4 | pbrook | TCGv_i32 t1, t2; |
1602 | 54843a58 | aurel32 | #endif
|
1603 | 79aceca5 | bellard | |
1604 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1605 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1606 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1607 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1608 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1609 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1610 | a7812ae4 | pbrook | t2 = tcg_temp_new_i32(); |
1611 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1612 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t2, t0); |
1613 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t1, t1, t2); |
1614 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1615 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1616 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1617 | 54843a58 | aurel32 | #else
|
1618 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1619 | 54843a58 | aurel32 | #endif
|
1620 | 76a66253 | j_mayer | if (unlikely(mb != 0 || me != 31)) { |
1621 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1622 | 76a66253 | j_mayer | mb += 32;
|
1623 | 76a66253 | j_mayer | me += 32;
|
1624 | 76a66253 | j_mayer | #endif
|
1625 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1626 | d03ef511 | aurel32 | } else {
|
1627 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1628 | 79aceca5 | bellard | } |
1629 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1630 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1631 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1632 | 79aceca5 | bellard | } |
1633 | 79aceca5 | bellard | |
1634 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1635 | d9bce9d9 | j_mayer | #define GEN_PPC64_R2(name, opc1, opc2) \
|
1636 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1637 | d9bce9d9 | j_mayer | { \ |
1638 | d9bce9d9 | j_mayer | gen_##name(ctx, 0); \ |
1639 | d9bce9d9 | j_mayer | } \ |
1640 | e8eaa2c0 | Blue Swirl | \ |
1641 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1642 | d9bce9d9 | j_mayer | { \ |
1643 | d9bce9d9 | j_mayer | gen_##name(ctx, 1); \ |
1644 | d9bce9d9 | j_mayer | } |
1645 | d9bce9d9 | j_mayer | #define GEN_PPC64_R4(name, opc1, opc2) \
|
1646 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1647 | d9bce9d9 | j_mayer | { \ |
1648 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 0); \ |
1649 | d9bce9d9 | j_mayer | } \ |
1650 | e8eaa2c0 | Blue Swirl | \ |
1651 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1652 | d9bce9d9 | j_mayer | { \ |
1653 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 1); \ |
1654 | d9bce9d9 | j_mayer | } \ |
1655 | e8eaa2c0 | Blue Swirl | \ |
1656 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##2)(DisasContext *ctx) \ |
1657 | d9bce9d9 | j_mayer | { \ |
1658 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 0); \ |
1659 | d9bce9d9 | j_mayer | } \ |
1660 | e8eaa2c0 | Blue Swirl | \ |
1661 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##3)(DisasContext *ctx) \ |
1662 | d9bce9d9 | j_mayer | { \ |
1663 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 1); \ |
1664 | d9bce9d9 | j_mayer | } |
1665 | 51789c41 | j_mayer | |
1666 | 636aa200 | Blue Swirl | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1667 | 636aa200 | Blue Swirl | uint32_t sh) |
1668 | 51789c41 | j_mayer | { |
1669 | d03ef511 | aurel32 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1670 | d03ef511 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1671 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
1672 | d03ef511 | aurel32 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
1673 | d03ef511 | aurel32 | } else {
|
1674 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1675 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1676 | d03ef511 | aurel32 | if (likely(mb == 0 && me == 63)) { |
1677 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1678 | d03ef511 | aurel32 | } else {
|
1679 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1680 | 51789c41 | j_mayer | } |
1681 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1682 | 51789c41 | j_mayer | } |
1683 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1684 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1685 | 51789c41 | j_mayer | } |
1686 | d9bce9d9 | j_mayer | /* rldicl - rldicl. */
|
1687 | 636aa200 | Blue Swirl | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
1688 | d9bce9d9 | j_mayer | { |
1689 | 51789c41 | j_mayer | uint32_t sh, mb; |
1690 | d9bce9d9 | j_mayer | |
1691 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1692 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1693 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63, sh);
|
1694 | d9bce9d9 | j_mayer | } |
1695 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1696 | d9bce9d9 | j_mayer | /* rldicr - rldicr. */
|
1697 | 636aa200 | Blue Swirl | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
1698 | d9bce9d9 | j_mayer | { |
1699 | 51789c41 | j_mayer | uint32_t sh, me; |
1700 | d9bce9d9 | j_mayer | |
1701 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1702 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1703 | 51789c41 | j_mayer | gen_rldinm(ctx, 0, me, sh);
|
1704 | d9bce9d9 | j_mayer | } |
1705 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1706 | d9bce9d9 | j_mayer | /* rldic - rldic. */
|
1707 | 636aa200 | Blue Swirl | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
1708 | d9bce9d9 | j_mayer | { |
1709 | 51789c41 | j_mayer | uint32_t sh, mb; |
1710 | d9bce9d9 | j_mayer | |
1711 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1712 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1713 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63 - sh, sh);
|
1714 | 51789c41 | j_mayer | } |
1715 | 51789c41 | j_mayer | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1716 | 51789c41 | j_mayer | |
1717 | 636aa200 | Blue Swirl | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
1718 | 51789c41 | j_mayer | { |
1719 | 54843a58 | aurel32 | TCGv t0; |
1720 | d03ef511 | aurel32 | |
1721 | d03ef511 | aurel32 | mb = MB(ctx->opcode); |
1722 | d03ef511 | aurel32 | me = ME(ctx->opcode); |
1723 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1724 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1725 | 54843a58 | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1726 | 51789c41 | j_mayer | if (unlikely(mb != 0 || me != 63)) { |
1727 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1728 | 54843a58 | aurel32 | } else {
|
1729 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1730 | 54843a58 | aurel32 | } |
1731 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1732 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1733 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1734 | d9bce9d9 | j_mayer | } |
1735 | 51789c41 | j_mayer | |
1736 | d9bce9d9 | j_mayer | /* rldcl - rldcl. */
|
1737 | 636aa200 | Blue Swirl | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
1738 | d9bce9d9 | j_mayer | { |
1739 | 51789c41 | j_mayer | uint32_t mb; |
1740 | d9bce9d9 | j_mayer | |
1741 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1742 | 51789c41 | j_mayer | gen_rldnm(ctx, mb, 63);
|
1743 | d9bce9d9 | j_mayer | } |
1744 | 36081602 | j_mayer | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1745 | d9bce9d9 | j_mayer | /* rldcr - rldcr. */
|
1746 | 636aa200 | Blue Swirl | static inline void gen_rldcr(DisasContext *ctx, int men) |
1747 | d9bce9d9 | j_mayer | { |
1748 | 51789c41 | j_mayer | uint32_t me; |
1749 | d9bce9d9 | j_mayer | |
1750 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1751 | 51789c41 | j_mayer | gen_rldnm(ctx, 0, me);
|
1752 | d9bce9d9 | j_mayer | } |
1753 | 36081602 | j_mayer | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1754 | d9bce9d9 | j_mayer | /* rldimi - rldimi. */
|
1755 | 636aa200 | Blue Swirl | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
1756 | d9bce9d9 | j_mayer | { |
1757 | 271a916e | j_mayer | uint32_t sh, mb, me; |
1758 | d9bce9d9 | j_mayer | |
1759 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1760 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1761 | 271a916e | j_mayer | me = 63 - sh;
|
1762 | d03ef511 | aurel32 | if (unlikely(sh == 0 && mb == 0)) { |
1763 | d03ef511 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1764 | d03ef511 | aurel32 | } else {
|
1765 | d03ef511 | aurel32 | TCGv t0, t1; |
1766 | d03ef511 | aurel32 | target_ulong mask; |
1767 | d03ef511 | aurel32 | |
1768 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1769 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1770 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1771 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1772 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1773 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1774 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1775 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1776 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1777 | 51789c41 | j_mayer | } |
1778 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1779 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1780 | d9bce9d9 | j_mayer | } |
1781 | 36081602 | j_mayer | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1782 | d9bce9d9 | j_mayer | #endif
|
1783 | d9bce9d9 | j_mayer | |
1784 | 79aceca5 | bellard | /*** Integer shift ***/
|
1785 | 99e300ef | Blue Swirl | |
1786 | 54623277 | Blue Swirl | /* slw & slw. */
|
1787 | 99e300ef | Blue Swirl | static void gen_slw(DisasContext *ctx) |
1788 | 26d67362 | aurel32 | { |
1789 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1790 | 26d67362 | aurel32 | |
1791 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1792 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1793 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1794 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1795 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1796 | 7fd6bf7d | Aurelien Jarno | #else
|
1797 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1798 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1799 | 7fd6bf7d | Aurelien Jarno | #endif
|
1800 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1801 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1802 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1803 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1804 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1805 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1806 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1807 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1808 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1809 | 26d67362 | aurel32 | } |
1810 | 99e300ef | Blue Swirl | |
1811 | 54623277 | Blue Swirl | /* sraw & sraw. */
|
1812 | 99e300ef | Blue Swirl | static void gen_sraw(DisasContext *ctx) |
1813 | 26d67362 | aurel32 | { |
1814 | a7812ae4 | pbrook | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
1815 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1816 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1817 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1818 | 26d67362 | aurel32 | } |
1819 | 99e300ef | Blue Swirl | |
1820 | 54623277 | Blue Swirl | /* srawi & srawi. */
|
1821 | 99e300ef | Blue Swirl | static void gen_srawi(DisasContext *ctx) |
1822 | 79aceca5 | bellard | { |
1823 | 26d67362 | aurel32 | int sh = SH(ctx->opcode);
|
1824 | 26d67362 | aurel32 | if (sh != 0) { |
1825 | 26d67362 | aurel32 | int l1, l2;
|
1826 | fea0c503 | aurel32 | TCGv t0; |
1827 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1828 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1829 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1830 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1831 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
1832 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1833 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1834 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1835 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1836 | 26d67362 | aurel32 | gen_set_label(l1); |
1837 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1838 | 26d67362 | aurel32 | gen_set_label(l2); |
1839 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1840 | fea0c503 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); |
1841 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1842 | 26d67362 | aurel32 | } else {
|
1843 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1844 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1845 | d9bce9d9 | j_mayer | } |
1846 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1847 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1848 | 79aceca5 | bellard | } |
1849 | 99e300ef | Blue Swirl | |
1850 | 54623277 | Blue Swirl | /* srw & srw. */
|
1851 | 99e300ef | Blue Swirl | static void gen_srw(DisasContext *ctx) |
1852 | 26d67362 | aurel32 | { |
1853 | fea0c503 | aurel32 | TCGv t0, t1; |
1854 | d9bce9d9 | j_mayer | |
1855 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1856 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1857 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1858 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1859 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1860 | 7fd6bf7d | Aurelien Jarno | #else
|
1861 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1862 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1863 | 7fd6bf7d | Aurelien Jarno | #endif
|
1864 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1865 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(t0, t0); |
1866 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1867 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1868 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1869 | fea0c503 | aurel32 | tcg_temp_free(t1); |
1870 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1871 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1872 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1873 | 26d67362 | aurel32 | } |
1874 | 54623277 | Blue Swirl | |
1875 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1876 | d9bce9d9 | j_mayer | /* sld & sld. */
|
1877 | 99e300ef | Blue Swirl | static void gen_sld(DisasContext *ctx) |
1878 | 26d67362 | aurel32 | { |
1879 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1880 | 26d67362 | aurel32 | |
1881 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1882 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
1883 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
1884 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1885 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1886 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1887 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1888 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1889 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1890 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1891 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1892 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1893 | 26d67362 | aurel32 | } |
1894 | 99e300ef | Blue Swirl | |
1895 | 54623277 | Blue Swirl | /* srad & srad. */
|
1896 | 99e300ef | Blue Swirl | static void gen_srad(DisasContext *ctx) |
1897 | 26d67362 | aurel32 | { |
1898 | a7812ae4 | pbrook | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
1899 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1900 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1901 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1902 | 26d67362 | aurel32 | } |
1903 | d9bce9d9 | j_mayer | /* sradi & sradi. */
|
1904 | 636aa200 | Blue Swirl | static inline void gen_sradi(DisasContext *ctx, int n) |
1905 | d9bce9d9 | j_mayer | { |
1906 | 26d67362 | aurel32 | int sh = SH(ctx->opcode) + (n << 5); |
1907 | d9bce9d9 | j_mayer | if (sh != 0) { |
1908 | 26d67362 | aurel32 | int l1, l2;
|
1909 | fea0c503 | aurel32 | TCGv t0; |
1910 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1911 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1912 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1913 | 26d67362 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
1914 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1915 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1916 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1917 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1918 | 26d67362 | aurel32 | gen_set_label(l1); |
1919 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1920 | 26d67362 | aurel32 | gen_set_label(l2); |
1921 | a9730017 | aurel32 | tcg_temp_free(t0); |
1922 | 26d67362 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1923 | 26d67362 | aurel32 | } else {
|
1924 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1925 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1926 | d9bce9d9 | j_mayer | } |
1927 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1928 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1929 | d9bce9d9 | j_mayer | } |
1930 | e8eaa2c0 | Blue Swirl | |
1931 | e8eaa2c0 | Blue Swirl | static void gen_sradi0(DisasContext *ctx) |
1932 | d9bce9d9 | j_mayer | { |
1933 | d9bce9d9 | j_mayer | gen_sradi(ctx, 0);
|
1934 | d9bce9d9 | j_mayer | } |
1935 | e8eaa2c0 | Blue Swirl | |
1936 | e8eaa2c0 | Blue Swirl | static void gen_sradi1(DisasContext *ctx) |
1937 | d9bce9d9 | j_mayer | { |
1938 | d9bce9d9 | j_mayer | gen_sradi(ctx, 1);
|
1939 | d9bce9d9 | j_mayer | } |
1940 | 99e300ef | Blue Swirl | |
1941 | 54623277 | Blue Swirl | /* srd & srd. */
|
1942 | 99e300ef | Blue Swirl | static void gen_srd(DisasContext *ctx) |
1943 | 26d67362 | aurel32 | { |
1944 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1945 | 26d67362 | aurel32 | |
1946 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1947 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
1948 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
1949 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1950 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1951 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1952 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1953 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1954 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1955 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1956 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1957 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1958 | 26d67362 | aurel32 | } |
1959 | d9bce9d9 | j_mayer | #endif
|
1960 | 79aceca5 | bellard | |
1961 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1962 | 7c58044c | j_mayer | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
1963 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
1964 | 9a64fbe4 | bellard | { \ |
1965 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1966 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
1967 | 3cc62370 | bellard | return; \
|
1968 | 3cc62370 | bellard | } \ |
1969 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
1970 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
1971 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1972 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1973 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
1974 | 4ecc3190 | bellard | if (isfloat) { \
|
1975 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
1976 | 4ecc3190 | bellard | } \ |
1977 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1978 | af12906f | aurel32 | Rc(ctx->opcode) != 0); \
|
1979 | 9a64fbe4 | bellard | } |
1980 | 9a64fbe4 | bellard | |
1981 | 7c58044c | j_mayer | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
1982 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
1983 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
1984 | 9a64fbe4 | bellard | |
1985 | 7c58044c | j_mayer | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
1986 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
1987 | 9a64fbe4 | bellard | { \ |
1988 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1989 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
1990 | 3cc62370 | bellard | return; \
|
1991 | 3cc62370 | bellard | } \ |
1992 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
1993 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
1994 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1995 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1996 | af12906f | aurel32 | cpu_fpr[rB(ctx->opcode)]); \ |
1997 | 4ecc3190 | bellard | if (isfloat) { \
|
1998 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
1999 | 4ecc3190 | bellard | } \ |
2000 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2001 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2002 | 9a64fbe4 | bellard | } |
2003 | 7c58044c | j_mayer | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
2004 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2005 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2006 | 9a64fbe4 | bellard | |
2007 | 7c58044c | j_mayer | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2008 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2009 | 9a64fbe4 | bellard | { \ |
2010 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2011 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2012 | 3cc62370 | bellard | return; \
|
2013 | 3cc62370 | bellard | } \ |
2014 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2015 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2016 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2017 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2018 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)]); \ |
2019 | 4ecc3190 | bellard | if (isfloat) { \
|
2020 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
2021 | 4ecc3190 | bellard | } \ |
2022 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2023 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2024 | 9a64fbe4 | bellard | } |
2025 | 7c58044c | j_mayer | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
2026 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2027 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2028 | 9a64fbe4 | bellard | |
2029 | 7c58044c | j_mayer | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
2030 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2031 | 9a64fbe4 | bellard | { \ |
2032 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2033 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2034 | 3cc62370 | bellard | return; \
|
2035 | 3cc62370 | bellard | } \ |
2036 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2037 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2038 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2039 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2040 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2041 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2042 | 79aceca5 | bellard | } |
2043 | 79aceca5 | bellard | |
2044 | 7c58044c | j_mayer | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
2045 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2046 | 9a64fbe4 | bellard | { \ |
2047 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2048 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2049 | 3cc62370 | bellard | return; \
|
2050 | 3cc62370 | bellard | } \ |
2051 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2052 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2053 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2054 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2055 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2056 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2057 | 79aceca5 | bellard | } |
2058 | 79aceca5 | bellard | |
2059 | 9a64fbe4 | bellard | /* fadd - fadds */
|
2060 | 7c58044c | j_mayer | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
2061 | 4ecc3190 | bellard | /* fdiv - fdivs */
|
2062 | 7c58044c | j_mayer | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
2063 | 4ecc3190 | bellard | /* fmul - fmuls */
|
2064 | 7c58044c | j_mayer | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
2065 | 79aceca5 | bellard | |
2066 | d7e4b87e | j_mayer | /* fre */
|
2067 | 7c58044c | j_mayer | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
2068 | d7e4b87e | j_mayer | |
2069 | a750fc0b | j_mayer | /* fres */
|
2070 | 7c58044c | j_mayer | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
2071 | 79aceca5 | bellard | |
2072 | a750fc0b | j_mayer | /* frsqrte */
|
2073 | 7c58044c | j_mayer | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2074 | 7c58044c | j_mayer | |
2075 | 7c58044c | j_mayer | /* frsqrtes */
|
2076 | 99e300ef | Blue Swirl | static void gen_frsqrtes(DisasContext *ctx) |
2077 | 7c58044c | j_mayer | { |
2078 | af12906f | aurel32 | if (unlikely(!ctx->fpu_enabled)) {
|
2079 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2080 | af12906f | aurel32 | return;
|
2081 | af12906f | aurel32 | } |
2082 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2083 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2084 | af12906f | aurel32 | gen_reset_fpstatus(); |
2085 | af12906f | aurel32 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2086 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2087 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2088 | 7c58044c | j_mayer | } |
2089 | 79aceca5 | bellard | |
2090 | a750fc0b | j_mayer | /* fsel */
|
2091 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
2092 | 4ecc3190 | bellard | /* fsub - fsubs */
|
2093 | 7c58044c | j_mayer | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
2094 | 79aceca5 | bellard | /* Optional: */
|
2095 | 99e300ef | Blue Swirl | |
2096 | 54623277 | Blue Swirl | /* fsqrt */
|
2097 | 99e300ef | Blue Swirl | static void gen_fsqrt(DisasContext *ctx) |
2098 | c7d344af | bellard | { |
2099 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2100 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2101 | c7d344af | bellard | return;
|
2102 | c7d344af | bellard | } |
2103 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2104 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2105 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2106 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2107 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2108 | c7d344af | bellard | } |
2109 | 79aceca5 | bellard | |
2110 | 99e300ef | Blue Swirl | static void gen_fsqrts(DisasContext *ctx) |
2111 | 79aceca5 | bellard | { |
2112 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2113 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2114 | 3cc62370 | bellard | return;
|
2115 | 3cc62370 | bellard | } |
2116 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2117 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2118 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2119 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2120 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2121 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2122 | 79aceca5 | bellard | } |
2123 | 79aceca5 | bellard | |
2124 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
2125 | 4ecc3190 | bellard | /* fmadd - fmadds */
|
2126 | 7c58044c | j_mayer | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
2127 | 4ecc3190 | bellard | /* fmsub - fmsubs */
|
2128 | 7c58044c | j_mayer | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
2129 | 4ecc3190 | bellard | /* fnmadd - fnmadds */
|
2130 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
2131 | 4ecc3190 | bellard | /* fnmsub - fnmsubs */
|
2132 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
2133 | 79aceca5 | bellard | |
2134 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
2135 | 79aceca5 | bellard | /* fctiw */
|
2136 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
2137 | 79aceca5 | bellard | /* fctiwz */
|
2138 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
2139 | 79aceca5 | bellard | /* frsp */
|
2140 | 7c58044c | j_mayer | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
2141 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
2142 | 426613db | j_mayer | /* fcfid */
|
2143 | 7c58044c | j_mayer | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
2144 | 426613db | j_mayer | /* fctid */
|
2145 | 7c58044c | j_mayer | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
2146 | 426613db | j_mayer | /* fctidz */
|
2147 | 7c58044c | j_mayer | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
2148 | 426613db | j_mayer | #endif
|
2149 | 79aceca5 | bellard | |
2150 | d7e4b87e | j_mayer | /* frin */
|
2151 | 7c58044c | j_mayer | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
2152 | d7e4b87e | j_mayer | /* friz */
|
2153 | 7c58044c | j_mayer | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
2154 | d7e4b87e | j_mayer | /* frip */
|
2155 | 7c58044c | j_mayer | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
2156 | d7e4b87e | j_mayer | /* frim */
|
2157 | 7c58044c | j_mayer | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
2158 | d7e4b87e | j_mayer | |
2159 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
2160 | 99e300ef | Blue Swirl | |
2161 | 54623277 | Blue Swirl | /* fcmpo */
|
2162 | 99e300ef | Blue Swirl | static void gen_fcmpo(DisasContext *ctx) |
2163 | 79aceca5 | bellard | { |
2164 | 330c483b | aurel32 | TCGv_i32 crf; |
2165 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2166 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2167 | 3cc62370 | bellard | return;
|
2168 | 3cc62370 | bellard | } |
2169 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2170 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2171 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2172 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2173 | 9a819377 | aurel32 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2174 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2175 | af12906f | aurel32 | gen_helper_float_check_status(); |
2176 | 79aceca5 | bellard | } |
2177 | 79aceca5 | bellard | |
2178 | 79aceca5 | bellard | /* fcmpu */
|
2179 | 99e300ef | Blue Swirl | static void gen_fcmpu(DisasContext *ctx) |
2180 | 79aceca5 | bellard | { |
2181 | 330c483b | aurel32 | TCGv_i32 crf; |
2182 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2183 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2184 | 3cc62370 | bellard | return;
|
2185 | 3cc62370 | bellard | } |
2186 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2187 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2188 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2189 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2190 | 9a819377 | aurel32 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2191 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2192 | af12906f | aurel32 | gen_helper_float_check_status(); |
2193 | 79aceca5 | bellard | } |
2194 | 79aceca5 | bellard | |
2195 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
2196 | 9a64fbe4 | bellard | /* fabs */
|
2197 | 7c58044c | j_mayer | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
2198 | 7c58044c | j_mayer | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
2199 | 9a64fbe4 | bellard | |
2200 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
2201 | 7c58044c | j_mayer | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
2202 | 99e300ef | Blue Swirl | static void gen_fmr(DisasContext *ctx) |
2203 | 9a64fbe4 | bellard | { |
2204 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2205 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2206 | 3cc62370 | bellard | return;
|
2207 | 3cc62370 | bellard | } |
2208 | af12906f | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2209 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2210 | 9a64fbe4 | bellard | } |
2211 | 9a64fbe4 | bellard | |
2212 | 9a64fbe4 | bellard | /* fnabs */
|
2213 | 7c58044c | j_mayer | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
2214 | 7c58044c | j_mayer | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
2215 | 9a64fbe4 | bellard | /* fneg */
|
2216 | 7c58044c | j_mayer | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
2217 | 7c58044c | j_mayer | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
2218 | 9a64fbe4 | bellard | |
2219 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
2220 | 99e300ef | Blue Swirl | |
2221 | 54623277 | Blue Swirl | /* mcrfs */
|
2222 | 99e300ef | Blue Swirl | static void gen_mcrfs(DisasContext *ctx) |
2223 | 79aceca5 | bellard | { |
2224 | 7c58044c | j_mayer | int bfa;
|
2225 | 7c58044c | j_mayer | |
2226 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2227 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2228 | 3cc62370 | bellard | return;
|
2229 | 3cc62370 | bellard | } |
2230 | 7c58044c | j_mayer | bfa = 4 * (7 - crfS(ctx->opcode)); |
2231 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2232 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
|
2233 | af12906f | aurel32 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
|
2234 | 79aceca5 | bellard | } |
2235 | 79aceca5 | bellard | |
2236 | 79aceca5 | bellard | /* mffs */
|
2237 | 99e300ef | Blue Swirl | static void gen_mffs(DisasContext *ctx) |
2238 | 79aceca5 | bellard | { |
2239 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2240 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2241 | 3cc62370 | bellard | return;
|
2242 | 3cc62370 | bellard | } |
2243 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2244 | af12906f | aurel32 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2245 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2246 | 79aceca5 | bellard | } |
2247 | 79aceca5 | bellard | |
2248 | 79aceca5 | bellard | /* mtfsb0 */
|
2249 | 99e300ef | Blue Swirl | static void gen_mtfsb0(DisasContext *ctx) |
2250 | 79aceca5 | bellard | { |
2251 | fb0eaffc | bellard | uint8_t crb; |
2252 | 3b46e624 | ths | |
2253 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2254 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2255 | 3cc62370 | bellard | return;
|
2256 | 3cc62370 | bellard | } |
2257 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2258 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2259 | 6e35d524 | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
|
2260 | eb44b959 | aurel32 | TCGv_i32 t0; |
2261 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2262 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2263 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2264 | 6e35d524 | aurel32 | gen_helper_fpscr_clrbit(t0); |
2265 | 6e35d524 | aurel32 | tcg_temp_free_i32(t0); |
2266 | 6e35d524 | aurel32 | } |
2267 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2268 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2269 | 7c58044c | j_mayer | } |
2270 | 79aceca5 | bellard | } |
2271 | 79aceca5 | bellard | |
2272 | 79aceca5 | bellard | /* mtfsb1 */
|
2273 | 99e300ef | Blue Swirl | static void gen_mtfsb1(DisasContext *ctx) |
2274 | 79aceca5 | bellard | { |
2275 | fb0eaffc | bellard | uint8_t crb; |
2276 | 3b46e624 | ths | |
2277 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2278 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2279 | 3cc62370 | bellard | return;
|
2280 | 3cc62370 | bellard | } |
2281 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2282 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2283 | 7c58044c | j_mayer | /* XXX: we pretend we can only do IEEE floating-point computations */
|
2284 | af12906f | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
|
2285 | eb44b959 | aurel32 | TCGv_i32 t0; |
2286 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2287 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2288 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2289 | af12906f | aurel32 | gen_helper_fpscr_setbit(t0); |
2290 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2291 | af12906f | aurel32 | } |
2292 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2293 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2294 | 7c58044c | j_mayer | } |
2295 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2296 | af12906f | aurel32 | gen_helper_float_check_status(); |
2297 | 79aceca5 | bellard | } |
2298 | 79aceca5 | bellard | |
2299 | 79aceca5 | bellard | /* mtfsf */
|
2300 | 99e300ef | Blue Swirl | static void gen_mtfsf(DisasContext *ctx) |
2301 | 79aceca5 | bellard | { |
2302 | 0f2f39c2 | aurel32 | TCGv_i32 t0; |
2303 | 4911012d | blueswir1 | int L = ctx->opcode & 0x02000000; |
2304 | af12906f | aurel32 | |
2305 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2306 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2307 | 3cc62370 | bellard | return;
|
2308 | 3cc62370 | bellard | } |
2309 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2310 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2311 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2312 | 4911012d | blueswir1 | if (L)
|
2313 | 4911012d | blueswir1 | t0 = tcg_const_i32(0xff);
|
2314 | 4911012d | blueswir1 | else
|
2315 | 4911012d | blueswir1 | t0 = tcg_const_i32(FM(ctx->opcode)); |
2316 | af12906f | aurel32 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
2317 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2318 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2319 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2320 | 7c58044c | j_mayer | } |
2321 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2322 | af12906f | aurel32 | gen_helper_float_check_status(); |
2323 | 79aceca5 | bellard | } |
2324 | 79aceca5 | bellard | |
2325 | 79aceca5 | bellard | /* mtfsfi */
|
2326 | 99e300ef | Blue Swirl | static void gen_mtfsfi(DisasContext *ctx) |
2327 | 79aceca5 | bellard | { |
2328 | 7c58044c | j_mayer | int bf, sh;
|
2329 | 0f2f39c2 | aurel32 | TCGv_i64 t0; |
2330 | 0f2f39c2 | aurel32 | TCGv_i32 t1; |
2331 | 7c58044c | j_mayer | |
2332 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2333 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2334 | 3cc62370 | bellard | return;
|
2335 | 3cc62370 | bellard | } |
2336 | 7c58044c | j_mayer | bf = crbD(ctx->opcode) >> 2;
|
2337 | 7c58044c | j_mayer | sh = 7 - bf;
|
2338 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2339 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2340 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2341 | 0f2f39c2 | aurel32 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
|
2342 | af12906f | aurel32 | t1 = tcg_const_i32(1 << sh);
|
2343 | af12906f | aurel32 | gen_helper_store_fpscr(t0, t1); |
2344 | 0f2f39c2 | aurel32 | tcg_temp_free_i64(t0); |
2345 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t1); |
2346 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2347 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2348 | 7c58044c | j_mayer | } |
2349 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2350 | af12906f | aurel32 | gen_helper_float_check_status(); |
2351 | 79aceca5 | bellard | } |
2352 | 79aceca5 | bellard | |
2353 | 76a66253 | j_mayer | /*** Addressing modes ***/
|
2354 | 76a66253 | j_mayer | /* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2355 | 636aa200 | Blue Swirl | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2356 | 636aa200 | Blue Swirl | target_long maskl) |
2357 | 76a66253 | j_mayer | { |
2358 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
2359 | 76a66253 | j_mayer | |
2360 | be147d08 | j_mayer | simm &= ~maskl; |
2361 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2362 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2363 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2364 | 76db3ba4 | aurel32 | tcg_gen_movi_tl(EA, (uint32_t)simm); |
2365 | 76db3ba4 | aurel32 | } else
|
2366 | 76db3ba4 | aurel32 | #endif
|
2367 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, simm); |
2368 | 76db3ba4 | aurel32 | } else if (likely(simm != 0)) { |
2369 | e2be8d8d | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
2370 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2371 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2372 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2373 | 76db3ba4 | aurel32 | } |
2374 | 76db3ba4 | aurel32 | #endif
|
2375 | 76db3ba4 | aurel32 | } else {
|
2376 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2377 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2378 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2379 | 76db3ba4 | aurel32 | } else
|
2380 | 76db3ba4 | aurel32 | #endif
|
2381 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2382 | 76db3ba4 | aurel32 | } |
2383 | 76a66253 | j_mayer | } |
2384 | 76a66253 | j_mayer | |
2385 | 636aa200 | Blue Swirl | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
2386 | 76a66253 | j_mayer | { |
2387 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2388 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2389 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2390 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2391 | 76db3ba4 | aurel32 | } else
|
2392 | 76db3ba4 | aurel32 | #endif
|
2393 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2394 | 76db3ba4 | aurel32 | } else {
|
2395 | e2be8d8d | aurel32 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2396 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2397 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2398 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2399 | 76db3ba4 | aurel32 | } |
2400 | 76db3ba4 | aurel32 | #endif
|
2401 | 76db3ba4 | aurel32 | } |
2402 | 76a66253 | j_mayer | } |
2403 | 76a66253 | j_mayer | |
2404 | 636aa200 | Blue Swirl | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
2405 | 76a66253 | j_mayer | { |
2406 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2407 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, 0);
|
2408 | 76db3ba4 | aurel32 | } else {
|
2409 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2410 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2411 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2412 | 76db3ba4 | aurel32 | } else
|
2413 | 76db3ba4 | aurel32 | #endif
|
2414 | 76db3ba4 | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2415 | 76db3ba4 | aurel32 | } |
2416 | 76db3ba4 | aurel32 | } |
2417 | 76db3ba4 | aurel32 | |
2418 | 636aa200 | Blue Swirl | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2419 | 636aa200 | Blue Swirl | target_long val) |
2420 | 76db3ba4 | aurel32 | { |
2421 | 76db3ba4 | aurel32 | tcg_gen_addi_tl(ret, arg1, val); |
2422 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2423 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2424 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(ret, ret); |
2425 | 76db3ba4 | aurel32 | } |
2426 | 76db3ba4 | aurel32 | #endif
|
2427 | 76a66253 | j_mayer | } |
2428 | 76a66253 | j_mayer | |
2429 | 636aa200 | Blue Swirl | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
2430 | cf360a32 | aurel32 | { |
2431 | cf360a32 | aurel32 | int l1 = gen_new_label();
|
2432 | cf360a32 | aurel32 | TCGv t0 = tcg_temp_new(); |
2433 | cf360a32 | aurel32 | TCGv_i32 t1, t2; |
2434 | cf360a32 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2435 | cf360a32 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2436 | cf360a32 | aurel32 | tcg_gen_andi_tl(t0, EA, mask); |
2437 | cf360a32 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
2438 | cf360a32 | aurel32 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); |
2439 | cf360a32 | aurel32 | t2 = tcg_const_i32(0);
|
2440 | cf360a32 | aurel32 | gen_helper_raise_exception_err(t1, t2); |
2441 | cf360a32 | aurel32 | tcg_temp_free_i32(t1); |
2442 | cf360a32 | aurel32 | tcg_temp_free_i32(t2); |
2443 | cf360a32 | aurel32 | gen_set_label(l1); |
2444 | cf360a32 | aurel32 | tcg_temp_free(t0); |
2445 | cf360a32 | aurel32 | } |
2446 | cf360a32 | aurel32 | |
2447 | 7863667f | j_mayer | /*** Integer load ***/
|
2448 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2449 | 76db3ba4 | aurel32 | { |
2450 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
2451 | 76db3ba4 | aurel32 | } |
2452 | 76db3ba4 | aurel32 | |
2453 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2454 | 76db3ba4 | aurel32 | { |
2455 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
2456 | 76db3ba4 | aurel32 | } |
2457 | 76db3ba4 | aurel32 | |
2458 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2459 | 76db3ba4 | aurel32 | { |
2460 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2461 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2462 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2463 | 76db3ba4 | aurel32 | } |
2464 | b61f2753 | aurel32 | } |
2465 | b61f2753 | aurel32 | |
2466 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2467 | b61f2753 | aurel32 | { |
2468 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2469 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2470 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2471 | 76db3ba4 | aurel32 | tcg_gen_ext16s_tl(arg1, arg1); |
2472 | 76db3ba4 | aurel32 | } else {
|
2473 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); |
2474 | 76db3ba4 | aurel32 | } |
2475 | b61f2753 | aurel32 | } |
2476 | b61f2753 | aurel32 | |
2477 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2478 | b61f2753 | aurel32 | { |
2479 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2480 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2481 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2482 | 76db3ba4 | aurel32 | } |
2483 | b61f2753 | aurel32 | } |
2484 | b61f2753 | aurel32 | |
2485 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2486 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2487 | b61f2753 | aurel32 | { |
2488 | a457e7ee | blueswir1 | if (unlikely(ctx->le_mode)) {
|
2489 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2490 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2491 | fa3966a3 | aurel32 | tcg_gen_ext32s_tl(arg1, arg1); |
2492 | b61f2753 | aurel32 | } else
|
2493 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
2494 | b61f2753 | aurel32 | } |
2495 | 76db3ba4 | aurel32 | #endif
|
2496 | b61f2753 | aurel32 | |
2497 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2498 | b61f2753 | aurel32 | { |
2499 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2500 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2501 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(arg1, arg1); |
2502 | 76db3ba4 | aurel32 | } |
2503 | b61f2753 | aurel32 | } |
2504 | b61f2753 | aurel32 | |
2505 | 636aa200 | Blue Swirl | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2506 | b61f2753 | aurel32 | { |
2507 | 76db3ba4 | aurel32 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
2508 | b61f2753 | aurel32 | } |
2509 | b61f2753 | aurel32 | |
2510 | 636aa200 | Blue Swirl | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2511 | b61f2753 | aurel32 | { |
2512 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2513 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2514 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2515 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2516 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2517 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2518 | 76db3ba4 | aurel32 | } else {
|
2519 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2520 | 76db3ba4 | aurel32 | } |
2521 | b61f2753 | aurel32 | } |
2522 | b61f2753 | aurel32 | |
2523 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2524 | b61f2753 | aurel32 | { |
2525 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2526 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2527 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2528 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2529 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2530 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2531 | 76db3ba4 | aurel32 | } else {
|
2532 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2533 | 76db3ba4 | aurel32 | } |
2534 | b61f2753 | aurel32 | } |
2535 | b61f2753 | aurel32 | |
2536 | 636aa200 | Blue Swirl | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2537 | b61f2753 | aurel32 | { |
2538 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2539 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_temp_new_i64(); |
2540 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(t0, arg1); |
2541 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
2542 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
2543 | b61f2753 | aurel32 | } else
|
2544 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
2545 | b61f2753 | aurel32 | } |
2546 | b61f2753 | aurel32 | |
2547 | 0c8aacd4 | aurel32 | #define GEN_LD(name, ldop, opc, type) \
|
2548 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2549 | 79aceca5 | bellard | { \ |
2550 | 76db3ba4 | aurel32 | TCGv EA; \ |
2551 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2552 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2553 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2554 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2555 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2556 | 79aceca5 | bellard | } |
2557 | 79aceca5 | bellard | |
2558 | 0c8aacd4 | aurel32 | #define GEN_LDU(name, ldop, opc, type) \
|
2559 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
2560 | 79aceca5 | bellard | { \ |
2561 | b61f2753 | aurel32 | TCGv EA; \ |
2562 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2563 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2564 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2565 | 9fddaa0c | bellard | return; \
|
2566 | 9a64fbe4 | bellard | } \ |
2567 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2568 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2569 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2570 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2571 | 9d53c753 | j_mayer | else \
|
2572 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2573 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2574 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2575 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2576 | 79aceca5 | bellard | } |
2577 | 79aceca5 | bellard | |
2578 | 0c8aacd4 | aurel32 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
2579 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2580 | 79aceca5 | bellard | { \ |
2581 | b61f2753 | aurel32 | TCGv EA; \ |
2582 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2583 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2584 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2585 | 9fddaa0c | bellard | return; \
|
2586 | 9a64fbe4 | bellard | } \ |
2587 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2588 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2589 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2590 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2591 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2592 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2593 | 79aceca5 | bellard | } |
2594 | 79aceca5 | bellard | |
2595 | 0c8aacd4 | aurel32 | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
2596 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2597 | 79aceca5 | bellard | { \ |
2598 | 76db3ba4 | aurel32 | TCGv EA; \ |
2599 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2600 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2601 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2602 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2603 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2604 | 79aceca5 | bellard | } |
2605 | 79aceca5 | bellard | |
2606 | 0c8aacd4 | aurel32 | #define GEN_LDS(name, ldop, op, type) \
|
2607 | 0c8aacd4 | aurel32 | GEN_LD(name, ldop, op | 0x20, type); \
|
2608 | 0c8aacd4 | aurel32 | GEN_LDU(name, ldop, op | 0x21, type); \
|
2609 | 0c8aacd4 | aurel32 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
2610 | 0c8aacd4 | aurel32 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
2611 | 79aceca5 | bellard | |
2612 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
2613 | 0c8aacd4 | aurel32 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
|
2614 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
2615 | 0c8aacd4 | aurel32 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
|
2616 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
2617 | 0c8aacd4 | aurel32 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
|
2618 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
2619 | 0c8aacd4 | aurel32 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
|
2620 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2621 | d9bce9d9 | j_mayer | /* lwaux */
|
2622 | 0c8aacd4 | aurel32 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
2623 | d9bce9d9 | j_mayer | /* lwax */
|
2624 | 0c8aacd4 | aurel32 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
2625 | d9bce9d9 | j_mayer | /* ldux */
|
2626 | 0c8aacd4 | aurel32 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
2627 | d9bce9d9 | j_mayer | /* ldx */
|
2628 | 0c8aacd4 | aurel32 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
2629 | 99e300ef | Blue Swirl | |
2630 | 99e300ef | Blue Swirl | static void gen_ld(DisasContext *ctx) |
2631 | d9bce9d9 | j_mayer | { |
2632 | b61f2753 | aurel32 | TCGv EA; |
2633 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode)) {
|
2634 | d9bce9d9 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || |
2635 | d9bce9d9 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { |
2636 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2637 | d9bce9d9 | j_mayer | return;
|
2638 | d9bce9d9 | j_mayer | } |
2639 | d9bce9d9 | j_mayer | } |
2640 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2641 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2642 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2643 | d9bce9d9 | j_mayer | if (ctx->opcode & 0x02) { |
2644 | d9bce9d9 | j_mayer | /* lwa (lwau is undefined) */
|
2645 | 76db3ba4 | aurel32 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2646 | d9bce9d9 | j_mayer | } else {
|
2647 | d9bce9d9 | j_mayer | /* ld - ldu */
|
2648 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2649 | d9bce9d9 | j_mayer | } |
2650 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode))
|
2651 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2652 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2653 | d9bce9d9 | j_mayer | } |
2654 | 99e300ef | Blue Swirl | |
2655 | 54623277 | Blue Swirl | /* lq */
|
2656 | 99e300ef | Blue Swirl | static void gen_lq(DisasContext *ctx) |
2657 | be147d08 | j_mayer | { |
2658 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2659 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2660 | be147d08 | j_mayer | #else
|
2661 | be147d08 | j_mayer | int ra, rd;
|
2662 | b61f2753 | aurel32 | TCGv EA; |
2663 | be147d08 | j_mayer | |
2664 | be147d08 | j_mayer | /* Restore CPU state */
|
2665 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2666 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2667 | be147d08 | j_mayer | return;
|
2668 | be147d08 | j_mayer | } |
2669 | be147d08 | j_mayer | ra = rA(ctx->opcode); |
2670 | be147d08 | j_mayer | rd = rD(ctx->opcode); |
2671 | be147d08 | j_mayer | if (unlikely((rd & 1) || rd == ra)) { |
2672 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2673 | be147d08 | j_mayer | return;
|
2674 | be147d08 | j_mayer | } |
2675 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2676 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2677 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2678 | be147d08 | j_mayer | return;
|
2679 | be147d08 | j_mayer | } |
2680 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2681 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2682 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x0F);
|
2683 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); |
2684 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2685 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
|
2686 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2687 | be147d08 | j_mayer | #endif
|
2688 | be147d08 | j_mayer | } |
2689 | d9bce9d9 | j_mayer | #endif
|
2690 | 79aceca5 | bellard | |
2691 | 79aceca5 | bellard | /*** Integer store ***/
|
2692 | 0c8aacd4 | aurel32 | #define GEN_ST(name, stop, opc, type) \
|
2693 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2694 | 79aceca5 | bellard | { \ |
2695 | 76db3ba4 | aurel32 | TCGv EA; \ |
2696 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2697 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2698 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2699 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2700 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2701 | 79aceca5 | bellard | } |
2702 | 79aceca5 | bellard | |
2703 | 0c8aacd4 | aurel32 | #define GEN_STU(name, stop, opc, type) \
|
2704 | 99e300ef | Blue Swirl | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
2705 | 79aceca5 | bellard | { \ |
2706 | b61f2753 | aurel32 | TCGv EA; \ |
2707 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2708 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2709 | 9fddaa0c | bellard | return; \
|
2710 | 9a64fbe4 | bellard | } \ |
2711 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2712 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2713 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2714 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2715 | 9d53c753 | j_mayer | else \
|
2716 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2717 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2718 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2719 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2720 | 79aceca5 | bellard | } |
2721 | 79aceca5 | bellard | |
2722 | 0c8aacd4 | aurel32 | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
2723 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2724 | 79aceca5 | bellard | { \ |
2725 | b61f2753 | aurel32 | TCGv EA; \ |
2726 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2727 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2728 | 9fddaa0c | bellard | return; \
|
2729 | 9a64fbe4 | bellard | } \ |
2730 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2731 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2732 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2733 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2734 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2735 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2736 | 79aceca5 | bellard | } |
2737 | 79aceca5 | bellard | |
2738 | 0c8aacd4 | aurel32 | #define GEN_STX(name, stop, opc2, opc3, type) \
|
2739 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2740 | 79aceca5 | bellard | { \ |
2741 | 76db3ba4 | aurel32 | TCGv EA; \ |
2742 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2743 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2744 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2745 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2746 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2747 | 79aceca5 | bellard | } |
2748 | 79aceca5 | bellard | |
2749 | 0c8aacd4 | aurel32 | #define GEN_STS(name, stop, op, type) \
|
2750 | 0c8aacd4 | aurel32 | GEN_ST(name, stop, op | 0x20, type); \
|
2751 | 0c8aacd4 | aurel32 | GEN_STU(name, stop, op | 0x21, type); \
|
2752 | 0c8aacd4 | aurel32 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
2753 | 0c8aacd4 | aurel32 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
2754 | 79aceca5 | bellard | |
2755 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
2756 | 0c8aacd4 | aurel32 | GEN_STS(stb, st8, 0x06, PPC_INTEGER);
|
2757 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
2758 | 0c8aacd4 | aurel32 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
|
2759 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
2760 | 0c8aacd4 | aurel32 | GEN_STS(stw, st32, 0x04, PPC_INTEGER);
|
2761 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2762 | 0c8aacd4 | aurel32 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2763 | 0c8aacd4 | aurel32 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); |
2764 | 99e300ef | Blue Swirl | |
2765 | 99e300ef | Blue Swirl | static void gen_std(DisasContext *ctx) |
2766 | d9bce9d9 | j_mayer | { |
2767 | be147d08 | j_mayer | int rs;
|
2768 | b61f2753 | aurel32 | TCGv EA; |
2769 | be147d08 | j_mayer | |
2770 | be147d08 | j_mayer | rs = rS(ctx->opcode); |
2771 | be147d08 | j_mayer | if ((ctx->opcode & 0x3) == 0x2) { |
2772 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2773 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2774 | be147d08 | j_mayer | #else
|
2775 | be147d08 | j_mayer | /* stq */
|
2776 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2777 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2778 | be147d08 | j_mayer | return;
|
2779 | be147d08 | j_mayer | } |
2780 | be147d08 | j_mayer | if (unlikely(rs & 1)) { |
2781 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2782 | d9bce9d9 | j_mayer | return;
|
2783 | d9bce9d9 | j_mayer | } |
2784 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2785 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2786 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2787 | be147d08 | j_mayer | return;
|
2788 | be147d08 | j_mayer | } |
2789 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2790 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2791 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2792 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2793 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2794 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
|
2795 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2796 | be147d08 | j_mayer | #endif
|
2797 | be147d08 | j_mayer | } else {
|
2798 | be147d08 | j_mayer | /* std / stdu */
|
2799 | be147d08 | j_mayer | if (Rc(ctx->opcode)) {
|
2800 | be147d08 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { |
2801 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2802 | be147d08 | j_mayer | return;
|
2803 | be147d08 | j_mayer | } |
2804 | be147d08 | j_mayer | } |
2805 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2806 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2807 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2808 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2809 | be147d08 | j_mayer | if (Rc(ctx->opcode))
|
2810 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2811 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2812 | d9bce9d9 | j_mayer | } |
2813 | d9bce9d9 | j_mayer | } |
2814 | d9bce9d9 | j_mayer | #endif
|
2815 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
2816 | 79aceca5 | bellard | /* lhbrx */
|
2817 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2818 | b61f2753 | aurel32 | { |
2819 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2820 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2821 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2822 | 76db3ba4 | aurel32 | } |
2823 | b61f2753 | aurel32 | } |
2824 | 0c8aacd4 | aurel32 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
2825 | b61f2753 | aurel32 | |
2826 | 79aceca5 | bellard | /* lwbrx */
|
2827 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2828 | b61f2753 | aurel32 | { |
2829 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2830 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2831 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2832 | 76db3ba4 | aurel32 | } |
2833 | b61f2753 | aurel32 | } |
2834 | 0c8aacd4 | aurel32 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
2835 | b61f2753 | aurel32 | |
2836 | 79aceca5 | bellard | /* sthbrx */
|
2837 | 86178a57 | Juan Quintela | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2838 | b61f2753 | aurel32 | { |
2839 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2840 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2841 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2842 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2843 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2844 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2845 | 76db3ba4 | aurel32 | } else {
|
2846 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2847 | 76db3ba4 | aurel32 | } |
2848 | b61f2753 | aurel32 | } |
2849 | 0c8aacd4 | aurel32 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
2850 | b61f2753 | aurel32 | |
2851 | 79aceca5 | bellard | /* stwbrx */
|
2852 | 86178a57 | Juan Quintela | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2853 | b61f2753 | aurel32 | { |
2854 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2855 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2856 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2857 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2858 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2859 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2860 | 76db3ba4 | aurel32 | } else {
|
2861 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2862 | 76db3ba4 | aurel32 | } |
2863 | b61f2753 | aurel32 | } |
2864 | 0c8aacd4 | aurel32 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
2865 | 79aceca5 | bellard | |
2866 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
2867 | 99e300ef | Blue Swirl | |
2868 | 54623277 | Blue Swirl | /* lmw */
|
2869 | 99e300ef | Blue Swirl | static void gen_lmw(DisasContext *ctx) |
2870 | 79aceca5 | bellard | { |
2871 | 76db3ba4 | aurel32 | TCGv t0; |
2872 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2873 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2874 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2875 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2876 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2877 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2878 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2879 | ff4a62cd | aurel32 | gen_helper_lmw(t0, t1); |
2880 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2881 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2882 | 79aceca5 | bellard | } |
2883 | 79aceca5 | bellard | |
2884 | 79aceca5 | bellard | /* stmw */
|
2885 | 99e300ef | Blue Swirl | static void gen_stmw(DisasContext *ctx) |
2886 | 79aceca5 | bellard | { |
2887 | 76db3ba4 | aurel32 | TCGv t0; |
2888 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2889 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2890 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2891 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2892 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2893 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rS(ctx->opcode)); |
2894 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2895 | ff4a62cd | aurel32 | gen_helper_stmw(t0, t1); |
2896 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2897 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2898 | 79aceca5 | bellard | } |
2899 | 79aceca5 | bellard | |
2900 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
2901 | 54623277 | Blue Swirl | |
2902 | 79aceca5 | bellard | /* lswi */
|
2903 | 3fc6c082 | bellard | /* PowerPC32 specification says we must generate an exception if
|
2904 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
2905 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
2906 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
2907 | 9a64fbe4 | bellard | */
|
2908 | 99e300ef | Blue Swirl | static void gen_lswi(DisasContext *ctx) |
2909 | 79aceca5 | bellard | { |
2910 | dfbc799d | aurel32 | TCGv t0; |
2911 | dfbc799d | aurel32 | TCGv_i32 t1, t2; |
2912 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
2913 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
2914 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
2915 | 79aceca5 | bellard | int nr;
|
2916 | 79aceca5 | bellard | |
2917 | 79aceca5 | bellard | if (nb == 0) |
2918 | 79aceca5 | bellard | nb = 32;
|
2919 | 79aceca5 | bellard | nr = nb / 4;
|
2920 | 76a66253 | j_mayer | if (unlikely(((start + nr) > 32 && |
2921 | 76a66253 | j_mayer | start <= ra && (start + nr - 32) > ra) ||
|
2922 | 76a66253 | j_mayer | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
2923 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
2924 | 9fddaa0c | bellard | return;
|
2925 | 297d8e62 | bellard | } |
2926 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2927 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2928 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2929 | dfbc799d | aurel32 | t0 = tcg_temp_new(); |
2930 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2931 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2932 | dfbc799d | aurel32 | t2 = tcg_const_i32(start); |
2933 | dfbc799d | aurel32 | gen_helper_lsw(t0, t1, t2); |
2934 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2935 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2936 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2937 | 79aceca5 | bellard | } |
2938 | 79aceca5 | bellard | |
2939 | 79aceca5 | bellard | /* lswx */
|
2940 | 99e300ef | Blue Swirl | static void gen_lswx(DisasContext *ctx) |
2941 | 79aceca5 | bellard | { |
2942 | 76db3ba4 | aurel32 | TCGv t0; |
2943 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2, t3; |
2944 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2945 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2946 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2947 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2948 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
2949 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2950 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rA(ctx->opcode)); |
2951 | 76db3ba4 | aurel32 | t3 = tcg_const_i32(rB(ctx->opcode)); |
2952 | dfbc799d | aurel32 | gen_helper_lswx(t0, t1, t2, t3); |
2953 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2954 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2955 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2956 | dfbc799d | aurel32 | tcg_temp_free_i32(t3); |
2957 | 79aceca5 | bellard | } |
2958 | 79aceca5 | bellard | |
2959 | 79aceca5 | bellard | /* stswi */
|
2960 | 99e300ef | Blue Swirl | static void gen_stswi(DisasContext *ctx) |
2961 | 79aceca5 | bellard | { |
2962 | 76db3ba4 | aurel32 | TCGv t0; |
2963 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
2964 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
2965 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2966 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2967 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2968 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2969 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2970 | 4b3686fa | bellard | if (nb == 0) |
2971 | 4b3686fa | bellard | nb = 32;
|
2972 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2973 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2974 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
2975 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2976 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2977 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2978 | 79aceca5 | bellard | } |
2979 | 79aceca5 | bellard | |
2980 | 79aceca5 | bellard | /* stswx */
|
2981 | 99e300ef | Blue Swirl | static void gen_stswx(DisasContext *ctx) |
2982 | 79aceca5 | bellard | { |
2983 | 76db3ba4 | aurel32 | TCGv t0; |
2984 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
2985 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2986 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2987 | 5fafdf24 | ths | gen_update_nip(ctx, ctx->nip - 4);
|
2988 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2989 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
2990 | 76db3ba4 | aurel32 | t1 = tcg_temp_new_i32(); |
2991 | dfbc799d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
2992 | dfbc799d | aurel32 | tcg_gen_andi_i32(t1, t1, 0x7F);
|
2993 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2994 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
2995 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2996 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2997 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2998 | 79aceca5 | bellard | } |
2999 | 79aceca5 | bellard | |
3000 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
3001 | 79aceca5 | bellard | /* eieio */
|
3002 | 99e300ef | Blue Swirl | static void gen_eieio(DisasContext *ctx) |
3003 | 79aceca5 | bellard | { |
3004 | 79aceca5 | bellard | } |
3005 | 79aceca5 | bellard | |
3006 | 79aceca5 | bellard | /* isync */
|
3007 | 99e300ef | Blue Swirl | static void gen_isync(DisasContext *ctx) |
3008 | 79aceca5 | bellard | { |
3009 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3010 | 79aceca5 | bellard | } |
3011 | 79aceca5 | bellard | |
3012 | 111bfab3 | bellard | /* lwarx */
|
3013 | 99e300ef | Blue Swirl | static void gen_lwarx(DisasContext *ctx) |
3014 | 79aceca5 | bellard | { |
3015 | 76db3ba4 | aurel32 | TCGv t0; |
3016 | 18b21a2f | Nathan Froyd | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
3017 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3018 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3019 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3020 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3021 | 18b21a2f | Nathan Froyd | gen_qemu_ld32u(ctx, gpr, t0); |
3022 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3023 | 18b21a2f | Nathan Froyd | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
3024 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3025 | 79aceca5 | bellard | } |
3026 | 79aceca5 | bellard | |
3027 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3028 | 4425265b | Nathan Froyd | static void gen_conditional_store (DisasContext *ctx, TCGv EA, |
3029 | 4425265b | Nathan Froyd | int reg, int size) |
3030 | 4425265b | Nathan Froyd | { |
3031 | 4425265b | Nathan Froyd | TCGv t0 = tcg_temp_new(); |
3032 | 4425265b | Nathan Froyd | uint32_t save_exception = ctx->exception; |
3033 | 4425265b | Nathan Froyd | |
3034 | 4425265b | Nathan Froyd | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea)); |
3035 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(t0, (size << 5) | reg);
|
3036 | 4425265b | Nathan Froyd | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info)); |
3037 | 4425265b | Nathan Froyd | tcg_temp_free(t0); |
3038 | 4425265b | Nathan Froyd | gen_update_nip(ctx, ctx->nip-4);
|
3039 | 4425265b | Nathan Froyd | ctx->exception = POWERPC_EXCP_BRANCH; |
3040 | 4425265b | Nathan Froyd | gen_exception(ctx, POWERPC_EXCP_STCX); |
3041 | 4425265b | Nathan Froyd | ctx->exception = save_exception; |
3042 | 4425265b | Nathan Froyd | } |
3043 | 4425265b | Nathan Froyd | #endif
|
3044 | 4425265b | Nathan Froyd | |
3045 | 79aceca5 | bellard | /* stwcx. */
|
3046 | e8eaa2c0 | Blue Swirl | static void gen_stwcx_(DisasContext *ctx) |
3047 | 79aceca5 | bellard | { |
3048 | 76db3ba4 | aurel32 | TCGv t0; |
3049 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3050 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3051 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3052 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3053 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3054 | 4425265b | Nathan Froyd | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
|
3055 | 4425265b | Nathan Froyd | #else
|
3056 | 4425265b | Nathan Froyd | { |
3057 | 4425265b | Nathan Froyd | int l1;
|
3058 | 4425265b | Nathan Froyd | |
3059 | 4425265b | Nathan Froyd | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3060 | 4425265b | Nathan Froyd | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3061 | 4425265b | Nathan Froyd | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3062 | 4425265b | Nathan Froyd | l1 = gen_new_label(); |
3063 | 4425265b | Nathan Froyd | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3064 | 4425265b | Nathan Froyd | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3065 | 4425265b | Nathan Froyd | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3066 | 4425265b | Nathan Froyd | gen_set_label(l1); |
3067 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(cpu_reserve, -1);
|
3068 | 4425265b | Nathan Froyd | } |
3069 | 4425265b | Nathan Froyd | #endif
|
3070 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3071 | 79aceca5 | bellard | } |
3072 | 79aceca5 | bellard | |
3073 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3074 | 426613db | j_mayer | /* ldarx */
|
3075 | 99e300ef | Blue Swirl | static void gen_ldarx(DisasContext *ctx) |
3076 | 426613db | j_mayer | { |
3077 | 76db3ba4 | aurel32 | TCGv t0; |
3078 | 18b21a2f | Nathan Froyd | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
3079 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3080 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3081 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3082 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3083 | 18b21a2f | Nathan Froyd | gen_qemu_ld64(ctx, gpr, t0); |
3084 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3085 | 18b21a2f | Nathan Froyd | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
3086 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3087 | 426613db | j_mayer | } |
3088 | 426613db | j_mayer | |
3089 | 426613db | j_mayer | /* stdcx. */
|
3090 | e8eaa2c0 | Blue Swirl | static void gen_stdcx_(DisasContext *ctx) |
3091 | 426613db | j_mayer | { |
3092 | 76db3ba4 | aurel32 | TCGv t0; |
3093 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3094 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3095 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3096 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3097 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3098 | 4425265b | Nathan Froyd | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
|
3099 | 4425265b | Nathan Froyd | #else
|
3100 | 4425265b | Nathan Froyd | { |
3101 | 4425265b | Nathan Froyd | int l1;
|
3102 | 4425265b | Nathan Froyd | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3103 | 4425265b | Nathan Froyd | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3104 | 4425265b | Nathan Froyd | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3105 | 4425265b | Nathan Froyd | l1 = gen_new_label(); |
3106 | 4425265b | Nathan Froyd | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3107 | 4425265b | Nathan Froyd | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3108 | 4425265b | Nathan Froyd | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3109 | 4425265b | Nathan Froyd | gen_set_label(l1); |
3110 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(cpu_reserve, -1);
|
3111 | 4425265b | Nathan Froyd | } |
3112 | 4425265b | Nathan Froyd | #endif
|
3113 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3114 | 426613db | j_mayer | } |
3115 | 426613db | j_mayer | #endif /* defined(TARGET_PPC64) */ |
3116 | 426613db | j_mayer | |
3117 | 79aceca5 | bellard | /* sync */
|
3118 | 99e300ef | Blue Swirl | static void gen_sync(DisasContext *ctx) |
3119 | 79aceca5 | bellard | { |
3120 | 79aceca5 | bellard | } |
3121 | 79aceca5 | bellard | |
3122 | 0db1b20e | j_mayer | /* wait */
|
3123 | 99e300ef | Blue Swirl | static void gen_wait(DisasContext *ctx) |
3124 | 0db1b20e | j_mayer | { |
3125 | 931ff272 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3126 | 931ff272 | aurel32 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); |
3127 | 931ff272 | aurel32 | tcg_temp_free_i32(t0); |
3128 | 0db1b20e | j_mayer | /* Stop translation, as the CPU is supposed to sleep from now */
|
3129 | e06fcd75 | aurel32 | gen_exception_err(ctx, EXCP_HLT, 1);
|
3130 | 0db1b20e | j_mayer | } |
3131 | 0db1b20e | j_mayer | |
3132 | 79aceca5 | bellard | /*** Floating-point load ***/
|
3133 | a0d7d5a7 | aurel32 | #define GEN_LDF(name, ldop, opc, type) \
|
3134 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3135 | 79aceca5 | bellard | { \ |
3136 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3137 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3138 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3139 | 4ecc3190 | bellard | return; \
|
3140 | 4ecc3190 | bellard | } \ |
3141 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3142 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3143 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3144 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3145 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3146 | 79aceca5 | bellard | } |
3147 | 79aceca5 | bellard | |
3148 | a0d7d5a7 | aurel32 | #define GEN_LDUF(name, ldop, opc, type) \
|
3149 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3150 | 79aceca5 | bellard | { \ |
3151 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3152 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3153 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3154 | 4ecc3190 | bellard | return; \
|
3155 | 4ecc3190 | bellard | } \ |
3156 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3157 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3158 | 9fddaa0c | bellard | return; \
|
3159 | 9a64fbe4 | bellard | } \ |
3160 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3161 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3162 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3163 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3164 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3165 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3166 | 79aceca5 | bellard | } |
3167 | 79aceca5 | bellard | |
3168 | a0d7d5a7 | aurel32 | #define GEN_LDUXF(name, ldop, opc, type) \
|
3169 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3170 | 79aceca5 | bellard | { \ |
3171 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3172 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3173 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3174 | 4ecc3190 | bellard | return; \
|
3175 | 4ecc3190 | bellard | } \ |
3176 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3177 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3178 | 9fddaa0c | bellard | return; \
|
3179 | 9a64fbe4 | bellard | } \ |
3180 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3181 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3182 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3183 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3184 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3185 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3186 | 79aceca5 | bellard | } |
3187 | 79aceca5 | bellard | |
3188 | a0d7d5a7 | aurel32 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
3189 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3190 | 79aceca5 | bellard | { \ |
3191 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3192 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3193 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3194 | 4ecc3190 | bellard | return; \
|
3195 | 4ecc3190 | bellard | } \ |
3196 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3197 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3198 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3199 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3200 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3201 | 79aceca5 | bellard | } |
3202 | 79aceca5 | bellard | |
3203 | a0d7d5a7 | aurel32 | #define GEN_LDFS(name, ldop, op, type) \
|
3204 | a0d7d5a7 | aurel32 | GEN_LDF(name, ldop, op | 0x20, type); \
|
3205 | a0d7d5a7 | aurel32 | GEN_LDUF(name, ldop, op | 0x21, type); \
|
3206 | a0d7d5a7 | aurel32 | GEN_LDUXF(name, ldop, op | 0x01, type); \
|
3207 | a0d7d5a7 | aurel32 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
3208 | a0d7d5a7 | aurel32 | |
3209 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3210 | a0d7d5a7 | aurel32 | { |
3211 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3212 | a0d7d5a7 | aurel32 | TCGv_i32 t1 = tcg_temp_new_i32(); |
3213 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, arg2); |
3214 | a0d7d5a7 | aurel32 | tcg_gen_trunc_tl_i32(t1, t0); |
3215 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3216 | a0d7d5a7 | aurel32 | gen_helper_float32_to_float64(arg1, t1); |
3217 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t1); |
3218 | a0d7d5a7 | aurel32 | } |
3219 | 79aceca5 | bellard | |
3220 | a0d7d5a7 | aurel32 | /* lfd lfdu lfdux lfdx */
|
3221 | a0d7d5a7 | aurel32 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
|
3222 | a0d7d5a7 | aurel32 | /* lfs lfsu lfsux lfsx */
|
3223 | a0d7d5a7 | aurel32 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
3224 | 79aceca5 | bellard | |
3225 | 79aceca5 | bellard | /*** Floating-point store ***/
|
3226 | a0d7d5a7 | aurel32 | #define GEN_STF(name, stop, opc, type) \
|
3227 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3228 | 79aceca5 | bellard | { \ |
3229 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3230 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3231 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3232 | 4ecc3190 | bellard | return; \
|
3233 | 4ecc3190 | bellard | } \ |
3234 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3235 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3236 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3237 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3238 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3239 | 79aceca5 | bellard | } |
3240 | 79aceca5 | bellard | |
3241 | a0d7d5a7 | aurel32 | #define GEN_STUF(name, stop, opc, type) \
|
3242 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3243 | 79aceca5 | bellard | { \ |
3244 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3245 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3246 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3247 | 4ecc3190 | bellard | return; \
|
3248 | 4ecc3190 | bellard | } \ |
3249 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3250 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3251 | 9fddaa0c | bellard | return; \
|
3252 | 9a64fbe4 | bellard | } \ |
3253 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3254 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3255 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3256 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3257 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3258 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3259 | 79aceca5 | bellard | } |
3260 | 79aceca5 | bellard | |
3261 | a0d7d5a7 | aurel32 | #define GEN_STUXF(name, stop, opc, type) \
|
3262 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3263 | 79aceca5 | bellard | { \ |
3264 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3265 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3266 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3267 | 4ecc3190 | bellard | return; \
|
3268 | 4ecc3190 | bellard | } \ |
3269 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3270 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3271 | 9fddaa0c | bellard | return; \
|
3272 | 9a64fbe4 | bellard | } \ |
3273 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3274 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3275 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3276 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3277 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3278 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3279 | 79aceca5 | bellard | } |
3280 | 79aceca5 | bellard | |
3281 | a0d7d5a7 | aurel32 | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
3282 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3283 | 79aceca5 | bellard | { \ |
3284 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3285 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3286 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3287 | 4ecc3190 | bellard | return; \
|
3288 | 4ecc3190 | bellard | } \ |
3289 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3290 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3291 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3292 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3293 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3294 | 79aceca5 | bellard | } |
3295 | 79aceca5 | bellard | |
3296 | a0d7d5a7 | aurel32 | #define GEN_STFS(name, stop, op, type) \
|
3297 | a0d7d5a7 | aurel32 | GEN_STF(name, stop, op | 0x20, type); \
|
3298 | a0d7d5a7 | aurel32 | GEN_STUF(name, stop, op | 0x21, type); \
|
3299 | a0d7d5a7 | aurel32 | GEN_STUXF(name, stop, op | 0x01, type); \
|
3300 | a0d7d5a7 | aurel32 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
3301 | a0d7d5a7 | aurel32 | |
3302 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3303 | a0d7d5a7 | aurel32 | { |
3304 | a0d7d5a7 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3305 | a0d7d5a7 | aurel32 | TCGv t1 = tcg_temp_new(); |
3306 | a0d7d5a7 | aurel32 | gen_helper_float64_to_float32(t0, arg1); |
3307 | a0d7d5a7 | aurel32 | tcg_gen_extu_i32_tl(t1, t0); |
3308 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t0); |
3309 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t1, arg2); |
3310 | a0d7d5a7 | aurel32 | tcg_temp_free(t1); |
3311 | a0d7d5a7 | aurel32 | } |
3312 | 79aceca5 | bellard | |
3313 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
3314 | a0d7d5a7 | aurel32 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
|
3315 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
3316 | a0d7d5a7 | aurel32 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
|
3317 | 79aceca5 | bellard | |
3318 | 79aceca5 | bellard | /* Optional: */
|
3319 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3320 | a0d7d5a7 | aurel32 | { |
3321 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3322 | a0d7d5a7 | aurel32 | tcg_gen_trunc_i64_tl(t0, arg1), |
3323 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, arg2); |
3324 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3325 | a0d7d5a7 | aurel32 | } |
3326 | 79aceca5 | bellard | /* stfiwx */
|
3327 | a0d7d5a7 | aurel32 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
3328 | 79aceca5 | bellard | |
3329 | 79aceca5 | bellard | /*** Branch ***/
|
3330 | 636aa200 | Blue Swirl | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
3331 | c1942362 | bellard | { |
3332 | c1942362 | bellard | TranslationBlock *tb; |
3333 | c1942362 | bellard | tb = ctx->tb; |
3334 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3335 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3336 | a2ffb812 | aurel32 | dest = (uint32_t) dest; |
3337 | a2ffb812 | aurel32 | #endif
|
3338 | 57fec1fe | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
3339 | 8cbcb4fa | aurel32 | likely(!ctx->singlestep_enabled)) { |
3340 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
3341 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3342 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + n);
|
3343 | c1942362 | bellard | } else {
|
3344 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3345 | 8cbcb4fa | aurel32 | if (unlikely(ctx->singlestep_enabled)) {
|
3346 | 8cbcb4fa | aurel32 | if ((ctx->singlestep_enabled &
|
3347 | bdc4e053 | aurel32 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
3348 | 8cbcb4fa | aurel32 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3349 | 8cbcb4fa | aurel32 | target_ulong tmp = ctx->nip; |
3350 | 8cbcb4fa | aurel32 | ctx->nip = dest; |
3351 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
3352 | 8cbcb4fa | aurel32 | ctx->nip = tmp; |
3353 | 8cbcb4fa | aurel32 | } |
3354 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3355 | e06fcd75 | aurel32 | gen_debug_exception(ctx); |
3356 | 8cbcb4fa | aurel32 | } |
3357 | 8cbcb4fa | aurel32 | } |
3358 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3359 | c1942362 | bellard | } |
3360 | c53be334 | bellard | } |
3361 | c53be334 | bellard | |
3362 | 636aa200 | Blue Swirl | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
3363 | e1833e1f | j_mayer | { |
3364 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
3365 | a2ffb812 | aurel32 | if (ctx->sf_mode == 0) |
3366 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); |
3367 | e1833e1f | j_mayer | else
|
3368 | e1833e1f | j_mayer | #endif
|
3369 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, nip); |
3370 | e1833e1f | j_mayer | } |
3371 | e1833e1f | j_mayer | |
3372 | 79aceca5 | bellard | /* b ba bl bla */
|
3373 | 99e300ef | Blue Swirl | static void gen_b(DisasContext *ctx) |
3374 | 79aceca5 | bellard | { |
3375 | 76a66253 | j_mayer | target_ulong li, target; |
3376 | 38a64f9d | bellard | |
3377 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3378 | 38a64f9d | bellard | /* sign extend LI */
|
3379 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
3380 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3381 | d9bce9d9 | j_mayer | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
3382 | d9bce9d9 | j_mayer | else
|
3383 | 76a66253 | j_mayer | #endif
|
3384 | d9bce9d9 | j_mayer | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
3385 | 76a66253 | j_mayer | if (likely(AA(ctx->opcode) == 0)) |
3386 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
3387 | 79aceca5 | bellard | else
|
3388 | 9a64fbe4 | bellard | target = li; |
3389 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3390 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3391 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3392 | 79aceca5 | bellard | } |
3393 | 79aceca5 | bellard | |
3394 | e98a6e40 | bellard | #define BCOND_IM 0 |
3395 | e98a6e40 | bellard | #define BCOND_LR 1 |
3396 | e98a6e40 | bellard | #define BCOND_CTR 2 |
3397 | e98a6e40 | bellard | |
3398 | 636aa200 | Blue Swirl | static inline void gen_bcond(DisasContext *ctx, int type) |
3399 | d9bce9d9 | j_mayer | { |
3400 | d9bce9d9 | j_mayer | uint32_t bo = BO(ctx->opcode); |
3401 | 05f92404 | Blue Swirl | int l1;
|
3402 | a2ffb812 | aurel32 | TCGv target; |
3403 | e98a6e40 | bellard | |
3404 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3405 | a2ffb812 | aurel32 | if (type == BCOND_LR || type == BCOND_CTR) {
|
3406 | a7812ae4 | pbrook | target = tcg_temp_local_new(); |
3407 | a2ffb812 | aurel32 | if (type == BCOND_CTR)
|
3408 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_ctr); |
3409 | a2ffb812 | aurel32 | else
|
3410 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_lr); |
3411 | d2e9fd8f | malc | } else {
|
3412 | d2e9fd8f | malc | TCGV_UNUSED(target); |
3413 | e98a6e40 | bellard | } |
3414 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3415 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3416 | a2ffb812 | aurel32 | l1 = gen_new_label(); |
3417 | a2ffb812 | aurel32 | if ((bo & 0x4) == 0) { |
3418 | a2ffb812 | aurel32 | /* Decrement and test CTR */
|
3419 | a7812ae4 | pbrook | TCGv temp = tcg_temp_new(); |
3420 | a2ffb812 | aurel32 | if (unlikely(type == BCOND_CTR)) {
|
3421 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3422 | a2ffb812 | aurel32 | return;
|
3423 | a2ffb812 | aurel32 | } |
3424 | a2ffb812 | aurel32 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
|
3425 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3426 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3427 | a2ffb812 | aurel32 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3428 | a2ffb812 | aurel32 | else
|
3429 | d9bce9d9 | j_mayer | #endif
|
3430 | a2ffb812 | aurel32 | tcg_gen_mov_tl(temp, cpu_ctr); |
3431 | a2ffb812 | aurel32 | if (bo & 0x2) { |
3432 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
|
3433 | a2ffb812 | aurel32 | } else {
|
3434 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
3435 | e98a6e40 | bellard | } |
3436 | a7812ae4 | pbrook | tcg_temp_free(temp); |
3437 | a2ffb812 | aurel32 | } |
3438 | a2ffb812 | aurel32 | if ((bo & 0x10) == 0) { |
3439 | a2ffb812 | aurel32 | /* Test CR */
|
3440 | a2ffb812 | aurel32 | uint32_t bi = BI(ctx->opcode); |
3441 | a2ffb812 | aurel32 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
3442 | a7812ae4 | pbrook | TCGv_i32 temp = tcg_temp_new_i32(); |
3443 | a2ffb812 | aurel32 | |
3444 | d9bce9d9 | j_mayer | if (bo & 0x8) { |
3445 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3446 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
|
3447 | d9bce9d9 | j_mayer | } else {
|
3448 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3449 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
|
3450 | d9bce9d9 | j_mayer | } |
3451 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3452 | d9bce9d9 | j_mayer | } |
3453 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3454 | a2ffb812 | aurel32 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3455 | a2ffb812 | aurel32 | if (likely(AA(ctx->opcode) == 0)) { |
3456 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
3457 | a2ffb812 | aurel32 | } else {
|
3458 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, li);
|
3459 | a2ffb812 | aurel32 | } |
3460 | c53be334 | bellard | gen_set_label(l1); |
3461 | c1942362 | bellard | gen_goto_tb(ctx, 1, ctx->nip);
|
3462 | e98a6e40 | bellard | } else {
|
3463 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3464 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3465 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
|
3466 | a2ffb812 | aurel32 | else
|
3467 | a2ffb812 | aurel32 | #endif
|
3468 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, ~3);
|
3469 | a2ffb812 | aurel32 | tcg_gen_exit_tb(0);
|
3470 | a2ffb812 | aurel32 | gen_set_label(l1); |
3471 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3472 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3473 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); |
3474 | d9bce9d9 | j_mayer | else
|
3475 | d9bce9d9 | j_mayer | #endif
|
3476 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
3477 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3478 | 08e46e54 | j_mayer | } |
3479 | e98a6e40 | bellard | } |
3480 | e98a6e40 | bellard | |
3481 | 99e300ef | Blue Swirl | static void gen_bc(DisasContext *ctx) |
3482 | 3b46e624 | ths | { |
3483 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
3484 | e98a6e40 | bellard | } |
3485 | e98a6e40 | bellard | |
3486 | 99e300ef | Blue Swirl | static void gen_bcctr(DisasContext *ctx) |
3487 | 3b46e624 | ths | { |
3488 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
3489 | e98a6e40 | bellard | } |
3490 | e98a6e40 | bellard | |
3491 | 99e300ef | Blue Swirl | static void gen_bclr(DisasContext *ctx) |
3492 | 3b46e624 | ths | { |
3493 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
3494 | e98a6e40 | bellard | } |
3495 | 79aceca5 | bellard | |
3496 | 79aceca5 | bellard | /*** Condition register logical ***/
|
3497 | e1571908 | aurel32 | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
3498 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3499 | 79aceca5 | bellard | { \ |
3500 | fc0d441e | j_mayer | uint8_t bitmask; \ |
3501 | fc0d441e | j_mayer | int sh; \
|
3502 | a7812ae4 | pbrook | TCGv_i32 t0, t1; \ |
3503 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3504 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); \ |
3505 | fc0d441e | j_mayer | if (sh > 0) \ |
3506 | fea0c503 | aurel32 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
|
3507 | fc0d441e | j_mayer | else if (sh < 0) \ |
3508 | fea0c503 | aurel32 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
|
3509 | e1571908 | aurel32 | else \
|
3510 | fea0c503 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
|
3511 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); \ |
3512 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3513 | fc0d441e | j_mayer | if (sh > 0) \ |
3514 | fea0c503 | aurel32 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
|
3515 | fc0d441e | j_mayer | else if (sh < 0) \ |
3516 | fea0c503 | aurel32 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
|
3517 | e1571908 | aurel32 | else \
|
3518 | fea0c503 | aurel32 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
|
3519 | fea0c503 | aurel32 | tcg_op(t0, t0, t1); \ |
3520 | fc0d441e | j_mayer | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3521 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3522 | fea0c503 | aurel32 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
|
3523 | fea0c503 | aurel32 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
|
3524 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
3525 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
3526 | 79aceca5 | bellard | } |
3527 | 79aceca5 | bellard | |
3528 | 79aceca5 | bellard | /* crand */
|
3529 | e1571908 | aurel32 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
|
3530 | 79aceca5 | bellard | /* crandc */
|
3531 | e1571908 | aurel32 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
|
3532 | 79aceca5 | bellard | /* creqv */
|
3533 | e1571908 | aurel32 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
|
3534 | 79aceca5 | bellard | /* crnand */
|
3535 | e1571908 | aurel32 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
|
3536 | 79aceca5 | bellard | /* crnor */
|
3537 | e1571908 | aurel32 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
|
3538 | 79aceca5 | bellard | /* cror */
|
3539 | e1571908 | aurel32 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
|
3540 | 79aceca5 | bellard | /* crorc */
|
3541 | e1571908 | aurel32 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
|
3542 | 79aceca5 | bellard | /* crxor */
|
3543 | e1571908 | aurel32 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
|
3544 | 99e300ef | Blue Swirl | |
3545 | 54623277 | Blue Swirl | /* mcrf */
|
3546 | 99e300ef | Blue Swirl | static void gen_mcrf(DisasContext *ctx) |
3547 | 79aceca5 | bellard | { |
3548 | 47e4661c | aurel32 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3549 | 79aceca5 | bellard | } |
3550 | 79aceca5 | bellard | |
3551 | 79aceca5 | bellard | /*** System linkage ***/
|
3552 | 99e300ef | Blue Swirl | |
3553 | 54623277 | Blue Swirl | /* rfi (mem_idx only) */
|
3554 | 99e300ef | Blue Swirl | static void gen_rfi(DisasContext *ctx) |
3555 | 79aceca5 | bellard | { |
3556 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3557 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3558 | 9a64fbe4 | bellard | #else
|
3559 | 9a64fbe4 | bellard | /* Restore CPU state */
|
3560 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3561 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3562 | 9fddaa0c | bellard | return;
|
3563 | 9a64fbe4 | bellard | } |
3564 | d72a19f7 | aurel32 | gen_helper_rfi(); |
3565 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3566 | 9a64fbe4 | bellard | #endif
|
3567 | 79aceca5 | bellard | } |
3568 | 79aceca5 | bellard | |
3569 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3570 | 99e300ef | Blue Swirl | static void gen_rfid(DisasContext *ctx) |
3571 | 426613db | j_mayer | { |
3572 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3573 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3574 | 426613db | j_mayer | #else
|
3575 | 426613db | j_mayer | /* Restore CPU state */
|
3576 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3577 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3578 | 426613db | j_mayer | return;
|
3579 | 426613db | j_mayer | } |
3580 | d72a19f7 | aurel32 | gen_helper_rfid(); |
3581 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3582 | 426613db | j_mayer | #endif
|
3583 | 426613db | j_mayer | } |
3584 | 426613db | j_mayer | |
3585 | 99e300ef | Blue Swirl | static void gen_hrfid(DisasContext *ctx) |
3586 | be147d08 | j_mayer | { |
3587 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3588 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3589 | be147d08 | j_mayer | #else
|
3590 | be147d08 | j_mayer | /* Restore CPU state */
|
3591 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx <= 1)) { |
3592 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3593 | be147d08 | j_mayer | return;
|
3594 | be147d08 | j_mayer | } |
3595 | d72a19f7 | aurel32 | gen_helper_hrfid(); |
3596 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3597 | be147d08 | j_mayer | #endif
|
3598 | be147d08 | j_mayer | } |
3599 | be147d08 | j_mayer | #endif
|
3600 | be147d08 | j_mayer | |
3601 | 79aceca5 | bellard | /* sc */
|
3602 | 417bf010 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3603 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3604 | 417bf010 | j_mayer | #else
|
3605 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3606 | 417bf010 | j_mayer | #endif
|
3607 | 99e300ef | Blue Swirl | static void gen_sc(DisasContext *ctx) |
3608 | 79aceca5 | bellard | { |
3609 | e1833e1f | j_mayer | uint32_t lev; |
3610 | e1833e1f | j_mayer | |
3611 | e1833e1f | j_mayer | lev = (ctx->opcode >> 5) & 0x7F; |
3612 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
3613 | 79aceca5 | bellard | } |
3614 | 79aceca5 | bellard | |
3615 | 79aceca5 | bellard | /*** Trap ***/
|
3616 | 99e300ef | Blue Swirl | |
3617 | 54623277 | Blue Swirl | /* tw */
|
3618 | 99e300ef | Blue Swirl | static void gen_tw(DisasContext *ctx) |
3619 | 79aceca5 | bellard | { |
3620 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3621 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3622 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3623 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3624 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3625 | 79aceca5 | bellard | } |
3626 | 79aceca5 | bellard | |
3627 | 79aceca5 | bellard | /* twi */
|
3628 | 99e300ef | Blue Swirl | static void gen_twi(DisasContext *ctx) |
3629 | 79aceca5 | bellard | { |
3630 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3631 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3632 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3633 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3634 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3635 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3636 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3637 | 79aceca5 | bellard | } |
3638 | 79aceca5 | bellard | |
3639 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3640 | d9bce9d9 | j_mayer | /* td */
|
3641 | 99e300ef | Blue Swirl | static void gen_td(DisasContext *ctx) |
3642 | d9bce9d9 | j_mayer | { |
3643 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3644 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3645 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3646 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3647 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3648 | d9bce9d9 | j_mayer | } |
3649 | d9bce9d9 | j_mayer | |
3650 | d9bce9d9 | j_mayer | /* tdi */
|
3651 | 99e300ef | Blue Swirl | static void gen_tdi(DisasContext *ctx) |
3652 | d9bce9d9 | j_mayer | { |
3653 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3654 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3655 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3656 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3657 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3658 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3659 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3660 | d9bce9d9 | j_mayer | } |
3661 | d9bce9d9 | j_mayer | #endif
|
3662 | d9bce9d9 | j_mayer | |
3663 | 79aceca5 | bellard | /*** Processor control ***/
|
3664 | 99e300ef | Blue Swirl | |
3665 | 54623277 | Blue Swirl | /* mcrxr */
|
3666 | 99e300ef | Blue Swirl | static void gen_mcrxr(DisasContext *ctx) |
3667 | 79aceca5 | bellard | { |
3668 | 3d7b417e | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3669 | 3d7b417e | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); |
3670 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
3671 | 79aceca5 | bellard | } |
3672 | 79aceca5 | bellard | |
3673 | 0cfe11ea | aurel32 | /* mfcr mfocrf */
|
3674 | 99e300ef | Blue Swirl | static void gen_mfcr(DisasContext *ctx) |
3675 | 79aceca5 | bellard | { |
3676 | 76a66253 | j_mayer | uint32_t crm, crn; |
3677 | 3b46e624 | ths | |
3678 | 76a66253 | j_mayer | if (likely(ctx->opcode & 0x00100000)) { |
3679 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3680 | 8dd640e4 | malc | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
3681 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3682 | e1571908 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
|
3683 | 0497d2f4 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3684 | 0497d2f4 | aurel32 | cpu_gpr[rD(ctx->opcode)], crn * 4);
|
3685 | 76a66253 | j_mayer | } |
3686 | d9bce9d9 | j_mayer | } else {
|
3687 | 651721b2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3688 | 651721b2 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[0]);
|
3689 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3690 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[1]);
|
3691 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3692 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[2]);
|
3693 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3694 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[3]);
|
3695 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3696 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[4]);
|
3697 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3698 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[5]);
|
3699 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3700 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[6]);
|
3701 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3702 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[7]);
|
3703 | 651721b2 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
3704 | 651721b2 | aurel32 | tcg_temp_free_i32(t0); |
3705 | d9bce9d9 | j_mayer | } |
3706 | 79aceca5 | bellard | } |
3707 | 79aceca5 | bellard | |
3708 | 79aceca5 | bellard | /* mfmsr */
|
3709 | 99e300ef | Blue Swirl | static void gen_mfmsr(DisasContext *ctx) |
3710 | 79aceca5 | bellard | { |
3711 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3712 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3713 | 9a64fbe4 | bellard | #else
|
3714 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3715 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3716 | 9fddaa0c | bellard | return;
|
3717 | 9a64fbe4 | bellard | } |
3718 | 6527f6ea | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
3719 | 9a64fbe4 | bellard | #endif
|
3720 | 79aceca5 | bellard | } |
3721 | 79aceca5 | bellard | |
3722 | 7b13448f | Blue Swirl | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3723 | 3fc6c082 | bellard | { |
3724 | 7b13448f | Blue Swirl | #if 0
|
3725 | 3fc6c082 | bellard | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
|
3726 | 3fc6c082 | bellard | printf("ERROR: try to access SPR %d !\n", sprn);
|
3727 | 7b13448f | Blue Swirl | #endif
|
3728 | 3fc6c082 | bellard | } |
3729 | 3fc6c082 | bellard | #define SPR_NOACCESS (&spr_noaccess)
|
3730 | 3fc6c082 | bellard | |
3731 | 79aceca5 | bellard | /* mfspr */
|
3732 | 636aa200 | Blue Swirl | static inline void gen_op_mfspr(DisasContext *ctx) |
3733 | 79aceca5 | bellard | { |
3734 | 45d827d2 | aurel32 | void (*read_cb)(void *opaque, int gprn, int sprn); |
3735 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3736 | 79aceca5 | bellard | |
3737 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3738 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3739 | be147d08 | j_mayer | read_cb = ctx->spr_cb[sprn].hea_read; |
3740 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3741 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].oea_read; |
3742 | 3fc6c082 | bellard | else
|
3743 | 9a64fbe4 | bellard | #endif
|
3744 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].uea_read; |
3745 | 76a66253 | j_mayer | if (likely(read_cb != NULL)) { |
3746 | 76a66253 | j_mayer | if (likely(read_cb != SPR_NOACCESS)) {
|
3747 | 45d827d2 | aurel32 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3748 | 3fc6c082 | bellard | } else {
|
3749 | 3fc6c082 | bellard | /* Privilege exception */
|
3750 | 9fceefa7 | j_mayer | /* This is a hack to avoid warnings when running Linux:
|
3751 | 9fceefa7 | j_mayer | * this OS breaks the PowerPC virtualisation model,
|
3752 | 9fceefa7 | j_mayer | * allowing userland application to read the PVR
|
3753 | 9fceefa7 | j_mayer | */
|
3754 | 9fceefa7 | j_mayer | if (sprn != SPR_PVR) {
|
3755 | 93fcfe39 | aliguori | qemu_log("Trying to read privileged spr %d %03x at "
|
3756 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3757 | 90e189ec | Blue Swirl | printf("Trying to read privileged spr %d %03x at "
|
3758 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3759 | f24e5695 | bellard | } |
3760 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3761 | 79aceca5 | bellard | } |
3762 | 3fc6c082 | bellard | } else {
|
3763 | 3fc6c082 | bellard | /* Not defined */
|
3764 | 93fcfe39 | aliguori | qemu_log("Trying to read invalid spr %d %03x at "
|
3765 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3766 | 90e189ec | Blue Swirl | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", |
3767 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3768 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3769 | 79aceca5 | bellard | } |
3770 | 79aceca5 | bellard | } |
3771 | 79aceca5 | bellard | |
3772 | 99e300ef | Blue Swirl | static void gen_mfspr(DisasContext *ctx) |
3773 | 79aceca5 | bellard | { |
3774 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3775 | 76a66253 | j_mayer | } |
3776 | 3fc6c082 | bellard | |
3777 | 3fc6c082 | bellard | /* mftb */
|
3778 | 99e300ef | Blue Swirl | static void gen_mftb(DisasContext *ctx) |
3779 | 3fc6c082 | bellard | { |
3780 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3781 | 79aceca5 | bellard | } |
3782 | 79aceca5 | bellard | |
3783 | 0cfe11ea | aurel32 | /* mtcrf mtocrf*/
|
3784 | 99e300ef | Blue Swirl | static void gen_mtcrf(DisasContext *ctx) |
3785 | 79aceca5 | bellard | { |
3786 | 76a66253 | j_mayer | uint32_t crm, crn; |
3787 | 3b46e624 | ths | |
3788 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3789 | 8dd640e4 | malc | if (likely((ctx->opcode & 0x00100000))) { |
3790 | 8dd640e4 | malc | if (crm && ((crm & (crm - 1)) == 0)) { |
3791 | 8dd640e4 | malc | TCGv_i32 temp = tcg_temp_new_i32(); |
3792 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3793 | 8dd640e4 | malc | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3794 | 0cfe11ea | aurel32 | tcg_gen_shri_i32(temp, temp, crn * 4);
|
3795 | 0cfe11ea | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
3796 | 8dd640e4 | malc | tcg_temp_free_i32(temp); |
3797 | 8dd640e4 | malc | } |
3798 | 76a66253 | j_mayer | } else {
|
3799 | 651721b2 | aurel32 | TCGv_i32 temp = tcg_temp_new_i32(); |
3800 | 651721b2 | aurel32 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3801 | 651721b2 | aurel32 | for (crn = 0 ; crn < 8 ; crn++) { |
3802 | 651721b2 | aurel32 | if (crm & (1 << crn)) { |
3803 | 651721b2 | aurel32 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
3804 | 651721b2 | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
3805 | 651721b2 | aurel32 | } |
3806 | 651721b2 | aurel32 | } |
3807 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3808 | 76a66253 | j_mayer | } |
3809 | 79aceca5 | bellard | } |
3810 | 79aceca5 | bellard | |
3811 | 79aceca5 | bellard | /* mtmsr */
|
3812 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3813 | 99e300ef | Blue Swirl | static void gen_mtmsrd(DisasContext *ctx) |
3814 | 426613db | j_mayer | { |
3815 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3816 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3817 | 426613db | j_mayer | #else
|
3818 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3819 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3820 | 426613db | j_mayer | return;
|
3821 | 426613db | j_mayer | } |
3822 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3823 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3824 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3825 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3826 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3827 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3828 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3829 | be147d08 | j_mayer | } else {
|
3830 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3831 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3832 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3833 | 056b05f8 | j_mayer | */
|
3834 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3835 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3836 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3837 | be147d08 | j_mayer | /* Note that mtmsr is not always defined as context-synchronizing */
|
3838 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3839 | be147d08 | j_mayer | } |
3840 | 426613db | j_mayer | #endif
|
3841 | 426613db | j_mayer | } |
3842 | 426613db | j_mayer | #endif
|
3843 | 426613db | j_mayer | |
3844 | 99e300ef | Blue Swirl | static void gen_mtmsr(DisasContext *ctx) |
3845 | 79aceca5 | bellard | { |
3846 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3847 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3848 | 9a64fbe4 | bellard | #else
|
3849 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3850 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3851 | 9fddaa0c | bellard | return;
|
3852 | 9a64fbe4 | bellard | } |
3853 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3854 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3855 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3856 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3857 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3858 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3859 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3860 | be147d08 | j_mayer | } else {
|
3861 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3862 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3863 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3864 | 056b05f8 | j_mayer | */
|
3865 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3866 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3867 | 6527f6ea | aurel32 | if (!ctx->sf_mode) {
|
3868 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3869 | 6527f6ea | aurel32 | TCGv t1 = tcg_temp_new(); |
3870 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
|
3871 | 6527f6ea | aurel32 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
3872 | 6527f6ea | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
3873 | 6527f6ea | aurel32 | tcg_temp_free(t1); |
3874 | 6527f6ea | aurel32 | gen_helper_store_msr(t0); |
3875 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3876 | 6527f6ea | aurel32 | } else
|
3877 | d9bce9d9 | j_mayer | #endif
|
3878 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3879 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3880 | 6527f6ea | aurel32 | /* Note that mtmsr is not always defined as context-synchronizing */
|
3881 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3882 | be147d08 | j_mayer | } |
3883 | 9a64fbe4 | bellard | #endif
|
3884 | 79aceca5 | bellard | } |
3885 | 79aceca5 | bellard | |
3886 | 79aceca5 | bellard | /* mtspr */
|
3887 | 99e300ef | Blue Swirl | static void gen_mtspr(DisasContext *ctx) |
3888 | 79aceca5 | bellard | { |
3889 | 45d827d2 | aurel32 | void (*write_cb)(void *opaque, int sprn, int gprn); |
3890 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3891 | 79aceca5 | bellard | |
3892 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3893 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3894 | be147d08 | j_mayer | write_cb = ctx->spr_cb[sprn].hea_write; |
3895 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3896 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].oea_write; |
3897 | 3fc6c082 | bellard | else
|
3898 | 9a64fbe4 | bellard | #endif
|
3899 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].uea_write; |
3900 | 76a66253 | j_mayer | if (likely(write_cb != NULL)) { |
3901 | 76a66253 | j_mayer | if (likely(write_cb != SPR_NOACCESS)) {
|
3902 | 45d827d2 | aurel32 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3903 | 3fc6c082 | bellard | } else {
|
3904 | 3fc6c082 | bellard | /* Privilege exception */
|
3905 | 93fcfe39 | aliguori | qemu_log("Trying to write privileged spr %d %03x at "
|
3906 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3907 | 90e189ec | Blue Swirl | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
|
3908 | 90e189ec | Blue Swirl | "\n", sprn, sprn, ctx->nip);
|
3909 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3910 | 76a66253 | j_mayer | } |
3911 | 3fc6c082 | bellard | } else {
|
3912 | 3fc6c082 | bellard | /* Not defined */
|
3913 | 93fcfe39 | aliguori | qemu_log("Trying to write invalid spr %d %03x at "
|
3914 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3915 | 90e189ec | Blue Swirl | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", |
3916 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3917 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3918 | 79aceca5 | bellard | } |
3919 | 79aceca5 | bellard | } |
3920 | 79aceca5 | bellard | |
3921 | 79aceca5 | bellard | /*** Cache management ***/
|
3922 | 99e300ef | Blue Swirl | |
3923 | 54623277 | Blue Swirl | /* dcbf */
|
3924 | 99e300ef | Blue Swirl | static void gen_dcbf(DisasContext *ctx) |
3925 | 79aceca5 | bellard | { |
3926 | dac454af | j_mayer | /* XXX: specification says this is treated as a load by the MMU */
|
3927 | 76db3ba4 | aurel32 | TCGv t0; |
3928 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3929 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3930 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3931 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3932 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3933 | 79aceca5 | bellard | } |
3934 | 79aceca5 | bellard | |
3935 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
3936 | 99e300ef | Blue Swirl | static void gen_dcbi(DisasContext *ctx) |
3937 | 79aceca5 | bellard | { |
3938 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
3939 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3940 | a541f297 | bellard | #else
|
3941 | b61f2753 | aurel32 | TCGv EA, val; |
3942 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3943 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3944 | 9fddaa0c | bellard | return;
|
3945 | 9a64fbe4 | bellard | } |
3946 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
3947 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3948 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
3949 | a7812ae4 | pbrook | val = tcg_temp_new(); |
3950 | 76a66253 | j_mayer | /* XXX: specification says this should be treated as a store by the MMU */
|
3951 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, val, EA); |
3952 | 76db3ba4 | aurel32 | gen_qemu_st8(ctx, val, EA); |
3953 | b61f2753 | aurel32 | tcg_temp_free(val); |
3954 | b61f2753 | aurel32 | tcg_temp_free(EA); |
3955 | a541f297 | bellard | #endif
|
3956 | 79aceca5 | bellard | } |
3957 | 79aceca5 | bellard | |
3958 | 79aceca5 | bellard | /* dcdst */
|
3959 | 99e300ef | Blue Swirl | static void gen_dcbst(DisasContext *ctx) |
3960 | 79aceca5 | bellard | { |
3961 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU */
|
3962 | 76db3ba4 | aurel32 | TCGv t0; |
3963 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3964 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3965 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3966 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3967 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3968 | 79aceca5 | bellard | } |
3969 | 79aceca5 | bellard | |
3970 | 79aceca5 | bellard | /* dcbt */
|
3971 | 99e300ef | Blue Swirl | static void gen_dcbt(DisasContext *ctx) |
3972 | 79aceca5 | bellard | { |
3973 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3974 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3975 | 76a66253 | j_mayer | * but does not generate any exception
|
3976 | 76a66253 | j_mayer | */
|
3977 | 79aceca5 | bellard | } |
3978 | 79aceca5 | bellard | |
3979 | 79aceca5 | bellard | /* dcbtst */
|
3980 | 99e300ef | Blue Swirl | static void gen_dcbtst(DisasContext *ctx) |
3981 | 79aceca5 | bellard | { |
3982 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3983 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3984 | 76a66253 | j_mayer | * but does not generate any exception
|
3985 | 76a66253 | j_mayer | */
|
3986 | 79aceca5 | bellard | } |
3987 | 79aceca5 | bellard | |
3988 | 79aceca5 | bellard | /* dcbz */
|
3989 | 99e300ef | Blue Swirl | static void gen_dcbz(DisasContext *ctx) |
3990 | 79aceca5 | bellard | { |
3991 | 76db3ba4 | aurel32 | TCGv t0; |
3992 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3993 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
3994 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
3995 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3996 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3997 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
3998 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
3999 | d63001d1 | j_mayer | } |
4000 | d63001d1 | j_mayer | |
4001 | e8eaa2c0 | Blue Swirl | static void gen_dcbz_970(DisasContext *ctx) |
4002 | d63001d1 | j_mayer | { |
4003 | 76db3ba4 | aurel32 | TCGv t0; |
4004 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4005 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
4006 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
4007 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4008 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4009 | d63001d1 | j_mayer | if (ctx->opcode & 0x00200000) |
4010 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
4011 | d63001d1 | j_mayer | else
|
4012 | 799a8c8d | aurel32 | gen_helper_dcbz_970(t0); |
4013 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
4014 | 79aceca5 | bellard | } |
4015 | 79aceca5 | bellard | |
4016 | ae1c1a3d | aurel32 | /* dst / dstt */
|
4017 | 99e300ef | Blue Swirl | static void gen_dst(DisasContext *ctx) |
4018 | ae1c1a3d | aurel32 | { |
4019 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4020 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4021 | ae1c1a3d | aurel32 | } else {
|
4022 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4023 | ae1c1a3d | aurel32 | } |
4024 | ae1c1a3d | aurel32 | } |
4025 | ae1c1a3d | aurel32 | |
4026 | ae1c1a3d | aurel32 | /* dstst /dststt */
|
4027 | 99e300ef | Blue Swirl | static void gen_dstst(DisasContext *ctx) |
4028 | ae1c1a3d | aurel32 | { |
4029 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4030 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4031 | ae1c1a3d | aurel32 | } else {
|
4032 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4033 | ae1c1a3d | aurel32 | } |
4034 | ae1c1a3d | aurel32 | |
4035 | ae1c1a3d | aurel32 | } |
4036 | ae1c1a3d | aurel32 | |
4037 | ae1c1a3d | aurel32 | /* dss / dssall */
|
4038 | 99e300ef | Blue Swirl | static void gen_dss(DisasContext *ctx) |
4039 | ae1c1a3d | aurel32 | { |
4040 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4041 | ae1c1a3d | aurel32 | } |
4042 | ae1c1a3d | aurel32 | |
4043 | 79aceca5 | bellard | /* icbi */
|
4044 | 99e300ef | Blue Swirl | static void gen_icbi(DisasContext *ctx) |
4045 | 79aceca5 | bellard | { |
4046 | 76db3ba4 | aurel32 | TCGv t0; |
4047 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4048 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4049 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4050 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4051 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4052 | 37d269df | aurel32 | gen_helper_icbi(t0); |
4053 | 37d269df | aurel32 | tcg_temp_free(t0); |
4054 | 79aceca5 | bellard | } |
4055 | 79aceca5 | bellard | |
4056 | 79aceca5 | bellard | /* Optional: */
|
4057 | 79aceca5 | bellard | /* dcba */
|
4058 | 99e300ef | Blue Swirl | static void gen_dcba(DisasContext *ctx) |
4059 | 79aceca5 | bellard | { |
4060 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4061 | 0db1b20e | j_mayer | /* XXX: specification say this is treated as a store by the MMU
|
4062 | 0db1b20e | j_mayer | * but does not generate any exception
|
4063 | 0db1b20e | j_mayer | */
|
4064 | 79aceca5 | bellard | } |
4065 | 79aceca5 | bellard | |
4066 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
4067 | 79aceca5 | bellard | /* Supervisor only: */
|
4068 | 99e300ef | Blue Swirl | |
4069 | 54623277 | Blue Swirl | /* mfsr */
|
4070 | 99e300ef | Blue Swirl | static void gen_mfsr(DisasContext *ctx) |
4071 | 79aceca5 | bellard | { |
4072 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4073 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4074 | 9a64fbe4 | bellard | #else
|
4075 | 74d37793 | aurel32 | TCGv t0; |
4076 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4077 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4078 | 9fddaa0c | bellard | return;
|
4079 | 9a64fbe4 | bellard | } |
4080 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4081 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4082 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4083 | 9a64fbe4 | bellard | #endif
|
4084 | 79aceca5 | bellard | } |
4085 | 79aceca5 | bellard | |
4086 | 79aceca5 | bellard | /* mfsrin */
|
4087 | 99e300ef | Blue Swirl | static void gen_mfsrin(DisasContext *ctx) |
4088 | 79aceca5 | bellard | { |
4089 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4090 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4091 | 9a64fbe4 | bellard | #else
|
4092 | 74d37793 | aurel32 | TCGv t0; |
4093 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4094 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4095 | 9fddaa0c | bellard | return;
|
4096 | 9a64fbe4 | bellard | } |
4097 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4098 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4099 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4100 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4101 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4102 | 9a64fbe4 | bellard | #endif
|
4103 | 79aceca5 | bellard | } |
4104 | 79aceca5 | bellard | |
4105 | 79aceca5 | bellard | /* mtsr */
|
4106 | 99e300ef | Blue Swirl | static void gen_mtsr(DisasContext *ctx) |
4107 | 79aceca5 | bellard | { |
4108 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4109 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4110 | 9a64fbe4 | bellard | #else
|
4111 | 74d37793 | aurel32 | TCGv t0; |
4112 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4113 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4114 | 9fddaa0c | bellard | return;
|
4115 | 9a64fbe4 | bellard | } |
4116 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4117 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4118 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4119 | 9a64fbe4 | bellard | #endif
|
4120 | 79aceca5 | bellard | } |
4121 | 79aceca5 | bellard | |
4122 | 79aceca5 | bellard | /* mtsrin */
|
4123 | 99e300ef | Blue Swirl | static void gen_mtsrin(DisasContext *ctx) |
4124 | 79aceca5 | bellard | { |
4125 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4126 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4127 | 9a64fbe4 | bellard | #else
|
4128 | 74d37793 | aurel32 | TCGv t0; |
4129 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4130 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4131 | 9fddaa0c | bellard | return;
|
4132 | 9a64fbe4 | bellard | } |
4133 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4134 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4135 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4136 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); |
4137 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4138 | 9a64fbe4 | bellard | #endif
|
4139 | 79aceca5 | bellard | } |
4140 | 79aceca5 | bellard | |
4141 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
4142 | 12de9a39 | j_mayer | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
4143 | e8eaa2c0 | Blue Swirl | |
4144 | 54623277 | Blue Swirl | /* mfsr */
|
4145 | e8eaa2c0 | Blue Swirl | static void gen_mfsr_64b(DisasContext *ctx) |
4146 | 12de9a39 | j_mayer | { |
4147 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4148 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4149 | 12de9a39 | j_mayer | #else
|
4150 | 74d37793 | aurel32 | TCGv t0; |
4151 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4152 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4153 | 12de9a39 | j_mayer | return;
|
4154 | 12de9a39 | j_mayer | } |
4155 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4156 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4157 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4158 | 12de9a39 | j_mayer | #endif
|
4159 | 12de9a39 | j_mayer | } |
4160 | 12de9a39 | j_mayer | |
4161 | 12de9a39 | j_mayer | /* mfsrin */
|
4162 | e8eaa2c0 | Blue Swirl | static void gen_mfsrin_64b(DisasContext *ctx) |
4163 | 12de9a39 | j_mayer | { |
4164 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4165 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4166 | 12de9a39 | j_mayer | #else
|
4167 | 74d37793 | aurel32 | TCGv t0; |
4168 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4169 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4170 | 12de9a39 | j_mayer | return;
|
4171 | 12de9a39 | j_mayer | } |
4172 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4173 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4174 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4175 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4176 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4177 | 12de9a39 | j_mayer | #endif
|
4178 | 12de9a39 | j_mayer | } |
4179 | 12de9a39 | j_mayer | |
4180 | 12de9a39 | j_mayer | /* mtsr */
|
4181 | e8eaa2c0 | Blue Swirl | static void gen_mtsr_64b(DisasContext *ctx) |
4182 | 12de9a39 | j_mayer | { |
4183 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4184 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4185 | 12de9a39 | j_mayer | #else
|
4186 | 74d37793 | aurel32 | TCGv t0; |
4187 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4188 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4189 | 12de9a39 | j_mayer | return;
|
4190 | 12de9a39 | j_mayer | } |
4191 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4192 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4193 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4194 | 12de9a39 | j_mayer | #endif
|
4195 | 12de9a39 | j_mayer | } |
4196 | 12de9a39 | j_mayer | |
4197 | 12de9a39 | j_mayer | /* mtsrin */
|
4198 | e8eaa2c0 | Blue Swirl | static void gen_mtsrin_64b(DisasContext *ctx) |
4199 | 12de9a39 | j_mayer | { |
4200 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4201 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4202 | 12de9a39 | j_mayer | #else
|
4203 | 74d37793 | aurel32 | TCGv t0; |
4204 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4205 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4206 | 12de9a39 | j_mayer | return;
|
4207 | 12de9a39 | j_mayer | } |
4208 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4209 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4210 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4211 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4212 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4213 | 12de9a39 | j_mayer | #endif
|
4214 | 12de9a39 | j_mayer | } |
4215 | f6b868fc | blueswir1 | |
4216 | f6b868fc | blueswir1 | /* slbmte */
|
4217 | e8eaa2c0 | Blue Swirl | static void gen_slbmte(DisasContext *ctx) |
4218 | f6b868fc | blueswir1 | { |
4219 | f6b868fc | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4220 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4221 | f6b868fc | blueswir1 | #else
|
4222 | f6b868fc | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4223 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4224 | f6b868fc | blueswir1 | return;
|
4225 | f6b868fc | blueswir1 | } |
4226 | f6b868fc | blueswir1 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
4227 | f6b868fc | blueswir1 | #endif
|
4228 | f6b868fc | blueswir1 | } |
4229 | f6b868fc | blueswir1 | |
4230 | efdef95f | David Gibson | static void gen_slbmfee(DisasContext *ctx) |
4231 | efdef95f | David Gibson | { |
4232 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4233 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4234 | efdef95f | David Gibson | #else
|
4235 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4236 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4237 | efdef95f | David Gibson | return;
|
4238 | efdef95f | David Gibson | } |
4239 | efdef95f | David Gibson | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], |
4240 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4241 | efdef95f | David Gibson | #endif
|
4242 | efdef95f | David Gibson | } |
4243 | efdef95f | David Gibson | |
4244 | efdef95f | David Gibson | static void gen_slbmfev(DisasContext *ctx) |
4245 | efdef95f | David Gibson | { |
4246 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4247 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4248 | efdef95f | David Gibson | #else
|
4249 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4250 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4251 | efdef95f | David Gibson | return;
|
4252 | efdef95f | David Gibson | } |
4253 | efdef95f | David Gibson | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], |
4254 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4255 | efdef95f | David Gibson | #endif
|
4256 | efdef95f | David Gibson | } |
4257 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
4258 | 12de9a39 | j_mayer | |
4259 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
4260 | 76db3ba4 | aurel32 | /* Optional & mem_idx only: */
|
4261 | 99e300ef | Blue Swirl | |
4262 | 54623277 | Blue Swirl | /* tlbia */
|
4263 | 99e300ef | Blue Swirl | static void gen_tlbia(DisasContext *ctx) |
4264 | 79aceca5 | bellard | { |
4265 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4266 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4267 | 9a64fbe4 | bellard | #else
|
4268 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4269 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4270 | 9fddaa0c | bellard | return;
|
4271 | 9a64fbe4 | bellard | } |
4272 | 74d37793 | aurel32 | gen_helper_tlbia(); |
4273 | 9a64fbe4 | bellard | #endif
|
4274 | 79aceca5 | bellard | } |
4275 | 79aceca5 | bellard | |
4276 | bf14b1ce | blueswir1 | /* tlbiel */
|
4277 | 99e300ef | Blue Swirl | static void gen_tlbiel(DisasContext *ctx) |
4278 | bf14b1ce | blueswir1 | { |
4279 | bf14b1ce | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4280 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4281 | bf14b1ce | blueswir1 | #else
|
4282 | bf14b1ce | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4283 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4284 | bf14b1ce | blueswir1 | return;
|
4285 | bf14b1ce | blueswir1 | } |
4286 | bf14b1ce | blueswir1 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4287 | bf14b1ce | blueswir1 | #endif
|
4288 | bf14b1ce | blueswir1 | } |
4289 | bf14b1ce | blueswir1 | |
4290 | 79aceca5 | bellard | /* tlbie */
|
4291 | 99e300ef | Blue Swirl | static void gen_tlbie(DisasContext *ctx) |
4292 | 79aceca5 | bellard | { |
4293 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4294 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4295 | 9a64fbe4 | bellard | #else
|
4296 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4297 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4298 | 9fddaa0c | bellard | return;
|
4299 | 9a64fbe4 | bellard | } |
4300 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
4301 | 74d37793 | aurel32 | if (!ctx->sf_mode) {
|
4302 | 74d37793 | aurel32 | TCGv t0 = tcg_temp_new(); |
4303 | 74d37793 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
4304 | 74d37793 | aurel32 | gen_helper_tlbie(t0); |
4305 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4306 | 74d37793 | aurel32 | } else
|
4307 | d9bce9d9 | j_mayer | #endif
|
4308 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4309 | 9a64fbe4 | bellard | #endif
|
4310 | 79aceca5 | bellard | } |
4311 | 79aceca5 | bellard | |
4312 | 79aceca5 | bellard | /* tlbsync */
|
4313 | 99e300ef | Blue Swirl | static void gen_tlbsync(DisasContext *ctx) |
4314 | 79aceca5 | bellard | { |
4315 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4316 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4317 | 9a64fbe4 | bellard | #else
|
4318 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4319 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4320 | 9fddaa0c | bellard | return;
|
4321 | 9a64fbe4 | bellard | } |
4322 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
4323 | 9a64fbe4 | bellard | * tlbie have completed
|
4324 | 9a64fbe4 | bellard | */
|
4325 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4326 | 9a64fbe4 | bellard | #endif
|
4327 | 79aceca5 | bellard | } |
4328 | 79aceca5 | bellard | |
4329 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
4330 | 426613db | j_mayer | /* slbia */
|
4331 | 99e300ef | Blue Swirl | static void gen_slbia(DisasContext *ctx) |
4332 | 426613db | j_mayer | { |
4333 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4334 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4335 | 426613db | j_mayer | #else
|
4336 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4337 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4338 | 426613db | j_mayer | return;
|
4339 | 426613db | j_mayer | } |
4340 | 74d37793 | aurel32 | gen_helper_slbia(); |
4341 | 426613db | j_mayer | #endif
|
4342 | 426613db | j_mayer | } |
4343 | 426613db | j_mayer | |
4344 | 426613db | j_mayer | /* slbie */
|
4345 | 99e300ef | Blue Swirl | static void gen_slbie(DisasContext *ctx) |
4346 | 426613db | j_mayer | { |
4347 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4348 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4349 | 426613db | j_mayer | #else
|
4350 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4351 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4352 | 426613db | j_mayer | return;
|
4353 | 426613db | j_mayer | } |
4354 | 74d37793 | aurel32 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
4355 | 426613db | j_mayer | #endif
|
4356 | 426613db | j_mayer | } |
4357 | 426613db | j_mayer | #endif
|
4358 | 426613db | j_mayer | |
4359 | 79aceca5 | bellard | /*** External control ***/
|
4360 | 79aceca5 | bellard | /* Optional: */
|
4361 | 99e300ef | Blue Swirl | |
4362 | 54623277 | Blue Swirl | /* eciwx */
|
4363 | 99e300ef | Blue Swirl | static void gen_eciwx(DisasContext *ctx) |
4364 | 79aceca5 | bellard | { |
4365 | 76db3ba4 | aurel32 | TCGv t0; |
4366 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4367 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4368 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4369 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4370 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4371 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4372 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4373 | 76a66253 | j_mayer | } |
4374 | 76a66253 | j_mayer | |
4375 | 76a66253 | j_mayer | /* ecowx */
|
4376 | 99e300ef | Blue Swirl | static void gen_ecowx(DisasContext *ctx) |
4377 | 76a66253 | j_mayer | { |
4378 | 76db3ba4 | aurel32 | TCGv t0; |
4379 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4380 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4381 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4382 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4383 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4384 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4385 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4386 | 76a66253 | j_mayer | } |
4387 | 76a66253 | j_mayer | |
4388 | 76a66253 | j_mayer | /* PowerPC 601 specific instructions */
|
4389 | 99e300ef | Blue Swirl | |
4390 | 54623277 | Blue Swirl | /* abs - abs. */
|
4391 | 99e300ef | Blue Swirl | static void gen_abs(DisasContext *ctx) |
4392 | 76a66253 | j_mayer | { |
4393 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4394 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4395 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4396 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4397 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4398 | 22e0e173 | aurel32 | gen_set_label(l1); |
4399 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4400 | 22e0e173 | aurel32 | gen_set_label(l2); |
4401 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4402 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4403 | 76a66253 | j_mayer | } |
4404 | 76a66253 | j_mayer | |
4405 | 76a66253 | j_mayer | /* abso - abso. */
|
4406 | 99e300ef | Blue Swirl | static void gen_abso(DisasContext *ctx) |
4407 | 76a66253 | j_mayer | { |
4408 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4409 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4410 | 22e0e173 | aurel32 | int l3 = gen_new_label();
|
4411 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4412 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4413 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
|
4414 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
|
4415 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4416 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4417 | 22e0e173 | aurel32 | gen_set_label(l1); |
4418 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4419 | 22e0e173 | aurel32 | tcg_gen_br(l3); |
4420 | 22e0e173 | aurel32 | gen_set_label(l2); |
4421 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4422 | 22e0e173 | aurel32 | gen_set_label(l3); |
4423 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4424 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4425 | 76a66253 | j_mayer | } |
4426 | 76a66253 | j_mayer | |
4427 | 76a66253 | j_mayer | /* clcs */
|
4428 | 99e300ef | Blue Swirl | static void gen_clcs(DisasContext *ctx) |
4429 | 76a66253 | j_mayer | { |
4430 | 22e0e173 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4431 | 22e0e173 | aurel32 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); |
4432 | 22e0e173 | aurel32 | tcg_temp_free_i32(t0); |
4433 | c7697e1f | j_mayer | /* Rc=1 sets CR0 to an undefined state */
|
4434 | 76a66253 | j_mayer | } |
4435 | 76a66253 | j_mayer | |
4436 | 76a66253 | j_mayer | /* div - div. */
|
4437 | 99e300ef | Blue Swirl | static void gen_div(DisasContext *ctx) |
4438 | 76a66253 | j_mayer | { |
4439 | 22e0e173 | aurel32 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4440 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4441 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4442 | 76a66253 | j_mayer | } |
4443 | 76a66253 | j_mayer | |
4444 | 76a66253 | j_mayer | /* divo - divo. */
|
4445 | 99e300ef | Blue Swirl | static void gen_divo(DisasContext *ctx) |
4446 | 76a66253 | j_mayer | { |
4447 | 22e0e173 | aurel32 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4448 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4449 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4450 | 76a66253 | j_mayer | } |
4451 | 76a66253 | j_mayer | |
4452 | 76a66253 | j_mayer | /* divs - divs. */
|
4453 | 99e300ef | Blue Swirl | static void gen_divs(DisasContext *ctx) |
4454 | 76a66253 | j_mayer | { |
4455 | 22e0e173 | aurel32 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4456 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4457 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4458 | 76a66253 | j_mayer | } |
4459 | 76a66253 | j_mayer | |
4460 | 76a66253 | j_mayer | /* divso - divso. */
|
4461 | 99e300ef | Blue Swirl | static void gen_divso(DisasContext *ctx) |
4462 | 76a66253 | j_mayer | { |
4463 | 22e0e173 | aurel32 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4464 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4465 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4466 | 76a66253 | j_mayer | } |
4467 | 76a66253 | j_mayer | |
4468 | 76a66253 | j_mayer | /* doz - doz. */
|
4469 | 99e300ef | Blue Swirl | static void gen_doz(DisasContext *ctx) |
4470 | 76a66253 | j_mayer | { |
4471 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4472 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4473 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4474 | 22e0e173 | aurel32 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4475 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4476 | 22e0e173 | aurel32 | gen_set_label(l1); |
4477 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4478 | 22e0e173 | aurel32 | gen_set_label(l2); |
4479 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4480 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4481 | 76a66253 | j_mayer | } |
4482 | 76a66253 | j_mayer | |
4483 | 76a66253 | j_mayer | /* dozo - dozo. */
|
4484 | 99e300ef | Blue Swirl | static void gen_dozo(DisasContext *ctx) |
4485 | 76a66253 | j_mayer | { |
4486 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4487 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4488 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4489 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4490 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4491 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4492 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4493 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4494 | 22e0e173 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4495 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4496 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
4497 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4498 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4499 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4500 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4501 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4502 | 22e0e173 | aurel32 | gen_set_label(l1); |
4503 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4504 | 22e0e173 | aurel32 | gen_set_label(l2); |
4505 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4506 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4507 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4508 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4509 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4510 | 76a66253 | j_mayer | } |
4511 | 76a66253 | j_mayer | |
4512 | 76a66253 | j_mayer | /* dozi */
|
4513 | 99e300ef | Blue Swirl | static void gen_dozi(DisasContext *ctx) |
4514 | 76a66253 | j_mayer | { |
4515 | 22e0e173 | aurel32 | target_long simm = SIMM(ctx->opcode); |
4516 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4517 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4518 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4519 | 22e0e173 | aurel32 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
4520 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4521 | 22e0e173 | aurel32 | gen_set_label(l1); |
4522 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4523 | 22e0e173 | aurel32 | gen_set_label(l2); |
4524 | 22e0e173 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
4525 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4526 | 76a66253 | j_mayer | } |
4527 | 76a66253 | j_mayer | |
4528 | 76a66253 | j_mayer | /* lscbx - lscbx. */
|
4529 | 99e300ef | Blue Swirl | static void gen_lscbx(DisasContext *ctx) |
4530 | 76a66253 | j_mayer | { |
4531 | bdb4b689 | aurel32 | TCGv t0 = tcg_temp_new(); |
4532 | bdb4b689 | aurel32 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
4533 | bdb4b689 | aurel32 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
4534 | bdb4b689 | aurel32 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
4535 | 76a66253 | j_mayer | |
4536 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4537 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4538 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4539 | bdb4b689 | aurel32 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
4540 | bdb4b689 | aurel32 | tcg_temp_free_i32(t1); |
4541 | bdb4b689 | aurel32 | tcg_temp_free_i32(t2); |
4542 | bdb4b689 | aurel32 | tcg_temp_free_i32(t3); |
4543 | 3d7b417e | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
|
4544 | bdb4b689 | aurel32 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
4545 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4546 | bdb4b689 | aurel32 | gen_set_Rc0(ctx, t0); |
4547 | bdb4b689 | aurel32 | tcg_temp_free(t0); |
4548 | 76a66253 | j_mayer | } |
4549 | 76a66253 | j_mayer | |
4550 | 76a66253 | j_mayer | /* maskg - maskg. */
|
4551 | 99e300ef | Blue Swirl | static void gen_maskg(DisasContext *ctx) |
4552 | 76a66253 | j_mayer | { |
4553 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4554 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4555 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4556 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4557 | 22e0e173 | aurel32 | TCGv t3 = tcg_temp_new(); |
4558 | 22e0e173 | aurel32 | tcg_gen_movi_tl(t3, 0xFFFFFFFF);
|
4559 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4560 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
|
4561 | 22e0e173 | aurel32 | tcg_gen_addi_tl(t2, t0, 1);
|
4562 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t2, t3, t2); |
4563 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t3, t3, t1); |
4564 | 22e0e173 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
4565 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
4566 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4567 | 22e0e173 | aurel32 | gen_set_label(l1); |
4568 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4569 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4570 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4571 | 22e0e173 | aurel32 | tcg_temp_free(t3); |
4572 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4573 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4574 | 76a66253 | j_mayer | } |
4575 | 76a66253 | j_mayer | |
4576 | 76a66253 | j_mayer | /* maskir - maskir. */
|
4577 | 99e300ef | Blue Swirl | static void gen_maskir(DisasContext *ctx) |
4578 | 76a66253 | j_mayer | { |
4579 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4580 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4581 | 22e0e173 | aurel32 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4582 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4583 | 22e0e173 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4584 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4585 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4586 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4587 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4588 | 76a66253 | j_mayer | } |
4589 | 76a66253 | j_mayer | |
4590 | 76a66253 | j_mayer | /* mul - mul. */
|
4591 | 99e300ef | Blue Swirl | static void gen_mul(DisasContext *ctx) |
4592 | 76a66253 | j_mayer | { |
4593 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4594 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4595 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4596 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4597 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4598 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4599 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4600 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4601 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4602 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4603 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4604 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4605 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4606 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4607 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4608 | 76a66253 | j_mayer | } |
4609 | 76a66253 | j_mayer | |
4610 | 76a66253 | j_mayer | /* mulo - mulo. */
|
4611 | 99e300ef | Blue Swirl | static void gen_mulo(DisasContext *ctx) |
4612 | 76a66253 | j_mayer | { |
4613 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4614 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4615 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4616 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4617 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4618 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4619 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4620 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4621 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4622 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4623 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4624 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4625 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4626 | 22e0e173 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
4627 | 22e0e173 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
4628 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4629 | 22e0e173 | aurel32 | gen_set_label(l1); |
4630 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4631 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4632 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4633 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4634 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4635 | 76a66253 | j_mayer | } |
4636 | 76a66253 | j_mayer | |
4637 | 76a66253 | j_mayer | /* nabs - nabs. */
|
4638 | 99e300ef | Blue Swirl | static void gen_nabs(DisasContext *ctx) |
4639 | 76a66253 | j_mayer | { |
4640 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4641 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4642 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4643 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4644 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4645 | 22e0e173 | aurel32 | gen_set_label(l1); |
4646 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4647 | 22e0e173 | aurel32 | gen_set_label(l2); |
4648 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4649 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4650 | 76a66253 | j_mayer | } |
4651 | 76a66253 | j_mayer | |
4652 | 76a66253 | j_mayer | /* nabso - nabso. */
|
4653 | 99e300ef | Blue Swirl | static void gen_nabso(DisasContext *ctx) |
4654 | 76a66253 | j_mayer | { |
4655 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4656 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4657 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4658 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4659 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4660 | 22e0e173 | aurel32 | gen_set_label(l1); |
4661 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4662 | 22e0e173 | aurel32 | gen_set_label(l2); |
4663 | 22e0e173 | aurel32 | /* nabs never overflows */
|
4664 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4665 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4666 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4667 | 76a66253 | j_mayer | } |
4668 | 76a66253 | j_mayer | |
4669 | 76a66253 | j_mayer | /* rlmi - rlmi. */
|
4670 | 99e300ef | Blue Swirl | static void gen_rlmi(DisasContext *ctx) |
4671 | 76a66253 | j_mayer | { |
4672 | 7487953d | aurel32 | uint32_t mb = MB(ctx->opcode); |
4673 | 7487953d | aurel32 | uint32_t me = ME(ctx->opcode); |
4674 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4675 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4676 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4677 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
4678 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); |
4679 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
4680 | 7487953d | aurel32 | tcg_temp_free(t0); |
4681 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4682 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4683 | 76a66253 | j_mayer | } |
4684 | 76a66253 | j_mayer | |
4685 | 76a66253 | j_mayer | /* rrib - rrib. */
|
4686 | 99e300ef | Blue Swirl | static void gen_rrib(DisasContext *ctx) |
4687 | 76a66253 | j_mayer | { |
4688 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4689 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4690 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4691 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0x80000000);
|
4692 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4693 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4694 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4695 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
4696 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4697 | 7487953d | aurel32 | tcg_temp_free(t0); |
4698 | 7487953d | aurel32 | tcg_temp_free(t1); |
4699 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4700 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4701 | 76a66253 | j_mayer | } |
4702 | 76a66253 | j_mayer | |
4703 | 76a66253 | j_mayer | /* sle - sle. */
|
4704 | 99e300ef | Blue Swirl | static void gen_sle(DisasContext *ctx) |
4705 | 76a66253 | j_mayer | { |
4706 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4707 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4708 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4709 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4710 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4711 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4712 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4713 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4714 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4715 | 7487953d | aurel32 | tcg_temp_free(t0); |
4716 | 7487953d | aurel32 | tcg_temp_free(t1); |
4717 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4718 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4719 | 76a66253 | j_mayer | } |
4720 | 76a66253 | j_mayer | |
4721 | 76a66253 | j_mayer | /* sleq - sleq. */
|
4722 | 99e300ef | Blue Swirl | static void gen_sleq(DisasContext *ctx) |
4723 | 76a66253 | j_mayer | { |
4724 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4725 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4726 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4727 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4728 | 7487953d | aurel32 | tcg_gen_movi_tl(t2, 0xFFFFFFFF);
|
4729 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, t2, t0); |
4730 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4731 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4732 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4733 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
4734 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4735 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4736 | 7487953d | aurel32 | tcg_temp_free(t0); |
4737 | 7487953d | aurel32 | tcg_temp_free(t1); |
4738 | 7487953d | aurel32 | tcg_temp_free(t2); |
4739 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4740 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4741 | 76a66253 | j_mayer | } |
4742 | 76a66253 | j_mayer | |
4743 | 76a66253 | j_mayer | /* sliq - sliq. */
|
4744 | 99e300ef | Blue Swirl | static void gen_sliq(DisasContext *ctx) |
4745 | 76a66253 | j_mayer | { |
4746 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4747 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4748 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4749 | 7487953d | aurel32 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4750 | 7487953d | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4751 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4752 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4753 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4754 | 7487953d | aurel32 | tcg_temp_free(t0); |
4755 | 7487953d | aurel32 | tcg_temp_free(t1); |
4756 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4757 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4758 | 76a66253 | j_mayer | } |
4759 | 76a66253 | j_mayer | |
4760 | 76a66253 | j_mayer | /* slliq - slliq. */
|
4761 | 99e300ef | Blue Swirl | static void gen_slliq(DisasContext *ctx) |
4762 | 76a66253 | j_mayer | { |
4763 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4764 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4765 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4766 | 7487953d | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4767 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4768 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4769 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
|
4770 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
|
4771 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4772 | 7487953d | aurel32 | tcg_temp_free(t0); |
4773 | 7487953d | aurel32 | tcg_temp_free(t1); |
4774 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4775 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4776 | 76a66253 | j_mayer | } |
4777 | 76a66253 | j_mayer | |
4778 | 76a66253 | j_mayer | /* sllq - sllq. */
|
4779 | 99e300ef | Blue Swirl | static void gen_sllq(DisasContext *ctx) |
4780 | 76a66253 | j_mayer | { |
4781 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4782 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4783 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
4784 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4785 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4786 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4787 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4788 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, t1, t2); |
4789 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4790 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4791 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
4792 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4793 | 7487953d | aurel32 | tcg_gen_br(l2); |
4794 | 7487953d | aurel32 | gen_set_label(l1); |
4795 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4796 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4797 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t2, t1); |
4798 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4799 | 7487953d | aurel32 | gen_set_label(l2); |
4800 | 7487953d | aurel32 | tcg_temp_free(t0); |
4801 | 7487953d | aurel32 | tcg_temp_free(t1); |
4802 | 7487953d | aurel32 | tcg_temp_free(t2); |
4803 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4804 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4805 | 76a66253 | j_mayer | } |
4806 | 76a66253 | j_mayer | |
4807 | 76a66253 | j_mayer | /* slq - slq. */
|
4808 | 99e300ef | Blue Swirl | static void gen_slq(DisasContext *ctx) |
4809 | 76a66253 | j_mayer | { |
4810 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4811 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4812 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4813 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4814 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4815 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4816 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4817 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4818 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4819 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4820 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4821 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4822 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
4823 | 7487953d | aurel32 | gen_set_label(l1); |
4824 | 7487953d | aurel32 | tcg_temp_free(t0); |
4825 | 7487953d | aurel32 | tcg_temp_free(t1); |
4826 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4827 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4828 | 76a66253 | j_mayer | } |
4829 | 76a66253 | j_mayer | |
4830 | d9bce9d9 | j_mayer | /* sraiq - sraiq. */
|
4831 | 99e300ef | Blue Swirl | static void gen_sraiq(DisasContext *ctx) |
4832 | 76a66253 | j_mayer | { |
4833 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4834 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4835 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4836 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4837 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4838 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4839 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
4840 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4841 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4842 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4843 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
4844 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4845 | 7487953d | aurel32 | gen_set_label(l1); |
4846 | 7487953d | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
4847 | 7487953d | aurel32 | tcg_temp_free(t0); |
4848 | 7487953d | aurel32 | tcg_temp_free(t1); |
4849 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4850 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4851 | 76a66253 | j_mayer | } |
4852 | 76a66253 | j_mayer | |
4853 | 76a66253 | j_mayer | /* sraq - sraq. */
|
4854 | 99e300ef | Blue Swirl | static void gen_sraq(DisasContext *ctx) |
4855 | 76a66253 | j_mayer | { |
4856 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4857 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4858 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4859 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4860 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4861 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4862 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4863 | 7487953d | aurel32 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
4864 | 7487953d | aurel32 | tcg_gen_subfi_tl(t2, 32, t2);
|
4865 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
4866 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t2); |
4867 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4868 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4869 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
|
4870 | 7487953d | aurel32 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
4871 | 7487953d | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
|
4872 | 7487953d | aurel32 | gen_set_label(l1); |
4873 | 7487953d | aurel32 | tcg_temp_free(t0); |
4874 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
4875 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4876 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4877 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
|
4878 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4879 | 7487953d | aurel32 | gen_set_label(l2); |
4880 | 7487953d | aurel32 | tcg_temp_free(t1); |
4881 | 7487953d | aurel32 | tcg_temp_free(t2); |
4882 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4883 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4884 | 76a66253 | j_mayer | } |
4885 | 76a66253 | j_mayer | |
4886 | 76a66253 | j_mayer | /* sre - sre. */
|
4887 | 99e300ef | Blue Swirl | static void gen_sre(DisasContext *ctx) |
4888 | 76a66253 | j_mayer | { |
4889 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4890 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4891 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4892 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4893 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4894 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4895 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4896 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4897 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4898 | 7487953d | aurel32 | tcg_temp_free(t0); |
4899 | 7487953d | aurel32 | tcg_temp_free(t1); |
4900 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4901 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4902 | 76a66253 | j_mayer | } |
4903 | 76a66253 | j_mayer | |
4904 | 76a66253 | j_mayer | /* srea - srea. */
|
4905 | 99e300ef | Blue Swirl | static void gen_srea(DisasContext *ctx) |
4906 | 76a66253 | j_mayer | { |
4907 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4908 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4909 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4910 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4911 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4912 | 7487953d | aurel32 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
4913 | 7487953d | aurel32 | tcg_temp_free(t0); |
4914 | 7487953d | aurel32 | tcg_temp_free(t1); |
4915 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4916 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4917 | 76a66253 | j_mayer | } |
4918 | 76a66253 | j_mayer | |
4919 | 76a66253 | j_mayer | /* sreq */
|
4920 | 99e300ef | Blue Swirl | static void gen_sreq(DisasContext *ctx) |
4921 | 76a66253 | j_mayer | { |
4922 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4923 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4924 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4925 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4926 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4927 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4928 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4929 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4930 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4931 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4932 | 7487953d | aurel32 | tcg_gen_andc_tl(t2, t2, t1); |
4933 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
4934 | 7487953d | aurel32 | tcg_temp_free(t0); |
4935 | 7487953d | aurel32 | tcg_temp_free(t1); |
4936 | 7487953d | aurel32 | tcg_temp_free(t2); |
4937 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4938 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4939 | 76a66253 | j_mayer | } |
4940 | 76a66253 | j_mayer | |
4941 | 76a66253 | j_mayer | /* sriq */
|
4942 | 99e300ef | Blue Swirl | static void gen_sriq(DisasContext *ctx) |
4943 | 76a66253 | j_mayer | { |
4944 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4945 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4946 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4947 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4948 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4949 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4950 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4951 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4952 | 7487953d | aurel32 | tcg_temp_free(t0); |
4953 | 7487953d | aurel32 | tcg_temp_free(t1); |
4954 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4955 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4956 | 76a66253 | j_mayer | } |
4957 | 76a66253 | j_mayer | |
4958 | 76a66253 | j_mayer | /* srliq */
|
4959 | 99e300ef | Blue Swirl | static void gen_srliq(DisasContext *ctx) |
4960 | 76a66253 | j_mayer | { |
4961 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4962 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4963 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4964 | 7487953d | aurel32 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4965 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4966 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4967 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
|
4968 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
|
4969 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4970 | 7487953d | aurel32 | tcg_temp_free(t0); |
4971 | 7487953d | aurel32 | tcg_temp_free(t1); |
4972 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4973 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4974 | 76a66253 | j_mayer | } |
4975 | 76a66253 | j_mayer | |
4976 | 76a66253 | j_mayer | /* srlq */
|
4977 | 99e300ef | Blue Swirl | static void gen_srlq(DisasContext *ctx) |
4978 | 76a66253 | j_mayer | { |
4979 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4980 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4981 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
4982 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4983 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4984 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4985 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4986 | 7487953d | aurel32 | tcg_gen_shr_tl(t2, t1, t2); |
4987 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4988 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4989 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
4990 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
4991 | 7487953d | aurel32 | tcg_gen_br(l2); |
4992 | 7487953d | aurel32 | gen_set_label(l1); |
4993 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4994 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
4995 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4996 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4997 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4998 | 7487953d | aurel32 | gen_set_label(l2); |
4999 | 7487953d | aurel32 | tcg_temp_free(t0); |
5000 | 7487953d | aurel32 | tcg_temp_free(t1); |
5001 | 7487953d | aurel32 | tcg_temp_free(t2); |
5002 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5003 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5004 | 76a66253 | j_mayer | } |
5005 | 76a66253 | j_mayer | |
5006 | 76a66253 | j_mayer | /* srq */
|
5007 | 99e300ef | Blue Swirl | static void gen_srq(DisasContext *ctx) |
5008 | 76a66253 | j_mayer | { |
5009 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5010 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5011 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5012 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5013 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5014 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5015 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5016 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5017 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5018 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5019 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5020 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5021 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
5022 | 7487953d | aurel32 | gen_set_label(l1); |
5023 | 7487953d | aurel32 | tcg_temp_free(t0); |
5024 | 7487953d | aurel32 | tcg_temp_free(t1); |
5025 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5026 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5027 | 76a66253 | j_mayer | } |
5028 | 76a66253 | j_mayer | |
5029 | 76a66253 | j_mayer | /* PowerPC 602 specific instructions */
|
5030 | 99e300ef | Blue Swirl | |
5031 | 54623277 | Blue Swirl | /* dsa */
|
5032 | 99e300ef | Blue Swirl | static void gen_dsa(DisasContext *ctx) |
5033 | 76a66253 | j_mayer | { |
5034 | 76a66253 | j_mayer | /* XXX: TODO */
|
5035 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5036 | 76a66253 | j_mayer | } |
5037 | 76a66253 | j_mayer | |
5038 | 76a66253 | j_mayer | /* esa */
|
5039 | 99e300ef | Blue Swirl | static void gen_esa(DisasContext *ctx) |
5040 | 76a66253 | j_mayer | { |
5041 | 76a66253 | j_mayer | /* XXX: TODO */
|
5042 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5043 | 76a66253 | j_mayer | } |
5044 | 76a66253 | j_mayer | |
5045 | 76a66253 | j_mayer | /* mfrom */
|
5046 | 99e300ef | Blue Swirl | static void gen_mfrom(DisasContext *ctx) |
5047 | 76a66253 | j_mayer | { |
5048 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5049 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5050 | 76a66253 | j_mayer | #else
|
5051 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5052 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5053 | 76a66253 | j_mayer | return;
|
5054 | 76a66253 | j_mayer | } |
5055 | cf02a65c | aurel32 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5056 | 76a66253 | j_mayer | #endif
|
5057 | 76a66253 | j_mayer | } |
5058 | 76a66253 | j_mayer | |
5059 | 76a66253 | j_mayer | /* 602 - 603 - G2 TLB management */
|
5060 | e8eaa2c0 | Blue Swirl | |
5061 | 54623277 | Blue Swirl | /* tlbld */
|
5062 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_6xx(DisasContext *ctx) |
5063 | 76a66253 | j_mayer | { |
5064 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5065 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5066 | 76a66253 | j_mayer | #else
|
5067 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5068 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5069 | 76a66253 | j_mayer | return;
|
5070 | 76a66253 | j_mayer | } |
5071 | 74d37793 | aurel32 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5072 | 76a66253 | j_mayer | #endif
|
5073 | 76a66253 | j_mayer | } |
5074 | 76a66253 | j_mayer | |
5075 | 76a66253 | j_mayer | /* tlbli */
|
5076 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_6xx(DisasContext *ctx) |
5077 | 76a66253 | j_mayer | { |
5078 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5079 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5080 | 76a66253 | j_mayer | #else
|
5081 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5082 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5083 | 76a66253 | j_mayer | return;
|
5084 | 76a66253 | j_mayer | } |
5085 | 74d37793 | aurel32 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5086 | 76a66253 | j_mayer | #endif
|
5087 | 76a66253 | j_mayer | } |
5088 | 76a66253 | j_mayer | |
5089 | 7dbe11ac | j_mayer | /* 74xx TLB management */
|
5090 | e8eaa2c0 | Blue Swirl | |
5091 | 54623277 | Blue Swirl | /* tlbld */
|
5092 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_74xx(DisasContext *ctx) |
5093 | 7dbe11ac | j_mayer | { |
5094 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5095 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5096 | 7dbe11ac | j_mayer | #else
|
5097 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5098 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5099 | 7dbe11ac | j_mayer | return;
|
5100 | 7dbe11ac | j_mayer | } |
5101 | 74d37793 | aurel32 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5102 | 7dbe11ac | j_mayer | #endif
|
5103 | 7dbe11ac | j_mayer | } |
5104 | 7dbe11ac | j_mayer | |
5105 | 7dbe11ac | j_mayer | /* tlbli */
|
5106 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_74xx(DisasContext *ctx) |
5107 | 7dbe11ac | j_mayer | { |
5108 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5109 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5110 | 7dbe11ac | j_mayer | #else
|
5111 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5112 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5113 | 7dbe11ac | j_mayer | return;
|
5114 | 7dbe11ac | j_mayer | } |
5115 | 74d37793 | aurel32 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5116 | 7dbe11ac | j_mayer | #endif
|
5117 | 7dbe11ac | j_mayer | } |
5118 | 7dbe11ac | j_mayer | |
5119 | 76a66253 | j_mayer | /* POWER instructions not in PowerPC 601 */
|
5120 | 99e300ef | Blue Swirl | |
5121 | 54623277 | Blue Swirl | /* clf */
|
5122 | 99e300ef | Blue Swirl | static void gen_clf(DisasContext *ctx) |
5123 | 76a66253 | j_mayer | { |
5124 | 76a66253 | j_mayer | /* Cache line flush: implemented as no-op */
|
5125 | 76a66253 | j_mayer | } |
5126 | 76a66253 | j_mayer | |
5127 | 76a66253 | j_mayer | /* cli */
|
5128 | 99e300ef | Blue Swirl | static void gen_cli(DisasContext *ctx) |
5129 | 76a66253 | j_mayer | { |
5130 | 7f75ffd3 | blueswir1 | /* Cache line invalidate: privileged and treated as no-op */
|
5131 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5132 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5133 | 76a66253 | j_mayer | #else
|
5134 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5135 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5136 | 76a66253 | j_mayer | return;
|
5137 | 76a66253 | j_mayer | } |
5138 | 76a66253 | j_mayer | #endif
|
5139 | 76a66253 | j_mayer | } |
5140 | 76a66253 | j_mayer | |
5141 | 76a66253 | j_mayer | /* dclst */
|
5142 | 99e300ef | Blue Swirl | static void gen_dclst(DisasContext *ctx) |
5143 | 76a66253 | j_mayer | { |
5144 | 76a66253 | j_mayer | /* Data cache line store: treated as no-op */
|
5145 | 76a66253 | j_mayer | } |
5146 | 76a66253 | j_mayer | |
5147 | 99e300ef | Blue Swirl | static void gen_mfsri(DisasContext *ctx) |
5148 | 76a66253 | j_mayer | { |
5149 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5150 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5151 | 76a66253 | j_mayer | #else
|
5152 | 74d37793 | aurel32 | int ra = rA(ctx->opcode);
|
5153 | 74d37793 | aurel32 | int rd = rD(ctx->opcode);
|
5154 | 74d37793 | aurel32 | TCGv t0; |
5155 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5156 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5157 | 76a66253 | j_mayer | return;
|
5158 | 76a66253 | j_mayer | } |
5159 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5160 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5161 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, t0, 28);
|
5162 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
5163 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rd], t0); |
5164 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5165 | 76a66253 | j_mayer | if (ra != 0 && ra != rd) |
5166 | 74d37793 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
5167 | 76a66253 | j_mayer | #endif
|
5168 | 76a66253 | j_mayer | } |
5169 | 76a66253 | j_mayer | |
5170 | 99e300ef | Blue Swirl | static void gen_rac(DisasContext *ctx) |
5171 | 76a66253 | j_mayer | { |
5172 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5173 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5174 | 76a66253 | j_mayer | #else
|
5175 | 22e0e173 | aurel32 | TCGv t0; |
5176 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5177 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5178 | 76a66253 | j_mayer | return;
|
5179 | 76a66253 | j_mayer | } |
5180 | 22e0e173 | aurel32 | t0 = tcg_temp_new(); |
5181 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5182 | 22e0e173 | aurel32 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
5183 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
5184 | 76a66253 | j_mayer | #endif
|
5185 | 76a66253 | j_mayer | } |
5186 | 76a66253 | j_mayer | |
5187 | 99e300ef | Blue Swirl | static void gen_rfsvc(DisasContext *ctx) |
5188 | 76a66253 | j_mayer | { |
5189 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5190 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5191 | 76a66253 | j_mayer | #else
|
5192 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5193 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5194 | 76a66253 | j_mayer | return;
|
5195 | 76a66253 | j_mayer | } |
5196 | d72a19f7 | aurel32 | gen_helper_rfsvc(); |
5197 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5198 | 76a66253 | j_mayer | #endif
|
5199 | 76a66253 | j_mayer | } |
5200 | 76a66253 | j_mayer | |
5201 | 76a66253 | j_mayer | /* svc is not implemented for now */
|
5202 | 76a66253 | j_mayer | |
5203 | 76a66253 | j_mayer | /* POWER2 specific instructions */
|
5204 | 76a66253 | j_mayer | /* Quad manipulation (load/store two floats at a time) */
|
5205 | 76a66253 | j_mayer | |
5206 | 76a66253 | j_mayer | /* lfq */
|
5207 | 99e300ef | Blue Swirl | static void gen_lfq(DisasContext *ctx) |
5208 | 76a66253 | j_mayer | { |
5209 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5210 | 76db3ba4 | aurel32 | TCGv t0; |
5211 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5212 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5213 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5214 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5215 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5216 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5217 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5218 | 76a66253 | j_mayer | } |
5219 | 76a66253 | j_mayer | |
5220 | 76a66253 | j_mayer | /* lfqu */
|
5221 | 99e300ef | Blue Swirl | static void gen_lfqu(DisasContext *ctx) |
5222 | 76a66253 | j_mayer | { |
5223 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5224 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5225 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5226 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5227 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5228 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5229 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5230 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5231 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5232 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5233 | 76a66253 | j_mayer | if (ra != 0) |
5234 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5235 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5236 | 01a4afeb | aurel32 | tcg_temp_free(t1); |
5237 | 76a66253 | j_mayer | } |
5238 | 76a66253 | j_mayer | |
5239 | 76a66253 | j_mayer | /* lfqux */
|
5240 | 99e300ef | Blue Swirl | static void gen_lfqux(DisasContext *ctx) |
5241 | 76a66253 | j_mayer | { |
5242 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5243 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5244 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5245 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5246 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5247 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5248 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5249 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5250 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5251 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5252 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5253 | 76a66253 | j_mayer | if (ra != 0) |
5254 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5255 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5256 | 76a66253 | j_mayer | } |
5257 | 76a66253 | j_mayer | |
5258 | 76a66253 | j_mayer | /* lfqx */
|
5259 | 99e300ef | Blue Swirl | static void gen_lfqx(DisasContext *ctx) |
5260 | 76a66253 | j_mayer | { |
5261 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5262 | 76db3ba4 | aurel32 | TCGv t0; |
5263 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5264 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5265 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5266 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5267 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5268 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5269 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5270 | 76a66253 | j_mayer | } |
5271 | 76a66253 | j_mayer | |
5272 | 76a66253 | j_mayer | /* stfq */
|
5273 | 99e300ef | Blue Swirl | static void gen_stfq(DisasContext *ctx) |
5274 | 76a66253 | j_mayer | { |
5275 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5276 | 76db3ba4 | aurel32 | TCGv t0; |
5277 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5278 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5279 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5280 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5281 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5282 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5283 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5284 | 76a66253 | j_mayer | } |
5285 | 76a66253 | j_mayer | |
5286 | 76a66253 | j_mayer | /* stfqu */
|
5287 | 99e300ef | Blue Swirl | static void gen_stfqu(DisasContext *ctx) |
5288 | 76a66253 | j_mayer | { |
5289 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5290 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5291 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5292 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5293 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5294 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5295 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5296 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5297 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5298 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5299 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5300 | 76a66253 | j_mayer | if (ra != 0) |
5301 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5302 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5303 | 76a66253 | j_mayer | } |
5304 | 76a66253 | j_mayer | |
5305 | 76a66253 | j_mayer | /* stfqux */
|
5306 | 99e300ef | Blue Swirl | static void gen_stfqux(DisasContext *ctx) |
5307 | 76a66253 | j_mayer | { |
5308 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5309 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5310 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5311 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5312 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5313 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5314 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5315 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5316 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5317 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5318 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5319 | 76a66253 | j_mayer | if (ra != 0) |
5320 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5321 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5322 | 76a66253 | j_mayer | } |
5323 | 76a66253 | j_mayer | |
5324 | 76a66253 | j_mayer | /* stfqx */
|
5325 | 99e300ef | Blue Swirl | static void gen_stfqx(DisasContext *ctx) |
5326 | 76a66253 | j_mayer | { |
5327 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5328 | 76db3ba4 | aurel32 | TCGv t0; |
5329 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5330 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5331 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5332 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5333 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5334 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5335 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5336 | 76a66253 | j_mayer | } |
5337 | 76a66253 | j_mayer | |
5338 | 76a66253 | j_mayer | /* BookE specific instructions */
|
5339 | 99e300ef | Blue Swirl | |
5340 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5341 | 99e300ef | Blue Swirl | static void gen_mfapidi(DisasContext *ctx) |
5342 | 76a66253 | j_mayer | { |
5343 | 76a66253 | j_mayer | /* XXX: TODO */
|
5344 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5345 | 76a66253 | j_mayer | } |
5346 | 76a66253 | j_mayer | |
5347 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5348 | 99e300ef | Blue Swirl | static void gen_tlbiva(DisasContext *ctx) |
5349 | 76a66253 | j_mayer | { |
5350 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5351 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5352 | 76a66253 | j_mayer | #else
|
5353 | 74d37793 | aurel32 | TCGv t0; |
5354 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5355 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5356 | 76a66253 | j_mayer | return;
|
5357 | 76a66253 | j_mayer | } |
5358 | ec72e276 | aurel32 | t0 = tcg_temp_new(); |
5359 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5360 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
5361 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5362 | 76a66253 | j_mayer | #endif
|
5363 | 76a66253 | j_mayer | } |
5364 | 76a66253 | j_mayer | |
5365 | 76a66253 | j_mayer | /* All 405 MAC instructions are translated here */
|
5366 | 636aa200 | Blue Swirl | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5367 | 636aa200 | Blue Swirl | int ra, int rb, int rt, int Rc) |
5368 | 76a66253 | j_mayer | { |
5369 | 182608d4 | aurel32 | TCGv t0, t1; |
5370 | 182608d4 | aurel32 | |
5371 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
5372 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
5373 | 182608d4 | aurel32 | |
5374 | 76a66253 | j_mayer | switch (opc3 & 0x0D) { |
5375 | 76a66253 | j_mayer | case 0x05: |
5376 | 76a66253 | j_mayer | /* macchw - macchw. - macchwo - macchwo. */
|
5377 | 76a66253 | j_mayer | /* macchws - macchws. - macchwso - macchwso. */
|
5378 | 76a66253 | j_mayer | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
5379 | 76a66253 | j_mayer | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
5380 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5381 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5382 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5383 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5384 | 76a66253 | j_mayer | break;
|
5385 | 76a66253 | j_mayer | case 0x04: |
5386 | 76a66253 | j_mayer | /* macchwu - macchwu. - macchwuo - macchwuo. */
|
5387 | 76a66253 | j_mayer | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
5388 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5389 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5390 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5391 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5392 | 76a66253 | j_mayer | break;
|
5393 | 76a66253 | j_mayer | case 0x01: |
5394 | 76a66253 | j_mayer | /* machhw - machhw. - machhwo - machhwo. */
|
5395 | 76a66253 | j_mayer | /* machhws - machhws. - machhwso - machhwso. */
|
5396 | 76a66253 | j_mayer | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
5397 | 76a66253 | j_mayer | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
5398 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5399 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
|
5400 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, t0); |
5401 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5402 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5403 | 76a66253 | j_mayer | break;
|
5404 | 76a66253 | j_mayer | case 0x00: |
5405 | 76a66253 | j_mayer | /* machhwu - machhwu. - machhwuo - machhwuo. */
|
5406 | 76a66253 | j_mayer | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
5407 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5408 | 182608d4 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
|
5409 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, t0); |
5410 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5411 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5412 | 76a66253 | j_mayer | break;
|
5413 | 76a66253 | j_mayer | case 0x0D: |
5414 | 76a66253 | j_mayer | /* maclhw - maclhw. - maclhwo - maclhwo. */
|
5415 | 76a66253 | j_mayer | /* maclhws - maclhws. - maclhwso - maclhwso. */
|
5416 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
5417 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
5418 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5419 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5420 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
5421 | 76a66253 | j_mayer | break;
|
5422 | 76a66253 | j_mayer | case 0x0C: |
5423 | 76a66253 | j_mayer | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
5424 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
5425 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5426 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5427 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
5428 | 76a66253 | j_mayer | break;
|
5429 | 76a66253 | j_mayer | } |
5430 | 76a66253 | j_mayer | if (opc2 & 0x04) { |
5431 | 182608d4 | aurel32 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */
|
5432 | 182608d4 | aurel32 | tcg_gen_mul_tl(t1, t0, t1); |
5433 | 182608d4 | aurel32 | if (opc2 & 0x02) { |
5434 | 182608d4 | aurel32 | /* nmultiply-and-accumulate (0x0E) */
|
5435 | 182608d4 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
5436 | 182608d4 | aurel32 | } else {
|
5437 | 182608d4 | aurel32 | /* multiply-and-accumulate (0x0C) */
|
5438 | 182608d4 | aurel32 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
5439 | 182608d4 | aurel32 | } |
5440 | 182608d4 | aurel32 | |
5441 | 182608d4 | aurel32 | if (opc3 & 0x12) { |
5442 | 182608d4 | aurel32 | /* Check overflow and/or saturate */
|
5443 | 182608d4 | aurel32 | int l1 = gen_new_label();
|
5444 | 182608d4 | aurel32 | |
5445 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5446 | 182608d4 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
5447 | 182608d4 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
5448 | 182608d4 | aurel32 | } |
5449 | 182608d4 | aurel32 | if (opc3 & 0x01) { |
5450 | 182608d4 | aurel32 | /* Signed */
|
5451 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
5452 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
|
5453 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
5454 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
5455 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5456 | 182608d4 | aurel32 | /* Saturate */
|
5457 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
|
5458 | 182608d4 | aurel32 | tcg_gen_xori_tl(t0, t0, 0x7fffffff);
|
5459 | 182608d4 | aurel32 | } |
5460 | 182608d4 | aurel32 | } else {
|
5461 | 182608d4 | aurel32 | /* Unsigned */
|
5462 | 182608d4 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
5463 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5464 | 182608d4 | aurel32 | /* Saturate */
|
5465 | 182608d4 | aurel32 | tcg_gen_movi_tl(t0, UINT32_MAX); |
5466 | 182608d4 | aurel32 | } |
5467 | 182608d4 | aurel32 | } |
5468 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5469 | 182608d4 | aurel32 | /* Check overflow */
|
5470 | 182608d4 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
5471 | 182608d4 | aurel32 | } |
5472 | 182608d4 | aurel32 | gen_set_label(l1); |
5473 | 182608d4 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
5474 | 182608d4 | aurel32 | } |
5475 | 182608d4 | aurel32 | } else {
|
5476 | 182608d4 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
5477 | 76a66253 | j_mayer | } |
5478 | 182608d4 | aurel32 | tcg_temp_free(t0); |
5479 | 182608d4 | aurel32 | tcg_temp_free(t1); |
5480 | 76a66253 | j_mayer | if (unlikely(Rc) != 0) { |
5481 | 76a66253 | j_mayer | /* Update Rc0 */
|
5482 | 182608d4 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
5483 | 76a66253 | j_mayer | } |
5484 | 76a66253 | j_mayer | } |
5485 | 76a66253 | j_mayer | |
5486 | a750fc0b | j_mayer | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
5487 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
5488 | 76a66253 | j_mayer | { \ |
5489 | 76a66253 | j_mayer | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
5490 | 76a66253 | j_mayer | rD(ctx->opcode), Rc(ctx->opcode)); \ |
5491 | 76a66253 | j_mayer | } |
5492 | 76a66253 | j_mayer | |
5493 | 76a66253 | j_mayer | /* macchw - macchw. */
|
5494 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
5495 | 76a66253 | j_mayer | /* macchwo - macchwo. */
|
5496 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
5497 | 76a66253 | j_mayer | /* macchws - macchws. */
|
5498 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
5499 | 76a66253 | j_mayer | /* macchwso - macchwso. */
|
5500 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
5501 | 76a66253 | j_mayer | /* macchwsu - macchwsu. */
|
5502 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
5503 | 76a66253 | j_mayer | /* macchwsuo - macchwsuo. */
|
5504 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
5505 | 76a66253 | j_mayer | /* macchwu - macchwu. */
|
5506 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
5507 | 76a66253 | j_mayer | /* macchwuo - macchwuo. */
|
5508 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
5509 | 76a66253 | j_mayer | /* machhw - machhw. */
|
5510 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
5511 | 76a66253 | j_mayer | /* machhwo - machhwo. */
|
5512 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
5513 | 76a66253 | j_mayer | /* machhws - machhws. */
|
5514 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
5515 | 76a66253 | j_mayer | /* machhwso - machhwso. */
|
5516 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
5517 | 76a66253 | j_mayer | /* machhwsu - machhwsu. */
|
5518 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
5519 | 76a66253 | j_mayer | /* machhwsuo - machhwsuo. */
|
5520 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
5521 | 76a66253 | j_mayer | /* machhwu - machhwu. */
|
5522 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
5523 | 76a66253 | j_mayer | /* machhwuo - machhwuo. */
|
5524 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
5525 | 76a66253 | j_mayer | /* maclhw - maclhw. */
|
5526 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
5527 | 76a66253 | j_mayer | /* maclhwo - maclhwo. */
|
5528 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
5529 | 76a66253 | j_mayer | /* maclhws - maclhws. */
|
5530 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
5531 | 76a66253 | j_mayer | /* maclhwso - maclhwso. */
|
5532 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
5533 | 76a66253 | j_mayer | /* maclhwu - maclhwu. */
|
5534 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
5535 | 76a66253 | j_mayer | /* maclhwuo - maclhwuo. */
|
5536 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
5537 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. */
|
5538 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
5539 | 76a66253 | j_mayer | /* maclhwsuo - maclhwsuo. */
|
5540 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
5541 | 76a66253 | j_mayer | /* nmacchw - nmacchw. */
|
5542 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
5543 | 76a66253 | j_mayer | /* nmacchwo - nmacchwo. */
|
5544 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
5545 | 76a66253 | j_mayer | /* nmacchws - nmacchws. */
|
5546 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
5547 | 76a66253 | j_mayer | /* nmacchwso - nmacchwso. */
|
5548 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
5549 | 76a66253 | j_mayer | /* nmachhw - nmachhw. */
|
5550 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
5551 | 76a66253 | j_mayer | /* nmachhwo - nmachhwo. */
|
5552 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
5553 | 76a66253 | j_mayer | /* nmachhws - nmachhws. */
|
5554 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
5555 | 76a66253 | j_mayer | /* nmachhwso - nmachhwso. */
|
5556 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
5557 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. */
|
5558 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
5559 | 76a66253 | j_mayer | /* nmaclhwo - nmaclhwo. */
|
5560 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
5561 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. */
|
5562 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
5563 | 76a66253 | j_mayer | /* nmaclhwso - nmaclhwso. */
|
5564 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
5565 | 76a66253 | j_mayer | |
5566 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5567 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
5568 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5569 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
5570 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5571 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
5572 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5573 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
5574 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5575 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
5576 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5577 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
5578 | 76a66253 | j_mayer | |
5579 | 76a66253 | j_mayer | /* mfdcr */
|
5580 | 99e300ef | Blue Swirl | static void gen_mfdcr(DisasContext *ctx) |
5581 | 76a66253 | j_mayer | { |
5582 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5583 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5584 | 76a66253 | j_mayer | #else
|
5585 | 06dca6a7 | aurel32 | TCGv dcrn; |
5586 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5587 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5588 | 76a66253 | j_mayer | return;
|
5589 | 76a66253 | j_mayer | } |
5590 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5591 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5592 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5593 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); |
5594 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5595 | 76a66253 | j_mayer | #endif
|
5596 | 76a66253 | j_mayer | } |
5597 | 76a66253 | j_mayer | |
5598 | 76a66253 | j_mayer | /* mtdcr */
|
5599 | 99e300ef | Blue Swirl | static void gen_mtdcr(DisasContext *ctx) |
5600 | 76a66253 | j_mayer | { |
5601 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5602 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5603 | 76a66253 | j_mayer | #else
|
5604 | 06dca6a7 | aurel32 | TCGv dcrn; |
5605 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5606 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5607 | 76a66253 | j_mayer | return;
|
5608 | 76a66253 | j_mayer | } |
5609 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5610 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5611 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5612 | 06dca6a7 | aurel32 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); |
5613 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5614 | a42bd6cc | j_mayer | #endif
|
5615 | a42bd6cc | j_mayer | } |
5616 | a42bd6cc | j_mayer | |
5617 | a42bd6cc | j_mayer | /* mfdcrx */
|
5618 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5619 | 99e300ef | Blue Swirl | static void gen_mfdcrx(DisasContext *ctx) |
5620 | a42bd6cc | j_mayer | { |
5621 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5622 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5623 | a42bd6cc | j_mayer | #else
|
5624 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5625 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5626 | a42bd6cc | j_mayer | return;
|
5627 | a42bd6cc | j_mayer | } |
5628 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5629 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5630 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5631 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5632 | a42bd6cc | j_mayer | #endif
|
5633 | a42bd6cc | j_mayer | } |
5634 | a42bd6cc | j_mayer | |
5635 | a42bd6cc | j_mayer | /* mtdcrx */
|
5636 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5637 | 99e300ef | Blue Swirl | static void gen_mtdcrx(DisasContext *ctx) |
5638 | a42bd6cc | j_mayer | { |
5639 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5640 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5641 | a42bd6cc | j_mayer | #else
|
5642 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5643 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5644 | a42bd6cc | j_mayer | return;
|
5645 | a42bd6cc | j_mayer | } |
5646 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5647 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5648 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5649 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5650 | 76a66253 | j_mayer | #endif
|
5651 | 76a66253 | j_mayer | } |
5652 | 76a66253 | j_mayer | |
5653 | a750fc0b | j_mayer | /* mfdcrux (PPC 460) : user-mode access to DCR */
|
5654 | 99e300ef | Blue Swirl | static void gen_mfdcrux(DisasContext *ctx) |
5655 | a750fc0b | j_mayer | { |
5656 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5657 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5658 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5659 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5660 | a750fc0b | j_mayer | } |
5661 | a750fc0b | j_mayer | |
5662 | a750fc0b | j_mayer | /* mtdcrux (PPC 460) : user-mode access to DCR */
|
5663 | 99e300ef | Blue Swirl | static void gen_mtdcrux(DisasContext *ctx) |
5664 | a750fc0b | j_mayer | { |
5665 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5666 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5667 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5668 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5669 | a750fc0b | j_mayer | } |
5670 | a750fc0b | j_mayer | |
5671 | 76a66253 | j_mayer | /* dccci */
|
5672 | 99e300ef | Blue Swirl | static void gen_dccci(DisasContext *ctx) |
5673 | 76a66253 | j_mayer | { |
5674 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5675 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5676 | 76a66253 | j_mayer | #else
|
5677 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5678 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5679 | 76a66253 | j_mayer | return;
|
5680 | 76a66253 | j_mayer | } |
5681 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5682 | 76a66253 | j_mayer | #endif
|
5683 | 76a66253 | j_mayer | } |
5684 | 76a66253 | j_mayer | |
5685 | 76a66253 | j_mayer | /* dcread */
|
5686 | 99e300ef | Blue Swirl | static void gen_dcread(DisasContext *ctx) |
5687 | 76a66253 | j_mayer | { |
5688 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5689 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5690 | 76a66253 | j_mayer | #else
|
5691 | b61f2753 | aurel32 | TCGv EA, val; |
5692 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5693 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5694 | 76a66253 | j_mayer | return;
|
5695 | 76a66253 | j_mayer | } |
5696 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
5697 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
5698 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
5699 | a7812ae4 | pbrook | val = tcg_temp_new(); |
5700 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, val, EA); |
5701 | b61f2753 | aurel32 | tcg_temp_free(val); |
5702 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
5703 | b61f2753 | aurel32 | tcg_temp_free(EA); |
5704 | 76a66253 | j_mayer | #endif
|
5705 | 76a66253 | j_mayer | } |
5706 | 76a66253 | j_mayer | |
5707 | 76a66253 | j_mayer | /* icbt */
|
5708 | e8eaa2c0 | Blue Swirl | static void gen_icbt_40x(DisasContext *ctx) |
5709 | 76a66253 | j_mayer | { |
5710 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5711 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
5712 | 76a66253 | j_mayer | * but does not generate any exception
|
5713 | 76a66253 | j_mayer | */
|
5714 | 76a66253 | j_mayer | } |
5715 | 76a66253 | j_mayer | |
5716 | 76a66253 | j_mayer | /* iccci */
|
5717 | 99e300ef | Blue Swirl | static void gen_iccci(DisasContext *ctx) |
5718 | 76a66253 | j_mayer | { |
5719 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5720 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5721 | 76a66253 | j_mayer | #else
|
5722 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5723 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5724 | 76a66253 | j_mayer | return;
|
5725 | 76a66253 | j_mayer | } |
5726 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5727 | 76a66253 | j_mayer | #endif
|
5728 | 76a66253 | j_mayer | } |
5729 | 76a66253 | j_mayer | |
5730 | 76a66253 | j_mayer | /* icread */
|
5731 | 99e300ef | Blue Swirl | static void gen_icread(DisasContext *ctx) |
5732 | 76a66253 | j_mayer | { |
5733 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5734 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5735 | 76a66253 | j_mayer | #else
|
5736 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5737 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5738 | 76a66253 | j_mayer | return;
|
5739 | 76a66253 | j_mayer | } |
5740 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5741 | 76a66253 | j_mayer | #endif
|
5742 | 76a66253 | j_mayer | } |
5743 | 76a66253 | j_mayer | |
5744 | 76db3ba4 | aurel32 | /* rfci (mem_idx only) */
|
5745 | e8eaa2c0 | Blue Swirl | static void gen_rfci_40x(DisasContext *ctx) |
5746 | a42bd6cc | j_mayer | { |
5747 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5748 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5749 | a42bd6cc | j_mayer | #else
|
5750 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5751 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5752 | a42bd6cc | j_mayer | return;
|
5753 | a42bd6cc | j_mayer | } |
5754 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5755 | d72a19f7 | aurel32 | gen_helper_40x_rfci(); |
5756 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5757 | a42bd6cc | j_mayer | #endif
|
5758 | a42bd6cc | j_mayer | } |
5759 | a42bd6cc | j_mayer | |
5760 | 99e300ef | Blue Swirl | static void gen_rfci(DisasContext *ctx) |
5761 | a42bd6cc | j_mayer | { |
5762 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5763 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5764 | a42bd6cc | j_mayer | #else
|
5765 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5766 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5767 | a42bd6cc | j_mayer | return;
|
5768 | a42bd6cc | j_mayer | } |
5769 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5770 | d72a19f7 | aurel32 | gen_helper_rfci(); |
5771 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5772 | a42bd6cc | j_mayer | #endif
|
5773 | a42bd6cc | j_mayer | } |
5774 | a42bd6cc | j_mayer | |
5775 | a42bd6cc | j_mayer | /* BookE specific */
|
5776 | 99e300ef | Blue Swirl | |
5777 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5778 | 99e300ef | Blue Swirl | static void gen_rfdi(DisasContext *ctx) |
5779 | 76a66253 | j_mayer | { |
5780 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5781 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5782 | 76a66253 | j_mayer | #else
|
5783 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5784 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5785 | 76a66253 | j_mayer | return;
|
5786 | 76a66253 | j_mayer | } |
5787 | 76a66253 | j_mayer | /* Restore CPU state */
|
5788 | d72a19f7 | aurel32 | gen_helper_rfdi(); |
5789 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5790 | 76a66253 | j_mayer | #endif
|
5791 | 76a66253 | j_mayer | } |
5792 | 76a66253 | j_mayer | |
5793 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5794 | 99e300ef | Blue Swirl | static void gen_rfmci(DisasContext *ctx) |
5795 | a42bd6cc | j_mayer | { |
5796 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5797 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5798 | a42bd6cc | j_mayer | #else
|
5799 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5800 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5801 | a42bd6cc | j_mayer | return;
|
5802 | a42bd6cc | j_mayer | } |
5803 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5804 | d72a19f7 | aurel32 | gen_helper_rfmci(); |
5805 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5806 | a42bd6cc | j_mayer | #endif
|
5807 | a42bd6cc | j_mayer | } |
5808 | 5eb7995e | j_mayer | |
5809 | d9bce9d9 | j_mayer | /* TLB management - PowerPC 405 implementation */
|
5810 | e8eaa2c0 | Blue Swirl | |
5811 | 54623277 | Blue Swirl | /* tlbre */
|
5812 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_40x(DisasContext *ctx) |
5813 | 76a66253 | j_mayer | { |
5814 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5815 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5816 | 76a66253 | j_mayer | #else
|
5817 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5818 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5819 | 76a66253 | j_mayer | return;
|
5820 | 76a66253 | j_mayer | } |
5821 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5822 | 76a66253 | j_mayer | case 0: |
5823 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5824 | 76a66253 | j_mayer | break;
|
5825 | 76a66253 | j_mayer | case 1: |
5826 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5827 | 76a66253 | j_mayer | break;
|
5828 | 76a66253 | j_mayer | default:
|
5829 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5830 | 76a66253 | j_mayer | break;
|
5831 | 9a64fbe4 | bellard | } |
5832 | 76a66253 | j_mayer | #endif
|
5833 | 76a66253 | j_mayer | } |
5834 | 76a66253 | j_mayer | |
5835 | d9bce9d9 | j_mayer | /* tlbsx - tlbsx. */
|
5836 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_40x(DisasContext *ctx) |
5837 | 76a66253 | j_mayer | { |
5838 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5839 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5840 | 76a66253 | j_mayer | #else
|
5841 | 74d37793 | aurel32 | TCGv t0; |
5842 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5843 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5844 | 76a66253 | j_mayer | return;
|
5845 | 76a66253 | j_mayer | } |
5846 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5847 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5848 | 74d37793 | aurel32 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5849 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5850 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5851 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5852 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5853 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5854 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5855 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5856 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5857 | 74d37793 | aurel32 | gen_set_label(l1); |
5858 | 74d37793 | aurel32 | } |
5859 | 76a66253 | j_mayer | #endif
|
5860 | 79aceca5 | bellard | } |
5861 | 79aceca5 | bellard | |
5862 | 76a66253 | j_mayer | /* tlbwe */
|
5863 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_40x(DisasContext *ctx) |
5864 | 79aceca5 | bellard | { |
5865 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5866 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5867 | 76a66253 | j_mayer | #else
|
5868 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5869 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5870 | 76a66253 | j_mayer | return;
|
5871 | 76a66253 | j_mayer | } |
5872 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5873 | 76a66253 | j_mayer | case 0: |
5874 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5875 | 76a66253 | j_mayer | break;
|
5876 | 76a66253 | j_mayer | case 1: |
5877 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5878 | 76a66253 | j_mayer | break;
|
5879 | 76a66253 | j_mayer | default:
|
5880 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5881 | 76a66253 | j_mayer | break;
|
5882 | 9a64fbe4 | bellard | } |
5883 | 76a66253 | j_mayer | #endif
|
5884 | 76a66253 | j_mayer | } |
5885 | 76a66253 | j_mayer | |
5886 | a4bb6c3e | j_mayer | /* TLB management - PowerPC 440 implementation */
|
5887 | e8eaa2c0 | Blue Swirl | |
5888 | 54623277 | Blue Swirl | /* tlbre */
|
5889 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_440(DisasContext *ctx) |
5890 | 5eb7995e | j_mayer | { |
5891 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5892 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5893 | 5eb7995e | j_mayer | #else
|
5894 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5895 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5896 | 5eb7995e | j_mayer | return;
|
5897 | 5eb7995e | j_mayer | } |
5898 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5899 | 5eb7995e | j_mayer | case 0: |
5900 | 5eb7995e | j_mayer | case 1: |
5901 | 5eb7995e | j_mayer | case 2: |
5902 | 74d37793 | aurel32 | { |
5903 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5904 | 5823947f | Edgar E. Iglesias | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]); |
5905 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5906 | 74d37793 | aurel32 | } |
5907 | 5eb7995e | j_mayer | break;
|
5908 | 5eb7995e | j_mayer | default:
|
5909 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5910 | 5eb7995e | j_mayer | break;
|
5911 | 5eb7995e | j_mayer | } |
5912 | 5eb7995e | j_mayer | #endif
|
5913 | 5eb7995e | j_mayer | } |
5914 | 5eb7995e | j_mayer | |
5915 | 5eb7995e | j_mayer | /* tlbsx - tlbsx. */
|
5916 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_440(DisasContext *ctx) |
5917 | 5eb7995e | j_mayer | { |
5918 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5919 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5920 | 5eb7995e | j_mayer | #else
|
5921 | 74d37793 | aurel32 | TCGv t0; |
5922 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5923 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5924 | 5eb7995e | j_mayer | return;
|
5925 | 5eb7995e | j_mayer | } |
5926 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5927 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5928 | 74d37793 | aurel32 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5929 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5930 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5931 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5932 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5933 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5934 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5935 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5936 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5937 | 74d37793 | aurel32 | gen_set_label(l1); |
5938 | 74d37793 | aurel32 | } |
5939 | 5eb7995e | j_mayer | #endif
|
5940 | 5eb7995e | j_mayer | } |
5941 | 5eb7995e | j_mayer | |
5942 | 5eb7995e | j_mayer | /* tlbwe */
|
5943 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_440(DisasContext *ctx) |
5944 | 5eb7995e | j_mayer | { |
5945 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5946 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5947 | 5eb7995e | j_mayer | #else
|
5948 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5949 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5950 | 5eb7995e | j_mayer | return;
|
5951 | 5eb7995e | j_mayer | } |
5952 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5953 | 5eb7995e | j_mayer | case 0: |
5954 | 5eb7995e | j_mayer | case 1: |
5955 | 5eb7995e | j_mayer | case 2: |
5956 | 74d37793 | aurel32 | { |
5957 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5958 | 74d37793 | aurel32 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5959 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5960 | 74d37793 | aurel32 | } |
5961 | 5eb7995e | j_mayer | break;
|
5962 | 5eb7995e | j_mayer | default:
|
5963 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5964 | 5eb7995e | j_mayer | break;
|
5965 | 5eb7995e | j_mayer | } |
5966 | 5eb7995e | j_mayer | #endif
|
5967 | 5eb7995e | j_mayer | } |
5968 | 5eb7995e | j_mayer | |
5969 | 76a66253 | j_mayer | /* wrtee */
|
5970 | 99e300ef | Blue Swirl | static void gen_wrtee(DisasContext *ctx) |
5971 | 76a66253 | j_mayer | { |
5972 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5973 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5974 | 76a66253 | j_mayer | #else
|
5975 | 6527f6ea | aurel32 | TCGv t0; |
5976 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5977 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5978 | 76a66253 | j_mayer | return;
|
5979 | 76a66253 | j_mayer | } |
5980 | 6527f6ea | aurel32 | t0 = tcg_temp_new(); |
5981 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
|
5982 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
5983 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
5984 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
5985 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
5986 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
5987 | dee96f6c | j_mayer | */
|
5988 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
5989 | 76a66253 | j_mayer | #endif
|
5990 | 76a66253 | j_mayer | } |
5991 | 76a66253 | j_mayer | |
5992 | 76a66253 | j_mayer | /* wrteei */
|
5993 | 99e300ef | Blue Swirl | static void gen_wrteei(DisasContext *ctx) |
5994 | 76a66253 | j_mayer | { |
5995 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5996 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5997 | 76a66253 | j_mayer | #else
|
5998 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5999 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6000 | 76a66253 | j_mayer | return;
|
6001 | 76a66253 | j_mayer | } |
6002 | fbe73008 | Baojun Wang | if (ctx->opcode & 0x00008000) { |
6003 | 6527f6ea | aurel32 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
|
6004 | 6527f6ea | aurel32 | /* Stop translation to have a chance to raise an exception */
|
6005 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
6006 | 6527f6ea | aurel32 | } else {
|
6007 | 1b6e5f99 | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
6008 | 6527f6ea | aurel32 | } |
6009 | 76a66253 | j_mayer | #endif
|
6010 | 76a66253 | j_mayer | } |
6011 | 76a66253 | j_mayer | |
6012 | 08e46e54 | j_mayer | /* PowerPC 440 specific instructions */
|
6013 | 99e300ef | Blue Swirl | |
6014 | 54623277 | Blue Swirl | /* dlmzb */
|
6015 | 99e300ef | Blue Swirl | static void gen_dlmzb(DisasContext *ctx) |
6016 | 76a66253 | j_mayer | { |
6017 | ef0d51af | aurel32 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6018 | ef0d51af | aurel32 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
6019 | ef0d51af | aurel32 | cpu_gpr[rB(ctx->opcode)], t0); |
6020 | ef0d51af | aurel32 | tcg_temp_free_i32(t0); |
6021 | 76a66253 | j_mayer | } |
6022 | 76a66253 | j_mayer | |
6023 | 76a66253 | j_mayer | /* mbar replaces eieio on 440 */
|
6024 | 99e300ef | Blue Swirl | static void gen_mbar(DisasContext *ctx) |
6025 | 76a66253 | j_mayer | { |
6026 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6027 | 76a66253 | j_mayer | } |
6028 | 76a66253 | j_mayer | |
6029 | 76a66253 | j_mayer | /* msync replaces sync on 440 */
|
6030 | 99e300ef | Blue Swirl | static void gen_msync(DisasContext *ctx) |
6031 | 76a66253 | j_mayer | { |
6032 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6033 | 76a66253 | j_mayer | } |
6034 | 76a66253 | j_mayer | |
6035 | 76a66253 | j_mayer | /* icbt */
|
6036 | e8eaa2c0 | Blue Swirl | static void gen_icbt_440(DisasContext *ctx) |
6037 | 76a66253 | j_mayer | { |
6038 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6039 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
6040 | 76a66253 | j_mayer | * but does not generate any exception
|
6041 | 76a66253 | j_mayer | */
|
6042 | 79aceca5 | bellard | } |
6043 | 79aceca5 | bellard | |
6044 | a9d9eb8f | j_mayer | /*** Altivec vector extension ***/
|
6045 | a9d9eb8f | j_mayer | /* Altivec registers moves */
|
6046 | a9d9eb8f | j_mayer | |
6047 | 636aa200 | Blue Swirl | static inline TCGv_ptr gen_avr_ptr(int reg) |
6048 | 564e571a | aurel32 | { |
6049 | e4704b3b | aurel32 | TCGv_ptr r = tcg_temp_new_ptr(); |
6050 | 564e571a | aurel32 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6051 | 564e571a | aurel32 | return r;
|
6052 | 564e571a | aurel32 | } |
6053 | 564e571a | aurel32 | |
6054 | a9d9eb8f | j_mayer | #define GEN_VR_LDX(name, opc2, opc3) \
|
6055 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6056 | a9d9eb8f | j_mayer | { \ |
6057 | fe1e5c53 | aurel32 | TCGv EA; \ |
6058 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6059 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6060 | a9d9eb8f | j_mayer | return; \
|
6061 | a9d9eb8f | j_mayer | } \ |
6062 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6063 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6064 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6065 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6066 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6067 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6068 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6069 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6070 | fe1e5c53 | aurel32 | } else { \
|
6071 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6072 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6073 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6074 | fe1e5c53 | aurel32 | } \ |
6075 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6076 | a9d9eb8f | j_mayer | } |
6077 | a9d9eb8f | j_mayer | |
6078 | a9d9eb8f | j_mayer | #define GEN_VR_STX(name, opc2, opc3) \
|
6079 | 99e300ef | Blue Swirl | static void gen_st##name(DisasContext *ctx) \ |
6080 | a9d9eb8f | j_mayer | { \ |
6081 | fe1e5c53 | aurel32 | TCGv EA; \ |
6082 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6083 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6084 | a9d9eb8f | j_mayer | return; \
|
6085 | a9d9eb8f | j_mayer | } \ |
6086 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6087 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6088 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6089 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6090 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6091 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6092 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6093 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6094 | fe1e5c53 | aurel32 | } else { \
|
6095 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6096 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6097 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6098 | fe1e5c53 | aurel32 | } \ |
6099 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6100 | a9d9eb8f | j_mayer | } |
6101 | a9d9eb8f | j_mayer | |
6102 | cbfb6ae9 | aurel32 | #define GEN_VR_LVE(name, opc2, opc3) \
|
6103 | 99e300ef | Blue Swirl | static void gen_lve##name(DisasContext *ctx) \ |
6104 | cbfb6ae9 | aurel32 | { \ |
6105 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6106 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6107 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6108 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6109 | cbfb6ae9 | aurel32 | return; \
|
6110 | cbfb6ae9 | aurel32 | } \ |
6111 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6112 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6113 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6114 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6115 | cbfb6ae9 | aurel32 | gen_helper_lve##name (rs, EA); \ |
6116 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6117 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6118 | cbfb6ae9 | aurel32 | } |
6119 | cbfb6ae9 | aurel32 | |
6120 | cbfb6ae9 | aurel32 | #define GEN_VR_STVE(name, opc2, opc3) \
|
6121 | 99e300ef | Blue Swirl | static void gen_stve##name(DisasContext *ctx) \ |
6122 | cbfb6ae9 | aurel32 | { \ |
6123 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6124 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6125 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6126 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6127 | cbfb6ae9 | aurel32 | return; \
|
6128 | cbfb6ae9 | aurel32 | } \ |
6129 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6130 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6131 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6132 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6133 | cbfb6ae9 | aurel32 | gen_helper_stve##name (rs, EA); \ |
6134 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6135 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6136 | cbfb6ae9 | aurel32 | } |
6137 | cbfb6ae9 | aurel32 | |
6138 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvx, 0x07, 0x03); |
6139 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
6140 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
6141 | a9d9eb8f | j_mayer | |
6142 | cbfb6ae9 | aurel32 | GEN_VR_LVE(bx, 0x07, 0x00); |
6143 | cbfb6ae9 | aurel32 | GEN_VR_LVE(hx, 0x07, 0x01); |
6144 | cbfb6ae9 | aurel32 | GEN_VR_LVE(wx, 0x07, 0x02); |
6145 | cbfb6ae9 | aurel32 | |
6146 | fe1e5c53 | aurel32 | GEN_VR_STX(svx, 0x07, 0x07); |
6147 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
6148 | fe1e5c53 | aurel32 | GEN_VR_STX(svxl, 0x07, 0x0F); |
6149 | a9d9eb8f | j_mayer | |
6150 | cbfb6ae9 | aurel32 | GEN_VR_STVE(bx, 0x07, 0x04); |
6151 | cbfb6ae9 | aurel32 | GEN_VR_STVE(hx, 0x07, 0x05); |
6152 | cbfb6ae9 | aurel32 | GEN_VR_STVE(wx, 0x07, 0x06); |
6153 | cbfb6ae9 | aurel32 | |
6154 | 99e300ef | Blue Swirl | static void gen_lvsl(DisasContext *ctx) |
6155 | bf8d8ded | aurel32 | { |
6156 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6157 | bf8d8ded | aurel32 | TCGv EA; |
6158 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6159 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6160 | bf8d8ded | aurel32 | return;
|
6161 | bf8d8ded | aurel32 | } |
6162 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6163 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6164 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6165 | bf8d8ded | aurel32 | gen_helper_lvsl(rd, EA); |
6166 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6167 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6168 | bf8d8ded | aurel32 | } |
6169 | bf8d8ded | aurel32 | |
6170 | 99e300ef | Blue Swirl | static void gen_lvsr(DisasContext *ctx) |
6171 | bf8d8ded | aurel32 | { |
6172 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6173 | bf8d8ded | aurel32 | TCGv EA; |
6174 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6175 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6176 | bf8d8ded | aurel32 | return;
|
6177 | bf8d8ded | aurel32 | } |
6178 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6179 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6180 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6181 | bf8d8ded | aurel32 | gen_helper_lvsr(rd, EA); |
6182 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6183 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6184 | bf8d8ded | aurel32 | } |
6185 | bf8d8ded | aurel32 | |
6186 | 99e300ef | Blue Swirl | static void gen_mfvscr(DisasContext *ctx) |
6187 | 785f451b | aurel32 | { |
6188 | 785f451b | aurel32 | TCGv_i32 t; |
6189 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6190 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6191 | 785f451b | aurel32 | return;
|
6192 | 785f451b | aurel32 | } |
6193 | 785f451b | aurel32 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
|
6194 | 785f451b | aurel32 | t = tcg_temp_new_i32(); |
6195 | 785f451b | aurel32 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); |
6196 | 785f451b | aurel32 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
6197 | fce5ecb7 | aurel32 | tcg_temp_free_i32(t); |
6198 | 785f451b | aurel32 | } |
6199 | 785f451b | aurel32 | |
6200 | 99e300ef | Blue Swirl | static void gen_mtvscr(DisasContext *ctx) |
6201 | 785f451b | aurel32 | { |
6202 | 6e87b7c7 | aurel32 | TCGv_ptr p; |
6203 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6204 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6205 | 785f451b | aurel32 | return;
|
6206 | 785f451b | aurel32 | } |
6207 | 6e87b7c7 | aurel32 | p = gen_avr_ptr(rD(ctx->opcode)); |
6208 | 6e87b7c7 | aurel32 | gen_helper_mtvscr(p); |
6209 | 6e87b7c7 | aurel32 | tcg_temp_free_ptr(p); |
6210 | 785f451b | aurel32 | } |
6211 | 785f451b | aurel32 | |
6212 | 7a9b96cf | aurel32 | /* Logical operations */
|
6213 | 7a9b96cf | aurel32 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
6214 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6215 | 7a9b96cf | aurel32 | { \ |
6216 | 7a9b96cf | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6217 | 7a9b96cf | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6218 | 7a9b96cf | aurel32 | return; \
|
6219 | 7a9b96cf | aurel32 | } \ |
6220 | 7a9b96cf | aurel32 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ |
6221 | 7a9b96cf | aurel32 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ |
6222 | 7a9b96cf | aurel32 | } |
6223 | 7a9b96cf | aurel32 | |
6224 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); |
6225 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); |
6226 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); |
6227 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); |
6228 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); |
6229 | 7a9b96cf | aurel32 | |
6230 | 8e27dd6f | aurel32 | #define GEN_VXFORM(name, opc2, opc3) \
|
6231 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6232 | 8e27dd6f | aurel32 | { \ |
6233 | 8e27dd6f | aurel32 | TCGv_ptr ra, rb, rd; \ |
6234 | 8e27dd6f | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6235 | 8e27dd6f | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6236 | 8e27dd6f | aurel32 | return; \
|
6237 | 8e27dd6f | aurel32 | } \ |
6238 | 8e27dd6f | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6239 | 8e27dd6f | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6240 | 8e27dd6f | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6241 | 8e27dd6f | aurel32 | gen_helper_##name (rd, ra, rb); \ |
6242 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(ra); \ |
6243 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rb); \ |
6244 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rd); \ |
6245 | 8e27dd6f | aurel32 | } |
6246 | 8e27dd6f | aurel32 | |
6247 | 7872c51c | aurel32 | GEN_VXFORM(vaddubm, 0, 0); |
6248 | 7872c51c | aurel32 | GEN_VXFORM(vadduhm, 0, 1); |
6249 | 7872c51c | aurel32 | GEN_VXFORM(vadduwm, 0, 2); |
6250 | 7872c51c | aurel32 | GEN_VXFORM(vsububm, 0, 16); |
6251 | 7872c51c | aurel32 | GEN_VXFORM(vsubuhm, 0, 17); |
6252 | 7872c51c | aurel32 | GEN_VXFORM(vsubuwm, 0, 18); |
6253 | e4039339 | aurel32 | GEN_VXFORM(vmaxub, 1, 0); |
6254 | e4039339 | aurel32 | GEN_VXFORM(vmaxuh, 1, 1); |
6255 | e4039339 | aurel32 | GEN_VXFORM(vmaxuw, 1, 2); |
6256 | e4039339 | aurel32 | GEN_VXFORM(vmaxsb, 1, 4); |
6257 | e4039339 | aurel32 | GEN_VXFORM(vmaxsh, 1, 5); |
6258 | e4039339 | aurel32 | GEN_VXFORM(vmaxsw, 1, 6); |
6259 | e4039339 | aurel32 | GEN_VXFORM(vminub, 1, 8); |
6260 | e4039339 | aurel32 | GEN_VXFORM(vminuh, 1, 9); |
6261 | e4039339 | aurel32 | GEN_VXFORM(vminuw, 1, 10); |
6262 | e4039339 | aurel32 | GEN_VXFORM(vminsb, 1, 12); |
6263 | e4039339 | aurel32 | GEN_VXFORM(vminsh, 1, 13); |
6264 | e4039339 | aurel32 | GEN_VXFORM(vminsw, 1, 14); |
6265 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgub, 1, 16); |
6266 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguh, 1, 17); |
6267 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguw, 1, 18); |
6268 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsb, 1, 20); |
6269 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsh, 1, 21); |
6270 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsw, 1, 22); |
6271 | 3b430048 | aurel32 | GEN_VXFORM(vmrghb, 6, 0); |
6272 | 3b430048 | aurel32 | GEN_VXFORM(vmrghh, 6, 1); |
6273 | 3b430048 | aurel32 | GEN_VXFORM(vmrghw, 6, 2); |
6274 | 3b430048 | aurel32 | GEN_VXFORM(vmrglb, 6, 4); |
6275 | 3b430048 | aurel32 | GEN_VXFORM(vmrglh, 6, 5); |
6276 | 3b430048 | aurel32 | GEN_VXFORM(vmrglw, 6, 6); |
6277 | 2c277908 | aurel32 | GEN_VXFORM(vmuloub, 4, 0); |
6278 | 2c277908 | aurel32 | GEN_VXFORM(vmulouh, 4, 1); |
6279 | 2c277908 | aurel32 | GEN_VXFORM(vmulosb, 4, 4); |
6280 | 2c277908 | aurel32 | GEN_VXFORM(vmulosh, 4, 5); |
6281 | 2c277908 | aurel32 | GEN_VXFORM(vmuleub, 4, 8); |
6282 | 2c277908 | aurel32 | GEN_VXFORM(vmuleuh, 4, 9); |
6283 | 2c277908 | aurel32 | GEN_VXFORM(vmulesb, 4, 12); |
6284 | 2c277908 | aurel32 | GEN_VXFORM(vmulesh, 4, 13); |
6285 | d79f0809 | aurel32 | GEN_VXFORM(vslb, 2, 4); |
6286 | d79f0809 | aurel32 | GEN_VXFORM(vslh, 2, 5); |
6287 | d79f0809 | aurel32 | GEN_VXFORM(vslw, 2, 6); |
6288 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrb, 2, 8); |
6289 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrh, 2, 9); |
6290 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrw, 2, 10); |
6291 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrab, 2, 12); |
6292 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrah, 2, 13); |
6293 | 07ef34c3 | aurel32 | GEN_VXFORM(vsraw, 2, 14); |
6294 | 7b239bec | aurel32 | GEN_VXFORM(vslo, 6, 16); |
6295 | 7b239bec | aurel32 | GEN_VXFORM(vsro, 6, 17); |
6296 | e343da72 | aurel32 | GEN_VXFORM(vaddcuw, 0, 6); |
6297 | e343da72 | aurel32 | GEN_VXFORM(vsubcuw, 0, 22); |
6298 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddubs, 0, 8); |
6299 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduhs, 0, 9); |
6300 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduws, 0, 10); |
6301 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsbs, 0, 12); |
6302 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddshs, 0, 13); |
6303 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsws, 0, 14); |
6304 | 5ab09f33 | aurel32 | GEN_VXFORM(vsububs, 0, 24); |
6305 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuhs, 0, 25); |
6306 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuws, 0, 26); |
6307 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsbs, 0, 28); |
6308 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubshs, 0, 29); |
6309 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsws, 0, 30); |
6310 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlb, 2, 0); |
6311 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlh, 2, 1); |
6312 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlw, 2, 2); |
6313 | d9430add | aurel32 | GEN_VXFORM(vsl, 2, 7); |
6314 | d9430add | aurel32 | GEN_VXFORM(vsr, 2, 11); |
6315 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhum, 7, 0); |
6316 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwum, 7, 1); |
6317 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhus, 7, 2); |
6318 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwus, 7, 3); |
6319 | 5335a145 | aurel32 | GEN_VXFORM(vpkshus, 7, 4); |
6320 | 5335a145 | aurel32 | GEN_VXFORM(vpkswus, 7, 5); |
6321 | 5335a145 | aurel32 | GEN_VXFORM(vpkshss, 7, 6); |
6322 | 5335a145 | aurel32 | GEN_VXFORM(vpkswss, 7, 7); |
6323 | 1dd9ffb9 | aurel32 | GEN_VXFORM(vpkpx, 7, 12); |
6324 | 8142cddd | aurel32 | GEN_VXFORM(vsum4ubs, 4, 24); |
6325 | 8142cddd | aurel32 | GEN_VXFORM(vsum4sbs, 4, 28); |
6326 | 8142cddd | aurel32 | GEN_VXFORM(vsum4shs, 4, 25); |
6327 | 8142cddd | aurel32 | GEN_VXFORM(vsum2sws, 4, 26); |
6328 | 8142cddd | aurel32 | GEN_VXFORM(vsumsws, 4, 30); |
6329 | 56fdd213 | aurel32 | GEN_VXFORM(vaddfp, 5, 0); |
6330 | 56fdd213 | aurel32 | GEN_VXFORM(vsubfp, 5, 1); |
6331 | 1536ff64 | aurel32 | GEN_VXFORM(vmaxfp, 5, 16); |
6332 | 1536ff64 | aurel32 | GEN_VXFORM(vminfp, 5, 17); |
6333 | fab3cbe9 | aurel32 | |
6334 | 0cbcd906 | aurel32 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
6335 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6336 | 0cbcd906 | aurel32 | { \ |
6337 | 0cbcd906 | aurel32 | TCGv_ptr ra, rb, rd; \ |
6338 | 0cbcd906 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6339 | 0cbcd906 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6340 | 0cbcd906 | aurel32 | return; \
|
6341 | 0cbcd906 | aurel32 | } \ |
6342 | 0cbcd906 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6343 | 0cbcd906 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6344 | 0cbcd906 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6345 | 0cbcd906 | aurel32 | gen_helper_##opname (rd, ra, rb); \ |
6346 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(ra); \ |
6347 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rb); \ |
6348 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rd); \ |
6349 | 0cbcd906 | aurel32 | } |
6350 | 0cbcd906 | aurel32 | |
6351 | 0cbcd906 | aurel32 | #define GEN_VXRFORM(name, opc2, opc3) \
|
6352 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
6353 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
6354 | 0cbcd906 | aurel32 | |
6355 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequb, 3, 0) |
6356 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequh, 3, 1) |
6357 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequw, 3, 2) |
6358 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
6359 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
6360 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
6361 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtub, 3, 8) |
6362 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
6363 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
6364 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6365 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6366 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
6367 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpbfp, 3, 15) |
6368 | 1add6e23 | aurel32 | |
6369 | c026766b | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6370 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6371 | c026766b | aurel32 | { \ |
6372 | c026766b | aurel32 | TCGv_ptr rd; \ |
6373 | c026766b | aurel32 | TCGv_i32 simm; \ |
6374 | c026766b | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6375 | c026766b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6376 | c026766b | aurel32 | return; \
|
6377 | c026766b | aurel32 | } \ |
6378 | c026766b | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6379 | c026766b | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6380 | c026766b | aurel32 | gen_helper_##name (rd, simm); \ |
6381 | c026766b | aurel32 | tcg_temp_free_i32(simm); \ |
6382 | c026766b | aurel32 | tcg_temp_free_ptr(rd); \ |
6383 | c026766b | aurel32 | } |
6384 | c026766b | aurel32 | |
6385 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisb, 6, 12); |
6386 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltish, 6, 13); |
6387 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisw, 6, 14); |
6388 | c026766b | aurel32 | |
6389 | de5f2484 | aurel32 | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
6390 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6391 | de5f2484 | aurel32 | { \ |
6392 | de5f2484 | aurel32 | TCGv_ptr rb, rd; \ |
6393 | de5f2484 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6394 | de5f2484 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6395 | de5f2484 | aurel32 | return; \
|
6396 | de5f2484 | aurel32 | } \ |
6397 | de5f2484 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6398 | de5f2484 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6399 | de5f2484 | aurel32 | gen_helper_##name (rd, rb); \ |
6400 | de5f2484 | aurel32 | tcg_temp_free_ptr(rb); \ |
6401 | de5f2484 | aurel32 | tcg_temp_free_ptr(rd); \ |
6402 | de5f2484 | aurel32 | } |
6403 | de5f2484 | aurel32 | |
6404 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6405 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsh, 7, 9); |
6406 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
6407 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsh, 7, 11); |
6408 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6409 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupklpx, 7, 15); |
6410 | bdfbac35 | aurel32 | GEN_VXFORM_NOA(vrefp, 5, 4); |
6411 | 071fc3b1 | aurel32 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
6412 | 0bffbc6c | Aurelien Jarno | GEN_VXFORM_NOA(vexptefp, 5, 6); |
6413 | b580763f | aurel32 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
6414 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfim, 5, 8); |
6415 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfin, 5, 9); |
6416 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfip, 5, 10); |
6417 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfiz, 5, 11); |
6418 | 79f85c3a | aurel32 | |
6419 | 21d21583 | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6420 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6421 | 21d21583 | aurel32 | { \ |
6422 | 21d21583 | aurel32 | TCGv_ptr rd; \ |
6423 | 21d21583 | aurel32 | TCGv_i32 simm; \ |
6424 | 21d21583 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6425 | 21d21583 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6426 | 21d21583 | aurel32 | return; \
|
6427 | 21d21583 | aurel32 | } \ |
6428 | 21d21583 | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6429 | 21d21583 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6430 | 21d21583 | aurel32 | gen_helper_##name (rd, simm); \ |
6431 | 21d21583 | aurel32 | tcg_temp_free_i32(simm); \ |
6432 | 21d21583 | aurel32 | tcg_temp_free_ptr(rd); \ |
6433 | 21d21583 | aurel32 | } |
6434 | 21d21583 | aurel32 | |
6435 | 27a4edb3 | aurel32 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
6436 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6437 | 27a4edb3 | aurel32 | { \ |
6438 | 27a4edb3 | aurel32 | TCGv_ptr rb, rd; \ |
6439 | 27a4edb3 | aurel32 | TCGv_i32 uimm; \ |
6440 | 27a4edb3 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6441 | 27a4edb3 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6442 | 27a4edb3 | aurel32 | return; \
|
6443 | 27a4edb3 | aurel32 | } \ |
6444 | 27a4edb3 | aurel32 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
6445 | 27a4edb3 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6446 | 27a4edb3 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6447 | 27a4edb3 | aurel32 | gen_helper_##name (rd, rb, uimm); \ |
6448 | 27a4edb3 | aurel32 | tcg_temp_free_i32(uimm); \ |
6449 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rb); \ |
6450 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rd); \ |
6451 | 27a4edb3 | aurel32 | } |
6452 | 27a4edb3 | aurel32 | |
6453 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6454 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vsplth, 6, 9); |
6455 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltw, 6, 10); |
6456 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
6457 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfsx, 5, 13); |
6458 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
6459 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctsxs, 5, 15); |
6460 | e4e6bee7 | aurel32 | |
6461 | 99e300ef | Blue Swirl | static void gen_vsldoi(DisasContext *ctx) |
6462 | cd633b10 | aurel32 | { |
6463 | cd633b10 | aurel32 | TCGv_ptr ra, rb, rd; |
6464 | fce5ecb7 | aurel32 | TCGv_i32 sh; |
6465 | cd633b10 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6466 | cd633b10 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6467 | cd633b10 | aurel32 | return;
|
6468 | cd633b10 | aurel32 | } |
6469 | cd633b10 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6470 | cd633b10 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6471 | cd633b10 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6472 | cd633b10 | aurel32 | sh = tcg_const_i32(VSH(ctx->opcode)); |
6473 | cd633b10 | aurel32 | gen_helper_vsldoi (rd, ra, rb, sh); |
6474 | cd633b10 | aurel32 | tcg_temp_free_ptr(ra); |
6475 | cd633b10 | aurel32 | tcg_temp_free_ptr(rb); |
6476 | cd633b10 | aurel32 | tcg_temp_free_ptr(rd); |
6477 | fce5ecb7 | aurel32 | tcg_temp_free_i32(sh); |
6478 | cd633b10 | aurel32 | } |
6479 | cd633b10 | aurel32 | |
6480 | 707cec33 | aurel32 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
6481 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6482 | 707cec33 | aurel32 | { \ |
6483 | 707cec33 | aurel32 | TCGv_ptr ra, rb, rc, rd; \ |
6484 | 707cec33 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6485 | 707cec33 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6486 | 707cec33 | aurel32 | return; \
|
6487 | 707cec33 | aurel32 | } \ |
6488 | 707cec33 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6489 | 707cec33 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6490 | 707cec33 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); \ |
6491 | 707cec33 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6492 | 707cec33 | aurel32 | if (Rc(ctx->opcode)) { \
|
6493 | 707cec33 | aurel32 | gen_helper_##name1 (rd, ra, rb, rc); \ |
6494 | 707cec33 | aurel32 | } else { \
|
6495 | 707cec33 | aurel32 | gen_helper_##name0 (rd, ra, rb, rc); \ |
6496 | 707cec33 | aurel32 | } \ |
6497 | 707cec33 | aurel32 | tcg_temp_free_ptr(ra); \ |
6498 | 707cec33 | aurel32 | tcg_temp_free_ptr(rb); \ |
6499 | 707cec33 | aurel32 | tcg_temp_free_ptr(rc); \ |
6500 | 707cec33 | aurel32 | tcg_temp_free_ptr(rd); \ |
6501 | 707cec33 | aurel32 | } |
6502 | 707cec33 | aurel32 | |
6503 | b161ae27 | aurel32 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
|
6504 | b161ae27 | aurel32 | |
6505 | 99e300ef | Blue Swirl | static void gen_vmladduhm(DisasContext *ctx) |
6506 | bcd2ee23 | aurel32 | { |
6507 | bcd2ee23 | aurel32 | TCGv_ptr ra, rb, rc, rd; |
6508 | bcd2ee23 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6509 | bcd2ee23 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6510 | bcd2ee23 | aurel32 | return;
|
6511 | bcd2ee23 | aurel32 | } |
6512 | bcd2ee23 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6513 | bcd2ee23 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6514 | bcd2ee23 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); |
6515 | bcd2ee23 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6516 | bcd2ee23 | aurel32 | gen_helper_vmladduhm(rd, ra, rb, rc); |
6517 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(ra); |
6518 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rb); |
6519 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rc); |
6520 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rd); |
6521 | bcd2ee23 | aurel32 | } |
6522 | bcd2ee23 | aurel32 | |
6523 | b04ae981 | aurel32 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
|
6524 | 4d9903b6 | aurel32 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
|
6525 | eae07261 | aurel32 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
|
6526 | d1258698 | aurel32 | GEN_VAFORM_PAIRED(vsel, vperm, 21)
|
6527 | 35cf7c7e | aurel32 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
|
6528 | b04ae981 | aurel32 | |
6529 | 0487d6a8 | j_mayer | /*** SPE extension ***/
|
6530 | 0487d6a8 | j_mayer | /* Register moves */
|
6531 | 3cd7d1dd | j_mayer | |
6532 | a0e13900 | Fabien Chouteau | |
6533 | a0e13900 | Fabien Chouteau | static inline void gen_evmra(DisasContext *ctx) |
6534 | a0e13900 | Fabien Chouteau | { |
6535 | a0e13900 | Fabien Chouteau | |
6536 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
6537 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
6538 | a0e13900 | Fabien Chouteau | return;
|
6539 | a0e13900 | Fabien Chouteau | } |
6540 | a0e13900 | Fabien Chouteau | |
6541 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
6542 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
6543 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6544 | a0e13900 | Fabien Chouteau | |
6545 | a0e13900 | Fabien Chouteau | /* spe_acc := rA */
|
6546 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], |
6547 | a0e13900 | Fabien Chouteau | cpu_env, |
6548 | a0e13900 | Fabien Chouteau | offsetof(CPUState, spe_acc)); |
6549 | a0e13900 | Fabien Chouteau | #else
|
6550 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
6551 | a0e13900 | Fabien Chouteau | |
6552 | a0e13900 | Fabien Chouteau | /* tmp := rA_lo + rA_hi << 32 */
|
6553 | a0e13900 | Fabien Chouteau | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6554 | a0e13900 | Fabien Chouteau | |
6555 | a0e13900 | Fabien Chouteau | /* spe_acc := tmp */
|
6556 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
6557 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
6558 | a0e13900 | Fabien Chouteau | |
6559 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
6560 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6561 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6562 | a0e13900 | Fabien Chouteau | #endif
|
6563 | a0e13900 | Fabien Chouteau | } |
6564 | a0e13900 | Fabien Chouteau | |
6565 | 636aa200 | Blue Swirl | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6566 | 636aa200 | Blue Swirl | { |
6567 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6568 | f78fb44e | aurel32 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
6569 | f78fb44e | aurel32 | #else
|
6570 | 36aa55dc | pbrook | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
6571 | 3cd7d1dd | j_mayer | #endif
|
6572 | f78fb44e | aurel32 | } |
6573 | 3cd7d1dd | j_mayer | |
6574 | 636aa200 | Blue Swirl | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6575 | 636aa200 | Blue Swirl | { |
6576 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6577 | f78fb44e | aurel32 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
6578 | f78fb44e | aurel32 | #else
|
6579 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
6580 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
6581 | f78fb44e | aurel32 | tcg_gen_shri_i64(tmp, t, 32);
|
6582 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
6583 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
6584 | 3cd7d1dd | j_mayer | #endif
|
6585 | f78fb44e | aurel32 | } |
6586 | 3cd7d1dd | j_mayer | |
6587 | 0487d6a8 | j_mayer | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
6588 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6589 | 0487d6a8 | j_mayer | { \ |
6590 | 0487d6a8 | j_mayer | if (Rc(ctx->opcode)) \
|
6591 | 0487d6a8 | j_mayer | gen_##name1(ctx); \ |
6592 | 0487d6a8 | j_mayer | else \
|
6593 | 0487d6a8 | j_mayer | gen_##name0(ctx); \ |
6594 | 0487d6a8 | j_mayer | } |
6595 | 0487d6a8 | j_mayer | |
6596 | 0487d6a8 | j_mayer | /* Handler for undefined SPE opcodes */
|
6597 | 636aa200 | Blue Swirl | static inline void gen_speundef(DisasContext *ctx) |
6598 | 0487d6a8 | j_mayer | { |
6599 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6600 | 0487d6a8 | j_mayer | } |
6601 | 0487d6a8 | j_mayer | |
6602 | 57951c27 | aurel32 | /* SPE logic */
|
6603 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6604 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6605 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6606 | 0487d6a8 | j_mayer | { \ |
6607 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6608 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6609 | 0487d6a8 | j_mayer | return; \
|
6610 | 0487d6a8 | j_mayer | } \ |
6611 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6612 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6613 | 57951c27 | aurel32 | } |
6614 | 57951c27 | aurel32 | #else
|
6615 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6616 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6617 | 57951c27 | aurel32 | { \ |
6618 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6619 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6620 | 57951c27 | aurel32 | return; \
|
6621 | 57951c27 | aurel32 | } \ |
6622 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6623 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6624 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6625 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6626 | 0487d6a8 | j_mayer | } |
6627 | 57951c27 | aurel32 | #endif
|
6628 | 57951c27 | aurel32 | |
6629 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); |
6630 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); |
6631 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); |
6632 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); |
6633 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); |
6634 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); |
6635 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); |
6636 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); |
6637 | 0487d6a8 | j_mayer | |
6638 | 57951c27 | aurel32 | /* SPE logic immediate */
|
6639 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6640 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6641 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6642 | 3d3a6a0a | aurel32 | { \ |
6643 | 3d3a6a0a | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6644 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6645 | 3d3a6a0a | aurel32 | return; \
|
6646 | 3d3a6a0a | aurel32 | } \ |
6647 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6648 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6649 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6650 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6651 | 57951c27 | aurel32 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
6652 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6653 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6654 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6655 | 57951c27 | aurel32 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6656 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6657 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6658 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6659 | 3d3a6a0a | aurel32 | } |
6660 | 57951c27 | aurel32 | #else
|
6661 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6662 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6663 | 0487d6a8 | j_mayer | { \ |
6664 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6665 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6666 | 0487d6a8 | j_mayer | return; \
|
6667 | 0487d6a8 | j_mayer | } \ |
6668 | 57951c27 | aurel32 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6669 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6670 | 57951c27 | aurel32 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6671 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6672 | 0487d6a8 | j_mayer | } |
6673 | 57951c27 | aurel32 | #endif
|
6674 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
6675 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); |
6676 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); |
6677 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); |
6678 | 0487d6a8 | j_mayer | |
6679 | 57951c27 | aurel32 | /* SPE arithmetic */
|
6680 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6681 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6682 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6683 | 0487d6a8 | j_mayer | { \ |
6684 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6685 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6686 | 0487d6a8 | j_mayer | return; \
|
6687 | 0487d6a8 | j_mayer | } \ |
6688 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6689 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6690 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6691 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6692 | 57951c27 | aurel32 | tcg_op(t0, t0); \ |
6693 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6694 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6695 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6696 | 57951c27 | aurel32 | tcg_op(t1, t1); \ |
6697 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6698 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6699 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6700 | 0487d6a8 | j_mayer | } |
6701 | 57951c27 | aurel32 | #else
|
6702 | a7812ae4 | pbrook | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6703 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6704 | 57951c27 | aurel32 | { \ |
6705 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6706 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6707 | 57951c27 | aurel32 | return; \
|
6708 | 57951c27 | aurel32 | } \ |
6709 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
6710 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ |
6711 | 57951c27 | aurel32 | } |
6712 | 57951c27 | aurel32 | #endif
|
6713 | 0487d6a8 | j_mayer | |
6714 | 636aa200 | Blue Swirl | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
6715 | 57951c27 | aurel32 | { |
6716 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
6717 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
6718 | 0487d6a8 | j_mayer | |
6719 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
|
6720 | 57951c27 | aurel32 | tcg_gen_neg_i32(ret, arg1); |
6721 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6722 | 57951c27 | aurel32 | gen_set_label(l1); |
6723 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, arg1); |
6724 | 57951c27 | aurel32 | gen_set_label(l2); |
6725 | 57951c27 | aurel32 | } |
6726 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); |
6727 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
6728 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
6729 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
6730 | 636aa200 | Blue Swirl | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
6731 | 0487d6a8 | j_mayer | { |
6732 | 57951c27 | aurel32 | tcg_gen_addi_i32(ret, arg1, 0x8000);
|
6733 | 57951c27 | aurel32 | tcg_gen_ext16u_i32(ret, ret); |
6734 | 57951c27 | aurel32 | } |
6735 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); |
6736 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
6737 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); |
6738 | 0487d6a8 | j_mayer | |
6739 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6740 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6741 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6742 | 0487d6a8 | j_mayer | { \ |
6743 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6744 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6745 | 0487d6a8 | j_mayer | return; \
|
6746 | 0487d6a8 | j_mayer | } \ |
6747 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6748 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6749 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ |
6750 | 501e23c4 | aurel32 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
6751 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6752 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ |
6753 | 57951c27 | aurel32 | tcg_op(t0, t0, t2); \ |
6754 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
|
6755 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t3); \ |
6756 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
|
6757 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, t3); \ |
6758 | a7812ae4 | pbrook | tcg_temp_free_i64(t3); \ |
6759 | 57951c27 | aurel32 | tcg_op(t1, t1, t2); \ |
6760 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); \ |
6761 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6762 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6763 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6764 | 0487d6a8 | j_mayer | } |
6765 | 57951c27 | aurel32 | #else
|
6766 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6767 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6768 | 0487d6a8 | j_mayer | { \ |
6769 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6770 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6771 | 0487d6a8 | j_mayer | return; \
|
6772 | 0487d6a8 | j_mayer | } \ |
6773 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6774 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6775 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6776 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6777 | 0487d6a8 | j_mayer | } |
6778 | 57951c27 | aurel32 | #endif
|
6779 | 0487d6a8 | j_mayer | |
6780 | 636aa200 | Blue Swirl | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6781 | 57951c27 | aurel32 | { |
6782 | a7812ae4 | pbrook | TCGv_i32 t0; |
6783 | 57951c27 | aurel32 | int l1, l2;
|
6784 | 0487d6a8 | j_mayer | |
6785 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6786 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6787 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6788 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6789 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6790 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6791 | 57951c27 | aurel32 | tcg_gen_shr_i32(ret, arg1, t0); |
6792 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6793 | 57951c27 | aurel32 | gen_set_label(l1); |
6794 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6795 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
6796 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6797 | 57951c27 | aurel32 | } |
6798 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
6799 | 636aa200 | Blue Swirl | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6800 | 57951c27 | aurel32 | { |
6801 | a7812ae4 | pbrook | TCGv_i32 t0; |
6802 | 57951c27 | aurel32 | int l1, l2;
|
6803 | 57951c27 | aurel32 | |
6804 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6805 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6806 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6807 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6808 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6809 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6810 | 57951c27 | aurel32 | tcg_gen_sar_i32(ret, arg1, t0); |
6811 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6812 | 57951c27 | aurel32 | gen_set_label(l1); |
6813 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6814 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
6815 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6816 | 57951c27 | aurel32 | } |
6817 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
6818 | 636aa200 | Blue Swirl | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6819 | 57951c27 | aurel32 | { |
6820 | a7812ae4 | pbrook | TCGv_i32 t0; |
6821 | 57951c27 | aurel32 | int l1, l2;
|
6822 | 57951c27 | aurel32 | |
6823 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6824 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6825 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6826 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6827 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6828 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6829 | 57951c27 | aurel32 | tcg_gen_shl_i32(ret, arg1, t0); |
6830 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6831 | 57951c27 | aurel32 | gen_set_label(l1); |
6832 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6833 | e29ef9fa | Aurelien Jarno | gen_set_label(l2); |
6834 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6835 | 57951c27 | aurel32 | } |
6836 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
6837 | 636aa200 | Blue Swirl | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6838 | 57951c27 | aurel32 | { |
6839 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_new_i32(); |
6840 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x1F);
|
6841 | 57951c27 | aurel32 | tcg_gen_rotl_i32(ret, arg1, t0); |
6842 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6843 | 57951c27 | aurel32 | } |
6844 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
6845 | 636aa200 | Blue Swirl | static inline void gen_evmergehi(DisasContext *ctx) |
6846 | 57951c27 | aurel32 | { |
6847 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6848 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6849 | 57951c27 | aurel32 | return;
|
6850 | 57951c27 | aurel32 | } |
6851 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6852 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6853 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6854 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
6855 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
6856 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6857 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6858 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6859 | 57951c27 | aurel32 | #else
|
6860 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
6861 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6862 | 57951c27 | aurel32 | #endif
|
6863 | 57951c27 | aurel32 | } |
6864 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
6865 | 636aa200 | Blue Swirl | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6866 | 0487d6a8 | j_mayer | { |
6867 | 57951c27 | aurel32 | tcg_gen_sub_i32(ret, arg2, arg1); |
6868 | 57951c27 | aurel32 | } |
6869 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); |
6870 | 0487d6a8 | j_mayer | |
6871 | 57951c27 | aurel32 | /* SPE arithmetic immediate */
|
6872 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6873 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6874 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6875 | 57951c27 | aurel32 | { \ |
6876 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6877 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6878 | 57951c27 | aurel32 | return; \
|
6879 | 57951c27 | aurel32 | } \ |
6880 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6881 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6882 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6883 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
6884 | 57951c27 | aurel32 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
6885 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
6886 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6887 | e06fcd75 | aurel32 | tcg_temp_free_i64(t2); \ |
6888 | 57951c27 | aurel32 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
6889 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6890 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6891 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6892 | 57951c27 | aurel32 | } |
6893 | 57951c27 | aurel32 | #else
|
6894 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6895 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6896 | 57951c27 | aurel32 | { \ |
6897 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6898 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6899 | 57951c27 | aurel32 | return; \
|
6900 | 57951c27 | aurel32 | } \ |
6901 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
6902 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6903 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ |
6904 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6905 | 57951c27 | aurel32 | } |
6906 | 57951c27 | aurel32 | #endif
|
6907 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
6908 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); |
6909 | 57951c27 | aurel32 | |
6910 | 57951c27 | aurel32 | /* SPE comparison */
|
6911 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6912 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
6913 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6914 | 57951c27 | aurel32 | { \ |
6915 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6916 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6917 | 57951c27 | aurel32 | return; \
|
6918 | 57951c27 | aurel32 | } \ |
6919 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
6920 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
6921 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
6922 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
6923 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6924 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6925 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6926 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6927 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
6928 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ |
6929 | a7812ae4 | pbrook | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
|
6930 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
6931 | 57951c27 | aurel32 | gen_set_label(l1); \ |
6932 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
6933 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
6934 | 57951c27 | aurel32 | gen_set_label(l2); \ |
6935 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6936 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, t2); \ |
6937 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
6938 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6939 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6940 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
6941 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6942 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
6943 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
6944 | 57951c27 | aurel32 | gen_set_label(l3); \ |
6945 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6946 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
6947 | 57951c27 | aurel32 | gen_set_label(l4); \ |
6948 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6949 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6950 | 57951c27 | aurel32 | } |
6951 | 57951c27 | aurel32 | #else
|
6952 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
6953 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6954 | 57951c27 | aurel32 | { \ |
6955 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6956 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6957 | 57951c27 | aurel32 | return; \
|
6958 | 57951c27 | aurel32 | } \ |
6959 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
6960 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
6961 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
6962 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
6963 | 57951c27 | aurel32 | \ |
6964 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ |
6965 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)], l1); \ |
6966 | 57951c27 | aurel32 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
|
6967 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
6968 | 57951c27 | aurel32 | gen_set_label(l1); \ |
6969 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
6970 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
6971 | 57951c27 | aurel32 | gen_set_label(l2); \ |
6972 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
6973 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)], l3); \ |
6974 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6975 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
6976 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
6977 | 57951c27 | aurel32 | gen_set_label(l3); \ |
6978 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
6979 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
6980 | 57951c27 | aurel32 | gen_set_label(l4); \ |
6981 | 57951c27 | aurel32 | } |
6982 | 57951c27 | aurel32 | #endif
|
6983 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
6984 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); |
6985 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); |
6986 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); |
6987 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
6988 | 57951c27 | aurel32 | |
6989 | 57951c27 | aurel32 | /* SPE misc */
|
6990 | 636aa200 | Blue Swirl | static inline void gen_brinc(DisasContext *ctx) |
6991 | 57951c27 | aurel32 | { |
6992 | 57951c27 | aurel32 | /* Note: brinc is usable even if SPE is disabled */
|
6993 | a7812ae4 | pbrook | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
6994 | a7812ae4 | pbrook | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6995 | 0487d6a8 | j_mayer | } |
6996 | 636aa200 | Blue Swirl | static inline void gen_evmergelo(DisasContext *ctx) |
6997 | 57951c27 | aurel32 | { |
6998 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6999 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7000 | 57951c27 | aurel32 | return;
|
7001 | 57951c27 | aurel32 | } |
7002 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7003 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7004 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7005 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
7006 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
7007 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7008 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7009 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7010 | 57951c27 | aurel32 | #else
|
7011 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7012 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7013 | 57951c27 | aurel32 | #endif
|
7014 | 57951c27 | aurel32 | } |
7015 | 636aa200 | Blue Swirl | static inline void gen_evmergehilo(DisasContext *ctx) |
7016 | 57951c27 | aurel32 | { |
7017 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7018 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7019 | 57951c27 | aurel32 | return;
|
7020 | 57951c27 | aurel32 | } |
7021 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7022 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7023 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7024 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
7025 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
7026 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7027 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7028 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7029 | 57951c27 | aurel32 | #else
|
7030 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7031 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7032 | 57951c27 | aurel32 | #endif
|
7033 | 57951c27 | aurel32 | } |
7034 | 636aa200 | Blue Swirl | static inline void gen_evmergelohi(DisasContext *ctx) |
7035 | 57951c27 | aurel32 | { |
7036 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7037 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7038 | 57951c27 | aurel32 | return;
|
7039 | 57951c27 | aurel32 | } |
7040 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7041 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7042 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7043 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
7044 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
7045 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7046 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7047 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7048 | 57951c27 | aurel32 | #else
|
7049 | 33890b3e | Nathan Froyd | if (rD(ctx->opcode) == rA(ctx->opcode)) {
|
7050 | 33890b3e | Nathan Froyd | TCGv_i32 tmp = tcg_temp_new_i32(); |
7051 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); |
7052 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7053 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); |
7054 | 33890b3e | Nathan Froyd | tcg_temp_free_i32(tmp); |
7055 | 33890b3e | Nathan Froyd | } else {
|
7056 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7057 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7058 | 33890b3e | Nathan Froyd | } |
7059 | 57951c27 | aurel32 | #endif
|
7060 | 57951c27 | aurel32 | } |
7061 | 636aa200 | Blue Swirl | static inline void gen_evsplati(DisasContext *ctx) |
7062 | 57951c27 | aurel32 | { |
7063 | ae01847f | Nathan Froyd | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
7064 | 0487d6a8 | j_mayer | |
7065 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7066 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
7067 | 57951c27 | aurel32 | #else
|
7068 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
7069 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
7070 | 57951c27 | aurel32 | #endif
|
7071 | 57951c27 | aurel32 | } |
7072 | 636aa200 | Blue Swirl | static inline void gen_evsplatfi(DisasContext *ctx) |
7073 | 0487d6a8 | j_mayer | { |
7074 | ae01847f | Nathan Froyd | uint64_t imm = rA(ctx->opcode) << 27;
|
7075 | 0487d6a8 | j_mayer | |
7076 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7077 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
7078 | 57951c27 | aurel32 | #else
|
7079 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
7080 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
7081 | 57951c27 | aurel32 | #endif
|
7082 | 0487d6a8 | j_mayer | } |
7083 | 0487d6a8 | j_mayer | |
7084 | 636aa200 | Blue Swirl | static inline void gen_evsel(DisasContext *ctx) |
7085 | 57951c27 | aurel32 | { |
7086 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
7087 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
7088 | 57951c27 | aurel32 | int l3 = gen_new_label();
|
7089 | 57951c27 | aurel32 | int l4 = gen_new_label();
|
7090 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
7091 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7092 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_local_new(); |
7093 | a7812ae4 | pbrook | TCGv t2 = tcg_temp_local_new(); |
7094 | 57951c27 | aurel32 | #endif
|
7095 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
7096 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
7097 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7098 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
7099 | 57951c27 | aurel32 | #else
|
7100 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7101 | 57951c27 | aurel32 | #endif
|
7102 | 57951c27 | aurel32 | tcg_gen_br(l2); |
7103 | 57951c27 | aurel32 | gen_set_label(l1); |
7104 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7105 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
7106 | 57951c27 | aurel32 | #else
|
7107 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7108 | 57951c27 | aurel32 | #endif
|
7109 | 57951c27 | aurel32 | gen_set_label(l2); |
7110 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); |
7111 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
|
7112 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7113 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
7114 | 57951c27 | aurel32 | #else
|
7115 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7116 | 57951c27 | aurel32 | #endif
|
7117 | 57951c27 | aurel32 | tcg_gen_br(l4); |
7118 | 57951c27 | aurel32 | gen_set_label(l3); |
7119 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7120 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
7121 | 57951c27 | aurel32 | #else
|
7122 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7123 | 57951c27 | aurel32 | #endif
|
7124 | 57951c27 | aurel32 | gen_set_label(l4); |
7125 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
7126 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7127 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); |
7128 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7129 | 57951c27 | aurel32 | tcg_temp_free(t2); |
7130 | 57951c27 | aurel32 | #endif
|
7131 | 57951c27 | aurel32 | } |
7132 | e8eaa2c0 | Blue Swirl | |
7133 | e8eaa2c0 | Blue Swirl | static void gen_evsel0(DisasContext *ctx) |
7134 | 57951c27 | aurel32 | { |
7135 | 57951c27 | aurel32 | gen_evsel(ctx); |
7136 | 57951c27 | aurel32 | } |
7137 | e8eaa2c0 | Blue Swirl | |
7138 | e8eaa2c0 | Blue Swirl | static void gen_evsel1(DisasContext *ctx) |
7139 | 57951c27 | aurel32 | { |
7140 | 57951c27 | aurel32 | gen_evsel(ctx); |
7141 | 57951c27 | aurel32 | } |
7142 | e8eaa2c0 | Blue Swirl | |
7143 | e8eaa2c0 | Blue Swirl | static void gen_evsel2(DisasContext *ctx) |
7144 | 57951c27 | aurel32 | { |
7145 | 57951c27 | aurel32 | gen_evsel(ctx); |
7146 | 57951c27 | aurel32 | } |
7147 | e8eaa2c0 | Blue Swirl | |
7148 | e8eaa2c0 | Blue Swirl | static void gen_evsel3(DisasContext *ctx) |
7149 | 57951c27 | aurel32 | { |
7150 | 57951c27 | aurel32 | gen_evsel(ctx); |
7151 | 57951c27 | aurel32 | } |
7152 | 0487d6a8 | j_mayer | |
7153 | a0e13900 | Fabien Chouteau | /* Multiply */
|
7154 | a0e13900 | Fabien Chouteau | |
7155 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumi(DisasContext *ctx) |
7156 | a0e13900 | Fabien Chouteau | { |
7157 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
7158 | a0e13900 | Fabien Chouteau | |
7159 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7160 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7161 | a0e13900 | Fabien Chouteau | return;
|
7162 | a0e13900 | Fabien Chouteau | } |
7163 | a0e13900 | Fabien Chouteau | |
7164 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
7165 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
7166 | a0e13900 | Fabien Chouteau | |
7167 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
7168 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
7169 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
7170 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
7171 | a0e13900 | Fabien Chouteau | #else
|
7172 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
7173 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
7174 | a0e13900 | Fabien Chouteau | #endif
|
7175 | a0e13900 | Fabien Chouteau | |
7176 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
7177 | a0e13900 | Fabien Chouteau | |
7178 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
7179 | a0e13900 | Fabien Chouteau | |
7180 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
7181 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
7182 | a0e13900 | Fabien Chouteau | } |
7183 | a0e13900 | Fabien Chouteau | |
7184 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumia(DisasContext *ctx) |
7185 | a0e13900 | Fabien Chouteau | { |
7186 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7187 | a0e13900 | Fabien Chouteau | |
7188 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7189 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7190 | a0e13900 | Fabien Chouteau | return;
|
7191 | a0e13900 | Fabien Chouteau | } |
7192 | a0e13900 | Fabien Chouteau | |
7193 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
7194 | a0e13900 | Fabien Chouteau | |
7195 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7196 | a0e13900 | Fabien Chouteau | |
7197 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
7198 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7199 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
7200 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7201 | a0e13900 | Fabien Chouteau | } |
7202 | a0e13900 | Fabien Chouteau | |
7203 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumiaa(DisasContext *ctx) |
7204 | a0e13900 | Fabien Chouteau | { |
7205 | a0e13900 | Fabien Chouteau | TCGv_i64 acc; |
7206 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7207 | a0e13900 | Fabien Chouteau | |
7208 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7209 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7210 | a0e13900 | Fabien Chouteau | return;
|
7211 | a0e13900 | Fabien Chouteau | } |
7212 | a0e13900 | Fabien Chouteau | |
7213 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
7214 | a0e13900 | Fabien Chouteau | |
7215 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
7216 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7217 | a0e13900 | Fabien Chouteau | |
7218 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
7219 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7220 | a0e13900 | Fabien Chouteau | |
7221 | a0e13900 | Fabien Chouteau | /* Load acc */
|
7222 | a0e13900 | Fabien Chouteau | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7223 | a0e13900 | Fabien Chouteau | |
7224 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
7225 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
7226 | a0e13900 | Fabien Chouteau | |
7227 | a0e13900 | Fabien Chouteau | /* Store acc */
|
7228 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7229 | a0e13900 | Fabien Chouteau | |
7230 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
7231 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
7232 | a0e13900 | Fabien Chouteau | |
7233 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
7234 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7235 | a0e13900 | Fabien Chouteau | } |
7236 | a0e13900 | Fabien Chouteau | |
7237 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmi(DisasContext *ctx) |
7238 | a0e13900 | Fabien Chouteau | { |
7239 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
7240 | a0e13900 | Fabien Chouteau | |
7241 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7242 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7243 | a0e13900 | Fabien Chouteau | return;
|
7244 | a0e13900 | Fabien Chouteau | } |
7245 | a0e13900 | Fabien Chouteau | |
7246 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
7247 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
7248 | a0e13900 | Fabien Chouteau | |
7249 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
7250 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
7251 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
7252 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
7253 | a0e13900 | Fabien Chouteau | #else
|
7254 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
7255 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
7256 | a0e13900 | Fabien Chouteau | #endif
|
7257 | a0e13900 | Fabien Chouteau | |
7258 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
7259 | a0e13900 | Fabien Chouteau | |
7260 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
7261 | a0e13900 | Fabien Chouteau | |
7262 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
7263 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
7264 | a0e13900 | Fabien Chouteau | } |
7265 | a0e13900 | Fabien Chouteau | |
7266 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmia(DisasContext *ctx) |
7267 | a0e13900 | Fabien Chouteau | { |
7268 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7269 | a0e13900 | Fabien Chouteau | |
7270 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
7271 | a0e13900 | Fabien Chouteau | |
7272 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7273 | a0e13900 | Fabien Chouteau | |
7274 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
7275 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7276 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
7277 | a0e13900 | Fabien Chouteau | |
7278 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7279 | a0e13900 | Fabien Chouteau | } |
7280 | a0e13900 | Fabien Chouteau | |
7281 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmiaa(DisasContext *ctx) |
7282 | a0e13900 | Fabien Chouteau | { |
7283 | a0e13900 | Fabien Chouteau | TCGv_i64 acc = tcg_temp_new_i64(); |
7284 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
7285 | a0e13900 | Fabien Chouteau | |
7286 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
7287 | a0e13900 | Fabien Chouteau | |
7288 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
7289 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7290 | a0e13900 | Fabien Chouteau | |
7291 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
7292 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7293 | a0e13900 | Fabien Chouteau | |
7294 | a0e13900 | Fabien Chouteau | /* Load acc */
|
7295 | a0e13900 | Fabien Chouteau | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7296 | a0e13900 | Fabien Chouteau | |
7297 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
7298 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
7299 | a0e13900 | Fabien Chouteau | |
7300 | a0e13900 | Fabien Chouteau | /* Store acc */
|
7301 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7302 | a0e13900 | Fabien Chouteau | |
7303 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
7304 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
7305 | a0e13900 | Fabien Chouteau | |
7306 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
7307 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7308 | a0e13900 | Fabien Chouteau | } |
7309 | a0e13900 | Fabien Chouteau | |
7310 | 0487d6a8 | j_mayer | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
7311 | 0487d6a8 | j_mayer | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
7312 | 0487d6a8 | j_mayer | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
7313 | 0487d6a8 | j_mayer | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
7314 | 0487d6a8 | j_mayer | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
7315 | 0487d6a8 | j_mayer | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
7316 | 0487d6a8 | j_mayer | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
7317 | 0487d6a8 | j_mayer | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
7318 | a0e13900 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE); |
7319 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
7320 | 0487d6a8 | j_mayer | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
7321 | 0487d6a8 | j_mayer | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
7322 | 0487d6a8 | j_mayer | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
7323 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); |
7324 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); |
7325 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); |
7326 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
7327 | 0487d6a8 | j_mayer | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
7328 | 0487d6a8 | j_mayer | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
7329 | 0487d6a8 | j_mayer | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
7330 | 0487d6a8 | j_mayer | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
7331 | 0487d6a8 | j_mayer | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
7332 | 0487d6a8 | j_mayer | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
7333 | 0487d6a8 | j_mayer | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
7334 | 0487d6a8 | j_mayer | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
7335 | 0487d6a8 | j_mayer | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
7336 | 0487d6a8 | j_mayer | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
7337 | 0487d6a8 | j_mayer | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
7338 | 0487d6a8 | j_mayer | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
7339 | 0487d6a8 | j_mayer | |
7340 | 6a6ae23f | aurel32 | /* SPE load and stores */
|
7341 | 636aa200 | Blue Swirl | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
7342 | 6a6ae23f | aurel32 | { |
7343 | 6a6ae23f | aurel32 | target_ulong uimm = rB(ctx->opcode); |
7344 | 6a6ae23f | aurel32 | |
7345 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
7346 | 6a6ae23f | aurel32 | tcg_gen_movi_tl(EA, uimm << sh); |
7347 | 76db3ba4 | aurel32 | } else {
|
7348 | 6a6ae23f | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
7349 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
7350 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
7351 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
7352 | 76db3ba4 | aurel32 | } |
7353 | 76db3ba4 | aurel32 | #endif
|
7354 | 76db3ba4 | aurel32 | } |
7355 | 0487d6a8 | j_mayer | } |
7356 | 6a6ae23f | aurel32 | |
7357 | 636aa200 | Blue Swirl | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
7358 | 6a6ae23f | aurel32 | { |
7359 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7360 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7361 | 6a6ae23f | aurel32 | #else
|
7362 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7363 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, t0, addr); |
7364 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7365 | 6a6ae23f | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
7366 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); |
7367 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7368 | 6a6ae23f | aurel32 | #endif
|
7369 | 0487d6a8 | j_mayer | } |
7370 | 6a6ae23f | aurel32 | |
7371 | 636aa200 | Blue Swirl | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
7372 | 6a6ae23f | aurel32 | { |
7373 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7374 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7375 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7376 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7377 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7378 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7379 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7380 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7381 | 6a6ae23f | aurel32 | #else
|
7382 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7383 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7384 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7385 | 6a6ae23f | aurel32 | #endif
|
7386 | 0487d6a8 | j_mayer | } |
7387 | 6a6ae23f | aurel32 | |
7388 | 636aa200 | Blue Swirl | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
7389 | 6a6ae23f | aurel32 | { |
7390 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7391 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7392 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7393 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7394 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7395 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7396 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7397 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7398 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7399 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7400 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7401 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7402 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7403 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7404 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7405 | 0487d6a8 | j_mayer | #else
|
7406 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7407 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7408 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7409 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7410 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7411 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7412 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7413 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7414 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7415 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7416 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7417 | 0487d6a8 | j_mayer | #endif
|
7418 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7419 | 0487d6a8 | j_mayer | } |
7420 | 0487d6a8 | j_mayer | |
7421 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
7422 | 6a6ae23f | aurel32 | { |
7423 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7424 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7425 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7426 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7427 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7428 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7429 | 6a6ae23f | aurel32 | #else
|
7430 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7431 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7432 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7433 | 6a6ae23f | aurel32 | #endif
|
7434 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7435 | 0487d6a8 | j_mayer | } |
7436 | 0487d6a8 | j_mayer | |
7437 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
7438 | 6a6ae23f | aurel32 | { |
7439 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7440 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7441 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7442 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7443 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7444 | 6a6ae23f | aurel32 | #else
|
7445 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7446 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7447 | 6a6ae23f | aurel32 | #endif
|
7448 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7449 | 0487d6a8 | j_mayer | } |
7450 | 0487d6a8 | j_mayer | |
7451 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
7452 | 6a6ae23f | aurel32 | { |
7453 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7454 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7455 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7456 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7457 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(t0, t0); |
7458 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7459 | 6a6ae23f | aurel32 | #else
|
7460 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7461 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7462 | 6a6ae23f | aurel32 | #endif
|
7463 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7464 | 6a6ae23f | aurel32 | } |
7465 | 6a6ae23f | aurel32 | |
7466 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
7467 | 6a6ae23f | aurel32 | { |
7468 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7469 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7470 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7471 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7472 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7473 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7474 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7475 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7476 | 6a6ae23f | aurel32 | #else
|
7477 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7478 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7479 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7480 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7481 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7482 | 6a6ae23f | aurel32 | #endif
|
7483 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7484 | 6a6ae23f | aurel32 | } |
7485 | 6a6ae23f | aurel32 | |
7486 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
7487 | 6a6ae23f | aurel32 | { |
7488 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7489 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7490 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7491 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7492 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7493 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7494 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7495 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7496 | 6a6ae23f | aurel32 | #else
|
7497 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7498 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7499 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7500 | 6a6ae23f | aurel32 | #endif
|
7501 | 6a6ae23f | aurel32 | } |
7502 | 6a6ae23f | aurel32 | |
7503 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
7504 | 6a6ae23f | aurel32 | { |
7505 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7506 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7507 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7508 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7509 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7510 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7511 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7512 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7513 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7514 | 6a6ae23f | aurel32 | #else
|
7515 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7516 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7517 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7518 | 6a6ae23f | aurel32 | #endif
|
7519 | 6a6ae23f | aurel32 | } |
7520 | 6a6ae23f | aurel32 | |
7521 | 636aa200 | Blue Swirl | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
7522 | 6a6ae23f | aurel32 | { |
7523 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7524 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7525 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7526 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7527 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7528 | 6a6ae23f | aurel32 | #else
|
7529 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7530 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7531 | 6a6ae23f | aurel32 | #endif
|
7532 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7533 | 6a6ae23f | aurel32 | } |
7534 | 6a6ae23f | aurel32 | |
7535 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
7536 | 6a6ae23f | aurel32 | { |
7537 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7538 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7539 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7540 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7541 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7542 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7543 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7544 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7545 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7546 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7547 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7548 | 6a6ae23f | aurel32 | #else
|
7549 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7550 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7551 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7552 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7553 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7554 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7555 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7556 | 0487d6a8 | j_mayer | #endif
|
7557 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7558 | 6a6ae23f | aurel32 | } |
7559 | 6a6ae23f | aurel32 | |
7560 | 636aa200 | Blue Swirl | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
7561 | 6a6ae23f | aurel32 | { |
7562 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7563 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7564 | 0487d6a8 | j_mayer | #else
|
7565 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7566 | 6a6ae23f | aurel32 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); |
7567 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, t0, addr); |
7568 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7569 | 6a6ae23f | aurel32 | #endif
|
7570 | 6a6ae23f | aurel32 | } |
7571 | 6a6ae23f | aurel32 | |
7572 | 636aa200 | Blue Swirl | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
7573 | 6a6ae23f | aurel32 | { |
7574 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7575 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7576 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7577 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7578 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7579 | 6a6ae23f | aurel32 | #else
|
7580 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7581 | 6a6ae23f | aurel32 | #endif
|
7582 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7583 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7584 | 6a6ae23f | aurel32 | } |
7585 | 6a6ae23f | aurel32 | |
7586 | 636aa200 | Blue Swirl | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
7587 | 6a6ae23f | aurel32 | { |
7588 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7589 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7590 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7591 | 6a6ae23f | aurel32 | #else
|
7592 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7593 | 6a6ae23f | aurel32 | #endif
|
7594 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7595 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7596 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7597 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7598 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7599 | 6a6ae23f | aurel32 | #else
|
7600 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7601 | 6a6ae23f | aurel32 | #endif
|
7602 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7603 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7604 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7605 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7606 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7607 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7608 | 6a6ae23f | aurel32 | } |
7609 | 6a6ae23f | aurel32 | |
7610 | 636aa200 | Blue Swirl | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
7611 | 6a6ae23f | aurel32 | { |
7612 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7613 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7614 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7615 | 6a6ae23f | aurel32 | #else
|
7616 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7617 | 6a6ae23f | aurel32 | #endif
|
7618 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7619 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7620 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7621 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7622 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7623 | 6a6ae23f | aurel32 | } |
7624 | 6a6ae23f | aurel32 | |
7625 | 636aa200 | Blue Swirl | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
7626 | 6a6ae23f | aurel32 | { |
7627 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7628 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7629 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7630 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7631 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7632 | 6a6ae23f | aurel32 | #else
|
7633 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7634 | 6a6ae23f | aurel32 | #endif
|
7635 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7636 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7637 | 6a6ae23f | aurel32 | } |
7638 | 6a6ae23f | aurel32 | |
7639 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
7640 | 6a6ae23f | aurel32 | { |
7641 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7642 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7643 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7644 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7645 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7646 | 6a6ae23f | aurel32 | #else
|
7647 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7648 | 6a6ae23f | aurel32 | #endif
|
7649 | 6a6ae23f | aurel32 | } |
7650 | 6a6ae23f | aurel32 | |
7651 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
7652 | 6a6ae23f | aurel32 | { |
7653 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7654 | 6a6ae23f | aurel32 | } |
7655 | 6a6ae23f | aurel32 | |
7656 | 6a6ae23f | aurel32 | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
7657 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
7658 | 6a6ae23f | aurel32 | { \ |
7659 | 6a6ae23f | aurel32 | TCGv t0; \ |
7660 | 6a6ae23f | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7661 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7662 | 6a6ae23f | aurel32 | return; \
|
7663 | 6a6ae23f | aurel32 | } \ |
7664 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
7665 | 6a6ae23f | aurel32 | t0 = tcg_temp_new(); \ |
7666 | 6a6ae23f | aurel32 | if (Rc(ctx->opcode)) { \
|
7667 | 76db3ba4 | aurel32 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
7668 | 6a6ae23f | aurel32 | } else { \
|
7669 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); \ |
7670 | 6a6ae23f | aurel32 | } \ |
7671 | 6a6ae23f | aurel32 | gen_op_##name(ctx, t0); \ |
7672 | 6a6ae23f | aurel32 | tcg_temp_free(t0); \ |
7673 | 6a6ae23f | aurel32 | } |
7674 | 6a6ae23f | aurel32 | |
7675 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldd, 0x00, 3); |
7676 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldw, 0x01, 3); |
7677 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldh, 0x02, 3); |
7678 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); |
7679 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); |
7680 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); |
7681 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); |
7682 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); |
7683 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); |
7684 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); |
7685 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); |
7686 | 6a6ae23f | aurel32 | |
7687 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdd, 0x10, 3); |
7688 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdw, 0x11, 3); |
7689 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdh, 0x12, 3); |
7690 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); |
7691 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); |
7692 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); |
7693 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); |
7694 | 0487d6a8 | j_mayer | |
7695 | 0487d6a8 | j_mayer | /* Multiply and add - TODO */
|
7696 | 0487d6a8 | j_mayer | #if 0
|
7697 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
|
7698 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
|
7699 | 0487d6a8 | j_mayer | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
|
7700 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
|
7701 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
|
7702 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
|
7703 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
|
7704 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
|
7705 | 0487d6a8 | j_mayer | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
|
7706 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
|
7707 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
|
7708 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
|
7709 | 0487d6a8 | j_mayer | |
7710 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
|
7711 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
|
7712 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
|
7713 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
|
7714 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
|
7715 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
|
7716 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
|
7717 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
|
7718 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
|
7719 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
|
7720 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
|
7721 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
|
7722 | 0487d6a8 | j_mayer | |
7723 | 0487d6a8 | j_mayer | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
|
7724 | 0487d6a8 | j_mayer | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
|
7725 | 0487d6a8 | j_mayer | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
|
7726 | 0487d6a8 | j_mayer | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
|
7727 | 0487d6a8 | j_mayer | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
|
7728 | 0487d6a8 | j_mayer | |
7729 | 0487d6a8 | j_mayer | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
|
7730 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
|
7731 | 0487d6a8 | j_mayer | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
|
7732 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
|
7733 | 0487d6a8 | j_mayer | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
|
7734 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
|
7735 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
|
7736 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
|
7737 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
|
7738 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
|
7739 | 0487d6a8 | j_mayer | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
|
7740 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
|
7741 | 0487d6a8 | j_mayer | |
7742 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
|
7743 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
|
7744 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
|
7745 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
|
7746 | 0487d6a8 | j_mayer | |
7747 | 0487d6a8 | j_mayer | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
|
7748 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
|
7749 | 0487d6a8 | j_mayer | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
|
7750 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
|
7751 | 0487d6a8 | j_mayer | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
|
7752 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
|
7753 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
|
7754 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
|
7755 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
|
7756 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
|
7757 | 0487d6a8 | j_mayer | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
|
7758 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
|
7759 | 0487d6a8 | j_mayer | |
7760 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
|
7761 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
|
7762 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
|
7763 | 0487d6a8 | j_mayer | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
|
7764 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
|
7765 | 0487d6a8 | j_mayer | #endif
|
7766 | 0487d6a8 | j_mayer | |
7767 | 0487d6a8 | j_mayer | /*** SPE floating-point extension ***/
|
7768 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7769 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7770 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7771 | 0487d6a8 | j_mayer | { \ |
7772 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7773 | 1c97856d | aurel32 | TCGv t1; \ |
7774 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7775 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7776 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7777 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7778 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7779 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7780 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7781 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7782 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7783 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7784 | 0487d6a8 | j_mayer | } |
7785 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7786 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7787 | 1c97856d | aurel32 | { \ |
7788 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7789 | 1c97856d | aurel32 | TCGv t1; \ |
7790 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7791 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7792 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7793 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7794 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7795 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7796 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7797 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7798 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7799 | 1c97856d | aurel32 | } |
7800 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7801 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7802 | 1c97856d | aurel32 | { \ |
7803 | 1c97856d | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); \ |
7804 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7805 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7806 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7807 | 1c97856d | aurel32 | } |
7808 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7809 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7810 | 1c97856d | aurel32 | { \ |
7811 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7812 | 1c97856d | aurel32 | } |
7813 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7814 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7815 | 57951c27 | aurel32 | { \ |
7816 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7817 | 1c97856d | aurel32 | TCGv_i64 t2; \ |
7818 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7819 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7820 | 57951c27 | aurel32 | return; \
|
7821 | 57951c27 | aurel32 | } \ |
7822 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7823 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7824 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7825 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7826 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
7827 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7828 | 1c97856d | aurel32 | t2 = tcg_temp_new(); \ |
7829 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t2, t0); \ |
7830 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7831 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7832 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7833 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ |
7834 | 1c97856d | aurel32 | tcg_temp_free(t2); \ |
7835 | 57951c27 | aurel32 | } |
7836 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
7837 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7838 | 57951c27 | aurel32 | { \ |
7839 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7840 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7841 | 57951c27 | aurel32 | return; \
|
7842 | 57951c27 | aurel32 | } \ |
7843 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7844 | 1c97856d | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
7845 | 57951c27 | aurel32 | } |
7846 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
7847 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7848 | 57951c27 | aurel32 | { \ |
7849 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7850 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7851 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7852 | 57951c27 | aurel32 | return; \
|
7853 | 57951c27 | aurel32 | } \ |
7854 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7855 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7856 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7857 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7858 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
7859 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7860 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7861 | 1c97856d | aurel32 | } |
7862 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
7863 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7864 | 1c97856d | aurel32 | { \ |
7865 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7866 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7867 | 1c97856d | aurel32 | return; \
|
7868 | 1c97856d | aurel32 | } \ |
7869 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
7870 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7871 | 1c97856d | aurel32 | } |
7872 | 1c97856d | aurel32 | #else
|
7873 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7874 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7875 | 1c97856d | aurel32 | { \ |
7876 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7877 | 57951c27 | aurel32 | } |
7878 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7879 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7880 | 1c97856d | aurel32 | { \ |
7881 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7882 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7883 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7884 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7885 | 1c97856d | aurel32 | } |
7886 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7887 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7888 | 1c97856d | aurel32 | { \ |
7889 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7890 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7891 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7892 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7893 | 1c97856d | aurel32 | } |
7894 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7895 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7896 | 1c97856d | aurel32 | { \ |
7897 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7898 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7899 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7900 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7901 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7902 | 1c97856d | aurel32 | } |
7903 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7904 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7905 | 1c97856d | aurel32 | { \ |
7906 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7907 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7908 | 1c97856d | aurel32 | return; \
|
7909 | 1c97856d | aurel32 | } \ |
7910 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ |
7911 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7912 | 1c97856d | aurel32 | } |
7913 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
7914 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7915 | 1c97856d | aurel32 | { \ |
7916 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
7917 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7918 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7919 | 1c97856d | aurel32 | return; \
|
7920 | 1c97856d | aurel32 | } \ |
7921 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
7922 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
7923 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
7924 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
7925 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
7926 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7927 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7928 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
7929 | 1c97856d | aurel32 | } |
7930 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
7931 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7932 | 1c97856d | aurel32 | { \ |
7933 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7934 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7935 | 1c97856d | aurel32 | return; \
|
7936 | 1c97856d | aurel32 | } \ |
7937 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
7938 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7939 | 1c97856d | aurel32 | } |
7940 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
7941 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7942 | 1c97856d | aurel32 | { \ |
7943 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
7944 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7945 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7946 | 1c97856d | aurel32 | return; \
|
7947 | 1c97856d | aurel32 | } \ |
7948 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
7949 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
7950 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
7951 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
7952 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
7953 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7954 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
7955 | 1c97856d | aurel32 | } |
7956 | 1c97856d | aurel32 | #endif
|
7957 | 57951c27 | aurel32 | |
7958 | 0487d6a8 | j_mayer | /* Single precision floating-point vectors operations */
|
7959 | 0487d6a8 | j_mayer | /* Arithmetic */
|
7960 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
7961 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
7962 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
7963 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
7964 | 636aa200 | Blue Swirl | static inline void gen_evfsabs(DisasContext *ctx) |
7965 | 1c97856d | aurel32 | { |
7966 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7967 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7968 | 1c97856d | aurel32 | return;
|
7969 | 1c97856d | aurel32 | } |
7970 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7971 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
|
7972 | 1c97856d | aurel32 | #else
|
7973 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
7974 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
7975 | 1c97856d | aurel32 | #endif
|
7976 | 1c97856d | aurel32 | } |
7977 | 636aa200 | Blue Swirl | static inline void gen_evfsnabs(DisasContext *ctx) |
7978 | 1c97856d | aurel32 | { |
7979 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7980 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7981 | 1c97856d | aurel32 | return;
|
7982 | 1c97856d | aurel32 | } |
7983 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7984 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
7985 | 1c97856d | aurel32 | #else
|
7986 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
7987 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
7988 | 1c97856d | aurel32 | #endif
|
7989 | 1c97856d | aurel32 | } |
7990 | 636aa200 | Blue Swirl | static inline void gen_evfsneg(DisasContext *ctx) |
7991 | 1c97856d | aurel32 | { |
7992 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7993 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7994 | 1c97856d | aurel32 | return;
|
7995 | 1c97856d | aurel32 | } |
7996 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7997 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
7998 | 1c97856d | aurel32 | #else
|
7999 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8000 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8001 | 1c97856d | aurel32 | #endif
|
8002 | 1c97856d | aurel32 | } |
8003 | 1c97856d | aurel32 | |
8004 | 0487d6a8 | j_mayer | /* Conversion */
|
8005 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8006 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); |
8007 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); |
8008 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); |
8009 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctui); |
8010 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); |
8011 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); |
8012 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); |
8013 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); |
8014 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); |
8015 | 1c97856d | aurel32 | |
8016 | 0487d6a8 | j_mayer | /* Comparison */
|
8017 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8018 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmplt); |
8019 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpeq); |
8020 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststgt); |
8021 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststlt); |
8022 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststeq); |
8023 | 0487d6a8 | j_mayer | |
8024 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8025 | 40569b7e | aurel32 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8026 | 40569b7e | aurel32 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
8027 | 40569b7e | aurel32 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
8028 | 40569b7e | aurel32 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8029 | 40569b7e | aurel32 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8030 | 40569b7e | aurel32 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8031 | 40569b7e | aurel32 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8032 | 40569b7e | aurel32 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8033 | 40569b7e | aurel32 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8034 | 40569b7e | aurel32 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8035 | 40569b7e | aurel32 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8036 | 40569b7e | aurel32 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8037 | 40569b7e | aurel32 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8038 | 40569b7e | aurel32 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8039 | 0487d6a8 | j_mayer | |
8040 | 0487d6a8 | j_mayer | /* Single precision floating-point operations */
|
8041 | 0487d6a8 | j_mayer | /* Arithmetic */
|
8042 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8043 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efssub); |
8044 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
8045 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
8046 | 636aa200 | Blue Swirl | static inline void gen_efsabs(DisasContext *ctx) |
8047 | 1c97856d | aurel32 | { |
8048 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8049 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8050 | 1c97856d | aurel32 | return;
|
8051 | 1c97856d | aurel32 | } |
8052 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
|
8053 | 1c97856d | aurel32 | } |
8054 | 636aa200 | Blue Swirl | static inline void gen_efsnabs(DisasContext *ctx) |
8055 | 1c97856d | aurel32 | { |
8056 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8057 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8058 | 1c97856d | aurel32 | return;
|
8059 | 1c97856d | aurel32 | } |
8060 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8061 | 1c97856d | aurel32 | } |
8062 | 636aa200 | Blue Swirl | static inline void gen_efsneg(DisasContext *ctx) |
8063 | 1c97856d | aurel32 | { |
8064 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8065 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8066 | 1c97856d | aurel32 | return;
|
8067 | 1c97856d | aurel32 | } |
8068 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8069 | 1c97856d | aurel32 | } |
8070 | 1c97856d | aurel32 | |
8071 | 0487d6a8 | j_mayer | /* Conversion */
|
8072 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8073 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsi); |
8074 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfuf); |
8075 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsf); |
8076 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctui); |
8077 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsi); |
8078 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuf); |
8079 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsf); |
8080 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); |
8081 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); |
8082 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efscfd); |
8083 | 1c97856d | aurel32 | |
8084 | 0487d6a8 | j_mayer | /* Comparison */
|
8085 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8086 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmplt); |
8087 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpeq); |
8088 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststgt); |
8089 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststlt); |
8090 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststeq); |
8091 | 0487d6a8 | j_mayer | |
8092 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8093 | 40569b7e | aurel32 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8094 | 40569b7e | aurel32 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
8095 | 40569b7e | aurel32 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
8096 | 40569b7e | aurel32 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8097 | 40569b7e | aurel32 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8098 | 40569b7e | aurel32 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8099 | 40569b7e | aurel32 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8100 | 40569b7e | aurel32 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8101 | 40569b7e | aurel32 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8102 | 40569b7e | aurel32 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8103 | 40569b7e | aurel32 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8104 | 40569b7e | aurel32 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8105 | 40569b7e | aurel32 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8106 | 40569b7e | aurel32 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8107 | 0487d6a8 | j_mayer | |
8108 | 0487d6a8 | j_mayer | /* Double precision floating-point operations */
|
8109 | 0487d6a8 | j_mayer | /* Arithmetic */
|
8110 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8111 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
8112 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
8113 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
8114 | 636aa200 | Blue Swirl | static inline void gen_efdabs(DisasContext *ctx) |
8115 | 1c97856d | aurel32 | { |
8116 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8117 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8118 | 1c97856d | aurel32 | return;
|
8119 | 1c97856d | aurel32 | } |
8120 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8121 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
8122 | 1c97856d | aurel32 | #else
|
8123 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8124 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
8125 | 1c97856d | aurel32 | #endif
|
8126 | 1c97856d | aurel32 | } |
8127 | 636aa200 | Blue Swirl | static inline void gen_efdnabs(DisasContext *ctx) |
8128 | 1c97856d | aurel32 | { |
8129 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8130 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8131 | 1c97856d | aurel32 | return;
|
8132 | 1c97856d | aurel32 | } |
8133 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8134 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
8135 | 1c97856d | aurel32 | #else
|
8136 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8137 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8138 | 1c97856d | aurel32 | #endif
|
8139 | 1c97856d | aurel32 | } |
8140 | 636aa200 | Blue Swirl | static inline void gen_efdneg(DisasContext *ctx) |
8141 | 1c97856d | aurel32 | { |
8142 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8143 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8144 | 1c97856d | aurel32 | return;
|
8145 | 1c97856d | aurel32 | } |
8146 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8147 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
8148 | 1c97856d | aurel32 | #else
|
8149 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8150 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8151 | 1c97856d | aurel32 | #endif
|
8152 | 1c97856d | aurel32 | } |
8153 | 1c97856d | aurel32 | |
8154 | 0487d6a8 | j_mayer | /* Conversion */
|
8155 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8156 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); |
8157 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); |
8158 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); |
8159 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctui); |
8160 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsi); |
8161 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuf); |
8162 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsf); |
8163 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); |
8164 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); |
8165 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfs); |
8166 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); |
8167 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); |
8168 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); |
8169 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); |
8170 | 0487d6a8 | j_mayer | |
8171 | 0487d6a8 | j_mayer | /* Comparison */
|
8172 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8173 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmplt); |
8174 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpeq); |
8175 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstgt); |
8176 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstlt); |
8177 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtsteq); |
8178 | 0487d6a8 | j_mayer | |
8179 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8180 | 40569b7e | aurel32 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8181 | 40569b7e | aurel32 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8182 | 40569b7e | aurel32 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
8183 | 40569b7e | aurel32 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
8184 | 40569b7e | aurel32 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8185 | 40569b7e | aurel32 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8186 | 40569b7e | aurel32 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8187 | 40569b7e | aurel32 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8188 | 40569b7e | aurel32 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8189 | 40569b7e | aurel32 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8190 | 40569b7e | aurel32 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8191 | 40569b7e | aurel32 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8192 | 40569b7e | aurel32 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8193 | 40569b7e | aurel32 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8194 | 40569b7e | aurel32 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8195 | 40569b7e | aurel32 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8196 | 0487d6a8 | j_mayer | |
8197 | c227f099 | Anthony Liguori | static opcode_t opcodes[] = {
|
8198 | 5c55ff99 | Blue Swirl | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8199 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
8200 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
8201 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), |
8202 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
8203 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
8204 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8205 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8206 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8207 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8208 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
8209 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
8210 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
8211 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
8212 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8213 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8214 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
8215 | 5c55ff99 | Blue Swirl | #endif
|
8216 | 5c55ff99 | Blue Swirl | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
8217 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
8218 | 5c55ff99 | Blue Swirl | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8219 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8220 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8221 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
8222 | 5c55ff99 | Blue Swirl | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
8223 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
8224 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8225 | 5c55ff99 | Blue Swirl | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8226 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8227 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8228 | 5c55ff99 | Blue Swirl | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), |
8229 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8230 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8231 | 5c55ff99 | Blue Swirl | #endif
|
8232 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8233 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8234 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8235 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
8236 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
8237 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
8238 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
8239 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8240 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
8241 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
8242 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
8243 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
8244 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
8245 | 5c55ff99 | Blue Swirl | #endif
|
8246 | 5c55ff99 | Blue Swirl | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), |
8247 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
8248 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
8249 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), |
8250 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), |
8251 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
8252 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
8253 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), |
8254 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), |
8255 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), |
8256 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), |
8257 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), |
8258 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8259 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8260 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
8261 | 5c55ff99 | Blue Swirl | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8262 | 5c55ff99 | Blue Swirl | #endif
|
8263 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8264 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8265 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
8266 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
8267 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
8268 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
8269 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), |
8270 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
8271 | f844c817 | Alexander Graf | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
8272 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8273 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8274 | f844c817 | Alexander Graf | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
8275 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8276 | 5c55ff99 | Blue Swirl | #endif
|
8277 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
8278 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
8279 | 5c55ff99 | Blue Swirl | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8280 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8281 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
8282 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
8283 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
8284 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
8285 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8286 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
8287 | 5c55ff99 | Blue Swirl | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
8288 | 5c55ff99 | Blue Swirl | #endif
|
8289 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
8290 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
8291 | 5c55ff99 | Blue Swirl | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8292 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8293 | 5c55ff99 | Blue Swirl | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
8294 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8295 | 5c55ff99 | Blue Swirl | #endif
|
8296 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
8297 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
8298 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
8299 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
8300 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
8301 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
8302 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8303 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
8304 | 5c55ff99 | Blue Swirl | #endif
|
8305 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), |
8306 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), |
8307 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
8308 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
8309 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
8310 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), |
8311 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), |
8312 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), |
8313 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), |
8314 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8315 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |
8316 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
8317 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
8318 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
8319 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
8320 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
8321 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
8322 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
8323 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8324 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
8325 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
8326 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8327 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
8328 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
8329 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8330 | efdef95f | David Gibson | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8331 | efdef95f | David Gibson | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), |
8332 | efdef95f | David Gibson | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), |
8333 | 5c55ff99 | Blue Swirl | #endif
|
8334 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
8335 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), |
8336 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), |
8337 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
8338 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8339 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |
8340 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
8341 | 5c55ff99 | Blue Swirl | #endif
|
8342 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
8343 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
8344 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
8345 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
8346 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
8347 | 5c55ff99 | Blue Swirl | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
8348 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
8349 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
8350 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
8351 | 5c55ff99 | Blue Swirl | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
8352 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
8353 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8354 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
8355 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
8356 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
8357 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
8358 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
8359 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
8360 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
8361 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8362 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
8363 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
8364 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
8365 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
8366 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
8367 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
8368 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
8369 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
8370 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
8371 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
8372 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
8373 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
8374 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
8375 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
8376 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
8377 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
8378 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
8379 | 5c55ff99 | Blue Swirl | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
8380 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
8381 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
8382 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
8383 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
8384 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
8385 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
8386 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
8387 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
8388 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
8389 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
8390 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
8391 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8392 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8393 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
8394 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
8395 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8396 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8397 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
8398 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
8399 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
8400 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
8401 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
8402 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
8403 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
8404 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
8405 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
8406 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
8407 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
8408 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
8409 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
8410 | 5c55ff99 | Blue Swirl | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
8411 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
8412 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
8413 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE), |
8414 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8415 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
8416 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
8417 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
8418 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
8419 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
8420 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
8421 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
8422 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
8423 | fbe73008 | Baojun Wang | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
8424 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
8425 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE), |
8426 | 5c55ff99 | Blue Swirl | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
8427 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE), |
8428 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8429 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
8430 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
8431 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
8432 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), |
8433 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
8434 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), |
8435 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), |
8436 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), |
8437 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), |
8438 | 5c55ff99 | Blue Swirl | |
8439 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD
|
8440 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD_CONST
|
8441 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
8442 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
8443 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
8444 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8445 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
8446 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
8447 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
8448 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
8449 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
8450 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
8451 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
8452 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
8453 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
8454 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
8455 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
8456 | 5c55ff99 | Blue Swirl | |
8457 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVW
|
8458 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
8459 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
8460 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
8461 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
8462 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
8463 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
8464 | 5c55ff99 | Blue Swirl | |
8465 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8466 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVD
|
8467 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
8468 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8469 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
8470 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
8471 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
8472 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
8473 | 5c55ff99 | Blue Swirl | |
8474 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_MUL_HELPER
|
8475 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
8476 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8477 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
|
8478 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
|
8479 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
|
8480 | 5c55ff99 | Blue Swirl | #endif
|
8481 | 5c55ff99 | Blue Swirl | |
8482 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF
|
8483 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF_CONST
|
8484 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
8485 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
8486 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
8487 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8488 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
8489 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
8490 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
8491 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
8492 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
8493 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
8494 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
8495 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
8496 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
8497 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
8498 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
8499 | 5c55ff99 | Blue Swirl | |
8500 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL1
|
8501 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL2
|
8502 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
8503 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
8504 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
8505 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
8506 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
|
8507 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
|
8508 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
|
8509 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
|
8510 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
|
8511 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
|
8512 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
|
8513 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
|
8514 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8515 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
|
8516 | 5c55ff99 | Blue Swirl | #endif
|
8517 | 5c55ff99 | Blue Swirl | |
8518 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8519 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R2
|
8520 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R4
|
8521 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R2(name, opc1, opc2) \
|
8522 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8523 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8524 | 5c55ff99 | Blue Swirl | PPC_64B) |
8525 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R4(name, opc1, opc2) \
|
8526 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8527 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
8528 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8529 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8530 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8531 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
8532 | 5c55ff99 | Blue Swirl | PPC_64B) |
8533 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
8534 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
8535 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
8536 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
8537 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
8538 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
8539 | 5c55ff99 | Blue Swirl | #endif
|
8540 | 5c55ff99 | Blue Swirl | |
8541 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_ACB
|
8542 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_ACB
|
8543 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AB
|
8544 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AB
|
8545 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AC
|
8546 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AC
|
8547 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_B
|
8548 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_BS
|
8549 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
8550 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) |
8551 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
8552 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ |
8553 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) |
8554 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8555 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8556 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
8557 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8558 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8559 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8560 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8561 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
8562 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8563 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8564 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
8565 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) |
8566 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
8567 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) |
8568 | 5c55ff99 | Blue Swirl | |
8569 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), |
8570 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), |
8571 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), |
8572 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), |
8573 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), |
8574 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), |
8575 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), |
8576 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), |
8577 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), |
8578 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), |
8579 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), |
8580 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), |
8581 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
8582 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
8583 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
8584 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8585 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), |
8586 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
8587 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
8588 | 5c55ff99 | Blue Swirl | #endif
|
8589 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
8590 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), |
8591 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), |
8592 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), |
8593 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), |
8594 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), |
8595 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), |
8596 | 5c55ff99 | Blue Swirl | |
8597 | 5c55ff99 | Blue Swirl | #undef GEN_LD
|
8598 | 5c55ff99 | Blue Swirl | #undef GEN_LDU
|
8599 | 5c55ff99 | Blue Swirl | #undef GEN_LDUX
|
8600 | 5c55ff99 | Blue Swirl | #undef GEN_LDX
|
8601 | 5c55ff99 | Blue Swirl | #undef GEN_LDS
|
8602 | 5c55ff99 | Blue Swirl | #define GEN_LD(name, ldop, opc, type) \
|
8603 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8604 | 5c55ff99 | Blue Swirl | #define GEN_LDU(name, ldop, opc, type) \
|
8605 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8606 | 5c55ff99 | Blue Swirl | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
8607 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8608 | 5c55ff99 | Blue Swirl | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
8609 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8610 | 5c55ff99 | Blue Swirl | #define GEN_LDS(name, ldop, op, type) \
|
8611 | 5c55ff99 | Blue Swirl | GEN_LD(name, ldop, op | 0x20, type) \
|
8612 | 5c55ff99 | Blue Swirl | GEN_LDU(name, ldop, op | 0x21, type) \
|
8613 | 5c55ff99 | Blue Swirl | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
8614 | 5c55ff99 | Blue Swirl | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
8615 | 5c55ff99 | Blue Swirl | |
8616 | 5c55ff99 | Blue Swirl | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
|
8617 | 5c55ff99 | Blue Swirl | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
|
8618 | 5c55ff99 | Blue Swirl | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
|
8619 | 5c55ff99 | Blue Swirl | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
|
8620 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8621 | 5c55ff99 | Blue Swirl | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
8622 | 5c55ff99 | Blue Swirl | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
8623 | 5c55ff99 | Blue Swirl | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) |
8624 | 5c55ff99 | Blue Swirl | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) |
8625 | 5c55ff99 | Blue Swirl | #endif
|
8626 | 5c55ff99 | Blue Swirl | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
8627 | 5c55ff99 | Blue Swirl | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
8628 | 5c55ff99 | Blue Swirl | |
8629 | 5c55ff99 | Blue Swirl | #undef GEN_ST
|
8630 | 5c55ff99 | Blue Swirl | #undef GEN_STU
|
8631 | 5c55ff99 | Blue Swirl | #undef GEN_STUX
|
8632 | 5c55ff99 | Blue Swirl | #undef GEN_STX
|
8633 | 5c55ff99 | Blue Swirl | #undef GEN_STS
|
8634 | 5c55ff99 | Blue Swirl | #define GEN_ST(name, stop, opc, type) \
|
8635 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8636 | 5c55ff99 | Blue Swirl | #define GEN_STU(name, stop, opc, type) \
|
8637 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8638 | 5c55ff99 | Blue Swirl | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
8639 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8640 | 5c55ff99 | Blue Swirl | #define GEN_STX(name, stop, opc2, opc3, type) \
|
8641 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8642 | 5c55ff99 | Blue Swirl | #define GEN_STS(name, stop, op, type) \
|
8643 | 5c55ff99 | Blue Swirl | GEN_ST(name, stop, op | 0x20, type) \
|
8644 | 5c55ff99 | Blue Swirl | GEN_STU(name, stop, op | 0x21, type) \
|
8645 | 5c55ff99 | Blue Swirl | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
8646 | 5c55ff99 | Blue Swirl | GEN_STX(name, stop, 0x17, op | 0x00, type) |
8647 | 5c55ff99 | Blue Swirl | |
8648 | 5c55ff99 | Blue Swirl | GEN_STS(stb, st8, 0x06, PPC_INTEGER)
|
8649 | 5c55ff99 | Blue Swirl | GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
|
8650 | 5c55ff99 | Blue Swirl | GEN_STS(stw, st32, 0x04, PPC_INTEGER)
|
8651 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8652 | 5c55ff99 | Blue Swirl | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) |
8653 | 5c55ff99 | Blue Swirl | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) |
8654 | 5c55ff99 | Blue Swirl | #endif
|
8655 | 5c55ff99 | Blue Swirl | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
8656 | 5c55ff99 | Blue Swirl | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
8657 | 5c55ff99 | Blue Swirl | |
8658 | 5c55ff99 | Blue Swirl | #undef GEN_LDF
|
8659 | 5c55ff99 | Blue Swirl | #undef GEN_LDUF
|
8660 | 5c55ff99 | Blue Swirl | #undef GEN_LDUXF
|
8661 | 5c55ff99 | Blue Swirl | #undef GEN_LDXF
|
8662 | 5c55ff99 | Blue Swirl | #undef GEN_LDFS
|
8663 | 5c55ff99 | Blue Swirl | #define GEN_LDF(name, ldop, opc, type) \
|
8664 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8665 | 5c55ff99 | Blue Swirl | #define GEN_LDUF(name, ldop, opc, type) \
|
8666 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8667 | 5c55ff99 | Blue Swirl | #define GEN_LDUXF(name, ldop, opc, type) \
|
8668 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8669 | 5c55ff99 | Blue Swirl | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
8670 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8671 | 5c55ff99 | Blue Swirl | #define GEN_LDFS(name, ldop, op, type) \
|
8672 | 5c55ff99 | Blue Swirl | GEN_LDF(name, ldop, op | 0x20, type) \
|
8673 | 5c55ff99 | Blue Swirl | GEN_LDUF(name, ldop, op | 0x21, type) \
|
8674 | 5c55ff99 | Blue Swirl | GEN_LDUXF(name, ldop, op | 0x01, type) \
|
8675 | 5c55ff99 | Blue Swirl | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
8676 | 5c55ff99 | Blue Swirl | |
8677 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
8678 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
8679 | 5c55ff99 | Blue Swirl | |
8680 | 5c55ff99 | Blue Swirl | #undef GEN_STF
|
8681 | 5c55ff99 | Blue Swirl | #undef GEN_STUF
|
8682 | 5c55ff99 | Blue Swirl | #undef GEN_STUXF
|
8683 | 5c55ff99 | Blue Swirl | #undef GEN_STXF
|
8684 | 5c55ff99 | Blue Swirl | #undef GEN_STFS
|
8685 | 5c55ff99 | Blue Swirl | #define GEN_STF(name, stop, opc, type) \
|
8686 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8687 | 5c55ff99 | Blue Swirl | #define GEN_STUF(name, stop, opc, type) \
|
8688 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8689 | 5c55ff99 | Blue Swirl | #define GEN_STUXF(name, stop, opc, type) \
|
8690 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8691 | 5c55ff99 | Blue Swirl | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
8692 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8693 | 5c55ff99 | Blue Swirl | #define GEN_STFS(name, stop, op, type) \
|
8694 | 5c55ff99 | Blue Swirl | GEN_STF(name, stop, op | 0x20, type) \
|
8695 | 5c55ff99 | Blue Swirl | GEN_STUF(name, stop, op | 0x21, type) \
|
8696 | 5c55ff99 | Blue Swirl | GEN_STUXF(name, stop, op | 0x01, type) \
|
8697 | 5c55ff99 | Blue Swirl | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
8698 | 5c55ff99 | Blue Swirl | |
8699 | 5c55ff99 | Blue Swirl | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
|
8700 | 5c55ff99 | Blue Swirl | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
|
8701 | 5c55ff99 | Blue Swirl | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) |
8702 | 5c55ff99 | Blue Swirl | |
8703 | 5c55ff99 | Blue Swirl | #undef GEN_CRLOGIC
|
8704 | 5c55ff99 | Blue Swirl | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
8705 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
8706 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
|
8707 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
|
8708 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
|
8709 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
|
8710 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
|
8711 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
|
8712 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
|
8713 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
|
8714 | 5c55ff99 | Blue Swirl | |
8715 | 5c55ff99 | Blue Swirl | #undef GEN_MAC_HANDLER
|
8716 | 5c55ff99 | Blue Swirl | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
8717 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
8718 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
8719 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
8720 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
8721 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
8722 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
8723 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
8724 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
8725 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
8726 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
8727 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
8728 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
8729 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
8730 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
8731 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
8732 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
8733 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
8734 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
8735 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
8736 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
8737 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
8738 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
8739 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
8740 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
8741 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
8742 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
8743 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
8744 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
8745 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
8746 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
8747 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
8748 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
8749 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
8750 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
8751 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
8752 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
8753 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
8754 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
8755 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
8756 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
8757 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
8758 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
8759 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
8760 | 5c55ff99 | Blue Swirl | |
8761 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LDX
|
8762 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STX
|
8763 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LVE
|
8764 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STVE
|
8765 | 5c55ff99 | Blue Swirl | #define GEN_VR_LDX(name, opc2, opc3) \
|
8766 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8767 | 5c55ff99 | Blue Swirl | #define GEN_VR_STX(name, opc2, opc3) \
|
8768 | 5c55ff99 | Blue Swirl | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8769 | 5c55ff99 | Blue Swirl | #define GEN_VR_LVE(name, opc2, opc3) \
|
8770 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8771 | 5c55ff99 | Blue Swirl | #define GEN_VR_STVE(name, opc2, opc3) \
|
8772 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8773 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvx, 0x07, 0x03), |
8774 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvxl, 0x07, 0x0B), |
8775 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(bx, 0x07, 0x00), |
8776 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(hx, 0x07, 0x01), |
8777 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(wx, 0x07, 0x02), |
8778 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svx, 0x07, 0x07), |
8779 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svxl, 0x07, 0x0F), |
8780 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(bx, 0x07, 0x04), |
8781 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(hx, 0x07, 0x05), |
8782 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(wx, 0x07, 0x06), |
8783 | 5c55ff99 | Blue Swirl | |
8784 | 5c55ff99 | Blue Swirl | #undef GEN_VX_LOGICAL
|
8785 | 5c55ff99 | Blue Swirl | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
8786 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8787 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
8788 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), |
8789 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), |
8790 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), |
8791 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), |
8792 | 5c55ff99 | Blue Swirl | |
8793 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM
|
8794 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM(name, opc2, opc3) \
|
8795 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8796 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubm, 0, 0), |
8797 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhm, 0, 1), |
8798 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduwm, 0, 2), |
8799 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububm, 0, 16), |
8800 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhm, 0, 17), |
8801 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuwm, 0, 18), |
8802 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxub, 1, 0), |
8803 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuh, 1, 1), |
8804 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuw, 1, 2), |
8805 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsb, 1, 4), |
8806 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsh, 1, 5), |
8807 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsw, 1, 6), |
8808 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminub, 1, 8), |
8809 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuh, 1, 9), |
8810 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuw, 1, 10), |
8811 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsb, 1, 12), |
8812 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsh, 1, 13), |
8813 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsw, 1, 14), |
8814 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgub, 1, 16), |
8815 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguh, 1, 17), |
8816 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguw, 1, 18), |
8817 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsb, 1, 20), |
8818 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsh, 1, 21), |
8819 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsw, 1, 22), |
8820 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghb, 6, 0), |
8821 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghh, 6, 1), |
8822 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghw, 6, 2), |
8823 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglb, 6, 4), |
8824 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglh, 6, 5), |
8825 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglw, 6, 6), |
8826 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuloub, 4, 0), |
8827 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulouh, 4, 1), |
8828 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosb, 4, 4), |
8829 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosh, 4, 5), |
8830 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleub, 4, 8), |
8831 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleuh, 4, 9), |
8832 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesb, 4, 12), |
8833 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesh, 4, 13), |
8834 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslb, 2, 4), |
8835 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslh, 2, 5), |
8836 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslw, 2, 6), |
8837 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrb, 2, 8), |
8838 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrh, 2, 9), |
8839 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrw, 2, 10), |
8840 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrab, 2, 12), |
8841 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrah, 2, 13), |
8842 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsraw, 2, 14), |
8843 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslo, 6, 16), |
8844 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsro, 6, 17), |
8845 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddcuw, 0, 6), |
8846 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubcuw, 0, 22), |
8847 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubs, 0, 8), |
8848 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhs, 0, 9), |
8849 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduws, 0, 10), |
8850 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsbs, 0, 12), |
8851 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddshs, 0, 13), |
8852 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsws, 0, 14), |
8853 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububs, 0, 24), |
8854 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhs, 0, 25), |
8855 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuws, 0, 26), |
8856 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsbs, 0, 28), |
8857 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubshs, 0, 29), |
8858 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsws, 0, 30), |
8859 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlb, 2, 0), |
8860 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlh, 2, 1), |
8861 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlw, 2, 2), |
8862 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsl, 2, 7), |
8863 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsr, 2, 11), |
8864 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhum, 7, 0), |
8865 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwum, 7, 1), |
8866 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhus, 7, 2), |
8867 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwus, 7, 3), |
8868 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshus, 7, 4), |
8869 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswus, 7, 5), |
8870 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshss, 7, 6), |
8871 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswss, 7, 7), |
8872 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkpx, 7, 12), |
8873 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4ubs, 4, 24), |
8874 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4sbs, 4, 28), |
8875 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4shs, 4, 25), |
8876 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum2sws, 4, 26), |
8877 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsumsws, 4, 30), |
8878 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddfp, 5, 0), |
8879 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubfp, 5, 1), |
8880 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxfp, 5, 16), |
8881 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminfp, 5, 17), |
8882 | 5c55ff99 | Blue Swirl | |
8883 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM1
|
8884 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM
|
8885 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
8886 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), |
8887 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM(name, opc2, opc3) \
|
8888 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
8889 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
8890 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequb, 3, 0) |
8891 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequh, 3, 1) |
8892 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequw, 3, 2) |
8893 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsb, 3, 12) |
8894 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsh, 3, 13) |
8895 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsw, 3, 14) |
8896 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtub, 3, 8) |
8897 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuh, 3, 9) |
8898 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuw, 3, 10) |
8899 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpeqfp, 3, 3) |
8900 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgefp, 3, 7) |
8901 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtfp, 3, 11) |
8902 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpbfp, 3, 15) |
8903 | 5c55ff99 | Blue Swirl | |
8904 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_SIMM
|
8905 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
8906 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8907 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisb, 6, 12), |
8908 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltish, 6, 13), |
8909 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisw, 6, 14), |
8910 | 5c55ff99 | Blue Swirl | |
8911 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_NOA
|
8912 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
8913 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) |
8914 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsb, 7, 8), |
8915 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsh, 7, 9), |
8916 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsb, 7, 10), |
8917 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsh, 7, 11), |
8918 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
8919 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklpx, 7, 15), |
8920 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrefp, 5, 4), |
8921 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), |
8922 | 0bffbc6c | Aurelien Jarno | GEN_VXFORM_NOA(vexptefp, 5, 6), |
8923 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vlogefp, 5, 7), |
8924 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfim, 5, 8), |
8925 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfin, 5, 9), |
8926 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfip, 5, 10), |
8927 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfiz, 5, 11), |
8928 | 5c55ff99 | Blue Swirl | |
8929 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_UIMM
|
8930 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
8931 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8932 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltb, 6, 8), |
8933 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vsplth, 6, 9), |
8934 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltw, 6, 10), |
8935 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfux, 5, 12), |
8936 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfsx, 5, 13), |
8937 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctuxs, 5, 14), |
8938 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctsxs, 5, 15), |
8939 | 5c55ff99 | Blue Swirl | |
8940 | 5c55ff99 | Blue Swirl | #undef GEN_VAFORM_PAIRED
|
8941 | 5c55ff99 | Blue Swirl | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
8942 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) |
8943 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
|
8944 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
|
8945 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
|
8946 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
|
8947 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vsel, vperm, 21),
|
8948 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
|
8949 | 5c55ff99 | Blue Swirl | |
8950 | 5c55ff99 | Blue Swirl | #undef GEN_SPE
|
8951 | 5c55ff99 | Blue Swirl | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
8952 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) |
8953 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE), |
8954 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE), |
8955 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE), |
8956 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE), |
8957 | 5c55ff99 | Blue Swirl | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE), |
8958 | 5c55ff99 | Blue Swirl | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE), |
8959 | 5c55ff99 | Blue Swirl | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE), |
8960 | 5c55ff99 | Blue Swirl | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE), |
8961 | a0e13900 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE), |
8962 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE), |
8963 | 5c55ff99 | Blue Swirl | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE), |
8964 | 5c55ff99 | Blue Swirl | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE), |
8965 | 5c55ff99 | Blue Swirl | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE), |
8966 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE), |
8967 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE), |
8968 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE), |
8969 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE), |
8970 | 5c55ff99 | Blue Swirl | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE), |
8971 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE), |
8972 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE), |
8973 | 5c55ff99 | Blue Swirl | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE), |
8974 | 5c55ff99 | Blue Swirl | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE), |
8975 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE), |
8976 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE), |
8977 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE), |
8978 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE), |
8979 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE), |
8980 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE), |
8981 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE), |
8982 | 5c55ff99 | Blue Swirl | |
8983 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
8984 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
8985 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
8986 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
8987 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8988 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8989 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8990 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8991 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8992 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8993 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8994 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
8995 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8996 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
8997 | 5c55ff99 | Blue Swirl | |
8998 | 5c55ff99 | Blue Swirl | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
8999 | 5c55ff99 | Blue Swirl | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
9000 | 5c55ff99 | Blue Swirl | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
9001 | 5c55ff99 | Blue Swirl | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
9002 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9003 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9004 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9005 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9006 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9007 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9008 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9009 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9010 | 5c55ff99 | Blue Swirl | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9011 | 5c55ff99 | Blue Swirl | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9012 | 5c55ff99 | Blue Swirl | |
9013 | 5c55ff99 | Blue Swirl | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
9014 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9015 | 5c55ff99 | Blue Swirl | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
9016 | 5c55ff99 | Blue Swirl | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
9017 | 5c55ff99 | Blue Swirl | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
9018 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9019 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9020 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9021 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9022 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9023 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9024 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9025 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9026 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9027 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9028 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9029 | 5c55ff99 | Blue Swirl | |
9030 | 5c55ff99 | Blue Swirl | #undef GEN_SPEOP_LDST
|
9031 | 5c55ff99 | Blue Swirl | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
9032 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) |
9033 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldd, 0x00, 3), |
9034 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldw, 0x01, 3), |
9035 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldh, 0x02, 3), |
9036 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), |
9037 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), |
9038 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), |
9039 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhe, 0x08, 2), |
9040 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), |
9041 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), |
9042 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), |
9043 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), |
9044 | 5c55ff99 | Blue Swirl | |
9045 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdd, 0x10, 3), |
9046 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdw, 0x11, 3), |
9047 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdh, 0x12, 3), |
9048 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwhe, 0x18, 2), |
9049 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwho, 0x1A, 2), |
9050 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), |
9051 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), |
9052 | 5c55ff99 | Blue Swirl | }; |
9053 | 5c55ff99 | Blue Swirl | |
9054 | 3fc6c082 | bellard | #include "translate_init.c" |
9055 | 0411a972 | j_mayer | #include "helper_regs.h" |
9056 | 79aceca5 | bellard | |
9057 | 9a64fbe4 | bellard | /*****************************************************************************/
|
9058 | 3fc6c082 | bellard | /* Misc PowerPC helpers */
|
9059 | 9a78eead | Stefan Weil | void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
9060 | 36081602 | j_mayer | int flags)
|
9061 | 79aceca5 | bellard | { |
9062 | 3fc6c082 | bellard | #define RGPL 4 |
9063 | 3fc6c082 | bellard | #define RFPL 4 |
9064 | 3fc6c082 | bellard | |
9065 | 79aceca5 | bellard | int i;
|
9066 | 79aceca5 | bellard | |
9067 | 90e189ec | Blue Swirl | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9068 | 9a78eead | Stefan Weil | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
9069 | 9a78eead | Stefan Weil | env->nip, env->lr, env->ctr, env->xer); |
9070 | 90e189ec | Blue Swirl | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9071 | 90e189ec | Blue Swirl | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
|
9072 | 90e189ec | Blue Swirl | env->hflags, env->mmu_idx); |
9073 | d9bce9d9 | j_mayer | #if !defined(NO_TIMER_DUMP)
|
9074 | 9a78eead | Stefan Weil | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
9075 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9076 | 9a78eead | Stefan Weil | " DECR %08" PRIu32
|
9077 | 76a66253 | j_mayer | #endif
|
9078 | 76a66253 | j_mayer | "\n",
|
9079 | 077fc206 | j_mayer | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
9080 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9081 | 76a66253 | j_mayer | , cpu_ppc_load_decr(env) |
9082 | 76a66253 | j_mayer | #endif
|
9083 | 76a66253 | j_mayer | ); |
9084 | 077fc206 | j_mayer | #endif
|
9085 | 76a66253 | j_mayer | for (i = 0; i < 32; i++) { |
9086 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == 0) |
9087 | 3fc6c082 | bellard | cpu_fprintf(f, "GPR%02d", i);
|
9088 | b11ebf64 | Blue Swirl | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
|
9089 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == (RGPL - 1)) |
9090 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
9091 | 76a66253 | j_mayer | } |
9092 | 3fc6c082 | bellard | cpu_fprintf(f, "CR ");
|
9093 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) |
9094 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
9095 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
9096 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) { |
9097 | 76a66253 | j_mayer | char a = '-'; |
9098 | 76a66253 | j_mayer | if (env->crf[i] & 0x08) |
9099 | 76a66253 | j_mayer | a = 'L';
|
9100 | 76a66253 | j_mayer | else if (env->crf[i] & 0x04) |
9101 | 76a66253 | j_mayer | a = 'G';
|
9102 | 76a66253 | j_mayer | else if (env->crf[i] & 0x02) |
9103 | 76a66253 | j_mayer | a = 'E';
|
9104 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
9105 | 76a66253 | j_mayer | } |
9106 | 90e189ec | Blue Swirl | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9107 | 90e189ec | Blue Swirl | env->reserve_addr); |
9108 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
9109 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == 0) |
9110 | 3fc6c082 | bellard | cpu_fprintf(f, "FPR%02d", i);
|
9111 | 26a76461 | bellard | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
9112 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == (RFPL - 1)) |
9113 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
9114 | 79aceca5 | bellard | } |
9115 | 7889270a | aurel32 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
|
9116 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9117 | 90e189ec | Blue Swirl | cpu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " SDR1 " |
9118 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", env->spr[SPR_SRR0], env->spr[SPR_SRR1],
|
9119 | 90e189ec | Blue Swirl | env->sdr1); |
9120 | f2e63a42 | j_mayer | #endif
|
9121 | 79aceca5 | bellard | |
9122 | 3fc6c082 | bellard | #undef RGPL
|
9123 | 3fc6c082 | bellard | #undef RFPL
|
9124 | 79aceca5 | bellard | } |
9125 | 79aceca5 | bellard | |
9126 | 9a78eead | Stefan Weil | void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
|
9127 | 76a66253 | j_mayer | int flags)
|
9128 | 76a66253 | j_mayer | { |
9129 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
9130 | c227f099 | Anthony Liguori | opc_handler_t **t1, **t2, **t3, *handler; |
9131 | 76a66253 | j_mayer | int op1, op2, op3;
|
9132 | 76a66253 | j_mayer | |
9133 | 76a66253 | j_mayer | t1 = env->opcodes; |
9134 | 76a66253 | j_mayer | for (op1 = 0; op1 < 64; op1++) { |
9135 | 76a66253 | j_mayer | handler = t1[op1]; |
9136 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
9137 | 76a66253 | j_mayer | t2 = ind_table(handler); |
9138 | 76a66253 | j_mayer | for (op2 = 0; op2 < 32; op2++) { |
9139 | 76a66253 | j_mayer | handler = t2[op2]; |
9140 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
9141 | 76a66253 | j_mayer | t3 = ind_table(handler); |
9142 | 76a66253 | j_mayer | for (op3 = 0; op3 < 32; op3++) { |
9143 | 76a66253 | j_mayer | handler = t3[op3]; |
9144 | 76a66253 | j_mayer | if (handler->count == 0) |
9145 | 76a66253 | j_mayer | continue;
|
9146 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
9147 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
9148 | 76a66253 | j_mayer | op1, op2, op3, op1, (op3 << 5) | op2,
|
9149 | 76a66253 | j_mayer | handler->oname, |
9150 | 76a66253 | j_mayer | handler->count, handler->count); |
9151 | 76a66253 | j_mayer | } |
9152 | 76a66253 | j_mayer | } else {
|
9153 | 76a66253 | j_mayer | if (handler->count == 0) |
9154 | 76a66253 | j_mayer | continue;
|
9155 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
9156 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
9157 | 76a66253 | j_mayer | op1, op2, op1, op2, handler->oname, |
9158 | 76a66253 | j_mayer | handler->count, handler->count); |
9159 | 76a66253 | j_mayer | } |
9160 | 76a66253 | j_mayer | } |
9161 | 76a66253 | j_mayer | } else {
|
9162 | 76a66253 | j_mayer | if (handler->count == 0) |
9163 | 76a66253 | j_mayer | continue;
|
9164 | 0bfcd599 | Blue Swirl | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
|
9165 | 0bfcd599 | Blue Swirl | " %" PRId64 "\n", |
9166 | 76a66253 | j_mayer | op1, op1, handler->oname, |
9167 | 76a66253 | j_mayer | handler->count, handler->count); |
9168 | 76a66253 | j_mayer | } |
9169 | 76a66253 | j_mayer | } |
9170 | 76a66253 | j_mayer | #endif
|
9171 | 76a66253 | j_mayer | } |
9172 | 76a66253 | j_mayer | |
9173 | 9a64fbe4 | bellard | /*****************************************************************************/
|
9174 | 636aa200 | Blue Swirl | static inline void gen_intermediate_code_internal(CPUState *env, |
9175 | 636aa200 | Blue Swirl | TranslationBlock *tb, |
9176 | 636aa200 | Blue Swirl | int search_pc)
|
9177 | 79aceca5 | bellard | { |
9178 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
9179 | c227f099 | Anthony Liguori | opc_handler_t **table, *handler; |
9180 | 0fa85d43 | bellard | target_ulong pc_start; |
9181 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
9182 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
9183 | 79aceca5 | bellard | int j, lj = -1; |
9184 | 2e70f6ef | pbrook | int num_insns;
|
9185 | 2e70f6ef | pbrook | int max_insns;
|
9186 | 79aceca5 | bellard | |
9187 | 79aceca5 | bellard | pc_start = tb->pc; |
9188 | 79aceca5 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
9189 | 046d6672 | bellard | ctx.nip = pc_start; |
9190 | 79aceca5 | bellard | ctx.tb = tb; |
9191 | e1833e1f | j_mayer | ctx.exception = POWERPC_EXCP_NONE; |
9192 | 3fc6c082 | bellard | ctx.spr_cb = env->spr_cb; |
9193 | 76db3ba4 | aurel32 | ctx.mem_idx = env->mmu_idx; |
9194 | 76db3ba4 | aurel32 | ctx.access_type = -1;
|
9195 | 76db3ba4 | aurel32 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; |
9196 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
9197 | d9bce9d9 | j_mayer | ctx.sf_mode = msr_sf; |
9198 | 9a64fbe4 | bellard | #endif
|
9199 | 3cc62370 | bellard | ctx.fpu_enabled = msr_fp; |
9200 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
9201 | d26bfc9a | j_mayer | ctx.spe_enabled = msr_spe; |
9202 | d26bfc9a | j_mayer | else
|
9203 | d26bfc9a | j_mayer | ctx.spe_enabled = 0;
|
9204 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
9205 | a9d9eb8f | j_mayer | ctx.altivec_enabled = msr_vr; |
9206 | a9d9eb8f | j_mayer | else
|
9207 | a9d9eb8f | j_mayer | ctx.altivec_enabled = 0;
|
9208 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
9209 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
9210 | d26bfc9a | j_mayer | else
|
9211 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = 0;
|
9212 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
9213 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9214 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled))
|
9215 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
9216 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
9217 | 9a64fbe4 | bellard | /* Single step trace mode */
|
9218 | 9a64fbe4 | bellard | msr_se = 1;
|
9219 | 9a64fbe4 | bellard | #endif
|
9220 | 2e70f6ef | pbrook | num_insns = 0;
|
9221 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
9222 | 2e70f6ef | pbrook | if (max_insns == 0) |
9223 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
9224 | 2e70f6ef | pbrook | |
9225 | 2e70f6ef | pbrook | gen_icount_start(); |
9226 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
9227 | e1833e1f | j_mayer | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
9228 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
9229 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
9230 | a1d1bb31 | aliguori | if (bp->pc == ctx.nip) {
|
9231 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
9232 | ea4e754f | bellard | break;
|
9233 | ea4e754f | bellard | } |
9234 | ea4e754f | bellard | } |
9235 | ea4e754f | bellard | } |
9236 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
9237 | 79aceca5 | bellard | j = gen_opc_ptr - gen_opc_buf; |
9238 | 79aceca5 | bellard | if (lj < j) {
|
9239 | 79aceca5 | bellard | lj++; |
9240 | 79aceca5 | bellard | while (lj < j)
|
9241 | 79aceca5 | bellard | gen_opc_instr_start[lj++] = 0;
|
9242 | 79aceca5 | bellard | } |
9243 | af4b6c54 | aurel32 | gen_opc_pc[lj] = ctx.nip; |
9244 | af4b6c54 | aurel32 | gen_opc_instr_start[lj] = 1;
|
9245 | af4b6c54 | aurel32 | gen_opc_icount[lj] = num_insns; |
9246 | 79aceca5 | bellard | } |
9247 | d12d51d5 | aliguori | LOG_DISAS("----------------\n");
|
9248 | 90e189ec | Blue Swirl | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
9249 | d12d51d5 | aliguori | ctx.nip, ctx.mem_idx, (int)msr_ir);
|
9250 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9251 | 2e70f6ef | pbrook | gen_io_start(); |
9252 | 76db3ba4 | aurel32 | if (unlikely(ctx.le_mode)) {
|
9253 | 056401ea | j_mayer | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
9254 | 056401ea | j_mayer | } else {
|
9255 | 056401ea | j_mayer | ctx.opcode = ldl_code(ctx.nip); |
9256 | 111bfab3 | bellard | } |
9257 | d12d51d5 | aliguori | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
|
9258 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
9259 | 056401ea | j_mayer | opc3(ctx.opcode), little_endian ? "little" : "big"); |
9260 | 731c54f8 | Aurelien Jarno | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
9261 | 731c54f8 | Aurelien Jarno | tcg_gen_debug_insn_start(ctx.nip); |
9262 | 046d6672 | bellard | ctx.nip += 4;
|
9263 | 3fc6c082 | bellard | table = env->opcodes; |
9264 | 2e70f6ef | pbrook | num_insns++; |
9265 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
9266 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
9267 | 79aceca5 | bellard | table = ind_table(handler); |
9268 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
9269 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
9270 | 79aceca5 | bellard | table = ind_table(handler); |
9271 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
9272 | 79aceca5 | bellard | } |
9273 | 79aceca5 | bellard | } |
9274 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
9275 | 76a66253 | j_mayer | if (unlikely(handler->handler == &gen_invalid)) {
|
9276 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
9277 | 93fcfe39 | aliguori | qemu_log("invalid/unsupported opcode: "
|
9278 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9279 | 90e189ec | Blue Swirl | opc1(ctx.opcode), opc2(ctx.opcode), |
9280 | 90e189ec | Blue Swirl | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
9281 | 4b3686fa | bellard | } |
9282 | 76a66253 | j_mayer | } else {
|
9283 | 76a66253 | j_mayer | if (unlikely((ctx.opcode & handler->inval) != 0)) { |
9284 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
9285 | 93fcfe39 | aliguori | qemu_log("invalid bits: %08x for opcode: "
|
9286 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
9287 | 90e189ec | Blue Swirl | ctx.opcode & handler->inval, opc1(ctx.opcode), |
9288 | 90e189ec | Blue Swirl | opc2(ctx.opcode), opc3(ctx.opcode), |
9289 | 90e189ec | Blue Swirl | ctx.opcode, ctx.nip - 4);
|
9290 | 76a66253 | j_mayer | } |
9291 | e06fcd75 | aurel32 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
9292 | 4b3686fa | bellard | break;
|
9293 | 79aceca5 | bellard | } |
9294 | 79aceca5 | bellard | } |
9295 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
9296 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
9297 | 76a66253 | j_mayer | handler->count++; |
9298 | 76a66253 | j_mayer | #endif
|
9299 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
9300 | 8cbcb4fa | aurel32 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
9301 | 8cbcb4fa | aurel32 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
9302 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_SYSCALL && |
9303 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_TRAP && |
9304 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
9305 | e06fcd75 | aurel32 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
9306 | d26bfc9a | j_mayer | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
9307 | 2e70f6ef | pbrook | (env->singlestep_enabled) || |
9308 | 1b530a6d | aurel32 | singlestep || |
9309 | 2e70f6ef | pbrook | num_insns >= max_insns)) { |
9310 | d26bfc9a | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
9311 | d26bfc9a | j_mayer | * generation
|
9312 | d26bfc9a | j_mayer | */
|
9313 | 8dd4983c | bellard | break;
|
9314 | 76a66253 | j_mayer | } |
9315 | 3fc6c082 | bellard | } |
9316 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
9317 | 2e70f6ef | pbrook | gen_io_end(); |
9318 | e1833e1f | j_mayer | if (ctx.exception == POWERPC_EXCP_NONE) {
|
9319 | c1942362 | bellard | gen_goto_tb(&ctx, 0, ctx.nip);
|
9320 | e1833e1f | j_mayer | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
9321 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled)) {
|
9322 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
9323 | 8cbcb4fa | aurel32 | } |
9324 | 76a66253 | j_mayer | /* Generate the return instruction */
|
9325 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
9326 | 9a64fbe4 | bellard | } |
9327 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
9328 | 79aceca5 | bellard | *gen_opc_ptr = INDEX_op_end; |
9329 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
9330 | 9a64fbe4 | bellard | j = gen_opc_ptr - gen_opc_buf; |
9331 | 9a64fbe4 | bellard | lj++; |
9332 | 9a64fbe4 | bellard | while (lj <= j)
|
9333 | 9a64fbe4 | bellard | gen_opc_instr_start[lj++] = 0;
|
9334 | 9a64fbe4 | bellard | } else {
|
9335 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
9336 | 2e70f6ef | pbrook | tb->icount = num_insns; |
9337 | 9a64fbe4 | bellard | } |
9338 | d9bce9d9 | j_mayer | #if defined(DEBUG_DISAS)
|
9339 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
9340 | 76a66253 | j_mayer | int flags;
|
9341 | 237c0af0 | j_mayer | flags = env->bfd_mach; |
9342 | 76db3ba4 | aurel32 | flags |= ctx.le_mode << 16;
|
9343 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
9344 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.nip - pc_start, flags); |
9345 | 93fcfe39 | aliguori | qemu_log("\n");
|
9346 | 9fddaa0c | bellard | } |
9347 | 79aceca5 | bellard | #endif
|
9348 | 79aceca5 | bellard | } |
9349 | 79aceca5 | bellard | |
9350 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
9351 | 79aceca5 | bellard | { |
9352 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
9353 | 79aceca5 | bellard | } |
9354 | 79aceca5 | bellard | |
9355 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
9356 | 79aceca5 | bellard | { |
9357 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
9358 | 79aceca5 | bellard | } |
9359 | d2856f1a | aurel32 | |
9360 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
9361 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
9362 | d2856f1a | aurel32 | { |
9363 | d2856f1a | aurel32 | env->nip = gen_opc_pc[pc_pos]; |
9364 | d2856f1a | aurel32 | } |