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1
/*
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 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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25
#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "tcg-op.h"
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#include "qemu-common.h"
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#include "host-utils.h"
31

    
32
#include "helper.h"
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#define GEN_HELPER 1
34
#include "helper.h"
35

    
36
#define CPU_SINGLE_STEP 0x1
37
#define CPU_BRANCH_STEP 0x2
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#define GDBSTUB_SINGLE_STEP 0x4
39

    
40
/* Include definitions for instructions classes and implementations flags */
41
//#define PPC_DEBUG_DISAS
42
//#define DO_PPC_STATISTICS
43

    
44
#ifdef PPC_DEBUG_DISAS
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#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46
#else
47
#  define LOG_DISAS(...) do { } while (0)
48
#endif
49
/*****************************************************************************/
50
/* Code translation helpers                                                  */
51

    
52
/* global register indexes */
53
static TCGv_ptr cpu_env;
54
static char cpu_reg_names[10*3 + 22*4 /* GPR */
55
#if !defined(TARGET_PPC64)
56
    + 10*4 + 22*5 /* SPE GPRh */
57
#endif
58
    + 10*4 + 22*5 /* FPR */
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    + 2*(10*6 + 22*7) /* AVRh, AVRl */
60
    + 8*5 /* CRF */];
61
static TCGv cpu_gpr[32];
62
#if !defined(TARGET_PPC64)
63
static TCGv cpu_gprh[32];
64
#endif
65
static TCGv_i64 cpu_fpr[32];
66
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67
static TCGv_i32 cpu_crf[8];
68
static TCGv cpu_nip;
69
static TCGv cpu_msr;
70
static TCGv cpu_ctr;
71
static TCGv cpu_lr;
72
static TCGv cpu_xer;
73
static TCGv cpu_reserve;
74
static TCGv_i32 cpu_fpscr;
75
static TCGv_i32 cpu_access_type;
76

    
77
#include "gen-icount.h"
78

    
79
void ppc_translate_init(void)
80
{
81
    int i;
82
    char* p;
83
    size_t cpu_reg_names_size;
84
    static int done_init = 0;
85

    
86
    if (done_init)
87
        return;
88

    
89
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90

    
91
    p = cpu_reg_names;
92
    cpu_reg_names_size = sizeof(cpu_reg_names);
93

    
94
    for (i = 0; i < 8; i++) {
95
        snprintf(p, cpu_reg_names_size, "crf%d", i);
96
        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97
                                            offsetof(CPUState, crf[i]), p);
98
        p += 5;
99
        cpu_reg_names_size -= 5;
100
    }
101

    
102
    for (i = 0; i < 32; i++) {
103
        snprintf(p, cpu_reg_names_size, "r%d", i);
104
        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
105
                                        offsetof(CPUState, gpr[i]), p);
106
        p += (i < 10) ? 3 : 4;
107
        cpu_reg_names_size -= (i < 10) ? 3 : 4;
108
#if !defined(TARGET_PPC64)
109
        snprintf(p, cpu_reg_names_size, "r%dH", i);
110
        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
111
                                             offsetof(CPUState, gprh[i]), p);
112
        p += (i < 10) ? 4 : 5;
113
        cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
#endif
115

    
116
        snprintf(p, cpu_reg_names_size, "fp%d", i);
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        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118
                                            offsetof(CPUState, fpr[i]), p);
119
        p += (i < 10) ? 4 : 5;
120
        cpu_reg_names_size -= (i < 10) ? 4 : 5;
121

    
122
        snprintf(p, cpu_reg_names_size, "avr%dH", i);
123
#ifdef HOST_WORDS_BIGENDIAN
124
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125
                                             offsetof(CPUState, avr[i].u64[0]), p);
126
#else
127
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128
                                             offsetof(CPUState, avr[i].u64[1]), p);
129
#endif
130
        p += (i < 10) ? 6 : 7;
131
        cpu_reg_names_size -= (i < 10) ? 6 : 7;
132

    
133
        snprintf(p, cpu_reg_names_size, "avr%dL", i);
134
#ifdef HOST_WORDS_BIGENDIAN
135
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136
                                             offsetof(CPUState, avr[i].u64[1]), p);
137
#else
138
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139
                                             offsetof(CPUState, avr[i].u64[0]), p);
140
#endif
141
        p += (i < 10) ? 6 : 7;
142
        cpu_reg_names_size -= (i < 10) ? 6 : 7;
143
    }
144

    
145
    cpu_nip = tcg_global_mem_new(TCG_AREG0,
146
                                 offsetof(CPUState, nip), "nip");
147

    
148
    cpu_msr = tcg_global_mem_new(TCG_AREG0,
149
                                 offsetof(CPUState, msr), "msr");
150

    
151
    cpu_ctr = tcg_global_mem_new(TCG_AREG0,
152
                                 offsetof(CPUState, ctr), "ctr");
153

    
154
    cpu_lr = tcg_global_mem_new(TCG_AREG0,
155
                                offsetof(CPUState, lr), "lr");
156

    
157
    cpu_xer = tcg_global_mem_new(TCG_AREG0,
158
                                 offsetof(CPUState, xer), "xer");
159

    
160
    cpu_reserve = tcg_global_mem_new(TCG_AREG0,
161
                                     offsetof(CPUState, reserve_addr),
162
                                     "reserve_addr");
163

    
164
    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165
                                       offsetof(CPUState, fpscr), "fpscr");
166

    
167
    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168
                                             offsetof(CPUState, access_type), "access_type");
169

    
170
    /* register helpers */
171
#define GEN_HELPER 2
172
#include "helper.h"
173

    
174
    done_init = 1;
175
}
176

    
177
/* internal defines */
178
typedef struct DisasContext {
179
    struct TranslationBlock *tb;
180
    target_ulong nip;
181
    uint32_t opcode;
182
    uint32_t exception;
183
    /* Routine used to access memory */
184
    int mem_idx;
185
    int access_type;
186
    /* Translation flags */
187
    int le_mode;
188
#if defined(TARGET_PPC64)
189
    int sf_mode;
190
#endif
191
    int fpu_enabled;
192
    int altivec_enabled;
193
    int spe_enabled;
194
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
195
    int singlestep_enabled;
196
} DisasContext;
197

    
198
struct opc_handler_t {
199
    /* invalid bits */
200
    uint32_t inval;
201
    /* instruction type */
202
    uint64_t type;
203
    /* handler */
204
    void (*handler)(DisasContext *ctx);
205
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
206
    const char *oname;
207
#endif
208
#if defined(DO_PPC_STATISTICS)
209
    uint64_t count;
210
#endif
211
};
212

    
213
static inline void gen_reset_fpstatus(void)
214
{
215
#ifdef CONFIG_SOFTFLOAT
216
    gen_helper_reset_fpstatus();
217
#endif
218
}
219

    
220
static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
221
{
222
    TCGv_i32 t0 = tcg_temp_new_i32();
223

    
224
    if (set_fprf != 0) {
225
        /* This case might be optimized later */
226
        tcg_gen_movi_i32(t0, 1);
227
        gen_helper_compute_fprf(t0, arg, t0);
228
        if (unlikely(set_rc)) {
229
            tcg_gen_mov_i32(cpu_crf[1], t0);
230
        }
231
        gen_helper_float_check_status();
232
    } else if (unlikely(set_rc)) {
233
        /* We always need to compute fpcc */
234
        tcg_gen_movi_i32(t0, 0);
235
        gen_helper_compute_fprf(t0, arg, t0);
236
        tcg_gen_mov_i32(cpu_crf[1], t0);
237
    }
238

    
239
    tcg_temp_free_i32(t0);
240
}
241

    
242
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
243
{
244
    if (ctx->access_type != access_type) {
245
        tcg_gen_movi_i32(cpu_access_type, access_type);
246
        ctx->access_type = access_type;
247
    }
248
}
249

    
250
static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
251
{
252
#if defined(TARGET_PPC64)
253
    if (ctx->sf_mode)
254
        tcg_gen_movi_tl(cpu_nip, nip);
255
    else
256
#endif
257
        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
258
}
259

    
260
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
261
{
262
    TCGv_i32 t0, t1;
263
    if (ctx->exception == POWERPC_EXCP_NONE) {
264
        gen_update_nip(ctx, ctx->nip);
265
    }
266
    t0 = tcg_const_i32(excp);
267
    t1 = tcg_const_i32(error);
268
    gen_helper_raise_exception_err(t0, t1);
269
    tcg_temp_free_i32(t0);
270
    tcg_temp_free_i32(t1);
271
    ctx->exception = (excp);
272
}
273

    
274
static inline void gen_exception(DisasContext *ctx, uint32_t excp)
275
{
276
    TCGv_i32 t0;
277
    if (ctx->exception == POWERPC_EXCP_NONE) {
278
        gen_update_nip(ctx, ctx->nip);
279
    }
280
    t0 = tcg_const_i32(excp);
281
    gen_helper_raise_exception(t0);
282
    tcg_temp_free_i32(t0);
283
    ctx->exception = (excp);
284
}
285

    
286
static inline void gen_debug_exception(DisasContext *ctx)
287
{
288
    TCGv_i32 t0;
289

    
290
    if (ctx->exception != POWERPC_EXCP_BRANCH)
291
        gen_update_nip(ctx, ctx->nip);
292
    t0 = tcg_const_i32(EXCP_DEBUG);
293
    gen_helper_raise_exception(t0);
294
    tcg_temp_free_i32(t0);
295
}
296

    
297
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
298
{
299
    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
300
}
301

    
302
/* Stop translation */
303
static inline void gen_stop_exception(DisasContext *ctx)
304
{
305
    gen_update_nip(ctx, ctx->nip);
306
    ctx->exception = POWERPC_EXCP_STOP;
307
}
308

    
309
/* No need to update nip here, as execution flow will change */
310
static inline void gen_sync_exception(DisasContext *ctx)
311
{
312
    ctx->exception = POWERPC_EXCP_SYNC;
313
}
314

    
315
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
316
GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
317

    
318
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
319
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
320

    
321
typedef struct opcode_t {
322
    unsigned char opc1, opc2, opc3;
323
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
324
    unsigned char pad[5];
325
#else
326
    unsigned char pad[1];
327
#endif
328
    opc_handler_t handler;
329
    const char *oname;
330
} opcode_t;
331

    
332
/*****************************************************************************/
333
/***                           Instruction decoding                        ***/
334
#define EXTRACT_HELPER(name, shift, nb)                                       \
335
static inline uint32_t name(uint32_t opcode)                                  \
336
{                                                                             \
337
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
338
}
339

    
340
#define EXTRACT_SHELPER(name, shift, nb)                                      \
341
static inline int32_t name(uint32_t opcode)                                   \
342
{                                                                             \
343
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
344
}
345

    
346
/* Opcode part 1 */
347
EXTRACT_HELPER(opc1, 26, 6);
348
/* Opcode part 2 */
349
EXTRACT_HELPER(opc2, 1, 5);
350
/* Opcode part 3 */
351
EXTRACT_HELPER(opc3, 6, 5);
352
/* Update Cr0 flags */
353
EXTRACT_HELPER(Rc, 0, 1);
354
/* Destination */
355
EXTRACT_HELPER(rD, 21, 5);
356
/* Source */
357
EXTRACT_HELPER(rS, 21, 5);
358
/* First operand */
359
EXTRACT_HELPER(rA, 16, 5);
360
/* Second operand */
361
EXTRACT_HELPER(rB, 11, 5);
362
/* Third operand */
363
EXTRACT_HELPER(rC, 6, 5);
364
/***                               Get CRn                                 ***/
365
EXTRACT_HELPER(crfD, 23, 3);
366
EXTRACT_HELPER(crfS, 18, 3);
367
EXTRACT_HELPER(crbD, 21, 5);
368
EXTRACT_HELPER(crbA, 16, 5);
369
EXTRACT_HELPER(crbB, 11, 5);
370
/* SPR / TBL */
371
EXTRACT_HELPER(_SPR, 11, 10);
372
static inline uint32_t SPR(uint32_t opcode)
373
{
374
    uint32_t sprn = _SPR(opcode);
375

    
376
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
377
}
378
/***                              Get constants                            ***/
379
EXTRACT_HELPER(IMM, 12, 8);
380
/* 16 bits signed immediate value */
381
EXTRACT_SHELPER(SIMM, 0, 16);
382
/* 16 bits unsigned immediate value */
383
EXTRACT_HELPER(UIMM, 0, 16);
384
/* 5 bits signed immediate value */
385
EXTRACT_HELPER(SIMM5, 16, 5);
386
/* 5 bits signed immediate value */
387
EXTRACT_HELPER(UIMM5, 16, 5);
388
/* Bit count */
389
EXTRACT_HELPER(NB, 11, 5);
390
/* Shift count */
391
EXTRACT_HELPER(SH, 11, 5);
392
/* Vector shift count */
393
EXTRACT_HELPER(VSH, 6, 4);
394
/* Mask start */
395
EXTRACT_HELPER(MB, 6, 5);
396
/* Mask end */
397
EXTRACT_HELPER(ME, 1, 5);
398
/* Trap operand */
399
EXTRACT_HELPER(TO, 21, 5);
400

    
401
EXTRACT_HELPER(CRM, 12, 8);
402
EXTRACT_HELPER(FM, 17, 8);
403
EXTRACT_HELPER(SR, 16, 4);
404
EXTRACT_HELPER(FPIMM, 12, 4);
405

    
406
/***                            Jump target decoding                       ***/
407
/* Displacement */
408
EXTRACT_SHELPER(d, 0, 16);
409
/* Immediate address */
410
static inline target_ulong LI(uint32_t opcode)
411
{
412
    return (opcode >> 0) & 0x03FFFFFC;
413
}
414

    
415
static inline uint32_t BD(uint32_t opcode)
416
{
417
    return (opcode >> 0) & 0xFFFC;
418
}
419

    
420
EXTRACT_HELPER(BO, 21, 5);
421
EXTRACT_HELPER(BI, 16, 5);
422
/* Absolute/relative address */
423
EXTRACT_HELPER(AA, 1, 1);
424
/* Link */
425
EXTRACT_HELPER(LK, 0, 1);
426

    
427
/* Create a mask between <start> and <end> bits */
428
static inline target_ulong MASK(uint32_t start, uint32_t end)
429
{
430
    target_ulong ret;
431

    
432
#if defined(TARGET_PPC64)
433
    if (likely(start == 0)) {
434
        ret = UINT64_MAX << (63 - end);
435
    } else if (likely(end == 63)) {
436
        ret = UINT64_MAX >> start;
437
    }
438
#else
439
    if (likely(start == 0)) {
440
        ret = UINT32_MAX << (31  - end);
441
    } else if (likely(end == 31)) {
442
        ret = UINT32_MAX >> start;
443
    }
444
#endif
445
    else {
446
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
447
            (((target_ulong)(-1ULL) >> (end)) >> 1);
448
        if (unlikely(start > end))
449
            return ~ret;
450
    }
451

    
452
    return ret;
453
}
454

    
455
/*****************************************************************************/
456
/* PowerPC instructions table                                                */
457

    
458
#if defined(DO_PPC_STATISTICS)
459
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
460
{                                                                             \
461
    .opc1 = op1,                                                              \
462
    .opc2 = op2,                                                              \
463
    .opc3 = op3,                                                              \
464
    .pad  = { 0, },                                                           \
465
    .handler = {                                                              \
466
        .inval   = invl,                                                      \
467
        .type = _typ,                                                         \
468
        .handler = &gen_##name,                                               \
469
        .oname = stringify(name),                                             \
470
    },                                                                        \
471
    .oname = stringify(name),                                                 \
472
}
473
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
474
{                                                                             \
475
    .opc1 = op1,                                                              \
476
    .opc2 = op2,                                                              \
477
    .opc3 = op3,                                                              \
478
    .pad  = { 0, },                                                           \
479
    .handler = {                                                              \
480
        .inval   = invl,                                                      \
481
        .type = _typ,                                                         \
482
        .handler = &gen_##name,                                               \
483
        .oname = onam,                                                        \
484
    },                                                                        \
485
    .oname = onam,                                                            \
486
}
487
#else
488
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
489
{                                                                             \
490
    .opc1 = op1,                                                              \
491
    .opc2 = op2,                                                              \
492
    .opc3 = op3,                                                              \
493
    .pad  = { 0, },                                                           \
494
    .handler = {                                                              \
495
        .inval   = invl,                                                      \
496
        .type = _typ,                                                         \
497
        .handler = &gen_##name,                                               \
498
    },                                                                        \
499
    .oname = stringify(name),                                                 \
500
}
501
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
502
{                                                                             \
503
    .opc1 = op1,                                                              \
504
    .opc2 = op2,                                                              \
505
    .opc3 = op3,                                                              \
506
    .pad  = { 0, },                                                           \
507
    .handler = {                                                              \
508
        .inval   = invl,                                                      \
509
        .type = _typ,                                                         \
510
        .handler = &gen_##name,                                               \
511
    },                                                                        \
512
    .oname = onam,                                                            \
513
}
514
#endif
515

    
516
/* SPR load/store helpers */
517
static inline void gen_load_spr(TCGv t, int reg)
518
{
519
    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
520
}
521

    
522
static inline void gen_store_spr(int reg, TCGv t)
523
{
524
    tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
525
}
526

    
527
/* Invalid instruction */
528
static void gen_invalid(DisasContext *ctx)
529
{
530
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
531
}
532

    
533
static opc_handler_t invalid_handler = {
534
    .inval   = 0xFFFFFFFF,
535
    .type    = PPC_NONE,
536
    .handler = gen_invalid,
537
};
538

    
539
/***                           Integer comparison                          ***/
540

    
541
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
542
{
543
    int l1, l2, l3;
544

    
545
    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
546
    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
547
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
548

    
549
    l1 = gen_new_label();
550
    l2 = gen_new_label();
551
    l3 = gen_new_label();
552
    if (s) {
553
        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
554
        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
555
    } else {
556
        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
557
        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
558
    }
559
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
560
    tcg_gen_br(l3);
561
    gen_set_label(l1);
562
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
563
    tcg_gen_br(l3);
564
    gen_set_label(l2);
565
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
566
    gen_set_label(l3);
567
}
568

    
569
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
570
{
571
    TCGv t0 = tcg_const_local_tl(arg1);
572
    gen_op_cmp(arg0, t0, s, crf);
573
    tcg_temp_free(t0);
574
}
575

    
576
#if defined(TARGET_PPC64)
577
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
578
{
579
    TCGv t0, t1;
580
    t0 = tcg_temp_local_new();
581
    t1 = tcg_temp_local_new();
582
    if (s) {
583
        tcg_gen_ext32s_tl(t0, arg0);
584
        tcg_gen_ext32s_tl(t1, arg1);
585
    } else {
586
        tcg_gen_ext32u_tl(t0, arg0);
587
        tcg_gen_ext32u_tl(t1, arg1);
588
    }
589
    gen_op_cmp(t0, t1, s, crf);
590
    tcg_temp_free(t1);
591
    tcg_temp_free(t0);
592
}
593

    
594
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
595
{
596
    TCGv t0 = tcg_const_local_tl(arg1);
597
    gen_op_cmp32(arg0, t0, s, crf);
598
    tcg_temp_free(t0);
599
}
600
#endif
601

    
602
static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
603
{
604
#if defined(TARGET_PPC64)
605
    if (!(ctx->sf_mode))
606
        gen_op_cmpi32(reg, 0, 1, 0);
607
    else
608
#endif
609
        gen_op_cmpi(reg, 0, 1, 0);
610
}
611

    
612
/* cmp */
613
static void gen_cmp(DisasContext *ctx)
614
{
615
#if defined(TARGET_PPC64)
616
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
617
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
618
                     1, crfD(ctx->opcode));
619
    else
620
#endif
621
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
622
                   1, crfD(ctx->opcode));
623
}
624

    
625
/* cmpi */
626
static void gen_cmpi(DisasContext *ctx)
627
{
628
#if defined(TARGET_PPC64)
629
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
630
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
631
                      1, crfD(ctx->opcode));
632
    else
633
#endif
634
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
635
                    1, crfD(ctx->opcode));
636
}
637

    
638
/* cmpl */
639
static void gen_cmpl(DisasContext *ctx)
640
{
641
#if defined(TARGET_PPC64)
642
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
643
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
644
                     0, crfD(ctx->opcode));
645
    else
646
#endif
647
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
648
                   0, crfD(ctx->opcode));
649
}
650

    
651
/* cmpli */
652
static void gen_cmpli(DisasContext *ctx)
653
{
654
#if defined(TARGET_PPC64)
655
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
656
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
657
                      0, crfD(ctx->opcode));
658
    else
659
#endif
660
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
661
                    0, crfD(ctx->opcode));
662
}
663

    
664
/* isel (PowerPC 2.03 specification) */
665
static void gen_isel(DisasContext *ctx)
666
{
667
    int l1, l2;
668
    uint32_t bi = rC(ctx->opcode);
669
    uint32_t mask;
670
    TCGv_i32 t0;
671

    
672
    l1 = gen_new_label();
673
    l2 = gen_new_label();
674

    
675
    mask = 1 << (3 - (bi & 0x03));
676
    t0 = tcg_temp_new_i32();
677
    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
678
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
679
    if (rA(ctx->opcode) == 0)
680
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
681
    else
682
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
683
    tcg_gen_br(l2);
684
    gen_set_label(l1);
685
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
686
    gen_set_label(l2);
687
    tcg_temp_free_i32(t0);
688
}
689

    
690
/***                           Integer arithmetic                          ***/
691

    
692
static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
693
                                           TCGv arg1, TCGv arg2, int sub)
694
{
695
    int l1;
696
    TCGv t0;
697

    
698
    l1 = gen_new_label();
699
    /* Start with XER OV disabled, the most likely case */
700
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
701
    t0 = tcg_temp_local_new();
702
    tcg_gen_xor_tl(t0, arg0, arg1);
703
#if defined(TARGET_PPC64)
704
    if (!ctx->sf_mode)
705
        tcg_gen_ext32s_tl(t0, t0);
706
#endif
707
    if (sub)
708
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
709
    else
710
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
711
    tcg_gen_xor_tl(t0, arg1, arg2);
712
#if defined(TARGET_PPC64)
713
    if (!ctx->sf_mode)
714
        tcg_gen_ext32s_tl(t0, t0);
715
#endif
716
    if (sub)
717
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
718
    else
719
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
720
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
721
    gen_set_label(l1);
722
    tcg_temp_free(t0);
723
}
724

    
725
static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
726
                                           TCGv arg2, int sub)
727
{
728
    int l1 = gen_new_label();
729

    
730
#if defined(TARGET_PPC64)
731
    if (!(ctx->sf_mode)) {
732
        TCGv t0, t1;
733
        t0 = tcg_temp_new();
734
        t1 = tcg_temp_new();
735

    
736
        tcg_gen_ext32u_tl(t0, arg1);
737
        tcg_gen_ext32u_tl(t1, arg2);
738
        if (sub) {
739
            tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
740
        } else {
741
            tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
742
        }
743
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
744
        gen_set_label(l1);
745
        tcg_temp_free(t0);
746
        tcg_temp_free(t1);
747
    } else
748
#endif
749
    {
750
        if (sub) {
751
            tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
752
        } else {
753
            tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
754
        }
755
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
756
        gen_set_label(l1);
757
    }
758
}
759

    
760
/* Common add function */
761
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
762
                                    TCGv arg2, int add_ca, int compute_ca,
763
                                    int compute_ov)
764
{
765
    TCGv t0, t1;
766

    
767
    if ((!compute_ca && !compute_ov) ||
768
        (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {
769
        t0 = ret;
770
    } else {
771
        t0 = tcg_temp_local_new();
772
    }
773

    
774
    if (add_ca) {
775
        t1 = tcg_temp_local_new();
776
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
777
        tcg_gen_shri_tl(t1, t1, XER_CA);
778
    } else {
779
        TCGV_UNUSED(t1);
780
    }
781

    
782
    if (compute_ca && compute_ov) {
783
        /* Start with XER CA and OV disabled, the most likely case */
784
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
785
    } else if (compute_ca) {
786
        /* Start with XER CA disabled, the most likely case */
787
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
788
    } else if (compute_ov) {
789
        /* Start with XER OV disabled, the most likely case */
790
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
791
    }
792

    
793
    tcg_gen_add_tl(t0, arg1, arg2);
794

    
795
    if (compute_ca) {
796
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
797
    }
798
    if (add_ca) {
799
        tcg_gen_add_tl(t0, t0, t1);
800
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
801
        tcg_temp_free(t1);
802
    }
803
    if (compute_ov) {
804
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
805
    }
806

    
807
    if (unlikely(Rc(ctx->opcode) != 0))
808
        gen_set_Rc0(ctx, t0);
809

    
810
    if (!TCGV_EQUAL(t0, ret)) {
811
        tcg_gen_mov_tl(ret, t0);
812
        tcg_temp_free(t0);
813
    }
814
}
815
/* Add functions with two operands */
816
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
817
static void glue(gen_, name)(DisasContext *ctx)                                       \
818
{                                                                             \
819
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
820
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
821
                     add_ca, compute_ca, compute_ov);                         \
822
}
823
/* Add functions with one operand and one immediate */
824
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
825
                                add_ca, compute_ca, compute_ov)               \
826
static void glue(gen_, name)(DisasContext *ctx)                                       \
827
{                                                                             \
828
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
829
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
830
                     cpu_gpr[rA(ctx->opcode)], t0,                            \
831
                     add_ca, compute_ca, compute_ov);                         \
832
    tcg_temp_free(t0);                                                        \
833
}
834

    
835
/* add  add.  addo  addo. */
836
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
837
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
838
/* addc  addc.  addco  addco. */
839
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
840
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
841
/* adde  adde.  addeo  addeo. */
842
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
843
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
844
/* addme  addme.  addmeo  addmeo.  */
845
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
846
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
847
/* addze  addze.  addzeo  addzeo.*/
848
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
849
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
850
/* addi */
851
static void gen_addi(DisasContext *ctx)
852
{
853
    target_long simm = SIMM(ctx->opcode);
854

    
855
    if (rA(ctx->opcode) == 0) {
856
        /* li case */
857
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
858
    } else {
859
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
860
    }
861
}
862
/* addic  addic.*/
863
static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
864
                                int compute_Rc0)
865
{
866
    target_long simm = SIMM(ctx->opcode);
867

    
868
    /* Start with XER CA and OV disabled, the most likely case */
869
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
870

    
871
    if (likely(simm != 0)) {
872
        TCGv t0 = tcg_temp_local_new();
873
        tcg_gen_addi_tl(t0, arg1, simm);
874
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
875
        tcg_gen_mov_tl(ret, t0);
876
        tcg_temp_free(t0);
877
    } else {
878
        tcg_gen_mov_tl(ret, arg1);
879
    }
880
    if (compute_Rc0) {
881
        gen_set_Rc0(ctx, ret);
882
    }
883
}
884

    
885
static void gen_addic(DisasContext *ctx)
886
{
887
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
888
}
889

    
890
static void gen_addic_(DisasContext *ctx)
891
{
892
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
893
}
894

    
895
/* addis */
896
static void gen_addis(DisasContext *ctx)
897
{
898
    target_long simm = SIMM(ctx->opcode);
899

    
900
    if (rA(ctx->opcode) == 0) {
901
        /* lis case */
902
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
903
    } else {
904
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
905
    }
906
}
907

    
908
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
909
                                     TCGv arg2, int sign, int compute_ov)
910
{
911
    int l1 = gen_new_label();
912
    int l2 = gen_new_label();
913
    TCGv_i32 t0 = tcg_temp_local_new_i32();
914
    TCGv_i32 t1 = tcg_temp_local_new_i32();
915

    
916
    tcg_gen_trunc_tl_i32(t0, arg1);
917
    tcg_gen_trunc_tl_i32(t1, arg2);
918
    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
919
    if (sign) {
920
        int l3 = gen_new_label();
921
        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
922
        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
923
        gen_set_label(l3);
924
        tcg_gen_div_i32(t0, t0, t1);
925
    } else {
926
        tcg_gen_divu_i32(t0, t0, t1);
927
    }
928
    if (compute_ov) {
929
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
930
    }
931
    tcg_gen_br(l2);
932
    gen_set_label(l1);
933
    if (sign) {
934
        tcg_gen_sari_i32(t0, t0, 31);
935
    } else {
936
        tcg_gen_movi_i32(t0, 0);
937
    }
938
    if (compute_ov) {
939
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
940
    }
941
    gen_set_label(l2);
942
    tcg_gen_extu_i32_tl(ret, t0);
943
    tcg_temp_free_i32(t0);
944
    tcg_temp_free_i32(t1);
945
    if (unlikely(Rc(ctx->opcode) != 0))
946
        gen_set_Rc0(ctx, ret);
947
}
948
/* Div functions */
949
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
950
static void glue(gen_, name)(DisasContext *ctx)                                       \
951
{                                                                             \
952
    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
953
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
954
                     sign, compute_ov);                                       \
955
}
956
/* divwu  divwu.  divwuo  divwuo.   */
957
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959
/* divw  divw.  divwo  divwo.   */
960
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962
#if defined(TARGET_PPC64)
963
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964
                                     TCGv arg2, int sign, int compute_ov)
965
{
966
    int l1 = gen_new_label();
967
    int l2 = gen_new_label();
968

    
969
    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970
    if (sign) {
971
        int l3 = gen_new_label();
972
        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973
        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974
        gen_set_label(l3);
975
        tcg_gen_div_i64(ret, arg1, arg2);
976
    } else {
977
        tcg_gen_divu_i64(ret, arg1, arg2);
978
    }
979
    if (compute_ov) {
980
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
981
    }
982
    tcg_gen_br(l2);
983
    gen_set_label(l1);
984
    if (sign) {
985
        tcg_gen_sari_i64(ret, arg1, 63);
986
    } else {
987
        tcg_gen_movi_i64(ret, 0);
988
    }
989
    if (compute_ov) {
990
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
991
    }
992
    gen_set_label(l2);
993
    if (unlikely(Rc(ctx->opcode) != 0))
994
        gen_set_Rc0(ctx, ret);
995
}
996
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
997
static void glue(gen_, name)(DisasContext *ctx)                                       \
998
{                                                                             \
999
    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1000
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1001
                      sign, compute_ov);                                      \
1002
}
1003
/* divwu  divwu.  divwuo  divwuo.   */
1004
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1005
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1006
/* divw  divw.  divwo  divwo.   */
1007
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1008
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1009
#endif
1010

    
1011
/* mulhw  mulhw. */
1012
static void gen_mulhw(DisasContext *ctx)
1013
{
1014
    TCGv_i64 t0, t1;
1015

    
1016
    t0 = tcg_temp_new_i64();
1017
    t1 = tcg_temp_new_i64();
1018
#if defined(TARGET_PPC64)
1019
    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1020
    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1021
    tcg_gen_mul_i64(t0, t0, t1);
1022
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1023
#else
1024
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1025
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1026
    tcg_gen_mul_i64(t0, t0, t1);
1027
    tcg_gen_shri_i64(t0, t0, 32);
1028
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1029
#endif
1030
    tcg_temp_free_i64(t0);
1031
    tcg_temp_free_i64(t1);
1032
    if (unlikely(Rc(ctx->opcode) != 0))
1033
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034
}
1035

    
1036
/* mulhwu  mulhwu.  */
1037
static void gen_mulhwu(DisasContext *ctx)
1038
{
1039
    TCGv_i64 t0, t1;
1040

    
1041
    t0 = tcg_temp_new_i64();
1042
    t1 = tcg_temp_new_i64();
1043
#if defined(TARGET_PPC64)
1044
    tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1045
    tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1046
    tcg_gen_mul_i64(t0, t0, t1);
1047
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1048
#else
1049
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1050
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1051
    tcg_gen_mul_i64(t0, t0, t1);
1052
    tcg_gen_shri_i64(t0, t0, 32);
1053
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1054
#endif
1055
    tcg_temp_free_i64(t0);
1056
    tcg_temp_free_i64(t1);
1057
    if (unlikely(Rc(ctx->opcode) != 0))
1058
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1059
}
1060

    
1061
/* mullw  mullw. */
1062
static void gen_mullw(DisasContext *ctx)
1063
{
1064
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1065
                   cpu_gpr[rB(ctx->opcode)]);
1066
    tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1067
    if (unlikely(Rc(ctx->opcode) != 0))
1068
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1069
}
1070

    
1071
/* mullwo  mullwo. */
1072
static void gen_mullwo(DisasContext *ctx)
1073
{
1074
    int l1;
1075
    TCGv_i64 t0, t1;
1076

    
1077
    t0 = tcg_temp_new_i64();
1078
    t1 = tcg_temp_new_i64();
1079
    l1 = gen_new_label();
1080
    /* Start with XER OV disabled, the most likely case */
1081
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1082
#if defined(TARGET_PPC64)
1083
    tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1084
    tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1085
#else
1086
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1087
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1088
#endif
1089
    tcg_gen_mul_i64(t0, t0, t1);
1090
#if defined(TARGET_PPC64)
1091
    tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1092
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1093
#else
1094
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1095
    tcg_gen_ext32s_i64(t1, t0);
1096
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1097
#endif
1098
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1099
    gen_set_label(l1);
1100
    tcg_temp_free_i64(t0);
1101
    tcg_temp_free_i64(t1);
1102
    if (unlikely(Rc(ctx->opcode) != 0))
1103
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1104
}
1105

    
1106
/* mulli */
1107
static void gen_mulli(DisasContext *ctx)
1108
{
1109
    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1110
                    SIMM(ctx->opcode));
1111
}
1112
#if defined(TARGET_PPC64)
1113
#define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
1114
static void glue(gen_, name)(DisasContext *ctx)                                       \
1115
{                                                                             \
1116
    gen_helper_##name (cpu_gpr[rD(ctx->opcode)],                              \
1117
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);   \
1118
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1119
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1120
}
1121
/* mulhd  mulhd. */
1122
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1123
/* mulhdu  mulhdu. */
1124
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1125

    
1126
/* mulld  mulld. */
1127
static void gen_mulld(DisasContext *ctx)
1128
{
1129
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1130
                   cpu_gpr[rB(ctx->opcode)]);
1131
    if (unlikely(Rc(ctx->opcode) != 0))
1132
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1133
}
1134
/* mulldo  mulldo. */
1135
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1136
#endif
1137

    
1138
/* neg neg. nego nego. */
1139
static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1140
                                    int ov_check)
1141
{
1142
    int l1 = gen_new_label();
1143
    int l2 = gen_new_label();
1144
    TCGv t0 = tcg_temp_local_new();
1145
#if defined(TARGET_PPC64)
1146
    if (ctx->sf_mode) {
1147
        tcg_gen_mov_tl(t0, arg1);
1148
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1149
    } else
1150
#endif
1151
    {
1152
        tcg_gen_ext32s_tl(t0, arg1);
1153
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1154
    }
1155
    tcg_gen_neg_tl(ret, arg1);
1156
    if (ov_check) {
1157
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1158
    }
1159
    tcg_gen_br(l2);
1160
    gen_set_label(l1);
1161
    tcg_gen_mov_tl(ret, t0);
1162
    if (ov_check) {
1163
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1164
    }
1165
    gen_set_label(l2);
1166
    tcg_temp_free(t0);
1167
    if (unlikely(Rc(ctx->opcode) != 0))
1168
        gen_set_Rc0(ctx, ret);
1169
}
1170

    
1171
static void gen_neg(DisasContext *ctx)
1172
{
1173
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1174
}
1175

    
1176
static void gen_nego(DisasContext *ctx)
1177
{
1178
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1179
}
1180

    
1181
/* Common subf function */
1182
static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1183
                                     TCGv arg2, int add_ca, int compute_ca,
1184
                                     int compute_ov)
1185
{
1186
    TCGv t0, t1;
1187

    
1188
    if ((!compute_ca && !compute_ov) ||
1189
        (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2)))  {
1190
        t0 = ret;
1191
    } else {
1192
        t0 = tcg_temp_local_new();
1193
    }
1194

    
1195
    if (add_ca) {
1196
        t1 = tcg_temp_local_new();
1197
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1198
        tcg_gen_shri_tl(t1, t1, XER_CA);
1199
    } else {
1200
        TCGV_UNUSED(t1);
1201
    }
1202

    
1203
    if (compute_ca && compute_ov) {
1204
        /* Start with XER CA and OV disabled, the most likely case */
1205
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1206
    } else if (compute_ca) {
1207
        /* Start with XER CA disabled, the most likely case */
1208
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1209
    } else if (compute_ov) {
1210
        /* Start with XER OV disabled, the most likely case */
1211
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1212
    }
1213

    
1214
    if (add_ca) {
1215
        tcg_gen_not_tl(t0, arg1);
1216
        tcg_gen_add_tl(t0, t0, arg2);
1217
        gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1218
        tcg_gen_add_tl(t0, t0, t1);
1219
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
1220
        tcg_temp_free(t1);
1221
    } else {
1222
        tcg_gen_sub_tl(t0, arg2, arg1);
1223
        if (compute_ca) {
1224
            gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1225
        }
1226
    }
1227
    if (compute_ov) {
1228
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1229
    }
1230

    
1231
    if (unlikely(Rc(ctx->opcode) != 0))
1232
        gen_set_Rc0(ctx, t0);
1233

    
1234
    if (!TCGV_EQUAL(t0, ret)) {
1235
        tcg_gen_mov_tl(ret, t0);
1236
        tcg_temp_free(t0);
1237
    }
1238
}
1239
/* Sub functions with Two operands functions */
1240
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1241
static void glue(gen_, name)(DisasContext *ctx)                                       \
1242
{                                                                             \
1243
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1244
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1245
                      add_ca, compute_ca, compute_ov);                        \
1246
}
1247
/* Sub functions with one operand and one immediate */
1248
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1249
                                add_ca, compute_ca, compute_ov)               \
1250
static void glue(gen_, name)(DisasContext *ctx)                                       \
1251
{                                                                             \
1252
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
1253
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1254
                      cpu_gpr[rA(ctx->opcode)], t0,                           \
1255
                      add_ca, compute_ca, compute_ov);                        \
1256
    tcg_temp_free(t0);                                                        \
1257
}
1258
/* subf  subf.  subfo  subfo. */
1259
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1260
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1261
/* subfc  subfc.  subfco  subfco. */
1262
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1263
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1264
/* subfe  subfe.  subfeo  subfo. */
1265
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1266
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1267
/* subfme  subfme.  subfmeo  subfmeo.  */
1268
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1269
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1270
/* subfze  subfze.  subfzeo  subfzeo.*/
1271
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1272
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1273

    
1274
/* subfic */
1275
static void gen_subfic(DisasContext *ctx)
1276
{
1277
    /* Start with XER CA and OV disabled, the most likely case */
1278
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1279
    TCGv t0 = tcg_temp_local_new();
1280
    TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1281
    tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1282
    gen_op_arith_compute_ca(ctx, t0, t1, 1);
1283
    tcg_temp_free(t1);
1284
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1285
    tcg_temp_free(t0);
1286
}
1287

    
1288
/***                            Integer logical                            ***/
1289
#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1290
static void glue(gen_, name)(DisasContext *ctx)                                       \
1291
{                                                                             \
1292
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1293
       cpu_gpr[rB(ctx->opcode)]);                                             \
1294
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1295
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1296
}
1297

    
1298
#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1299
static void glue(gen_, name)(DisasContext *ctx)                                       \
1300
{                                                                             \
1301
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1302
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1303
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1304
}
1305

    
1306
/* and & and. */
1307
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1308
/* andc & andc. */
1309
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1310

    
1311
/* andi. */
1312
static void gen_andi_(DisasContext *ctx)
1313
{
1314
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1315
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1316
}
1317

    
1318
/* andis. */
1319
static void gen_andis_(DisasContext *ctx)
1320
{
1321
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1322
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1323
}
1324

    
1325
/* cntlzw */
1326
static void gen_cntlzw(DisasContext *ctx)
1327
{
1328
    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1329
    if (unlikely(Rc(ctx->opcode) != 0))
1330
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1331
}
1332
/* eqv & eqv. */
1333
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1334
/* extsb & extsb. */
1335
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1336
/* extsh & extsh. */
1337
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1338
/* nand & nand. */
1339
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1340
/* nor & nor. */
1341
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1342

    
1343
/* or & or. */
1344
static void gen_or(DisasContext *ctx)
1345
{
1346
    int rs, ra, rb;
1347

    
1348
    rs = rS(ctx->opcode);
1349
    ra = rA(ctx->opcode);
1350
    rb = rB(ctx->opcode);
1351
    /* Optimisation for mr. ri case */
1352
    if (rs != ra || rs != rb) {
1353
        if (rs != rb)
1354
            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1355
        else
1356
            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1357
        if (unlikely(Rc(ctx->opcode) != 0))
1358
            gen_set_Rc0(ctx, cpu_gpr[ra]);
1359
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1360
        gen_set_Rc0(ctx, cpu_gpr[rs]);
1361
#if defined(TARGET_PPC64)
1362
    } else {
1363
        int prio = 0;
1364

    
1365
        switch (rs) {
1366
        case 1:
1367
            /* Set process priority to low */
1368
            prio = 2;
1369
            break;
1370
        case 6:
1371
            /* Set process priority to medium-low */
1372
            prio = 3;
1373
            break;
1374
        case 2:
1375
            /* Set process priority to normal */
1376
            prio = 4;
1377
            break;
1378
#if !defined(CONFIG_USER_ONLY)
1379
        case 31:
1380
            if (ctx->mem_idx > 0) {
1381
                /* Set process priority to very low */
1382
                prio = 1;
1383
            }
1384
            break;
1385
        case 5:
1386
            if (ctx->mem_idx > 0) {
1387
                /* Set process priority to medium-hight */
1388
                prio = 5;
1389
            }
1390
            break;
1391
        case 3:
1392
            if (ctx->mem_idx > 0) {
1393
                /* Set process priority to high */
1394
                prio = 6;
1395
            }
1396
            break;
1397
        case 7:
1398
            if (ctx->mem_idx > 1) {
1399
                /* Set process priority to very high */
1400
                prio = 7;
1401
            }
1402
            break;
1403
#endif
1404
        default:
1405
            /* nop */
1406
            break;
1407
        }
1408
        if (prio) {
1409
            TCGv t0 = tcg_temp_new();
1410
            gen_load_spr(t0, SPR_PPR);
1411
            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1412
            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1413
            gen_store_spr(SPR_PPR, t0);
1414
            tcg_temp_free(t0);
1415
        }
1416
#endif
1417
    }
1418
}
1419
/* orc & orc. */
1420
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1421

    
1422
/* xor & xor. */
1423
static void gen_xor(DisasContext *ctx)
1424
{
1425
    /* Optimisation for "set to zero" case */
1426
    if (rS(ctx->opcode) != rB(ctx->opcode))
1427
        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1428
    else
1429
        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1430
    if (unlikely(Rc(ctx->opcode) != 0))
1431
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1432
}
1433

    
1434
/* ori */
1435
static void gen_ori(DisasContext *ctx)
1436
{
1437
    target_ulong uimm = UIMM(ctx->opcode);
1438

    
1439
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1440
        /* NOP */
1441
        /* XXX: should handle special NOPs for POWER series */
1442
        return;
1443
    }
1444
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1445
}
1446

    
1447
/* oris */
1448
static void gen_oris(DisasContext *ctx)
1449
{
1450
    target_ulong uimm = UIMM(ctx->opcode);
1451

    
1452
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1453
        /* NOP */
1454
        return;
1455
    }
1456
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1457
}
1458

    
1459
/* xori */
1460
static void gen_xori(DisasContext *ctx)
1461
{
1462
    target_ulong uimm = UIMM(ctx->opcode);
1463

    
1464
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1465
        /* NOP */
1466
        return;
1467
    }
1468
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1469
}
1470

    
1471
/* xoris */
1472
static void gen_xoris(DisasContext *ctx)
1473
{
1474
    target_ulong uimm = UIMM(ctx->opcode);
1475

    
1476
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1477
        /* NOP */
1478
        return;
1479
    }
1480
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1481
}
1482

    
1483
/* popcntb : PowerPC 2.03 specification */
1484
static void gen_popcntb(DisasContext *ctx)
1485
{
1486
#if defined(TARGET_PPC64)
1487
    if (ctx->sf_mode)
1488
        gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1489
    else
1490
#endif
1491
        gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1492
}
1493

    
1494
#if defined(TARGET_PPC64)
1495
/* extsw & extsw. */
1496
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1497

    
1498
/* cntlzd */
1499
static void gen_cntlzd(DisasContext *ctx)
1500
{
1501
    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1502
    if (unlikely(Rc(ctx->opcode) != 0))
1503
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1504
}
1505
#endif
1506

    
1507
/***                             Integer rotate                            ***/
1508

    
1509
/* rlwimi & rlwimi. */
1510
static void gen_rlwimi(DisasContext *ctx)
1511
{
1512
    uint32_t mb, me, sh;
1513

    
1514
    mb = MB(ctx->opcode);
1515
    me = ME(ctx->opcode);
1516
    sh = SH(ctx->opcode);
1517
    if (likely(sh == 0 && mb == 0 && me == 31)) {
1518
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1519
    } else {
1520
        target_ulong mask;
1521
        TCGv t1;
1522
        TCGv t0 = tcg_temp_new();
1523
#if defined(TARGET_PPC64)
1524
        TCGv_i32 t2 = tcg_temp_new_i32();
1525
        tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1526
        tcg_gen_rotli_i32(t2, t2, sh);
1527
        tcg_gen_extu_i32_i64(t0, t2);
1528
        tcg_temp_free_i32(t2);
1529
#else
1530
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1531
#endif
1532
#if defined(TARGET_PPC64)
1533
        mb += 32;
1534
        me += 32;
1535
#endif
1536
        mask = MASK(mb, me);
1537
        t1 = tcg_temp_new();
1538
        tcg_gen_andi_tl(t0, t0, mask);
1539
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1540
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1541
        tcg_temp_free(t0);
1542
        tcg_temp_free(t1);
1543
    }
1544
    if (unlikely(Rc(ctx->opcode) != 0))
1545
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1546
}
1547

    
1548
/* rlwinm & rlwinm. */
1549
static void gen_rlwinm(DisasContext *ctx)
1550
{
1551
    uint32_t mb, me, sh;
1552

    
1553
    sh = SH(ctx->opcode);
1554
    mb = MB(ctx->opcode);
1555
    me = ME(ctx->opcode);
1556

    
1557
    if (likely(mb == 0 && me == (31 - sh))) {
1558
        if (likely(sh == 0)) {
1559
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560
        } else {
1561
            TCGv t0 = tcg_temp_new();
1562
            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1563
            tcg_gen_shli_tl(t0, t0, sh);
1564
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1565
            tcg_temp_free(t0);
1566
        }
1567
    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1568
        TCGv t0 = tcg_temp_new();
1569
        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1570
        tcg_gen_shri_tl(t0, t0, mb);
1571
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1572
        tcg_temp_free(t0);
1573
    } else {
1574
        TCGv t0 = tcg_temp_new();
1575
#if defined(TARGET_PPC64)
1576
        TCGv_i32 t1 = tcg_temp_new_i32();
1577
        tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1578
        tcg_gen_rotli_i32(t1, t1, sh);
1579
        tcg_gen_extu_i32_i64(t0, t1);
1580
        tcg_temp_free_i32(t1);
1581
#else
1582
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1583
#endif
1584
#if defined(TARGET_PPC64)
1585
        mb += 32;
1586
        me += 32;
1587
#endif
1588
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1589
        tcg_temp_free(t0);
1590
    }
1591
    if (unlikely(Rc(ctx->opcode) != 0))
1592
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1593
}
1594

    
1595
/* rlwnm & rlwnm. */
1596
static void gen_rlwnm(DisasContext *ctx)
1597
{
1598
    uint32_t mb, me;
1599
    TCGv t0;
1600
#if defined(TARGET_PPC64)
1601
    TCGv_i32 t1, t2;
1602
#endif
1603

    
1604
    mb = MB(ctx->opcode);
1605
    me = ME(ctx->opcode);
1606
    t0 = tcg_temp_new();
1607
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1608
#if defined(TARGET_PPC64)
1609
    t1 = tcg_temp_new_i32();
1610
    t2 = tcg_temp_new_i32();
1611
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1612
    tcg_gen_trunc_i64_i32(t2, t0);
1613
    tcg_gen_rotl_i32(t1, t1, t2);
1614
    tcg_gen_extu_i32_i64(t0, t1);
1615
    tcg_temp_free_i32(t1);
1616
    tcg_temp_free_i32(t2);
1617
#else
1618
    tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1619
#endif
1620
    if (unlikely(mb != 0 || me != 31)) {
1621
#if defined(TARGET_PPC64)
1622
        mb += 32;
1623
        me += 32;
1624
#endif
1625
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1626
    } else {
1627
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1628
    }
1629
    tcg_temp_free(t0);
1630
    if (unlikely(Rc(ctx->opcode) != 0))
1631
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632
}
1633

    
1634
#if defined(TARGET_PPC64)
1635
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1636
static void glue(gen_, name##0)(DisasContext *ctx)                            \
1637
{                                                                             \
1638
    gen_##name(ctx, 0);                                                       \
1639
}                                                                             \
1640
                                                                              \
1641
static void glue(gen_, name##1)(DisasContext *ctx)                            \
1642
{                                                                             \
1643
    gen_##name(ctx, 1);                                                       \
1644
}
1645
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1646
static void glue(gen_, name##0)(DisasContext *ctx)                            \
1647
{                                                                             \
1648
    gen_##name(ctx, 0, 0);                                                    \
1649
}                                                                             \
1650
                                                                              \
1651
static void glue(gen_, name##1)(DisasContext *ctx)                            \
1652
{                                                                             \
1653
    gen_##name(ctx, 0, 1);                                                    \
1654
}                                                                             \
1655
                                                                              \
1656
static void glue(gen_, name##2)(DisasContext *ctx)                            \
1657
{                                                                             \
1658
    gen_##name(ctx, 1, 0);                                                    \
1659
}                                                                             \
1660
                                                                              \
1661
static void glue(gen_, name##3)(DisasContext *ctx)                            \
1662
{                                                                             \
1663
    gen_##name(ctx, 1, 1);                                                    \
1664
}
1665

    
1666
static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1667
                              uint32_t sh)
1668
{
1669
    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1670
        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1671
    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1672
        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1673
    } else {
1674
        TCGv t0 = tcg_temp_new();
1675
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1676
        if (likely(mb == 0 && me == 63)) {
1677
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1678
        } else {
1679
            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1680
        }
1681
        tcg_temp_free(t0);
1682
    }
1683
    if (unlikely(Rc(ctx->opcode) != 0))
1684
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1685
}
1686
/* rldicl - rldicl. */
1687
static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1688
{
1689
    uint32_t sh, mb;
1690

    
1691
    sh = SH(ctx->opcode) | (shn << 5);
1692
    mb = MB(ctx->opcode) | (mbn << 5);
1693
    gen_rldinm(ctx, mb, 63, sh);
1694
}
1695
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1696
/* rldicr - rldicr. */
1697
static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1698
{
1699
    uint32_t sh, me;
1700

    
1701
    sh = SH(ctx->opcode) | (shn << 5);
1702
    me = MB(ctx->opcode) | (men << 5);
1703
    gen_rldinm(ctx, 0, me, sh);
1704
}
1705
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1706
/* rldic - rldic. */
1707
static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1708
{
1709
    uint32_t sh, mb;
1710

    
1711
    sh = SH(ctx->opcode) | (shn << 5);
1712
    mb = MB(ctx->opcode) | (mbn << 5);
1713
    gen_rldinm(ctx, mb, 63 - sh, sh);
1714
}
1715
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1716

    
1717
static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1718
{
1719
    TCGv t0;
1720

    
1721
    mb = MB(ctx->opcode);
1722
    me = ME(ctx->opcode);
1723
    t0 = tcg_temp_new();
1724
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1725
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1726
    if (unlikely(mb != 0 || me != 63)) {
1727
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1728
    } else {
1729
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1730
    }
1731
    tcg_temp_free(t0);
1732
    if (unlikely(Rc(ctx->opcode) != 0))
1733
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1734
}
1735

    
1736
/* rldcl - rldcl. */
1737
static inline void gen_rldcl(DisasContext *ctx, int mbn)
1738
{
1739
    uint32_t mb;
1740

    
1741
    mb = MB(ctx->opcode) | (mbn << 5);
1742
    gen_rldnm(ctx, mb, 63);
1743
}
1744
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1745
/* rldcr - rldcr. */
1746
static inline void gen_rldcr(DisasContext *ctx, int men)
1747
{
1748
    uint32_t me;
1749

    
1750
    me = MB(ctx->opcode) | (men << 5);
1751
    gen_rldnm(ctx, 0, me);
1752
}
1753
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1754
/* rldimi - rldimi. */
1755
static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1756
{
1757
    uint32_t sh, mb, me;
1758

    
1759
    sh = SH(ctx->opcode) | (shn << 5);
1760
    mb = MB(ctx->opcode) | (mbn << 5);
1761
    me = 63 - sh;
1762
    if (unlikely(sh == 0 && mb == 0)) {
1763
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1764
    } else {
1765
        TCGv t0, t1;
1766
        target_ulong mask;
1767

    
1768
        t0 = tcg_temp_new();
1769
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1770
        t1 = tcg_temp_new();
1771
        mask = MASK(mb, me);
1772
        tcg_gen_andi_tl(t0, t0, mask);
1773
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1774
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1775
        tcg_temp_free(t0);
1776
        tcg_temp_free(t1);
1777
    }
1778
    if (unlikely(Rc(ctx->opcode) != 0))
1779
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1780
}
1781
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1782
#endif
1783

    
1784
/***                             Integer shift                             ***/
1785

    
1786
/* slw & slw. */
1787
static void gen_slw(DisasContext *ctx)
1788
{
1789
    TCGv t0, t1;
1790

    
1791
    t0 = tcg_temp_new();
1792
    /* AND rS with a mask that is 0 when rB >= 0x20 */
1793
#if defined(TARGET_PPC64)
1794
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1795
    tcg_gen_sari_tl(t0, t0, 0x3f);
1796
#else
1797
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1798
    tcg_gen_sari_tl(t0, t0, 0x1f);
1799
#endif
1800
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1801
    t1 = tcg_temp_new();
1802
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1803
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1804
    tcg_temp_free(t1);
1805
    tcg_temp_free(t0);
1806
    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1807
    if (unlikely(Rc(ctx->opcode) != 0))
1808
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1809
}
1810

    
1811
/* sraw & sraw. */
1812
static void gen_sraw(DisasContext *ctx)
1813
{
1814
    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1815
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1816
    if (unlikely(Rc(ctx->opcode) != 0))
1817
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1818
}
1819

    
1820
/* srawi & srawi. */
1821
static void gen_srawi(DisasContext *ctx)
1822
{
1823
    int sh = SH(ctx->opcode);
1824
    if (sh != 0) {
1825
        int l1, l2;
1826
        TCGv t0;
1827
        l1 = gen_new_label();
1828
        l2 = gen_new_label();
1829
        t0 = tcg_temp_local_new();
1830
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1831
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1832
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1833
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1834
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1835
        tcg_gen_br(l2);
1836
        gen_set_label(l1);
1837
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1838
        gen_set_label(l2);
1839
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1840
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1841
        tcg_temp_free(t0);
1842
    } else {
1843
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1844
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1845
    }
1846
    if (unlikely(Rc(ctx->opcode) != 0))
1847
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1848
}
1849

    
1850
/* srw & srw. */
1851
static void gen_srw(DisasContext *ctx)
1852
{
1853
    TCGv t0, t1;
1854

    
1855
    t0 = tcg_temp_new();
1856
    /* AND rS with a mask that is 0 when rB >= 0x20 */
1857
#if defined(TARGET_PPC64)
1858
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859
    tcg_gen_sari_tl(t0, t0, 0x3f);
1860
#else
1861
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862
    tcg_gen_sari_tl(t0, t0, 0x1f);
1863
#endif
1864
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865
    tcg_gen_ext32u_tl(t0, t0);
1866
    t1 = tcg_temp_new();
1867
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1868
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1869
    tcg_temp_free(t1);
1870
    tcg_temp_free(t0);
1871
    if (unlikely(Rc(ctx->opcode) != 0))
1872
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873
}
1874

    
1875
#if defined(TARGET_PPC64)
1876
/* sld & sld. */
1877
static void gen_sld(DisasContext *ctx)
1878
{
1879
    TCGv t0, t1;
1880

    
1881
    t0 = tcg_temp_new();
1882
    /* AND rS with a mask that is 0 when rB >= 0x40 */
1883
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1884
    tcg_gen_sari_tl(t0, t0, 0x3f);
1885
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1886
    t1 = tcg_temp_new();
1887
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1888
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1889
    tcg_temp_free(t1);
1890
    tcg_temp_free(t0);
1891
    if (unlikely(Rc(ctx->opcode) != 0))
1892
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1893
}
1894

    
1895
/* srad & srad. */
1896
static void gen_srad(DisasContext *ctx)
1897
{
1898
    gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1899
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1900
    if (unlikely(Rc(ctx->opcode) != 0))
1901
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1902
}
1903
/* sradi & sradi. */
1904
static inline void gen_sradi(DisasContext *ctx, int n)
1905
{
1906
    int sh = SH(ctx->opcode) + (n << 5);
1907
    if (sh != 0) {
1908
        int l1, l2;
1909
        TCGv t0;
1910
        l1 = gen_new_label();
1911
        l2 = gen_new_label();
1912
        t0 = tcg_temp_local_new();
1913
        tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1914
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1915
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1916
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1917
        tcg_gen_br(l2);
1918
        gen_set_label(l1);
1919
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1920
        gen_set_label(l2);
1921
        tcg_temp_free(t0);
1922
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1923
    } else {
1924
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1925
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1926
    }
1927
    if (unlikely(Rc(ctx->opcode) != 0))
1928
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1929
}
1930

    
1931
static void gen_sradi0(DisasContext *ctx)
1932
{
1933
    gen_sradi(ctx, 0);
1934
}
1935

    
1936
static void gen_sradi1(DisasContext *ctx)
1937
{
1938
    gen_sradi(ctx, 1);
1939
}
1940

    
1941
/* srd & srd. */
1942
static void gen_srd(DisasContext *ctx)
1943
{
1944
    TCGv t0, t1;
1945

    
1946
    t0 = tcg_temp_new();
1947
    /* AND rS with a mask that is 0 when rB >= 0x40 */
1948
    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1949
    tcg_gen_sari_tl(t0, t0, 0x3f);
1950
    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1951
    t1 = tcg_temp_new();
1952
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1953
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1954
    tcg_temp_free(t1);
1955
    tcg_temp_free(t0);
1956
    if (unlikely(Rc(ctx->opcode) != 0))
1957
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1958
}
1959
#endif
1960

    
1961
/***                       Floating-Point arithmetic                       ***/
1962
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1963
static void gen_f##name(DisasContext *ctx)                                    \
1964
{                                                                             \
1965
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1966
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
1967
        return;                                                               \
1968
    }                                                                         \
1969
    /* NIP cannot be restored if the memory exception comes from an helper */ \
1970
    gen_update_nip(ctx, ctx->nip - 4);                                        \
1971
    gen_reset_fpstatus();                                                     \
1972
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
1973
                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
1974
    if (isfloat) {                                                            \
1975
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
1976
    }                                                                         \
1977
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf,                      \
1978
                     Rc(ctx->opcode) != 0);                                   \
1979
}
1980

    
1981
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1982
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1983
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1984

    
1985
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1986
static void gen_f##name(DisasContext *ctx)                                    \
1987
{                                                                             \
1988
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1989
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
1990
        return;                                                               \
1991
    }                                                                         \
1992
    /* NIP cannot be restored if the memory exception comes from an helper */ \
1993
    gen_update_nip(ctx, ctx->nip - 4);                                        \
1994
    gen_reset_fpstatus();                                                     \
1995
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
1996
                     cpu_fpr[rB(ctx->opcode)]);                               \
1997
    if (isfloat) {                                                            \
1998
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
1999
    }                                                                         \
2000
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2001
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2002
}
2003
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
2004
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2005
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2006

    
2007
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2008
static void gen_f##name(DisasContext *ctx)                                    \
2009
{                                                                             \
2010
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2011
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2012
        return;                                                               \
2013
    }                                                                         \
2014
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2015
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2016
    gen_reset_fpstatus();                                                     \
2017
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
2018
                       cpu_fpr[rC(ctx->opcode)]);                             \
2019
    if (isfloat) {                                                            \
2020
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2021
    }                                                                         \
2022
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2023
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2024
}
2025
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
2026
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2027
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2028

    
2029
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2030
static void gen_f##name(DisasContext *ctx)                                    \
2031
{                                                                             \
2032
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2033
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2034
        return;                                                               \
2035
    }                                                                         \
2036
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2037
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2038
    gen_reset_fpstatus();                                                     \
2039
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2040
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2041
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2042
}
2043

    
2044
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2045
static void gen_f##name(DisasContext *ctx)                                    \
2046
{                                                                             \
2047
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2048
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2049
        return;                                                               \
2050
    }                                                                         \
2051
    /* NIP cannot be restored if the memory exception comes from an helper */ \
2052
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2053
    gen_reset_fpstatus();                                                     \
2054
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
2055
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
2056
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2057
}
2058

    
2059
/* fadd - fadds */
2060
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2061
/* fdiv - fdivs */
2062
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2063
/* fmul - fmuls */
2064
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2065

    
2066
/* fre */
2067
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2068

    
2069
/* fres */
2070
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2071

    
2072
/* frsqrte */
2073
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2074

    
2075
/* frsqrtes */
2076
static void gen_frsqrtes(DisasContext *ctx)
2077
{
2078
    if (unlikely(!ctx->fpu_enabled)) {
2079
        gen_exception(ctx, POWERPC_EXCP_FPU);
2080
        return;
2081
    }
2082
    /* NIP cannot be restored if the memory exception comes from an helper */
2083
    gen_update_nip(ctx, ctx->nip - 4);
2084
    gen_reset_fpstatus();
2085
    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2086
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2087
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2088
}
2089

    
2090
/* fsel */
2091
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2092
/* fsub - fsubs */
2093
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2094
/* Optional: */
2095

    
2096
/* fsqrt */
2097
static void gen_fsqrt(DisasContext *ctx)
2098
{
2099
    if (unlikely(!ctx->fpu_enabled)) {
2100
        gen_exception(ctx, POWERPC_EXCP_FPU);
2101
        return;
2102
    }
2103
    /* NIP cannot be restored if the memory exception comes from an helper */
2104
    gen_update_nip(ctx, ctx->nip - 4);
2105
    gen_reset_fpstatus();
2106
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2107
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2108
}
2109

    
2110
static void gen_fsqrts(DisasContext *ctx)
2111
{
2112
    if (unlikely(!ctx->fpu_enabled)) {
2113
        gen_exception(ctx, POWERPC_EXCP_FPU);
2114
        return;
2115
    }
2116
    /* NIP cannot be restored if the memory exception comes from an helper */
2117
    gen_update_nip(ctx, ctx->nip - 4);
2118
    gen_reset_fpstatus();
2119
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2120
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2121
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2122
}
2123

    
2124
/***                     Floating-Point multiply-and-add                   ***/
2125
/* fmadd - fmadds */
2126
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2127
/* fmsub - fmsubs */
2128
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2129
/* fnmadd - fnmadds */
2130
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2131
/* fnmsub - fnmsubs */
2132
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2133

    
2134
/***                     Floating-Point round & convert                    ***/
2135
/* fctiw */
2136
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2137
/* fctiwz */
2138
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2139
/* frsp */
2140
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2141
#if defined(TARGET_PPC64)
2142
/* fcfid */
2143
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2144
/* fctid */
2145
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2146
/* fctidz */
2147
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2148
#endif
2149

    
2150
/* frin */
2151
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2152
/* friz */
2153
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2154
/* frip */
2155
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2156
/* frim */
2157
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2158

    
2159
/***                         Floating-Point compare                        ***/
2160

    
2161
/* fcmpo */
2162
static void gen_fcmpo(DisasContext *ctx)
2163
{
2164
    TCGv_i32 crf;
2165
    if (unlikely(!ctx->fpu_enabled)) {
2166
        gen_exception(ctx, POWERPC_EXCP_FPU);
2167
        return;
2168
    }
2169
    /* NIP cannot be restored if the memory exception comes from an helper */
2170
    gen_update_nip(ctx, ctx->nip - 4);
2171
    gen_reset_fpstatus();
2172
    crf = tcg_const_i32(crfD(ctx->opcode));
2173
    gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2174
    tcg_temp_free_i32(crf);
2175
    gen_helper_float_check_status();
2176
}
2177

    
2178
/* fcmpu */
2179
static void gen_fcmpu(DisasContext *ctx)
2180
{
2181
    TCGv_i32 crf;
2182
    if (unlikely(!ctx->fpu_enabled)) {
2183
        gen_exception(ctx, POWERPC_EXCP_FPU);
2184
        return;
2185
    }
2186
    /* NIP cannot be restored if the memory exception comes from an helper */
2187
    gen_update_nip(ctx, ctx->nip - 4);
2188
    gen_reset_fpstatus();
2189
    crf = tcg_const_i32(crfD(ctx->opcode));
2190
    gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2191
    tcg_temp_free_i32(crf);
2192
    gen_helper_float_check_status();
2193
}
2194

    
2195
/***                         Floating-point move                           ***/
2196
/* fabs */
2197
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2198
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2199

    
2200
/* fmr  - fmr. */
2201
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2202
static void gen_fmr(DisasContext *ctx)
2203
{
2204
    if (unlikely(!ctx->fpu_enabled)) {
2205
        gen_exception(ctx, POWERPC_EXCP_FPU);
2206
        return;
2207
    }
2208
    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2209
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2210
}
2211

    
2212
/* fnabs */
2213
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2214
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2215
/* fneg */
2216
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2217
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2218

    
2219
/***                  Floating-Point status & ctrl register                ***/
2220

    
2221
/* mcrfs */
2222
static void gen_mcrfs(DisasContext *ctx)
2223
{
2224
    int bfa;
2225

    
2226
    if (unlikely(!ctx->fpu_enabled)) {
2227
        gen_exception(ctx, POWERPC_EXCP_FPU);
2228
        return;
2229
    }
2230
    bfa = 4 * (7 - crfS(ctx->opcode));
2231
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2232
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2233
    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2234
}
2235

    
2236
/* mffs */
2237
static void gen_mffs(DisasContext *ctx)
2238
{
2239
    if (unlikely(!ctx->fpu_enabled)) {
2240
        gen_exception(ctx, POWERPC_EXCP_FPU);
2241
        return;
2242
    }
2243
    gen_reset_fpstatus();
2244
    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2245
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2246
}
2247

    
2248
/* mtfsb0 */
2249
static void gen_mtfsb0(DisasContext *ctx)
2250
{
2251
    uint8_t crb;
2252

    
2253
    if (unlikely(!ctx->fpu_enabled)) {
2254
        gen_exception(ctx, POWERPC_EXCP_FPU);
2255
        return;
2256
    }
2257
    crb = 31 - crbD(ctx->opcode);
2258
    gen_reset_fpstatus();
2259
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2260
        TCGv_i32 t0;
2261
        /* NIP cannot be restored if the memory exception comes from an helper */
2262
        gen_update_nip(ctx, ctx->nip - 4);
2263
        t0 = tcg_const_i32(crb);
2264
        gen_helper_fpscr_clrbit(t0);
2265
        tcg_temp_free_i32(t0);
2266
    }
2267
    if (unlikely(Rc(ctx->opcode) != 0)) {
2268
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2269
    }
2270
}
2271

    
2272
/* mtfsb1 */
2273
static void gen_mtfsb1(DisasContext *ctx)
2274
{
2275
    uint8_t crb;
2276

    
2277
    if (unlikely(!ctx->fpu_enabled)) {
2278
        gen_exception(ctx, POWERPC_EXCP_FPU);
2279
        return;
2280
    }
2281
    crb = 31 - crbD(ctx->opcode);
2282
    gen_reset_fpstatus();
2283
    /* XXX: we pretend we can only do IEEE floating-point computations */
2284
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2285
        TCGv_i32 t0;
2286
        /* NIP cannot be restored if the memory exception comes from an helper */
2287
        gen_update_nip(ctx, ctx->nip - 4);
2288
        t0 = tcg_const_i32(crb);
2289
        gen_helper_fpscr_setbit(t0);
2290
        tcg_temp_free_i32(t0);
2291
    }
2292
    if (unlikely(Rc(ctx->opcode) != 0)) {
2293
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2294
    }
2295
    /* We can raise a differed exception */
2296
    gen_helper_float_check_status();
2297
}
2298

    
2299
/* mtfsf */
2300
static void gen_mtfsf(DisasContext *ctx)
2301
{
2302
    TCGv_i32 t0;
2303
    int L = ctx->opcode & 0x02000000;
2304

    
2305
    if (unlikely(!ctx->fpu_enabled)) {
2306
        gen_exception(ctx, POWERPC_EXCP_FPU);
2307
        return;
2308
    }
2309
    /* NIP cannot be restored if the memory exception comes from an helper */
2310
    gen_update_nip(ctx, ctx->nip - 4);
2311
    gen_reset_fpstatus();
2312
    if (L)
2313
        t0 = tcg_const_i32(0xff);
2314
    else
2315
        t0 = tcg_const_i32(FM(ctx->opcode));
2316
    gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2317
    tcg_temp_free_i32(t0);
2318
    if (unlikely(Rc(ctx->opcode) != 0)) {
2319
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2320
    }
2321
    /* We can raise a differed exception */
2322
    gen_helper_float_check_status();
2323
}
2324

    
2325
/* mtfsfi */
2326
static void gen_mtfsfi(DisasContext *ctx)
2327
{
2328
    int bf, sh;
2329
    TCGv_i64 t0;
2330
    TCGv_i32 t1;
2331

    
2332
    if (unlikely(!ctx->fpu_enabled)) {
2333
        gen_exception(ctx, POWERPC_EXCP_FPU);
2334
        return;
2335
    }
2336
    bf = crbD(ctx->opcode) >> 2;
2337
    sh = 7 - bf;
2338
    /* NIP cannot be restored if the memory exception comes from an helper */
2339
    gen_update_nip(ctx, ctx->nip - 4);
2340
    gen_reset_fpstatus();
2341
    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2342
    t1 = tcg_const_i32(1 << sh);
2343
    gen_helper_store_fpscr(t0, t1);
2344
    tcg_temp_free_i64(t0);
2345
    tcg_temp_free_i32(t1);
2346
    if (unlikely(Rc(ctx->opcode) != 0)) {
2347
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2348
    }
2349
    /* We can raise a differed exception */
2350
    gen_helper_float_check_status();
2351
}
2352

    
2353
/***                           Addressing modes                            ***/
2354
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2355
static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2356
                                      target_long maskl)
2357
{
2358
    target_long simm = SIMM(ctx->opcode);
2359

    
2360
    simm &= ~maskl;
2361
    if (rA(ctx->opcode) == 0) {
2362
#if defined(TARGET_PPC64)
2363
        if (!ctx->sf_mode) {
2364
            tcg_gen_movi_tl(EA, (uint32_t)simm);
2365
        } else
2366
#endif
2367
        tcg_gen_movi_tl(EA, simm);
2368
    } else if (likely(simm != 0)) {
2369
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2370
#if defined(TARGET_PPC64)
2371
        if (!ctx->sf_mode) {
2372
            tcg_gen_ext32u_tl(EA, EA);
2373
        }
2374
#endif
2375
    } else {
2376
#if defined(TARGET_PPC64)
2377
        if (!ctx->sf_mode) {
2378
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2379
        } else
2380
#endif
2381
        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2382
    }
2383
}
2384

    
2385
static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2386
{
2387
    if (rA(ctx->opcode) == 0) {
2388
#if defined(TARGET_PPC64)
2389
        if (!ctx->sf_mode) {
2390
            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2391
        } else
2392
#endif
2393
        tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2394
    } else {
2395
        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2396
#if defined(TARGET_PPC64)
2397
        if (!ctx->sf_mode) {
2398
            tcg_gen_ext32u_tl(EA, EA);
2399
        }
2400
#endif
2401
    }
2402
}
2403

    
2404
static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2405
{
2406
    if (rA(ctx->opcode) == 0) {
2407
        tcg_gen_movi_tl(EA, 0);
2408
    } else {
2409
#if defined(TARGET_PPC64)
2410
        if (!ctx->sf_mode) {
2411
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2412
        } else
2413
#endif
2414
            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2415
    }
2416
}
2417

    
2418
static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2419
                                target_long val)
2420
{
2421
    tcg_gen_addi_tl(ret, arg1, val);
2422
#if defined(TARGET_PPC64)
2423
    if (!ctx->sf_mode) {
2424
        tcg_gen_ext32u_tl(ret, ret);
2425
    }
2426
#endif
2427
}
2428

    
2429
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2430
{
2431
    int l1 = gen_new_label();
2432
    TCGv t0 = tcg_temp_new();
2433
    TCGv_i32 t1, t2;
2434
    /* NIP cannot be restored if the memory exception comes from an helper */
2435
    gen_update_nip(ctx, ctx->nip - 4);
2436
    tcg_gen_andi_tl(t0, EA, mask);
2437
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2438
    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2439
    t2 = tcg_const_i32(0);
2440
    gen_helper_raise_exception_err(t1, t2);
2441
    tcg_temp_free_i32(t1);
2442
    tcg_temp_free_i32(t2);
2443
    gen_set_label(l1);
2444
    tcg_temp_free(t0);
2445
}
2446

    
2447
/***                             Integer load                              ***/
2448
static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449
{
2450
    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2451
}
2452

    
2453
static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2454
{
2455
    tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2456
}
2457

    
2458
static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2459
{
2460
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2461
    if (unlikely(ctx->le_mode)) {
2462
        tcg_gen_bswap16_tl(arg1, arg1);
2463
    }
2464
}
2465

    
2466
static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2467
{
2468
    if (unlikely(ctx->le_mode)) {
2469
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2470
        tcg_gen_bswap16_tl(arg1, arg1);
2471
        tcg_gen_ext16s_tl(arg1, arg1);
2472
    } else {
2473
        tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2474
    }
2475
}
2476

    
2477
static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2478
{
2479
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2480
    if (unlikely(ctx->le_mode)) {
2481
        tcg_gen_bswap32_tl(arg1, arg1);
2482
    }
2483
}
2484

    
2485
#if defined(TARGET_PPC64)
2486
static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2487
{
2488
    if (unlikely(ctx->le_mode)) {
2489
        tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2490
        tcg_gen_bswap32_tl(arg1, arg1);
2491
        tcg_gen_ext32s_tl(arg1, arg1);
2492
    } else
2493
        tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2494
}
2495
#endif
2496

    
2497
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2498
{
2499
    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2500
    if (unlikely(ctx->le_mode)) {
2501
        tcg_gen_bswap64_i64(arg1, arg1);
2502
    }
2503
}
2504

    
2505
static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2506
{
2507
    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2508
}
2509

    
2510
static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2511
{
2512
    if (unlikely(ctx->le_mode)) {
2513
        TCGv t0 = tcg_temp_new();
2514
        tcg_gen_ext16u_tl(t0, arg1);
2515
        tcg_gen_bswap16_tl(t0, t0);
2516
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2517
        tcg_temp_free(t0);
2518
    } else {
2519
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2520
    }
2521
}
2522

    
2523
static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2524
{
2525
    if (unlikely(ctx->le_mode)) {
2526
        TCGv t0 = tcg_temp_new();
2527
        tcg_gen_ext32u_tl(t0, arg1);
2528
        tcg_gen_bswap32_tl(t0, t0);
2529
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2530
        tcg_temp_free(t0);
2531
    } else {
2532
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2533
    }
2534
}
2535

    
2536
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2537
{
2538
    if (unlikely(ctx->le_mode)) {
2539
        TCGv_i64 t0 = tcg_temp_new_i64();
2540
        tcg_gen_bswap64_i64(t0, arg1);
2541
        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2542
        tcg_temp_free_i64(t0);
2543
    } else
2544
        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2545
}
2546

    
2547
#define GEN_LD(name, ldop, opc, type)                                         \
2548
static void glue(gen_, name)(DisasContext *ctx)                                       \
2549
{                                                                             \
2550
    TCGv EA;                                                                  \
2551
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2552
    EA = tcg_temp_new();                                                      \
2553
    gen_addr_imm_index(ctx, EA, 0);                                           \
2554
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2555
    tcg_temp_free(EA);                                                        \
2556
}
2557

    
2558
#define GEN_LDU(name, ldop, opc, type)                                        \
2559
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
2560
{                                                                             \
2561
    TCGv EA;                                                                  \
2562
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2563
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2564
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2565
        return;                                                               \
2566
    }                                                                         \
2567
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2568
    EA = tcg_temp_new();                                                      \
2569
    if (type == PPC_64B)                                                      \
2570
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2571
    else                                                                      \
2572
        gen_addr_imm_index(ctx, EA, 0);                                       \
2573
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2574
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2575
    tcg_temp_free(EA);                                                        \
2576
}
2577

    
2578
#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2579
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2580
{                                                                             \
2581
    TCGv EA;                                                                  \
2582
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2583
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2584
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2585
        return;                                                               \
2586
    }                                                                         \
2587
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2588
    EA = tcg_temp_new();                                                      \
2589
    gen_addr_reg_index(ctx, EA);                                              \
2590
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2591
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2592
    tcg_temp_free(EA);                                                        \
2593
}
2594

    
2595
#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2596
static void glue(gen_, name##x)(DisasContext *ctx)                            \
2597
{                                                                             \
2598
    TCGv EA;                                                                  \
2599
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2600
    EA = tcg_temp_new();                                                      \
2601
    gen_addr_reg_index(ctx, EA);                                              \
2602
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2603
    tcg_temp_free(EA);                                                        \
2604
}
2605

    
2606
#define GEN_LDS(name, ldop, op, type)                                         \
2607
GEN_LD(name, ldop, op | 0x20, type);                                          \
2608
GEN_LDU(name, ldop, op | 0x21, type);                                         \
2609
GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2610
GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2611

    
2612
/* lbz lbzu lbzux lbzx */
2613
GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2614
/* lha lhau lhaux lhax */
2615
GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2616
/* lhz lhzu lhzux lhzx */
2617
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2618
/* lwz lwzu lwzux lwzx */
2619
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2620
#if defined(TARGET_PPC64)
2621
/* lwaux */
2622
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2623
/* lwax */
2624
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2625
/* ldux */
2626
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2627
/* ldx */
2628
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2629

    
2630
static void gen_ld(DisasContext *ctx)
2631
{
2632
    TCGv EA;
2633
    if (Rc(ctx->opcode)) {
2634
        if (unlikely(rA(ctx->opcode) == 0 ||
2635
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2636
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2637
            return;
2638
        }
2639
    }
2640
    gen_set_access_type(ctx, ACCESS_INT);
2641
    EA = tcg_temp_new();
2642
    gen_addr_imm_index(ctx, EA, 0x03);
2643
    if (ctx->opcode & 0x02) {
2644
        /* lwa (lwau is undefined) */
2645
        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2646
    } else {
2647
        /* ld - ldu */
2648
        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2649
    }
2650
    if (Rc(ctx->opcode))
2651
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2652
    tcg_temp_free(EA);
2653
}
2654

    
2655
/* lq */
2656
static void gen_lq(DisasContext *ctx)
2657
{
2658
#if defined(CONFIG_USER_ONLY)
2659
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2660
#else
2661
    int ra, rd;
2662
    TCGv EA;
2663

    
2664
    /* Restore CPU state */
2665
    if (unlikely(ctx->mem_idx == 0)) {
2666
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2667
        return;
2668
    }
2669
    ra = rA(ctx->opcode);
2670
    rd = rD(ctx->opcode);
2671
    if (unlikely((rd & 1) || rd == ra)) {
2672
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2673
        return;
2674
    }
2675
    if (unlikely(ctx->le_mode)) {
2676
        /* Little-endian mode is not handled */
2677
        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2678
        return;
2679
    }
2680
    gen_set_access_type(ctx, ACCESS_INT);
2681
    EA = tcg_temp_new();
2682
    gen_addr_imm_index(ctx, EA, 0x0F);
2683
    gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2684
    gen_addr_add(ctx, EA, EA, 8);
2685
    gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2686
    tcg_temp_free(EA);
2687
#endif
2688
}
2689
#endif
2690

    
2691
/***                              Integer store                            ***/
2692
#define GEN_ST(name, stop, opc, type)                                         \
2693
static void glue(gen_, name)(DisasContext *ctx)                                       \
2694
{                                                                             \
2695
    TCGv EA;                                                                  \
2696
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2697
    EA = tcg_temp_new();                                                      \
2698
    gen_addr_imm_index(ctx, EA, 0);                                           \
2699
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2700
    tcg_temp_free(EA);                                                        \
2701
}
2702

    
2703
#define GEN_STU(name, stop, opc, type)                                        \
2704
static void glue(gen_, stop##u)(DisasContext *ctx)                                    \
2705
{                                                                             \
2706
    TCGv EA;                                                                  \
2707
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2708
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2709
        return;                                                               \
2710
    }                                                                         \
2711
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2712
    EA = tcg_temp_new();                                                      \
2713
    if (type == PPC_64B)                                                      \
2714
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2715
    else                                                                      \
2716
        gen_addr_imm_index(ctx, EA, 0);                                       \
2717
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2718
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2719
    tcg_temp_free(EA);                                                        \
2720
}
2721

    
2722
#define GEN_STUX(name, stop, opc2, opc3, type)                                \
2723
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2724
{                                                                             \
2725
    TCGv EA;                                                                  \
2726
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2727
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2728
        return;                                                               \
2729
    }                                                                         \
2730
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2731
    EA = tcg_temp_new();                                                      \
2732
    gen_addr_reg_index(ctx, EA);                                              \
2733
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2734
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2735
    tcg_temp_free(EA);                                                        \
2736
}
2737

    
2738
#define GEN_STX(name, stop, opc2, opc3, type)                                 \
2739
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
2740
{                                                                             \
2741
    TCGv EA;                                                                  \
2742
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2743
    EA = tcg_temp_new();                                                      \
2744
    gen_addr_reg_index(ctx, EA);                                              \
2745
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2746
    tcg_temp_free(EA);                                                        \
2747
}
2748

    
2749
#define GEN_STS(name, stop, op, type)                                         \
2750
GEN_ST(name, stop, op | 0x20, type);                                          \
2751
GEN_STU(name, stop, op | 0x21, type);                                         \
2752
GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
2753
GEN_STX(name, stop, 0x17, op | 0x00, type)
2754

    
2755
/* stb stbu stbux stbx */
2756
GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2757
/* sth sthu sthux sthx */
2758
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2759
/* stw stwu stwux stwx */
2760
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2761
#if defined(TARGET_PPC64)
2762
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2763
GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2764

    
2765
static void gen_std(DisasContext *ctx)
2766
{
2767
    int rs;
2768
    TCGv EA;
2769

    
2770
    rs = rS(ctx->opcode);
2771
    if ((ctx->opcode & 0x3) == 0x2) {
2772
#if defined(CONFIG_USER_ONLY)
2773
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2774
#else
2775
        /* stq */
2776
        if (unlikely(ctx->mem_idx == 0)) {
2777
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2778
            return;
2779
        }
2780
        if (unlikely(rs & 1)) {
2781
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2782
            return;
2783
        }
2784
        if (unlikely(ctx->le_mode)) {
2785
            /* Little-endian mode is not handled */
2786
            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2787
            return;
2788
        }
2789
        gen_set_access_type(ctx, ACCESS_INT);
2790
        EA = tcg_temp_new();
2791
        gen_addr_imm_index(ctx, EA, 0x03);
2792
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2793
        gen_addr_add(ctx, EA, EA, 8);
2794
        gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2795
        tcg_temp_free(EA);
2796
#endif
2797
    } else {
2798
        /* std / stdu */
2799
        if (Rc(ctx->opcode)) {
2800
            if (unlikely(rA(ctx->opcode) == 0)) {
2801
                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2802
                return;
2803
            }
2804
        }
2805
        gen_set_access_type(ctx, ACCESS_INT);
2806
        EA = tcg_temp_new();
2807
        gen_addr_imm_index(ctx, EA, 0x03);
2808
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2809
        if (Rc(ctx->opcode))
2810
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2811
        tcg_temp_free(EA);
2812
    }
2813
}
2814
#endif
2815
/***                Integer load and store with byte reverse               ***/
2816
/* lhbrx */
2817
static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2818
{
2819
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2820
    if (likely(!ctx->le_mode)) {
2821
        tcg_gen_bswap16_tl(arg1, arg1);
2822
    }
2823
}
2824
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2825

    
2826
/* lwbrx */
2827
static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2828
{
2829
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2830
    if (likely(!ctx->le_mode)) {
2831
        tcg_gen_bswap32_tl(arg1, arg1);
2832
    }
2833
}
2834
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2835

    
2836
/* sthbrx */
2837
static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838
{
2839
    if (likely(!ctx->le_mode)) {
2840
        TCGv t0 = tcg_temp_new();
2841
        tcg_gen_ext16u_tl(t0, arg1);
2842
        tcg_gen_bswap16_tl(t0, t0);
2843
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2844
        tcg_temp_free(t0);
2845
    } else {
2846
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2847
    }
2848
}
2849
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2850

    
2851
/* stwbrx */
2852
static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2853
{
2854
    if (likely(!ctx->le_mode)) {
2855
        TCGv t0 = tcg_temp_new();
2856
        tcg_gen_ext32u_tl(t0, arg1);
2857
        tcg_gen_bswap32_tl(t0, t0);
2858
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2859
        tcg_temp_free(t0);
2860
    } else {
2861
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2862
    }
2863
}
2864
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2865

    
2866
/***                    Integer load and store multiple                    ***/
2867

    
2868
/* lmw */
2869
static void gen_lmw(DisasContext *ctx)
2870
{
2871
    TCGv t0;
2872
    TCGv_i32 t1;
2873
    gen_set_access_type(ctx, ACCESS_INT);
2874
    /* NIP cannot be restored if the memory exception comes from an helper */
2875
    gen_update_nip(ctx, ctx->nip - 4);
2876
    t0 = tcg_temp_new();
2877
    t1 = tcg_const_i32(rD(ctx->opcode));
2878
    gen_addr_imm_index(ctx, t0, 0);
2879
    gen_helper_lmw(t0, t1);
2880
    tcg_temp_free(t0);
2881
    tcg_temp_free_i32(t1);
2882
}
2883

    
2884
/* stmw */
2885
static void gen_stmw(DisasContext *ctx)
2886
{
2887
    TCGv t0;
2888
    TCGv_i32 t1;
2889
    gen_set_access_type(ctx, ACCESS_INT);
2890
    /* NIP cannot be restored if the memory exception comes from an helper */
2891
    gen_update_nip(ctx, ctx->nip - 4);
2892
    t0 = tcg_temp_new();
2893
    t1 = tcg_const_i32(rS(ctx->opcode));
2894
    gen_addr_imm_index(ctx, t0, 0);
2895
    gen_helper_stmw(t0, t1);
2896
    tcg_temp_free(t0);
2897
    tcg_temp_free_i32(t1);
2898
}
2899

    
2900
/***                    Integer load and store strings                     ***/
2901

    
2902
/* lswi */
2903
/* PowerPC32 specification says we must generate an exception if
2904
 * rA is in the range of registers to be loaded.
2905
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2906
 * For now, I'll follow the spec...
2907
 */
2908
static void gen_lswi(DisasContext *ctx)
2909
{
2910
    TCGv t0;
2911
    TCGv_i32 t1, t2;
2912
    int nb = NB(ctx->opcode);
2913
    int start = rD(ctx->opcode);
2914
    int ra = rA(ctx->opcode);
2915
    int nr;
2916

    
2917
    if (nb == 0)
2918
        nb = 32;
2919
    nr = nb / 4;
2920
    if (unlikely(((start + nr) > 32  &&
2921
                  start <= ra && (start + nr - 32) > ra) ||
2922
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2923
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2924
        return;
2925
    }
2926
    gen_set_access_type(ctx, ACCESS_INT);
2927
    /* NIP cannot be restored if the memory exception comes from an helper */
2928
    gen_update_nip(ctx, ctx->nip - 4);
2929
    t0 = tcg_temp_new();
2930
    gen_addr_register(ctx, t0);
2931
    t1 = tcg_const_i32(nb);
2932
    t2 = tcg_const_i32(start);
2933
    gen_helper_lsw(t0, t1, t2);
2934
    tcg_temp_free(t0);
2935
    tcg_temp_free_i32(t1);
2936
    tcg_temp_free_i32(t2);
2937
}
2938

    
2939
/* lswx */
2940
static void gen_lswx(DisasContext *ctx)
2941
{
2942
    TCGv t0;
2943
    TCGv_i32 t1, t2, t3;
2944
    gen_set_access_type(ctx, ACCESS_INT);
2945
    /* NIP cannot be restored if the memory exception comes from an helper */
2946
    gen_update_nip(ctx, ctx->nip - 4);
2947
    t0 = tcg_temp_new();
2948
    gen_addr_reg_index(ctx, t0);
2949
    t1 = tcg_const_i32(rD(ctx->opcode));
2950
    t2 = tcg_const_i32(rA(ctx->opcode));
2951
    t3 = tcg_const_i32(rB(ctx->opcode));
2952
    gen_helper_lswx(t0, t1, t2, t3);
2953
    tcg_temp_free(t0);
2954
    tcg_temp_free_i32(t1);
2955
    tcg_temp_free_i32(t2);
2956
    tcg_temp_free_i32(t3);
2957
}
2958

    
2959
/* stswi */
2960
static void gen_stswi(DisasContext *ctx)
2961
{
2962
    TCGv t0;
2963
    TCGv_i32 t1, t2;
2964
    int nb = NB(ctx->opcode);
2965
    gen_set_access_type(ctx, ACCESS_INT);
2966
    /* NIP cannot be restored if the memory exception comes from an helper */
2967
    gen_update_nip(ctx, ctx->nip - 4);
2968
    t0 = tcg_temp_new();
2969
    gen_addr_register(ctx, t0);
2970
    if (nb == 0)
2971
        nb = 32;
2972
    t1 = tcg_const_i32(nb);
2973
    t2 = tcg_const_i32(rS(ctx->opcode));
2974
    gen_helper_stsw(t0, t1, t2);
2975
    tcg_temp_free(t0);
2976
    tcg_temp_free_i32(t1);
2977
    tcg_temp_free_i32(t2);
2978
}
2979

    
2980
/* stswx */
2981
static void gen_stswx(DisasContext *ctx)
2982
{
2983
    TCGv t0;
2984
    TCGv_i32 t1, t2;
2985
    gen_set_access_type(ctx, ACCESS_INT);
2986
    /* NIP cannot be restored if the memory exception comes from an helper */
2987
    gen_update_nip(ctx, ctx->nip - 4);
2988
    t0 = tcg_temp_new();
2989
    gen_addr_reg_index(ctx, t0);
2990
    t1 = tcg_temp_new_i32();
2991
    tcg_gen_trunc_tl_i32(t1, cpu_xer);
2992
    tcg_gen_andi_i32(t1, t1, 0x7F);
2993
    t2 = tcg_const_i32(rS(ctx->opcode));
2994
    gen_helper_stsw(t0, t1, t2);
2995
    tcg_temp_free(t0);
2996
    tcg_temp_free_i32(t1);
2997
    tcg_temp_free_i32(t2);
2998
}
2999

    
3000
/***                        Memory synchronisation                         ***/
3001
/* eieio */
3002
static void gen_eieio(DisasContext *ctx)
3003
{
3004
}
3005

    
3006
/* isync */
3007
static void gen_isync(DisasContext *ctx)
3008
{
3009
    gen_stop_exception(ctx);
3010
}
3011

    
3012
/* lwarx */
3013
static void gen_lwarx(DisasContext *ctx)
3014
{
3015
    TCGv t0;
3016
    TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3017
    gen_set_access_type(ctx, ACCESS_RES);
3018
    t0 = tcg_temp_local_new();
3019
    gen_addr_reg_index(ctx, t0);
3020
    gen_check_align(ctx, t0, 0x03);
3021
    gen_qemu_ld32u(ctx, gpr, t0);
3022
    tcg_gen_mov_tl(cpu_reserve, t0);
3023
    tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3024
    tcg_temp_free(t0);
3025
}
3026

    
3027
#if defined(CONFIG_USER_ONLY)
3028
static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3029
                                   int reg, int size)
3030
{
3031
    TCGv t0 = tcg_temp_new();
3032
    uint32_t save_exception = ctx->exception;
3033

    
3034
    tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3035
    tcg_gen_movi_tl(t0, (size << 5) | reg);
3036
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3037
    tcg_temp_free(t0);
3038
    gen_update_nip(ctx, ctx->nip-4);
3039
    ctx->exception = POWERPC_EXCP_BRANCH;
3040
    gen_exception(ctx, POWERPC_EXCP_STCX);
3041
    ctx->exception = save_exception;
3042
}
3043
#endif
3044

    
3045
/* stwcx. */
3046
static void gen_stwcx_(DisasContext *ctx)
3047
{
3048
    TCGv t0;
3049
    gen_set_access_type(ctx, ACCESS_RES);
3050
    t0 = tcg_temp_local_new();
3051
    gen_addr_reg_index(ctx, t0);
3052
    gen_check_align(ctx, t0, 0x03);
3053
#if defined(CONFIG_USER_ONLY)
3054
    gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3055
#else
3056
    {
3057
        int l1;
3058

    
3059
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3060
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3061
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3062
        l1 = gen_new_label();
3063
        tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3064
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3065
        gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3066
        gen_set_label(l1);
3067
        tcg_gen_movi_tl(cpu_reserve, -1);
3068
    }
3069
#endif
3070
    tcg_temp_free(t0);
3071
}
3072

    
3073
#if defined(TARGET_PPC64)
3074
/* ldarx */
3075
static void gen_ldarx(DisasContext *ctx)
3076
{
3077
    TCGv t0;
3078
    TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3079
    gen_set_access_type(ctx, ACCESS_RES);
3080
    t0 = tcg_temp_local_new();
3081
    gen_addr_reg_index(ctx, t0);
3082
    gen_check_align(ctx, t0, 0x07);
3083
    gen_qemu_ld64(ctx, gpr, t0);
3084
    tcg_gen_mov_tl(cpu_reserve, t0);
3085
    tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3086
    tcg_temp_free(t0);
3087
}
3088

    
3089
/* stdcx. */
3090
static void gen_stdcx_(DisasContext *ctx)
3091
{
3092
    TCGv t0;
3093
    gen_set_access_type(ctx, ACCESS_RES);
3094
    t0 = tcg_temp_local_new();
3095
    gen_addr_reg_index(ctx, t0);
3096
    gen_check_align(ctx, t0, 0x07);
3097
#if defined(CONFIG_USER_ONLY)
3098
    gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3099
#else
3100
    {
3101
        int l1;
3102
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3103
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3104
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3105
        l1 = gen_new_label();
3106
        tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3107
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3108
        gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3109
        gen_set_label(l1);
3110
        tcg_gen_movi_tl(cpu_reserve, -1);
3111
    }
3112
#endif
3113
    tcg_temp_free(t0);
3114
}
3115
#endif /* defined(TARGET_PPC64) */
3116

    
3117
/* sync */
3118
static void gen_sync(DisasContext *ctx)
3119
{
3120
}
3121

    
3122
/* wait */
3123
static void gen_wait(DisasContext *ctx)
3124
{
3125
    TCGv_i32 t0 = tcg_temp_new_i32();
3126
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3127
    tcg_temp_free_i32(t0);
3128
    /* Stop translation, as the CPU is supposed to sleep from now */
3129
    gen_exception_err(ctx, EXCP_HLT, 1);
3130
}
3131

    
3132
/***                         Floating-point load                           ***/
3133
#define GEN_LDF(name, ldop, opc, type)                                        \
3134
static void glue(gen_, name)(DisasContext *ctx)                                       \
3135
{                                                                             \
3136
    TCGv EA;                                                                  \
3137
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3138
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3139
        return;                                                               \
3140
    }                                                                         \
3141
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3142
    EA = tcg_temp_new();                                                      \
3143
    gen_addr_imm_index(ctx, EA, 0);                                           \
3144
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3145
    tcg_temp_free(EA);                                                        \
3146
}
3147

    
3148
#define GEN_LDUF(name, ldop, opc, type)                                       \
3149
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3150
{                                                                             \
3151
    TCGv EA;                                                                  \
3152
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3153
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3154
        return;                                                               \
3155
    }                                                                         \
3156
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3157
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3158
        return;                                                               \
3159
    }                                                                         \
3160
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3161
    EA = tcg_temp_new();                                                      \
3162
    gen_addr_imm_index(ctx, EA, 0);                                           \
3163
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3164
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3165
    tcg_temp_free(EA);                                                        \
3166
}
3167

    
3168
#define GEN_LDUXF(name, ldop, opc, type)                                      \
3169
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3170
{                                                                             \
3171
    TCGv EA;                                                                  \
3172
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3173
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3174
        return;                                                               \
3175
    }                                                                         \
3176
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3177
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3178
        return;                                                               \
3179
    }                                                                         \
3180
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3181
    EA = tcg_temp_new();                                                      \
3182
    gen_addr_reg_index(ctx, EA);                                              \
3183
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3184
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3185
    tcg_temp_free(EA);                                                        \
3186
}
3187

    
3188
#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
3189
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3190
{                                                                             \
3191
    TCGv EA;                                                                  \
3192
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3193
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3194
        return;                                                               \
3195
    }                                                                         \
3196
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3197
    EA = tcg_temp_new();                                                      \
3198
    gen_addr_reg_index(ctx, EA);                                              \
3199
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3200
    tcg_temp_free(EA);                                                        \
3201
}
3202

    
3203
#define GEN_LDFS(name, ldop, op, type)                                        \
3204
GEN_LDF(name, ldop, op | 0x20, type);                                         \
3205
GEN_LDUF(name, ldop, op | 0x21, type);                                        \
3206
GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
3207
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3208

    
3209
static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3210
{
3211
    TCGv t0 = tcg_temp_new();
3212
    TCGv_i32 t1 = tcg_temp_new_i32();
3213
    gen_qemu_ld32u(ctx, t0, arg2);
3214
    tcg_gen_trunc_tl_i32(t1, t0);
3215
    tcg_temp_free(t0);
3216
    gen_helper_float32_to_float64(arg1, t1);
3217
    tcg_temp_free_i32(t1);
3218
}
3219

    
3220
 /* lfd lfdu lfdux lfdx */
3221
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3222
 /* lfs lfsu lfsux lfsx */
3223
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3224

    
3225
/***                         Floating-point store                          ***/
3226
#define GEN_STF(name, stop, opc, type)                                        \
3227
static void glue(gen_, name)(DisasContext *ctx)                                       \
3228
{                                                                             \
3229
    TCGv EA;                                                                  \
3230
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3231
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3232
        return;                                                               \
3233
    }                                                                         \
3234
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3235
    EA = tcg_temp_new();                                                      \
3236
    gen_addr_imm_index(ctx, EA, 0);                                           \
3237
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3238
    tcg_temp_free(EA);                                                        \
3239
}
3240

    
3241
#define GEN_STUF(name, stop, opc, type)                                       \
3242
static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3243
{                                                                             \
3244
    TCGv EA;                                                                  \
3245
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3246
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3247
        return;                                                               \
3248
    }                                                                         \
3249
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3250
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3251
        return;                                                               \
3252
    }                                                                         \
3253
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3254
    EA = tcg_temp_new();                                                      \
3255
    gen_addr_imm_index(ctx, EA, 0);                                           \
3256
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3257
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3258
    tcg_temp_free(EA);                                                        \
3259
}
3260

    
3261
#define GEN_STUXF(name, stop, opc, type)                                      \
3262
static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3263
{                                                                             \
3264
    TCGv EA;                                                                  \
3265
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3266
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3267
        return;                                                               \
3268
    }                                                                         \
3269
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3270
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3271
        return;                                                               \
3272
    }                                                                         \
3273
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3274
    EA = tcg_temp_new();                                                      \
3275
    gen_addr_reg_index(ctx, EA);                                              \
3276
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3277
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3278
    tcg_temp_free(EA);                                                        \
3279
}
3280

    
3281
#define GEN_STXF(name, stop, opc2, opc3, type)                                \
3282
static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3283
{                                                                             \
3284
    TCGv EA;                                                                  \
3285
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3286
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3287
        return;                                                               \
3288
    }                                                                         \
3289
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3290
    EA = tcg_temp_new();                                                      \
3291
    gen_addr_reg_index(ctx, EA);                                              \
3292
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3293
    tcg_temp_free(EA);                                                        \
3294
}
3295

    
3296
#define GEN_STFS(name, stop, op, type)                                        \
3297
GEN_STF(name, stop, op | 0x20, type);                                         \
3298
GEN_STUF(name, stop, op | 0x21, type);                                        \
3299
GEN_STUXF(name, stop, op | 0x01, type);                                       \
3300
GEN_STXF(name, stop, 0x17, op | 0x00, type)
3301

    
3302
static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3303
{
3304
    TCGv_i32 t0 = tcg_temp_new_i32();
3305
    TCGv t1 = tcg_temp_new();
3306
    gen_helper_float64_to_float32(t0, arg1);
3307
    tcg_gen_extu_i32_tl(t1, t0);
3308
    tcg_temp_free_i32(t0);
3309
    gen_qemu_st32(ctx, t1, arg2);
3310
    tcg_temp_free(t1);
3311
}
3312

    
3313
/* stfd stfdu stfdux stfdx */
3314
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3315
/* stfs stfsu stfsux stfsx */
3316
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3317

    
3318
/* Optional: */
3319
static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3320
{
3321
    TCGv t0 = tcg_temp_new();
3322
    tcg_gen_trunc_i64_tl(t0, arg1),
3323
    gen_qemu_st32(ctx, t0, arg2);
3324
    tcg_temp_free(t0);
3325
}
3326
/* stfiwx */
3327
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3328

    
3329
/***                                Branch                                 ***/
3330
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3331
{
3332
    TranslationBlock *tb;
3333
    tb = ctx->tb;
3334
#if defined(TARGET_PPC64)
3335
    if (!ctx->sf_mode)
3336
        dest = (uint32_t) dest;
3337
#endif
3338
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3339
        likely(!ctx->singlestep_enabled)) {
3340
        tcg_gen_goto_tb(n);
3341
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3342
        tcg_gen_exit_tb((long)tb + n);
3343
    } else {
3344
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3345
        if (unlikely(ctx->singlestep_enabled)) {
3346
            if ((ctx->singlestep_enabled &
3347
                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3348
                ctx->exception == POWERPC_EXCP_BRANCH) {
3349
                target_ulong tmp = ctx->nip;
3350
                ctx->nip = dest;
3351
                gen_exception(ctx, POWERPC_EXCP_TRACE);
3352
                ctx->nip = tmp;
3353
            }
3354
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3355
                gen_debug_exception(ctx);
3356
            }
3357
        }
3358
        tcg_gen_exit_tb(0);
3359
    }
3360
}
3361

    
3362
static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3363
{
3364
#if defined(TARGET_PPC64)
3365
    if (ctx->sf_mode == 0)
3366
        tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3367
    else
3368
#endif
3369
        tcg_gen_movi_tl(cpu_lr, nip);
3370
}
3371

    
3372
/* b ba bl bla */
3373
static void gen_b(DisasContext *ctx)
3374
{
3375
    target_ulong li, target;
3376

    
3377
    ctx->exception = POWERPC_EXCP_BRANCH;
3378
    /* sign extend LI */
3379
#if defined(TARGET_PPC64)
3380
    if (ctx->sf_mode)
3381
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3382
    else
3383
#endif
3384
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3385
    if (likely(AA(ctx->opcode) == 0))
3386
        target = ctx->nip + li - 4;
3387
    else
3388
        target = li;
3389
    if (LK(ctx->opcode))
3390
        gen_setlr(ctx, ctx->nip);
3391
    gen_goto_tb(ctx, 0, target);
3392
}
3393

    
3394
#define BCOND_IM  0
3395
#define BCOND_LR  1
3396
#define BCOND_CTR 2
3397

    
3398
static inline void gen_bcond(DisasContext *ctx, int type)
3399
{
3400
    uint32_t bo = BO(ctx->opcode);
3401
    int l1;
3402
    TCGv target;
3403

    
3404
    ctx->exception = POWERPC_EXCP_BRANCH;
3405
    if (type == BCOND_LR || type == BCOND_CTR) {
3406
        target = tcg_temp_local_new();
3407
        if (type == BCOND_CTR)
3408
            tcg_gen_mov_tl(target, cpu_ctr);
3409
        else
3410
            tcg_gen_mov_tl(target, cpu_lr);
3411
    } else {
3412
        TCGV_UNUSED(target);
3413
    }
3414
    if (LK(ctx->opcode))
3415
        gen_setlr(ctx, ctx->nip);
3416
    l1 = gen_new_label();
3417
    if ((bo & 0x4) == 0) {
3418
        /* Decrement and test CTR */
3419
        TCGv temp = tcg_temp_new();
3420
        if (unlikely(type == BCOND_CTR)) {
3421
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3422
            return;
3423
        }
3424
        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3425
#if defined(TARGET_PPC64)
3426
        if (!ctx->sf_mode)
3427
            tcg_gen_ext32u_tl(temp, cpu_ctr);
3428
        else
3429
#endif
3430
            tcg_gen_mov_tl(temp, cpu_ctr);
3431
        if (bo & 0x2) {
3432
            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3433
        } else {
3434
            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3435
        }
3436
        tcg_temp_free(temp);
3437
    }
3438
    if ((bo & 0x10) == 0) {
3439
        /* Test CR */
3440
        uint32_t bi = BI(ctx->opcode);
3441
        uint32_t mask = 1 << (3 - (bi & 0x03));
3442
        TCGv_i32 temp = tcg_temp_new_i32();
3443

    
3444
        if (bo & 0x8) {
3445
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3446
            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3447
        } else {
3448
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3449
            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3450
        }
3451
        tcg_temp_free_i32(temp);
3452
    }
3453
    if (type == BCOND_IM) {
3454
        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3455
        if (likely(AA(ctx->opcode) == 0)) {
3456
            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3457
        } else {
3458
            gen_goto_tb(ctx, 0, li);
3459
        }
3460
        gen_set_label(l1);
3461
        gen_goto_tb(ctx, 1, ctx->nip);
3462
    } else {
3463
#if defined(TARGET_PPC64)
3464
        if (!(ctx->sf_mode))
3465
            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3466
        else
3467
#endif
3468
            tcg_gen_andi_tl(cpu_nip, target, ~3);
3469
        tcg_gen_exit_tb(0);
3470
        gen_set_label(l1);
3471
#if defined(TARGET_PPC64)
3472
        if (!(ctx->sf_mode))
3473
            tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3474
        else
3475
#endif
3476
            tcg_gen_movi_tl(cpu_nip, ctx->nip);
3477
        tcg_gen_exit_tb(0);
3478
    }
3479
}
3480

    
3481
static void gen_bc(DisasContext *ctx)
3482
{
3483
    gen_bcond(ctx, BCOND_IM);
3484
}
3485

    
3486
static void gen_bcctr(DisasContext *ctx)
3487
{
3488
    gen_bcond(ctx, BCOND_CTR);
3489
}
3490

    
3491
static void gen_bclr(DisasContext *ctx)
3492
{
3493
    gen_bcond(ctx, BCOND_LR);
3494
}
3495

    
3496
/***                      Condition register logical                       ***/
3497
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3498
static void glue(gen_, name)(DisasContext *ctx)                                       \
3499
{                                                                             \
3500
    uint8_t bitmask;                                                          \
3501
    int sh;                                                                   \
3502
    TCGv_i32 t0, t1;                                                          \
3503
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3504
    t0 = tcg_temp_new_i32();                                                  \
3505
    if (sh > 0)                                                               \
3506
        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3507
    else if (sh < 0)                                                          \
3508
        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3509
    else                                                                      \
3510
        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
3511
    t1 = tcg_temp_new_i32();                                                  \
3512
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3513
    if (sh > 0)                                                               \
3514
        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3515
    else if (sh < 0)                                                          \
3516
        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3517
    else                                                                      \
3518
        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
3519
    tcg_op(t0, t0, t1);                                                       \
3520
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3521
    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
3522
    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
3523
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
3524
    tcg_temp_free_i32(t0);                                                    \
3525
    tcg_temp_free_i32(t1);                                                    \
3526
}
3527

    
3528
/* crand */
3529
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3530
/* crandc */
3531
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3532
/* creqv */
3533
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3534
/* crnand */
3535
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3536
/* crnor */
3537
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3538
/* cror */
3539
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3540
/* crorc */
3541
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3542
/* crxor */
3543
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3544

    
3545
/* mcrf */
3546
static void gen_mcrf(DisasContext *ctx)
3547
{
3548
    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3549
}
3550

    
3551
/***                           System linkage                              ***/
3552

    
3553
/* rfi (mem_idx only) */
3554
static void gen_rfi(DisasContext *ctx)
3555
{
3556
#if defined(CONFIG_USER_ONLY)
3557
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3558
#else
3559
    /* Restore CPU state */
3560
    if (unlikely(!ctx->mem_idx)) {
3561
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3562
        return;
3563
    }
3564
    gen_helper_rfi();
3565
    gen_sync_exception(ctx);
3566
#endif
3567
}
3568

    
3569
#if defined(TARGET_PPC64)
3570
static void gen_rfid(DisasContext *ctx)
3571
{
3572
#if defined(CONFIG_USER_ONLY)
3573
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3574
#else
3575
    /* Restore CPU state */
3576
    if (unlikely(!ctx->mem_idx)) {
3577
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3578
        return;
3579
    }
3580
    gen_helper_rfid();
3581
    gen_sync_exception(ctx);
3582
#endif
3583
}
3584

    
3585
static void gen_hrfid(DisasContext *ctx)
3586
{
3587
#if defined(CONFIG_USER_ONLY)
3588
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3589
#else
3590
    /* Restore CPU state */
3591
    if (unlikely(ctx->mem_idx <= 1)) {
3592
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3593
        return;
3594
    }
3595
    gen_helper_hrfid();
3596
    gen_sync_exception(ctx);
3597
#endif
3598
}
3599
#endif
3600

    
3601
/* sc */
3602
#if defined(CONFIG_USER_ONLY)
3603
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3604
#else
3605
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3606
#endif
3607
static void gen_sc(DisasContext *ctx)
3608
{
3609
    uint32_t lev;
3610

    
3611
    lev = (ctx->opcode >> 5) & 0x7F;
3612
    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3613
}
3614

    
3615
/***                                Trap                                   ***/
3616

    
3617
/* tw */
3618
static void gen_tw(DisasContext *ctx)
3619
{
3620
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3621
    /* Update the nip since this might generate a trap exception */
3622
    gen_update_nip(ctx, ctx->nip);
3623
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3624
    tcg_temp_free_i32(t0);
3625
}
3626

    
3627
/* twi */
3628
static void gen_twi(DisasContext *ctx)
3629
{
3630
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3631
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3632
    /* Update the nip since this might generate a trap exception */
3633
    gen_update_nip(ctx, ctx->nip);
3634
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3635
    tcg_temp_free(t0);
3636
    tcg_temp_free_i32(t1);
3637
}
3638

    
3639
#if defined(TARGET_PPC64)
3640
/* td */
3641
static void gen_td(DisasContext *ctx)
3642
{
3643
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3644
    /* Update the nip since this might generate a trap exception */
3645
    gen_update_nip(ctx, ctx->nip);
3646
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3647
    tcg_temp_free_i32(t0);
3648
}
3649

    
3650
/* tdi */
3651
static void gen_tdi(DisasContext *ctx)
3652
{
3653
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3654
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3655
    /* Update the nip since this might generate a trap exception */
3656
    gen_update_nip(ctx, ctx->nip);
3657
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3658
    tcg_temp_free(t0);
3659
    tcg_temp_free_i32(t1);
3660
}
3661
#endif
3662

    
3663
/***                          Processor control                            ***/
3664

    
3665
/* mcrxr */
3666
static void gen_mcrxr(DisasContext *ctx)
3667
{
3668
    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3669
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3670
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3671
}
3672

    
3673
/* mfcr mfocrf */
3674
static void gen_mfcr(DisasContext *ctx)
3675
{
3676
    uint32_t crm, crn;
3677

    
3678
    if (likely(ctx->opcode & 0x00100000)) {
3679
        crm = CRM(ctx->opcode);
3680
        if (likely(crm && ((crm & (crm - 1)) == 0))) {
3681
            crn = ctz32 (crm);
3682
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3683
            tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3684
                            cpu_gpr[rD(ctx->opcode)], crn * 4);
3685
        }
3686
    } else {
3687
        TCGv_i32 t0 = tcg_temp_new_i32();
3688
        tcg_gen_mov_i32(t0, cpu_crf[0]);
3689
        tcg_gen_shli_i32(t0, t0, 4);
3690
        tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3691
        tcg_gen_shli_i32(t0, t0, 4);
3692
        tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3693
        tcg_gen_shli_i32(t0, t0, 4);
3694
        tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3695
        tcg_gen_shli_i32(t0, t0, 4);
3696
        tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3697
        tcg_gen_shli_i32(t0, t0, 4);
3698
        tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3699
        tcg_gen_shli_i32(t0, t0, 4);
3700
        tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3701
        tcg_gen_shli_i32(t0, t0, 4);
3702
        tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3703
        tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3704
        tcg_temp_free_i32(t0);
3705
    }
3706
}
3707

    
3708
/* mfmsr */
3709
static void gen_mfmsr(DisasContext *ctx)
3710
{
3711
#if defined(CONFIG_USER_ONLY)
3712
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3713
#else
3714
    if (unlikely(!ctx->mem_idx)) {
3715
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3716
        return;
3717
    }
3718
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3719
#endif
3720
}
3721

    
3722
static void spr_noaccess(void *opaque, int gprn, int sprn)
3723
{
3724
#if 0
3725
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3726
    printf("ERROR: try to access SPR %d !\n", sprn);
3727
#endif
3728
}
3729
#define SPR_NOACCESS (&spr_noaccess)
3730

    
3731
/* mfspr */
3732
static inline void gen_op_mfspr(DisasContext *ctx)
3733
{
3734
    void (*read_cb)(void *opaque, int gprn, int sprn);
3735
    uint32_t sprn = SPR(ctx->opcode);
3736

    
3737
#if !defined(CONFIG_USER_ONLY)
3738
    if (ctx->mem_idx == 2)
3739
        read_cb = ctx->spr_cb[sprn].hea_read;
3740
    else if (ctx->mem_idx)
3741
        read_cb = ctx->spr_cb[sprn].oea_read;
3742
    else
3743
#endif
3744
        read_cb = ctx->spr_cb[sprn].uea_read;
3745
    if (likely(read_cb != NULL)) {
3746
        if (likely(read_cb != SPR_NOACCESS)) {
3747
            (*read_cb)(ctx, rD(ctx->opcode), sprn);
3748
        } else {
3749
            /* Privilege exception */
3750
            /* This is a hack to avoid warnings when running Linux:
3751
             * this OS breaks the PowerPC virtualisation model,
3752
             * allowing userland application to read the PVR
3753
             */
3754
            if (sprn != SPR_PVR) {
3755
                qemu_log("Trying to read privileged spr %d %03x at "
3756
                         TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3757
                printf("Trying to read privileged spr %d %03x at "
3758
                       TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3759
            }
3760
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3761
        }
3762
    } else {
3763
        /* Not defined */
3764
        qemu_log("Trying to read invalid spr %d %03x at "
3765
                    TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3766
        printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3767
               sprn, sprn, ctx->nip);
3768
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3769
    }
3770
}
3771

    
3772
static void gen_mfspr(DisasContext *ctx)
3773
{
3774
    gen_op_mfspr(ctx);
3775
}
3776

    
3777
/* mftb */
3778
static void gen_mftb(DisasContext *ctx)
3779
{
3780
    gen_op_mfspr(ctx);
3781
}
3782

    
3783
/* mtcrf mtocrf*/
3784
static void gen_mtcrf(DisasContext *ctx)
3785
{
3786
    uint32_t crm, crn;
3787

    
3788
    crm = CRM(ctx->opcode);
3789
    if (likely((ctx->opcode & 0x00100000))) {
3790
        if (crm && ((crm & (crm - 1)) == 0)) {
3791
            TCGv_i32 temp = tcg_temp_new_i32();
3792
            crn = ctz32 (crm);
3793
            tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3794
            tcg_gen_shri_i32(temp, temp, crn * 4);
3795
            tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3796
            tcg_temp_free_i32(temp);
3797
        }
3798
    } else {
3799
        TCGv_i32 temp = tcg_temp_new_i32();
3800
        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3801
        for (crn = 0 ; crn < 8 ; crn++) {
3802
            if (crm & (1 << crn)) {
3803
                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3804
                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3805
            }
3806
        }
3807
        tcg_temp_free_i32(temp);
3808
    }
3809
}
3810

    
3811
/* mtmsr */
3812
#if defined(TARGET_PPC64)
3813
static void gen_mtmsrd(DisasContext *ctx)
3814
{
3815
#if defined(CONFIG_USER_ONLY)
3816
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3817
#else
3818
    if (unlikely(!ctx->mem_idx)) {
3819
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3820
        return;
3821
    }
3822
    if (ctx->opcode & 0x00010000) {
3823
        /* Special form that does not need any synchronisation */
3824
        TCGv t0 = tcg_temp_new();
3825
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3826
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3827
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3828
        tcg_temp_free(t0);
3829
    } else {
3830
        /* XXX: we need to update nip before the store
3831
         *      if we enter power saving mode, we will exit the loop
3832
         *      directly from ppc_store_msr
3833
         */
3834
        gen_update_nip(ctx, ctx->nip);
3835
        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3836
        /* Must stop the translation as machine state (may have) changed */
3837
        /* Note that mtmsr is not always defined as context-synchronizing */
3838
        gen_stop_exception(ctx);
3839
    }
3840
#endif
3841
}
3842
#endif
3843

    
3844
static void gen_mtmsr(DisasContext *ctx)
3845
{
3846
#if defined(CONFIG_USER_ONLY)
3847
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3848
#else
3849
    if (unlikely(!ctx->mem_idx)) {
3850
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3851
        return;
3852
    }
3853
    if (ctx->opcode & 0x00010000) {
3854
        /* Special form that does not need any synchronisation */
3855
        TCGv t0 = tcg_temp_new();
3856
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3857
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3858
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3859
        tcg_temp_free(t0);
3860
    } else {
3861
        /* XXX: we need to update nip before the store
3862
         *      if we enter power saving mode, we will exit the loop
3863
         *      directly from ppc_store_msr
3864
         */
3865
        gen_update_nip(ctx, ctx->nip);
3866
#if defined(TARGET_PPC64)
3867
        if (!ctx->sf_mode) {
3868
            TCGv t0 = tcg_temp_new();
3869
            TCGv t1 = tcg_temp_new();
3870
            tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3871
            tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3872
            tcg_gen_or_tl(t0, t0, t1);
3873
            tcg_temp_free(t1);
3874
            gen_helper_store_msr(t0);
3875
            tcg_temp_free(t0);
3876
        } else
3877
#endif
3878
            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3879
        /* Must stop the translation as machine state (may have) changed */
3880
        /* Note that mtmsr is not always defined as context-synchronizing */
3881
        gen_stop_exception(ctx);
3882
    }
3883
#endif
3884
}
3885

    
3886
/* mtspr */
3887
static void gen_mtspr(DisasContext *ctx)
3888
{
3889
    void (*write_cb)(void *opaque, int sprn, int gprn);
3890
    uint32_t sprn = SPR(ctx->opcode);
3891

    
3892
#if !defined(CONFIG_USER_ONLY)
3893
    if (ctx->mem_idx == 2)
3894
        write_cb = ctx->spr_cb[sprn].hea_write;
3895
    else if (ctx->mem_idx)
3896
        write_cb = ctx->spr_cb[sprn].oea_write;
3897
    else
3898
#endif
3899
        write_cb = ctx->spr_cb[sprn].uea_write;
3900
    if (likely(write_cb != NULL)) {
3901
        if (likely(write_cb != SPR_NOACCESS)) {
3902
            (*write_cb)(ctx, sprn, rS(ctx->opcode));
3903
        } else {
3904
            /* Privilege exception */
3905
            qemu_log("Trying to write privileged spr %d %03x at "
3906
                     TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3907
            printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3908
                   "\n", sprn, sprn, ctx->nip);
3909
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3910
        }
3911
    } else {
3912
        /* Not defined */
3913
        qemu_log("Trying to write invalid spr %d %03x at "
3914
                 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3915
        printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3916
               sprn, sprn, ctx->nip);
3917
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3918
    }
3919
}
3920

    
3921
/***                         Cache management                              ***/
3922

    
3923
/* dcbf */
3924
static void gen_dcbf(DisasContext *ctx)
3925
{
3926
    /* XXX: specification says this is treated as a load by the MMU */
3927
    TCGv t0;
3928
    gen_set_access_type(ctx, ACCESS_CACHE);
3929
    t0 = tcg_temp_new();
3930
    gen_addr_reg_index(ctx, t0);
3931
    gen_qemu_ld8u(ctx, t0, t0);
3932
    tcg_temp_free(t0);
3933
}
3934

    
3935
/* dcbi (Supervisor only) */
3936
static void gen_dcbi(DisasContext *ctx)
3937
{
3938
#if defined(CONFIG_USER_ONLY)
3939
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3940
#else
3941
    TCGv EA, val;
3942
    if (unlikely(!ctx->mem_idx)) {
3943
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3944
        return;
3945
    }
3946
    EA = tcg_temp_new();
3947
    gen_set_access_type(ctx, ACCESS_CACHE);
3948
    gen_addr_reg_index(ctx, EA);
3949
    val = tcg_temp_new();
3950
    /* XXX: specification says this should be treated as a store by the MMU */
3951
    gen_qemu_ld8u(ctx, val, EA);
3952
    gen_qemu_st8(ctx, val, EA);
3953
    tcg_temp_free(val);
3954
    tcg_temp_free(EA);
3955
#endif
3956
}
3957

    
3958
/* dcdst */
3959
static void gen_dcbst(DisasContext *ctx)
3960
{
3961
    /* XXX: specification say this is treated as a load by the MMU */
3962
    TCGv t0;
3963
    gen_set_access_type(ctx, ACCESS_CACHE);
3964
    t0 = tcg_temp_new();
3965
    gen_addr_reg_index(ctx, t0);
3966
    gen_qemu_ld8u(ctx, t0, t0);
3967
    tcg_temp_free(t0);
3968
}
3969

    
3970
/* dcbt */
3971
static void gen_dcbt(DisasContext *ctx)
3972
{
3973
    /* interpreted as no-op */
3974
    /* XXX: specification say this is treated as a load by the MMU
3975
     *      but does not generate any exception
3976
     */
3977
}
3978

    
3979
/* dcbtst */
3980
static void gen_dcbtst(DisasContext *ctx)
3981
{
3982
    /* interpreted as no-op */
3983
    /* XXX: specification say this is treated as a load by the MMU
3984
     *      but does not generate any exception
3985
     */
3986
}
3987

    
3988
/* dcbz */
3989
static void gen_dcbz(DisasContext *ctx)
3990
{
3991
    TCGv t0;
3992
    gen_set_access_type(ctx, ACCESS_CACHE);
3993
    /* NIP cannot be restored if the memory exception comes from an helper */
3994
    gen_update_nip(ctx, ctx->nip - 4);
3995
    t0 = tcg_temp_new();
3996
    gen_addr_reg_index(ctx, t0);
3997
    gen_helper_dcbz(t0);
3998
    tcg_temp_free(t0);
3999
}
4000

    
4001
static void gen_dcbz_970(DisasContext *ctx)
4002
{
4003
    TCGv t0;
4004
    gen_set_access_type(ctx, ACCESS_CACHE);
4005
    /* NIP cannot be restored if the memory exception comes from an helper */
4006
    gen_update_nip(ctx, ctx->nip - 4);
4007
    t0 = tcg_temp_new();
4008
    gen_addr_reg_index(ctx, t0);
4009
    if (ctx->opcode & 0x00200000)
4010
        gen_helper_dcbz(t0);
4011
    else
4012
        gen_helper_dcbz_970(t0);
4013
    tcg_temp_free(t0);
4014
}
4015

    
4016
/* dst / dstt */
4017
static void gen_dst(DisasContext *ctx)
4018
{
4019
    if (rA(ctx->opcode) == 0) {
4020
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4021
    } else {
4022
        /* interpreted as no-op */
4023
    }
4024
}
4025

    
4026
/* dstst /dststt */
4027
static void gen_dstst(DisasContext *ctx)
4028
{
4029
    if (rA(ctx->opcode) == 0) {
4030
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4031
    } else {
4032
        /* interpreted as no-op */
4033
    }
4034

    
4035
}
4036

    
4037
/* dss / dssall */
4038
static void gen_dss(DisasContext *ctx)
4039
{
4040
    /* interpreted as no-op */
4041
}
4042

    
4043
/* icbi */
4044
static void gen_icbi(DisasContext *ctx)
4045
{
4046
    TCGv t0;
4047
    gen_set_access_type(ctx, ACCESS_CACHE);
4048
    /* NIP cannot be restored if the memory exception comes from an helper */
4049
    gen_update_nip(ctx, ctx->nip - 4);
4050
    t0 = tcg_temp_new();
4051
    gen_addr_reg_index(ctx, t0);
4052
    gen_helper_icbi(t0);
4053
    tcg_temp_free(t0);
4054
}
4055

    
4056
/* Optional: */
4057
/* dcba */
4058
static void gen_dcba(DisasContext *ctx)
4059
{
4060
    /* interpreted as no-op */
4061
    /* XXX: specification say this is treated as a store by the MMU
4062
     *      but does not generate any exception
4063
     */
4064
}
4065

    
4066
/***                    Segment register manipulation                      ***/
4067
/* Supervisor only: */
4068

    
4069
/* mfsr */
4070
static void gen_mfsr(DisasContext *ctx)
4071
{
4072
#if defined(CONFIG_USER_ONLY)
4073
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4074
#else
4075
    TCGv t0;
4076
    if (unlikely(!ctx->mem_idx)) {
4077
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4078
        return;
4079
    }
4080
    t0 = tcg_const_tl(SR(ctx->opcode));
4081
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4082
    tcg_temp_free(t0);
4083
#endif
4084
}
4085

    
4086
/* mfsrin */
4087
static void gen_mfsrin(DisasContext *ctx)
4088
{
4089
#if defined(CONFIG_USER_ONLY)
4090
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4091
#else
4092
    TCGv t0;
4093
    if (unlikely(!ctx->mem_idx)) {
4094
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4095
        return;
4096
    }
4097
    t0 = tcg_temp_new();
4098
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4099
    tcg_gen_andi_tl(t0, t0, 0xF);
4100
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4101
    tcg_temp_free(t0);
4102
#endif
4103
}
4104

    
4105
/* mtsr */
4106
static void gen_mtsr(DisasContext *ctx)
4107
{
4108
#if defined(CONFIG_USER_ONLY)
4109
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4110
#else
4111
    TCGv t0;
4112
    if (unlikely(!ctx->mem_idx)) {
4113
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4114
        return;
4115
    }
4116
    t0 = tcg_const_tl(SR(ctx->opcode));
4117
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4118
    tcg_temp_free(t0);
4119
#endif
4120
}
4121

    
4122
/* mtsrin */
4123
static void gen_mtsrin(DisasContext *ctx)
4124
{
4125
#if defined(CONFIG_USER_ONLY)
4126
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4127
#else
4128
    TCGv t0;
4129
    if (unlikely(!ctx->mem_idx)) {
4130
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4131
        return;
4132
    }
4133
    t0 = tcg_temp_new();
4134
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4135
    tcg_gen_andi_tl(t0, t0, 0xF);
4136
    gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4137
    tcg_temp_free(t0);
4138
#endif
4139
}
4140

    
4141
#if defined(TARGET_PPC64)
4142
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4143

    
4144
/* mfsr */
4145
static void gen_mfsr_64b(DisasContext *ctx)
4146
{
4147
#if defined(CONFIG_USER_ONLY)
4148
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149
#else
4150
    TCGv t0;
4151
    if (unlikely(!ctx->mem_idx)) {
4152
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4153
        return;
4154
    }
4155
    t0 = tcg_const_tl(SR(ctx->opcode));
4156
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4157
    tcg_temp_free(t0);
4158
#endif
4159
}
4160

    
4161
/* mfsrin */
4162
static void gen_mfsrin_64b(DisasContext *ctx)
4163
{
4164
#if defined(CONFIG_USER_ONLY)
4165
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166
#else
4167
    TCGv t0;
4168
    if (unlikely(!ctx->mem_idx)) {
4169
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4170
        return;
4171
    }
4172
    t0 = tcg_temp_new();
4173
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4174
    tcg_gen_andi_tl(t0, t0, 0xF);
4175
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176
    tcg_temp_free(t0);
4177
#endif
4178
}
4179

    
4180
/* mtsr */
4181
static void gen_mtsr_64b(DisasContext *ctx)
4182
{
4183
#if defined(CONFIG_USER_ONLY)
4184
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185
#else
4186
    TCGv t0;
4187
    if (unlikely(!ctx->mem_idx)) {
4188
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189
        return;
4190
    }
4191
    t0 = tcg_const_tl(SR(ctx->opcode));
4192
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4193
    tcg_temp_free(t0);
4194
#endif
4195
}
4196

    
4197
/* mtsrin */
4198
static void gen_mtsrin_64b(DisasContext *ctx)
4199
{
4200
#if defined(CONFIG_USER_ONLY)
4201
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202
#else
4203
    TCGv t0;
4204
    if (unlikely(!ctx->mem_idx)) {
4205
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206
        return;
4207
    }
4208
    t0 = tcg_temp_new();
4209
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210
    tcg_gen_andi_tl(t0, t0, 0xF);
4211
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4212
    tcg_temp_free(t0);
4213
#endif
4214
}
4215

    
4216
/* slbmte */
4217
static void gen_slbmte(DisasContext *ctx)
4218
{
4219
#if defined(CONFIG_USER_ONLY)
4220
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221
#else
4222
    if (unlikely(!ctx->mem_idx)) {
4223
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4224
        return;
4225
    }
4226
    gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4227
#endif
4228
}
4229

    
4230
static void gen_slbmfee(DisasContext *ctx)
4231
{
4232
#if defined(CONFIG_USER_ONLY)
4233
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4234
#else
4235
    if (unlikely(!ctx->mem_idx)) {
4236
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4237
        return;
4238
    }
4239
    gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4240
                             cpu_gpr[rB(ctx->opcode)]);
4241
#endif
4242
}
4243

    
4244
static void gen_slbmfev(DisasContext *ctx)
4245
{
4246
#if defined(CONFIG_USER_ONLY)
4247
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248
#else
4249
    if (unlikely(!ctx->mem_idx)) {
4250
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4251
        return;
4252
    }
4253
    gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4254
                             cpu_gpr[rB(ctx->opcode)]);
4255
#endif
4256
}
4257
#endif /* defined(TARGET_PPC64) */
4258

    
4259
/***                      Lookaside buffer management                      ***/
4260
/* Optional & mem_idx only: */
4261

    
4262
/* tlbia */
4263
static void gen_tlbia(DisasContext *ctx)
4264
{
4265
#if defined(CONFIG_USER_ONLY)
4266
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4267
#else
4268
    if (unlikely(!ctx->mem_idx)) {
4269
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4270
        return;
4271
    }
4272
    gen_helper_tlbia();
4273
#endif
4274
}
4275

    
4276
/* tlbiel */
4277
static void gen_tlbiel(DisasContext *ctx)
4278
{
4279
#if defined(CONFIG_USER_ONLY)
4280
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4281
#else
4282
    if (unlikely(!ctx->mem_idx)) {
4283
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4284
        return;
4285
    }
4286
    gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4287
#endif
4288
}
4289

    
4290
/* tlbie */
4291
static void gen_tlbie(DisasContext *ctx)
4292
{
4293
#if defined(CONFIG_USER_ONLY)
4294
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4295
#else
4296
    if (unlikely(!ctx->mem_idx)) {
4297
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4298
        return;
4299
    }
4300
#if defined(TARGET_PPC64)
4301
    if (!ctx->sf_mode) {
4302
        TCGv t0 = tcg_temp_new();
4303
        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4304
        gen_helper_tlbie(t0);
4305
        tcg_temp_free(t0);
4306
    } else
4307
#endif
4308
        gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4309
#endif
4310
}
4311

    
4312
/* tlbsync */
4313
static void gen_tlbsync(DisasContext *ctx)
4314
{
4315
#if defined(CONFIG_USER_ONLY)
4316
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4317
#else
4318
    if (unlikely(!ctx->mem_idx)) {
4319
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4320
        return;
4321
    }
4322
    /* This has no effect: it should ensure that all previous
4323
     * tlbie have completed
4324
     */
4325
    gen_stop_exception(ctx);
4326
#endif
4327
}
4328

    
4329
#if defined(TARGET_PPC64)
4330
/* slbia */
4331
static void gen_slbia(DisasContext *ctx)
4332
{
4333
#if defined(CONFIG_USER_ONLY)
4334
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4335
#else
4336
    if (unlikely(!ctx->mem_idx)) {
4337
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4338
        return;
4339
    }
4340
    gen_helper_slbia();
4341
#endif
4342
}
4343

    
4344
/* slbie */
4345
static void gen_slbie(DisasContext *ctx)
4346
{
4347
#if defined(CONFIG_USER_ONLY)
4348
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4349
#else
4350
    if (unlikely(!ctx->mem_idx)) {
4351
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4352
        return;
4353
    }
4354
    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4355
#endif
4356
}
4357
#endif
4358

    
4359
/***                              External control                         ***/
4360
/* Optional: */
4361

    
4362
/* eciwx */
4363
static void gen_eciwx(DisasContext *ctx)
4364
{
4365
    TCGv t0;
4366
    /* Should check EAR[E] ! */
4367
    gen_set_access_type(ctx, ACCESS_EXT);
4368
    t0 = tcg_temp_new();
4369
    gen_addr_reg_index(ctx, t0);
4370
    gen_check_align(ctx, t0, 0x03);
4371
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4372
    tcg_temp_free(t0);
4373
}
4374

    
4375
/* ecowx */
4376
static void gen_ecowx(DisasContext *ctx)
4377
{
4378
    TCGv t0;
4379
    /* Should check EAR[E] ! */
4380
    gen_set_access_type(ctx, ACCESS_EXT);
4381
    t0 = tcg_temp_new();
4382
    gen_addr_reg_index(ctx, t0);
4383
    gen_check_align(ctx, t0, 0x03);
4384
    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4385
    tcg_temp_free(t0);
4386
}
4387

    
4388
/* PowerPC 601 specific instructions */
4389

    
4390
/* abs - abs. */
4391
static void gen_abs(DisasContext *ctx)
4392
{
4393
    int l1 = gen_new_label();
4394
    int l2 = gen_new_label();
4395
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4396
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4397
    tcg_gen_br(l2);
4398
    gen_set_label(l1);
4399
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4400
    gen_set_label(l2);
4401
    if (unlikely(Rc(ctx->opcode) != 0))
4402
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4403
}
4404

    
4405
/* abso - abso. */
4406
static void gen_abso(DisasContext *ctx)
4407
{
4408
    int l1 = gen_new_label();
4409
    int l2 = gen_new_label();
4410
    int l3 = gen_new_label();
4411
    /* Start with XER OV disabled, the most likely case */
4412
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4413
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4414
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4415
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4416
    tcg_gen_br(l2);
4417
    gen_set_label(l1);
4418
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4419
    tcg_gen_br(l3);
4420
    gen_set_label(l2);
4421
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4422
    gen_set_label(l3);
4423
    if (unlikely(Rc(ctx->opcode) != 0))
4424
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4425
}
4426

    
4427
/* clcs */
4428
static void gen_clcs(DisasContext *ctx)
4429
{
4430
    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4431
    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4432
    tcg_temp_free_i32(t0);
4433
    /* Rc=1 sets CR0 to an undefined state */
4434
}
4435

    
4436
/* div - div. */
4437
static void gen_div(DisasContext *ctx)
4438
{
4439
    gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4440
    if (unlikely(Rc(ctx->opcode) != 0))
4441
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4442
}
4443

    
4444
/* divo - divo. */
4445
static void gen_divo(DisasContext *ctx)
4446
{
4447
    gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4448
    if (unlikely(Rc(ctx->opcode) != 0))
4449
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4450
}
4451

    
4452
/* divs - divs. */
4453
static void gen_divs(DisasContext *ctx)
4454
{
4455
    gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4456
    if (unlikely(Rc(ctx->opcode) != 0))
4457
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4458
}
4459

    
4460
/* divso - divso. */
4461
static void gen_divso(DisasContext *ctx)
4462
{
4463
    gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4464
    if (unlikely(Rc(ctx->opcode) != 0))
4465
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4466
}
4467

    
4468
/* doz - doz. */
4469
static void gen_doz(DisasContext *ctx)
4470
{
4471
    int l1 = gen_new_label();
4472
    int l2 = gen_new_label();
4473
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4474
    tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4475
    tcg_gen_br(l2);
4476
    gen_set_label(l1);
4477
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4478
    gen_set_label(l2);
4479
    if (unlikely(Rc(ctx->opcode) != 0))
4480
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4481
}
4482

    
4483
/* dozo - dozo. */
4484
static void gen_dozo(DisasContext *ctx)
4485
{
4486
    int l1 = gen_new_label();
4487
    int l2 = gen_new_label();
4488
    TCGv t0 = tcg_temp_new();
4489
    TCGv t1 = tcg_temp_new();
4490
    TCGv t2 = tcg_temp_new();
4491
    /* Start with XER OV disabled, the most likely case */
4492
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4493
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4494
    tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4495
    tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4496
    tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4497
    tcg_gen_andc_tl(t1, t1, t2);
4498
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4499
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4500
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4501
    tcg_gen_br(l2);
4502
    gen_set_label(l1);
4503
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4504
    gen_set_label(l2);
4505
    tcg_temp_free(t0);
4506
    tcg_temp_free(t1);
4507
    tcg_temp_free(t2);
4508
    if (unlikely(Rc(ctx->opcode) != 0))
4509
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4510
}
4511

    
4512
/* dozi */
4513
static void gen_dozi(DisasContext *ctx)
4514
{
4515
    target_long simm = SIMM(ctx->opcode);
4516
    int l1 = gen_new_label();
4517
    int l2 = gen_new_label();
4518
    tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4519
    tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4520
    tcg_gen_br(l2);
4521
    gen_set_label(l1);
4522
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4523
    gen_set_label(l2);
4524
    if (unlikely(Rc(ctx->opcode) != 0))
4525
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4526
}
4527

    
4528
/* lscbx - lscbx. */
4529
static void gen_lscbx(DisasContext *ctx)
4530
{
4531
    TCGv t0 = tcg_temp_new();
4532
    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4533
    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4534
    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4535

    
4536
    gen_addr_reg_index(ctx, t0);
4537
    /* NIP cannot be restored if the memory exception comes from an helper */
4538
    gen_update_nip(ctx, ctx->nip - 4);
4539
    gen_helper_lscbx(t0, t0, t1, t2, t3);
4540
    tcg_temp_free_i32(t1);
4541
    tcg_temp_free_i32(t2);
4542
    tcg_temp_free_i32(t3);
4543
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4544
    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4545
    if (unlikely(Rc(ctx->opcode) != 0))
4546
        gen_set_Rc0(ctx, t0);
4547
    tcg_temp_free(t0);
4548
}
4549

    
4550
/* maskg - maskg. */
4551
static void gen_maskg(DisasContext *ctx)
4552
{
4553
    int l1 = gen_new_label();
4554
    TCGv t0 = tcg_temp_new();
4555
    TCGv t1 = tcg_temp_new();
4556
    TCGv t2 = tcg_temp_new();
4557
    TCGv t3 = tcg_temp_new();
4558
    tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4559
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4560
    tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4561
    tcg_gen_addi_tl(t2, t0, 1);
4562
    tcg_gen_shr_tl(t2, t3, t2);
4563
    tcg_gen_shr_tl(t3, t3, t1);
4564
    tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4565
    tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4566
    tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4567
    gen_set_label(l1);
4568
    tcg_temp_free(t0);
4569
    tcg_temp_free(t1);
4570
    tcg_temp_free(t2);
4571
    tcg_temp_free(t3);
4572
    if (unlikely(Rc(ctx->opcode) != 0))
4573
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4574
}
4575

    
4576
/* maskir - maskir. */
4577
static void gen_maskir(DisasContext *ctx)
4578
{
4579
    TCGv t0 = tcg_temp_new();
4580
    TCGv t1 = tcg_temp_new();
4581
    tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4582
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4583
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4584
    tcg_temp_free(t0);
4585
    tcg_temp_free(t1);
4586
    if (unlikely(Rc(ctx->opcode) != 0))
4587
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4588
}
4589

    
4590
/* mul - mul. */
4591
static void gen_mul(DisasContext *ctx)
4592
{
4593
    TCGv_i64 t0 = tcg_temp_new_i64();
4594
    TCGv_i64 t1 = tcg_temp_new_i64();
4595
    TCGv t2 = tcg_temp_new();
4596
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4597
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4598
    tcg_gen_mul_i64(t0, t0, t1);
4599
    tcg_gen_trunc_i64_tl(t2, t0);
4600
    gen_store_spr(SPR_MQ, t2);
4601
    tcg_gen_shri_i64(t1, t0, 32);
4602
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4603
    tcg_temp_free_i64(t0);
4604
    tcg_temp_free_i64(t1);
4605
    tcg_temp_free(t2);
4606
    if (unlikely(Rc(ctx->opcode) != 0))
4607
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4608
}
4609

    
4610
/* mulo - mulo. */
4611
static void gen_mulo(DisasContext *ctx)
4612
{
4613
    int l1 = gen_new_label();
4614
    TCGv_i64 t0 = tcg_temp_new_i64();
4615
    TCGv_i64 t1 = tcg_temp_new_i64();
4616
    TCGv t2 = tcg_temp_new();
4617
    /* Start with XER OV disabled, the most likely case */
4618
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4619
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4620
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4621
    tcg_gen_mul_i64(t0, t0, t1);
4622
    tcg_gen_trunc_i64_tl(t2, t0);
4623
    gen_store_spr(SPR_MQ, t2);
4624
    tcg_gen_shri_i64(t1, t0, 32);
4625
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4626
    tcg_gen_ext32s_i64(t1, t0);
4627
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4628
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4629
    gen_set_label(l1);
4630
    tcg_temp_free_i64(t0);
4631
    tcg_temp_free_i64(t1);
4632
    tcg_temp_free(t2);
4633
    if (unlikely(Rc(ctx->opcode) != 0))
4634
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4635
}
4636

    
4637
/* nabs - nabs. */
4638
static void gen_nabs(DisasContext *ctx)
4639
{
4640
    int l1 = gen_new_label();
4641
    int l2 = gen_new_label();
4642
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4643
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4644
    tcg_gen_br(l2);
4645
    gen_set_label(l1);
4646
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4647
    gen_set_label(l2);
4648
    if (unlikely(Rc(ctx->opcode) != 0))
4649
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4650
}
4651

    
4652
/* nabso - nabso. */
4653
static void gen_nabso(DisasContext *ctx)
4654
{
4655
    int l1 = gen_new_label();
4656
    int l2 = gen_new_label();
4657
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4658
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4659
    tcg_gen_br(l2);
4660
    gen_set_label(l1);
4661
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4662
    gen_set_label(l2);
4663
    /* nabs never overflows */
4664
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4665
    if (unlikely(Rc(ctx->opcode) != 0))
4666
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4667
}
4668

    
4669
/* rlmi - rlmi. */
4670
static void gen_rlmi(DisasContext *ctx)
4671
{
4672
    uint32_t mb = MB(ctx->opcode);
4673
    uint32_t me = ME(ctx->opcode);
4674
    TCGv t0 = tcg_temp_new();
4675
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4676
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4677
    tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4678
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4679
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4680
    tcg_temp_free(t0);
4681
    if (unlikely(Rc(ctx->opcode) != 0))
4682
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4683
}
4684

    
4685
/* rrib - rrib. */
4686
static void gen_rrib(DisasContext *ctx)
4687
{
4688
    TCGv t0 = tcg_temp_new();
4689
    TCGv t1 = tcg_temp_new();
4690
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4691
    tcg_gen_movi_tl(t1, 0x80000000);
4692
    tcg_gen_shr_tl(t1, t1, t0);
4693
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4694
    tcg_gen_and_tl(t0, t0, t1);
4695
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4696
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4697
    tcg_temp_free(t0);
4698
    tcg_temp_free(t1);
4699
    if (unlikely(Rc(ctx->opcode) != 0))
4700
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4701
}
4702

    
4703
/* sle - sle. */
4704
static void gen_sle(DisasContext *ctx)
4705
{
4706
    TCGv t0 = tcg_temp_new();
4707
    TCGv t1 = tcg_temp_new();
4708
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4709
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4710
    tcg_gen_subfi_tl(t1, 32, t1);
4711
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4712
    tcg_gen_or_tl(t1, t0, t1);
4713
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4714
    gen_store_spr(SPR_MQ, t1);
4715
    tcg_temp_free(t0);
4716
    tcg_temp_free(t1);
4717
    if (unlikely(Rc(ctx->opcode) != 0))
4718
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4719
}
4720

    
4721
/* sleq - sleq. */
4722
static void gen_sleq(DisasContext *ctx)
4723
{
4724
    TCGv t0 = tcg_temp_new();
4725
    TCGv t1 = tcg_temp_new();
4726
    TCGv t2 = tcg_temp_new();
4727
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4728
    tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4729
    tcg_gen_shl_tl(t2, t2, t0);
4730
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4731
    gen_load_spr(t1, SPR_MQ);
4732
    gen_store_spr(SPR_MQ, t0);
4733
    tcg_gen_and_tl(t0, t0, t2);
4734
    tcg_gen_andc_tl(t1, t1, t2);
4735
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4736
    tcg_temp_free(t0);
4737
    tcg_temp_free(t1);
4738
    tcg_temp_free(t2);
4739
    if (unlikely(Rc(ctx->opcode) != 0))
4740
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4741
}
4742

    
4743
/* sliq - sliq. */
4744
static void gen_sliq(DisasContext *ctx)
4745
{
4746
    int sh = SH(ctx->opcode);
4747
    TCGv t0 = tcg_temp_new();
4748
    TCGv t1 = tcg_temp_new();
4749
    tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4750
    tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4751
    tcg_gen_or_tl(t1, t0, t1);
4752
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4753
    gen_store_spr(SPR_MQ, t1);
4754
    tcg_temp_free(t0);
4755
    tcg_temp_free(t1);
4756
    if (unlikely(Rc(ctx->opcode) != 0))
4757
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4758
}
4759

    
4760
/* slliq - slliq. */
4761
static void gen_slliq(DisasContext *ctx)
4762
{
4763
    int sh = SH(ctx->opcode);
4764
    TCGv t0 = tcg_temp_new();
4765
    TCGv t1 = tcg_temp_new();
4766
    tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4767
    gen_load_spr(t1, SPR_MQ);
4768
    gen_store_spr(SPR_MQ, t0);
4769
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
4770
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4771
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4772
    tcg_temp_free(t0);
4773
    tcg_temp_free(t1);
4774
    if (unlikely(Rc(ctx->opcode) != 0))
4775
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4776
}
4777

    
4778
/* sllq - sllq. */
4779
static void gen_sllq(DisasContext *ctx)
4780
{
4781
    int l1 = gen_new_label();
4782
    int l2 = gen_new_label();
4783
    TCGv t0 = tcg_temp_local_new();
4784
    TCGv t1 = tcg_temp_local_new();
4785
    TCGv t2 = tcg_temp_local_new();
4786
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4787
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4788
    tcg_gen_shl_tl(t1, t1, t2);
4789
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4790
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4791
    gen_load_spr(t0, SPR_MQ);
4792
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4793
    tcg_gen_br(l2);
4794
    gen_set_label(l1);
4795
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4796
    gen_load_spr(t2, SPR_MQ);
4797
    tcg_gen_andc_tl(t1, t2, t1);
4798
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4799
    gen_set_label(l2);
4800
    tcg_temp_free(t0);
4801
    tcg_temp_free(t1);
4802
    tcg_temp_free(t2);
4803
    if (unlikely(Rc(ctx->opcode) != 0))
4804
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4805
}
4806

    
4807
/* slq - slq. */
4808
static void gen_slq(DisasContext *ctx)
4809
{
4810
    int l1 = gen_new_label();
4811
    TCGv t0 = tcg_temp_new();
4812
    TCGv t1 = tcg_temp_new();
4813
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4814
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4815
    tcg_gen_subfi_tl(t1, 32, t1);
4816
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4817
    tcg_gen_or_tl(t1, t0, t1);
4818
    gen_store_spr(SPR_MQ, t1);
4819
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4820
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4821
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4822
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4823
    gen_set_label(l1);
4824
    tcg_temp_free(t0);
4825
    tcg_temp_free(t1);
4826
    if (unlikely(Rc(ctx->opcode) != 0))
4827
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828
}
4829

    
4830
/* sraiq - sraiq. */
4831
static void gen_sraiq(DisasContext *ctx)
4832
{
4833
    int sh = SH(ctx->opcode);
4834
    int l1 = gen_new_label();
4835
    TCGv t0 = tcg_temp_new();
4836
    TCGv t1 = tcg_temp_new();
4837
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4838
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4839
    tcg_gen_or_tl(t0, t0, t1);
4840
    gen_store_spr(SPR_MQ, t0);
4841
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4842
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4843
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4844
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4845
    gen_set_label(l1);
4846
    tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4847
    tcg_temp_free(t0);
4848
    tcg_temp_free(t1);
4849
    if (unlikely(Rc(ctx->opcode) != 0))
4850
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4851
}
4852

    
4853
/* sraq - sraq. */
4854
static void gen_sraq(DisasContext *ctx)
4855
{
4856
    int l1 = gen_new_label();
4857
    int l2 = gen_new_label();
4858
    TCGv t0 = tcg_temp_new();
4859
    TCGv t1 = tcg_temp_local_new();
4860
    TCGv t2 = tcg_temp_local_new();
4861
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4862
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4863
    tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4864
    tcg_gen_subfi_tl(t2, 32, t2);
4865
    tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4866
    tcg_gen_or_tl(t0, t0, t2);
4867
    gen_store_spr(SPR_MQ, t0);
4868
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4869
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4870
    tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4871
    tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4872
    gen_set_label(l1);
4873
    tcg_temp_free(t0);
4874
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4875
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4876
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4877
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4878
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4879
    gen_set_label(l2);
4880
    tcg_temp_free(t1);
4881
    tcg_temp_free(t2);
4882
    if (unlikely(Rc(ctx->opcode) != 0))
4883
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4884
}
4885

    
4886
/* sre - sre. */
4887
static void gen_sre(DisasContext *ctx)
4888
{
4889
    TCGv t0 = tcg_temp_new();
4890
    TCGv t1 = tcg_temp_new();
4891
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4892
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4893
    tcg_gen_subfi_tl(t1, 32, t1);
4894
    tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4895
    tcg_gen_or_tl(t1, t0, t1);
4896
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4897
    gen_store_spr(SPR_MQ, t1);
4898
    tcg_temp_free(t0);
4899
    tcg_temp_free(t1);
4900
    if (unlikely(Rc(ctx->opcode) != 0))
4901
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4902
}
4903

    
4904
/* srea - srea. */
4905
static void gen_srea(DisasContext *ctx)
4906
{
4907
    TCGv t0 = tcg_temp_new();
4908
    TCGv t1 = tcg_temp_new();
4909
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4910
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4911
    gen_store_spr(SPR_MQ, t0);
4912
    tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4913
    tcg_temp_free(t0);
4914
    tcg_temp_free(t1);
4915
    if (unlikely(Rc(ctx->opcode) != 0))
4916
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4917
}
4918

    
4919
/* sreq */
4920
static void gen_sreq(DisasContext *ctx)
4921
{
4922
    TCGv t0 = tcg_temp_new();
4923
    TCGv t1 = tcg_temp_new();
4924
    TCGv t2 = tcg_temp_new();
4925
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4926
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4927
    tcg_gen_shr_tl(t1, t1, t0);
4928
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4929
    gen_load_spr(t2, SPR_MQ);
4930
    gen_store_spr(SPR_MQ, t0);
4931
    tcg_gen_and_tl(t0, t0, t1);
4932
    tcg_gen_andc_tl(t2, t2, t1);
4933
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4934
    tcg_temp_free(t0);
4935
    tcg_temp_free(t1);
4936
    tcg_temp_free(t2);
4937
    if (unlikely(Rc(ctx->opcode) != 0))
4938
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4939
}
4940

    
4941
/* sriq */
4942
static void gen_sriq(DisasContext *ctx)
4943
{
4944
    int sh = SH(ctx->opcode);
4945
    TCGv t0 = tcg_temp_new();
4946
    TCGv t1 = tcg_temp_new();
4947
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4948
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4949
    tcg_gen_or_tl(t1, t0, t1);
4950
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4951
    gen_store_spr(SPR_MQ, t1);
4952
    tcg_temp_free(t0);
4953
    tcg_temp_free(t1);
4954
    if (unlikely(Rc(ctx->opcode) != 0))
4955
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4956
}
4957

    
4958
/* srliq */
4959
static void gen_srliq(DisasContext *ctx)
4960
{
4961
    int sh = SH(ctx->opcode);
4962
    TCGv t0 = tcg_temp_new();
4963
    TCGv t1 = tcg_temp_new();
4964
    tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4965
    gen_load_spr(t1, SPR_MQ);
4966
    gen_store_spr(SPR_MQ, t0);
4967
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU >> sh));
4968
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4969
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4970
    tcg_temp_free(t0);
4971
    tcg_temp_free(t1);
4972
    if (unlikely(Rc(ctx->opcode) != 0))
4973
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974
}
4975

    
4976
/* srlq */
4977
static void gen_srlq(DisasContext *ctx)
4978
{
4979
    int l1 = gen_new_label();
4980
    int l2 = gen_new_label();
4981
    TCGv t0 = tcg_temp_local_new();
4982
    TCGv t1 = tcg_temp_local_new();
4983
    TCGv t2 = tcg_temp_local_new();
4984
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4985
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4986
    tcg_gen_shr_tl(t2, t1, t2);
4987
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4988
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4989
    gen_load_spr(t0, SPR_MQ);
4990
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4991
    tcg_gen_br(l2);
4992
    gen_set_label(l1);
4993
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4994
    tcg_gen_and_tl(t0, t0, t2);
4995
    gen_load_spr(t1, SPR_MQ);
4996
    tcg_gen_andc_tl(t1, t1, t2);
4997
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4998
    gen_set_label(l2);
4999
    tcg_temp_free(t0);
5000
    tcg_temp_free(t1);
5001
    tcg_temp_free(t2);
5002
    if (unlikely(Rc(ctx->opcode) != 0))
5003
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5004
}
5005

    
5006
/* srq */
5007
static void gen_srq(DisasContext *ctx)
5008
{
5009
    int l1 = gen_new_label();
5010
    TCGv t0 = tcg_temp_new();
5011
    TCGv t1 = tcg_temp_new();
5012
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5013
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5014
    tcg_gen_subfi_tl(t1, 32, t1);
5015
    tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5016
    tcg_gen_or_tl(t1, t0, t1);
5017
    gen_store_spr(SPR_MQ, t1);
5018
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
50