Statistics
| Branch: | Revision:

root / tcg @ efe72c8d

# Date Author Comment
efe72c8d 04/17/2010 07:00 am malc

tcg/ppc: Fix signed versions of brcond2

Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.

Signed-off-by: malc <>

60bf84cf 04/14/2010 01:59 am Stefan Weil

tcp/mips: Change TCG_AREG0 (fp -> s0)

Register fp (frame pointer) is a bad choice for compilations
without optimisation, because the compiler makes heavy use
of this register (so the resulting code crashes).

Register s0 had been used for TCG_AREG1 in earlier releases,...

837d987b 04/10/2010 04:36 am Aurelien Jarno

tcg/README: improve description of bswap*

Signed-off-by: Aurelien Jarno <>

3e1f46ea 04/08/2010 12:57 pm Richard Henderson

tcg-hppa: Don't try to calls to non-constant addresses.

PA-RISC uses procedure descriptors. We'd need to emit a call to
the millicode routine $$dyncall. However, this situation doesn't
actually arise, since we always have the descriptor available at
TCG code generation time....

91493631 04/08/2010 12:57 pm Richard Henderson

tcg-hppa: Fix in/out register overlap in add2/sub2.

Handle the output log part overlapping the input high parts.
Also, improve sub2 to handle some constants the second input low part.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a175b996 04/08/2010 12:11 pm Aurelien Jarno

tcg/ia64: fix tlb addend read

Signed-off-by: Aurelien Jarno <>

fd76e73a 04/08/2010 12:11 pm Richard Henderson

tcg-hppa: Finish the port.

Delete inline functions from tcg-target.h that don't need to be there,
move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for
0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE support
similar to ppc64, with the value stored in a register. Add missing...

98926b0a 04/07/2010 01:26 am malc

tcg/ppc64: Fix typo

Signed-off-by: malc <>

f7e2aca8 04/06/2010 02:10 am malc

tcg/ppc: Fix typo

Signed-off-by: malc <>

a884dcb8 04/06/2010 01:54 am malc

tcg/ppc: Implment bswap16/32

Signed-off-by: malc <>

ba0d89bb 04/05/2010 04:16 pm Aurelien Jarno

tcg/mips: fix 64-bit linux-user on big endian MIPS

Signed-off-by: Aurelien Jarno <>

116348de 04/05/2010 04:16 pm Aurelien Jarno

tcg/mips: use seb/seh instructions on MIPS32R2

Signed-off-by: Aurelien Jarno <>

aa77bebd 04/05/2010 03:09 pm malc

tcg/ppc: Implement eqv, nand and nor

Signed-off-by: malc <>

355b1943 04/05/2010 02:28 am Paul Brook

Split TLB addend and target_phys_addr_t

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t). However since the introduction of...

36368cf0 04/04/2010 07:36 pm malc

tcg/ppc: Fix not_i32

Thanks to Alexander Graf for bug report and a good reproducible test
case.

Signed-off-by: malc <>

a18f844f 04/01/2010 11:00 pm Aurelien Jarno

tcg/TODO: remove setcond

Signed-off-by: Aurelien Jarno <>

477ba620 04/01/2010 10:51 pm Aurelien Jarno

tcg: initial ia64 support

A few words about design choices:
  • On IA64, instructions should be grouped by bundle, and dependencies
    between instructions declared. A first version of this code tried to
    schedule instructions automatically, but was very complex and too...
6d8ff4d8 03/29/2010 03:09 am Aurelien Jarno

tcg/mips: fix branch offset during retranslation

Branch offsets should only be overwritten during relocation, to support
partial retranslation.

Signed-off-by: Aurelien Jarno <>

1584c845 03/28/2010 05:39 pm Stefan Weil

tcg/arm: Replace qemu_ld32u (left over from previous commit)

Commit 86feb1c860dc38e9c89e787c5210e8191800385e
did not change all occurrences of INDEX_op_qemu_ld32u
for tcg/arm.

Please note that I could not test this patch
(I have currently no arm system available)....

cc01cc8e 03/27/2010 06:31 pm Aurelien Jarno

tcg-mips: add guest base support

Signed-off-by: Aurelien Jarno <>

489722cf 03/27/2010 05:50 pm Aurelien Jarno

tcg/mips: implement the not_i32 op the same way as gcc

Signed-off-by: Aurelien Jarno <>

2b79487a 03/27/2010 05:32 pm Aurelien Jarno

tcg-mips: implement nor

Signed-off-by: Aurelien Jarno <>

86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...

32d98fbd 03/26/2010 10:52 pm Richard Henderson

tcg: Allow target-specific implementation of NOR.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

9940a96b 03/26/2010 10:44 pm Richard Henderson

tcg: Allow target-specific implementation of NAND.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

8d625cf1 03/26/2010 10:42 pm Richard Henderson

tcg: Allow target-specific implementation of EQV.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a10f9f4f 03/26/2010 10:29 pm Richard Henderson

tcg: Use not_i32 to implement not_i64.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

c02244a5 03/26/2010 10:29 pm Richard Henderson

tcg: Change TCGType to an enumeration.

The TCGType name was already used consistently. Changing it
to an enumeration instead of a set of defines aids debugging.

Signed-off-by: Aurelien Jarno <>

8a56e840 03/26/2010 10:29 pm Richard Henderson

tcg: Use TCGCond where appropriate.

Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a63b5829 03/26/2010 09:48 pm Paolo Bonzini

remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>

3f90f252 03/23/2010 11:00 pm Richard Henderson

tcg-hppa: Fix 64-bit argument ordering

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

9e97d8e9 03/20/2010 01:27 pm Aurelien Jarno

tcg/arm: don't save/restore r7 in prologue/epilogue

There is no need to save r7, it is used to store the address
of the env structure and is not modified by GCC.

Signed-off-by: Aurelien Jarno <>

26c5d372 03/20/2010 01:10 pm Aurelien Jarno

tcg/arm: fix load/store definitions for 32-bit targets

Signed-off-by: Aurelien Jarno <>

30138f28 03/20/2010 12:17 pm Aurelien Jarno

tcg: protect div2 in tcg/tcg-opc.h

Signed-off-by: Aurelien Jarno <>

dbfff4de 03/15/2010 12:01 am Aurelien Jarno

tcg: declare internal helpers as const and pure

TCG internal helpers only access to the values passed in arguments, and
do not modify the CPU internal state. Thus they can be declared as
const and pure.

Signed-off-by: Aurelien Jarno <>

2b71cd72 03/14/2010 11:04 pm Aurelien Jarno

tcg/arm: use helpers for divu/remu

Signed-off-by: Aurelien Jarno <>

31d66551 03/14/2010 11:04 pm Aurelien Jarno

tcg: add div/rem 32-bit helpers

Some targets like ARM would benefit to use 32-bit helpers for
div/rem/divu/remu.

Create a #define for div2 so that targets can select between
div, div2 and helper implementation. Use the helper version if none
of the #define are present....

a6c6f76c 03/13/2010 04:18 pm Blue Swirl

Fix build with -DNDEBUG in CFLAGS

Signed-off-by: Blue Swirl <>

932234f6 03/13/2010 12:46 pm Aurelien Jarno

tcg/arm: implement andc op

Signed-off-by: Aurelien Jarno <>

a3f5054b 03/13/2010 12:44 pm Aurelien Jarno

tcg: update README with const and pure helpers

Signed-off-by: Aurelien Jarno <>

4e17eae9 03/13/2010 12:44 pm Aurelien Jarno

tcg/arm: correctly save/restore registers in prologue/epilogue

Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes
on ARM hosts. This is not a bug of this commit, but a latent bug
revealed by this commit.

The TCG code is called through a procedure call using the prologue...

65850a02 03/13/2010 11:52 am Blue Swirl

Fix Sparc host build breakage

Fix error:
CC sparc-bsd-user/op_helper.o
In file included from /src/qemu/tcg/tcg.c:158:
/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined

Signed-off-by: Blue Swirl <>

35f6b599 03/12/2010 11:27 pm malc

tcg/ppc64: Only define addend load helpers in softmmu case

Signed-off-by: malc <>

20cb400d 03/12/2010 08:34 pm Paul Brook

Remove TLB from userspace

Remove TLB from userspace CPU structure.

Signed-off-by: Paul Brook <>

d3f137e3 03/03/2010 12:12 am Aurelien Jarno

tcg/arm: merge the two sets of #define for optional ops

Signed-off-by: Aurelien Jarno <>

023e77f8 03/02/2010 11:31 pm Aurelien Jarno

tcg/arm: accept immediate arguments for brcond/setcond

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

b525f0a9 03/02/2010 11:26 pm Andrzej Zaborowski

Add a missing break

e0404769 03/02/2010 11:19 pm Aurelien Jarno

tcg/arm: implement setcond2

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

f72a6cd7 03/02/2010 11:17 pm Aurelien Jarno

tcg/arm: implement setcond

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

6b658613 03/02/2010 09:19 pm Aurelien Jarno

tcg/arm: fix div2/divu2

When restoring register values, increase the stack register for skipped
values.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Andrzej Zaborowski <>

d616cf1d 02/27/2010 01:00 am malc

tcg/ppc: Fix right rotation

Signed-off-by: malc <>

98b8d951 02/22/2010 11:50 pm malc

tcg/ppc: Fix typo

Signed-off-by: malc <>

d34f4baf 02/22/2010 08:56 pm malc

tcg/ppc64: Use C90 style comments

Signed-off-by: malc <>

65fe043e 02/22/2010 08:50 pm malc

tcg/ppc: Implement some of the optional ops

Signed-off-by: malc <>

30c0c76c 02/22/2010 06:38 pm Jay Foad

tcg: fix build on 32-bit hppa, ppc and sparc hosts

The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <>
Signed-off-by: malc <>

2c92d62e 02/20/2010 12:26 pm Jay Foad

tcg: fix assertion with --enable-debug

On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the
following assertion failure:

qemu-alpha: tcg/tcg.c:1055:
tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.

Signed-off-by: Jay Foad <>...

36828256 02/20/2010 10:35 am Richard Henderson

tcg: Add comments for all optional instructions not implemented.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

18c8f7a3 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ORC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

dc69960d 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ANDC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

791d1262 02/20/2010 10:33 am Richard Henderson

tcg: Optional target implementation of ORC.

Previously ORC was always implemented by tcg-op.h with
an explicit NOT opcode. Allow a target implementation.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

241cbed4 02/20/2010 10:33 am Richard Henderson

tcg: Optional target implementation of ANDC.

Previously ANDC was always implemented by tcg-op.h with
an explicit NOT opcode. Allow a target implementation.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

be6551b1 02/20/2010 10:32 am Richard Henderson

tcg-sparc: Implement not.

The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

4b5a85c1 02/20/2010 10:31 am Richard Henderson

tcg-sparc: Implement neg.

The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <>...

6ec85236 02/20/2010 12:47 am malc

tcg/ppc: Consistently use calling convention selection macros

Signed-off-by: malc <>

5da79c86 02/20/2010 12:37 am Juergen Lock

Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}.

New version after malc's comments. (This avoids having to do
#if defined linux || defined FreeBSD || defined FreeBSD_kernel
for the third case.)
...

c68aaa18 02/18/2010 09:08 pm Stefan Weil

tcg: Add consistency checks for op definitions

When compiled with CONFIG_DEBUG_TCG, this code looks
for missing, duplicate and wrong entries in the
op definitions.

Errors will raise an assertion at program start
(all checks are done in the initial phase)....

dbfe80e1 02/16/2010 07:53 pm Richard Henderson

tcg-sparc: Implement setcond, setcond2.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

1c086220 02/16/2010 07:52 pm Richard Henderson

tcg: Add tcg_swap_cond.

Returns the condition as if with swapped comparison operands.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

cca1af8c 02/09/2010 11:54 pm Aurelien Jarno

tcg/mips: fix crash in tcg_out_qemu_ld()

The address register is overriden when it corresponds to v0 and the fast
path is taken, which leads to a crash. Fix that by using the a0 register
instead.

Signed-off-by: Aurelien Jarno <>

434254aa 02/09/2010 02:01 am Aurelien Jarno

tcg/mips: implement setcond2

Signed-off-by: Aurelien Jarno <>

4cb26382 02/08/2010 05:37 pm Aurelien Jarno

tcg/mips: implement setcond

Signed-off-by: Aurelien Jarno <>

5105c556 02/08/2010 01:10 pm Aurelien Jarno

tcg: move setcond* ops to non-optional section

setcond is not an optional op, move it to the non-optional section.

Signed-off-by: Aurelien Jarno <>

add1e7ea 02/08/2010 01:06 pm Aurelien Jarno

tcg: add setcondi pseudo-op

Signed-off-by: Aurelien Jarno <>

1cd62ae9 02/07/2010 01:48 am malc

tcg/ppc64: implement setcond

Signed-off-by: malc <>

27a7797b 02/07/2010 01:48 am malc

tcg/ppc32: proper setcond implementation

Signed-off-by: malc <>

b0809bf7 02/07/2010 01:18 am malc

tcg/ppc32: implement setcond2

Signed-off-by: malc <>

1d2699ae 02/06/2010 11:23 pm Richard Henderson

tcg-i386: Implement setcond.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

f75b56c1 02/06/2010 11:23 pm Richard Henderson

tcg-i386: Implement small forward branches.

There are places, like brcond2, where we know that the destination
of a forward branch will be within 127 bytes.

Add the R_386_PC8 relocation type to support this. Add a flag to
tcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the...

a38e609c 02/06/2010 06:14 pm Richard Henderson

tcg: document double-word support opcodes.

The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.

Signed-off-by: Richard Henderson <>...

be210acb 02/06/2010 06:14 pm Richard Henderson

tcg: generic support for conditional set

Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

401d466d 02/06/2010 06:14 pm Richard Henderson

tcg: add tcg_invert_cond

It is very handy to have a reliable mapping of a condition to its inverse.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

8f9db67c 02/06/2010 06:14 pm Richard Henderson

tcg-x86_64: implement setcond

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

09aac126 01/15/2010 08:32 am Richard Henderson

tcg/x86_64: Avoid unnecessary REX.B prefixes.

The existing P_REXB internal opcode flag unconditionally emits
the REX prefix. Technically it's not needed if the register in
question is %al, %bl, %cl, %dl.

Eliding the prefix requires splitting the P_REXB flag into two,...

57169903 01/14/2010 07:16 pm Richard Henderson

tcg/x86_64: Special-case all 32-bit AND operands.

This avoids an unnecessary REX.W prefix when dealing with AND
operands that fit into a 32-bit quantity. The most common change
actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes....

cc6dfecf 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement ext32[su]_i64

The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits. A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <>...

583d1215 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement division properly.

The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder. Sparc
is not such a system. Indeed, the remainder must be computed as

quot = a / b
rem = a - (quot * b)...
5e143c43 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Do not remove %o012 from 'r' constraint.

Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

7a3766f3 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement add2, sub2, mulu2.

Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

ba225198 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Add tcg_out_arithc.

Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well....

ff44c2f3 12/27/2009 11:09 am Richard Henderson

tcg: Add tcg_unsigned_cond.

Returns an unsigned version of a signed condition;
returns the original condition otherwise.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

56f4927e 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Implement brcond2.

Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

a212ea75 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.

The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving sparc_v9 or
sparc_v8plus should be reserved for something ISA related,
as with SMULX....

43172207 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Improve tcg_out_movi for sparc64.

Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <>...

4a09aa89 12/21/2009 10:49 pm Richard Henderson

tcg-sparc: Fix imm13 check in movi.

We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

591d6f1d 12/15/2009 06:45 pm malc

tcg/ppc64: Fix loading of 32bit constants

Signed-off-by: malc <>

5d7ff5bb 12/06/2009 05:20 pm Andreas Faerber

TCG: Mac OS X support for ppc64 target

Darwin/ppc64 does not use function descriptors,
adapt prologue and tcg_out_call accordingly.
GPR2 is available for general use, so let's use it.

http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...

2827822e 12/05/2009 06:36 pm Alexander Graf

S/390 fake TCG implementation

Qemu won't let us run a KVM target without having host TCG support. Well, for
now we don't have any so let's implement a fake target that only stubs out
everything.

I tried to keep the patch as close to Uli's source as possible, so whenever...

afa05235 12/01/2009 02:06 am Aurelien Jarno

tcg: initial mips support

Based on a patch from Arnaud Patard (Rtp) <>

A few words about design choices:
  • Two registers, at and t0, are reserved for TCG internal use. They are
    useful for bswap and 64-bit ops.
  • Most ops supports a constant argument with value 0, which is actually...
7d301752 11/24/2009 08:51 pm Aurelien Jarno

tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers

Signed-off-by: Aurelien Jarno <>