Revision f01be154 target-mips/cpu.h

b/target-mips/cpu.h
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#define FCR0_REV 0
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    /* fcsr */
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    uint32_t fcr31;
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#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
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#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
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#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
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#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
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#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
......
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#define MIPS_SHADOW_SET_MAX 16


  		





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#define MIPS_TC_MAX 5


  		





  
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#define MIPS_FPU_MAX 1


  		





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#define MIPS_DSP_ACC 4


  		





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typedef struct TCState TCState;


  		





  ......




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typedef struct CPUMIPSState CPUMIPSState;


  		





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struct CPUMIPSState {


  		





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    TCState active_tc;


  		





  
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    CPUMIPSFPUContext active_fpu;


  		





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    CPUMIPSMVPContext *mvp;


  		





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    CPUMIPSTLBContext *tlb;


  		





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    CPUMIPSFPUContext *fpu;


  		





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    uint32_t current_tc;


  		





  
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    uint32_t current_fpu;


  		





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    uint32_t SEGBITS;


  		





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    uint32_t PABITS;


  		





  ......




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    int32_t CP0_DESAVE;


  		





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    /* We waste some space so we can handle shadow registers like TCs. */


  		





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    TCState tcs[MIPS_SHADOW_SET_MAX];


  		





  
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    CPUMIPSFPUContext fpus[MIPS_FPU_MAX];


  		





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    /* Qemu */


  		





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    int error_code;


  		





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    uint32_t hflags;    /* CPU State */


  		












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