Revision f01be154 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 423 | 423 |
}; |
| 424 | 424 |
|
| 425 | 425 |
/* global register indices */ |
| 426 |
static TCGv cpu_env, bcond, btarget, current_fpu; |
|
| 426 |
static TCGv cpu_env, bcond, btarget; |
|
| 427 |
static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31; |
|
| 427 | 428 |
|
| 428 | 429 |
#include "gen-icount.h" |
| 429 | 430 |
|
| ... | ... | |
| 547 | 548 |
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 548 | 549 |
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; |
| 549 | 550 |
|
| 551 |
static const char *fregnames_64[] = |
|
| 552 |
{ "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
|
|
| 553 |
"F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", |
|
| 554 |
"F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", |
|
| 555 |
"F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", }; |
|
| 556 |
|
|
| 557 |
static const char *fregnames_h[] = |
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| 558 |
{ "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
|
|
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"h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", |
|
| 560 |
"h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", |
|
| 561 |
"h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", }; |
|
| 562 |
|
|
| 550 | 563 |
#ifdef MIPS_DEBUG_DISAS |
| 551 | 564 |
#define MIPS_DEBUG(fmt, args...) \ |
| 552 | 565 |
do { \
|
| ... | ... | |
| 652 | 665 |
/* Floating point register moves. */ |
| 653 | 666 |
static inline void gen_load_fpr32 (TCGv t, int reg) |
| 654 | 667 |
{
|
| 655 |
tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
|
|
| 668 |
tcg_gen_mov_i32(t, fpu_fpr32[reg]);
|
|
| 656 | 669 |
} |
| 657 | 670 |
|
| 658 | 671 |
static inline void gen_store_fpr32 (TCGv t, int reg) |
| 659 | 672 |
{
|
| 660 |
tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
|
|
| 673 |
tcg_gen_mov_i32(fpu_fpr32[reg], t);
|
|
| 661 | 674 |
} |
| 662 | 675 |
|
| 663 | 676 |
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg) |
| 664 | 677 |
{
|
| 665 |
if (ctx->hflags & MIPS_HFLAG_F64) {
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|
| 666 |
tcg_gen_ld_i64(t, current_fpu, 8 * reg); |
|
| 667 |
} else {
|
|
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
|
| 678 |
if (ctx->hflags & MIPS_HFLAG_F64) |
|
| 679 |
tcg_gen_mov_i64(t, fpu_fpr64[reg]); |
|
| 680 |
else {
|
|
| 669 | 681 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 670 | 682 |
|
| 671 |
tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX); |
|
| 672 |
tcg_gen_extu_i32_i64(t, r_tmp1); |
|
| 683 |
tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]); |
|
| 673 | 684 |
tcg_gen_shli_i64(t, t, 32); |
| 674 |
tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX); |
|
| 675 |
tcg_gen_extu_i32_i64(r_tmp2, r_tmp1); |
|
| 685 |
tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]); |
|
| 676 | 686 |
tcg_gen_or_i64(t, t, r_tmp2); |
| 677 |
tcg_temp_free(r_tmp1); |
|
| 678 | 687 |
tcg_temp_free(r_tmp2); |
| 679 | 688 |
} |
| 680 | 689 |
} |
| 681 | 690 |
|
| 682 | 691 |
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg) |
| 683 | 692 |
{
|
| 684 |
if (ctx->hflags & MIPS_HFLAG_F64) {
|
|
| 685 |
tcg_gen_st_i64(t, current_fpu, 8 * reg); |
|
| 686 |
} else {
|
|
| 687 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 688 |
|
|
| 689 |
tcg_gen_trunc_i64_i32(r_tmp, t); |
|
| 690 |
tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX); |
|
| 693 |
if (ctx->hflags & MIPS_HFLAG_F64) |
|
| 694 |
tcg_gen_mov_i64(fpu_fpr64[reg], t); |
|
| 695 |
else {
|
|
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tcg_gen_trunc_i64_i32(fpu_fpr32[reg & ~1], t); |
|
| 691 | 697 |
tcg_gen_shri_i64(t, t, 32); |
| 692 |
tcg_gen_trunc_i64_i32(r_tmp, t); |
|
| 693 |
tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX); |
|
| 694 |
tcg_temp_free(r_tmp); |
|
| 698 |
tcg_gen_trunc_i64_i32(fpu_fpr32[reg | 1], t); |
|
| 695 | 699 |
} |
| 696 | 700 |
} |
| 697 | 701 |
|
| 698 | 702 |
static inline void gen_load_fpr32h (TCGv t, int reg) |
| 699 | 703 |
{
|
| 700 |
tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
|
|
| 704 |
tcg_gen_mov_i32(t, fpu_fpr32h[reg]);
|
|
| 701 | 705 |
} |
| 702 | 706 |
|
| 703 | 707 |
static inline void gen_store_fpr32h (TCGv t, int reg) |
| 704 | 708 |
{
|
| 705 |
tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
|
|
| 709 |
tcg_gen_mov_i32(fpu_fpr32h[reg], t);
|
|
| 706 | 710 |
} |
| 707 | 711 |
|
| 708 | 712 |
static inline void get_fp_cond (TCGv t) |
| ... | ... | |
| 710 | 714 |
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32); |
| 711 | 715 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32); |
| 712 | 716 |
|
| 713 |
tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31)); |
|
| 714 |
tcg_gen_shri_i32(r_tmp2, r_tmp1, 24); |
|
| 717 |
tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24); |
|
| 715 | 718 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe); |
| 716 |
tcg_gen_shri_i32(r_tmp1, r_tmp1, 23);
|
|
| 719 |
tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23);
|
|
| 717 | 720 |
tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1); |
| 718 | 721 |
tcg_gen_or_i32(t, r_tmp1, r_tmp2); |
| 719 | 722 |
tcg_temp_free(r_tmp1); |
| ... | ... | |
| 6009 | 6012 |
|
| 6010 | 6013 |
gen_load_gpr(t0, rd); |
| 6011 | 6014 |
gen_load_gpr(t1, rs); |
| 6012 |
tcg_gen_ld_i32(r_tmp, current_fpu, offsetof(CPUMIPSFPUContext, fcr31)); |
|
| 6013 |
tcg_gen_andi_i32(r_tmp, r_tmp, ccbit); |
|
| 6015 |
tcg_gen_andi_i32(r_tmp, fpu_fcr31, ccbit); |
|
| 6014 | 6016 |
tcg_gen_brcondi_i32(cond, r_tmp, 0, l1); |
| 6015 | 6017 |
tcg_temp_free(r_tmp); |
| 6016 | 6018 |
|
| ... | ... | |
| 6043 | 6045 |
|
| 6044 | 6046 |
gen_load_fpr32(fp0, fs); |
| 6045 | 6047 |
gen_load_fpr32(fp1, fd); |
| 6046 |
tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31)); |
|
| 6047 |
tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit); |
|
| 6048 |
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); |
|
| 6048 | 6049 |
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); |
| 6049 | 6050 |
tcg_gen_mov_i32(fp1, fp0); |
| 6050 | 6051 |
tcg_temp_free(fp0); |
| ... | ... | |
| 6075 | 6076 |
|
| 6076 | 6077 |
gen_load_fpr64(ctx, fp0, fs); |
| 6077 | 6078 |
gen_load_fpr64(ctx, fp1, fd); |
| 6078 |
tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31)); |
|
| 6079 |
tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit); |
|
| 6079 |
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); |
|
| 6080 | 6080 |
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); |
| 6081 | 6081 |
tcg_gen_mov_i64(fp1, fp0); |
| 6082 | 6082 |
tcg_temp_free(fp0); |
| ... | ... | |
| 8632 | 8632 |
|
| 8633 | 8633 |
|
| 8634 | 8634 |
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", |
| 8635 |
env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
|
|
| 8636 |
get_float_exception_flags(&env->fpu->fp_status));
|
|
| 8635 |
env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
|
|
| 8636 |
get_float_exception_flags(&env->active_fpu.fp_status));
|
|
| 8637 | 8637 |
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
|
| 8638 | 8638 |
fpu_fprintf(f, "%3s: ", fregnames[i]); |
| 8639 |
printfpr(&env->fpu->fpr[i]);
|
|
| 8639 |
printfpr(&env->active_fpu.fpr[i]);
|
|
| 8640 | 8640 |
} |
| 8641 | 8641 |
|
| 8642 | 8642 |
#undef printfpr |
| ... | ... | |
| 8706 | 8706 |
|
| 8707 | 8707 |
static void mips_tcg_init(void) |
| 8708 | 8708 |
{
|
| 8709 |
int i; |
|
| 8709 | 8710 |
static int inited; |
| 8710 | 8711 |
|
| 8711 | 8712 |
/* Initialize various static tables. */ |
| ... | ... | |
| 8717 | 8718 |
offsetof(CPUState, bcond), "bcond"); |
| 8718 | 8719 |
btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 8719 | 8720 |
offsetof(CPUState, btarget), "btarget"); |
| 8720 |
current_fpu = tcg_global_mem_new(TCG_TYPE_PTR, |
|
| 8721 |
TCG_AREG0, |
|
| 8722 |
offsetof(CPUState, fpu), |
|
| 8723 |
"current_fpu"); |
|
| 8721 |
for (i = 0; i < 32; i++) |
|
| 8722 |
fpu_fpr32[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
|
| 8723 |
offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]), |
|
| 8724 |
fregnames[i]); |
|
| 8725 |
for (i = 0; i < 32; i++) |
|
| 8726 |
fpu_fpr64[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
|
| 8727 |
offsetof(CPUState, active_fpu.fpr[i]), |
|
| 8728 |
fregnames_64[i]); |
|
| 8729 |
for (i = 0; i < 32; i++) |
|
| 8730 |
fpu_fpr32h[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
|
| 8731 |
offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]), |
|
| 8732 |
fregnames_h[i]); |
|
| 8733 |
fpu_fcr0 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
|
| 8734 |
offsetof(CPUState, active_fpu.fcr0), |
|
| 8735 |
"fcr0"); |
|
| 8736 |
fpu_fcr31 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
|
| 8737 |
offsetof(CPUState, active_fpu.fcr31), |
|
| 8738 |
"fcr31"); |
|
| 8724 | 8739 |
|
| 8725 | 8740 |
/* register helpers */ |
| 8726 | 8741 |
#undef DEF_HELPER |
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