root / hw / mips_mipssim.c @ f0fc6f8f
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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | f0fc6f8f | ths | */
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7 | f0fc6f8f | ths | #include "vl.h" |
8 | f0fc6f8f | ths | |
9 | f0fc6f8f | ths | #ifdef TARGET_WORDS_BIGENDIAN
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10 | f0fc6f8f | ths | #define BIOS_FILENAME "mips_bios.bin" |
11 | f0fc6f8f | ths | #else
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12 | f0fc6f8f | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
13 | f0fc6f8f | ths | #endif
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14 | f0fc6f8f | ths | |
15 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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16 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
17 | f0fc6f8f | ths | #else
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18 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
19 | f0fc6f8f | ths | #endif
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20 | f0fc6f8f | ths | |
21 | f0fc6f8f | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
22 | f0fc6f8f | ths | |
23 | f0fc6f8f | ths | static void load_kernel (CPUState *env) |
24 | f0fc6f8f | ths | { |
25 | f0fc6f8f | ths | int64_t entry, kernel_low, kernel_high; |
26 | f0fc6f8f | ths | long kernel_size;
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27 | f0fc6f8f | ths | long initrd_size;
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28 | f0fc6f8f | ths | ram_addr_t initrd_offset; |
29 | f0fc6f8f | ths | |
30 | f0fc6f8f | ths | kernel_size = load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, |
31 | f0fc6f8f | ths | &entry, &kernel_low, &kernel_high); |
32 | f0fc6f8f | ths | if (kernel_size >= 0) { |
33 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
34 | f0fc6f8f | ths | entry = (int32_t)entry; |
35 | f0fc6f8f | ths | env->PC[env->current_tc] = entry; |
36 | f0fc6f8f | ths | } else {
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37 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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38 | f0fc6f8f | ths | env->kernel_filename); |
39 | f0fc6f8f | ths | exit(1);
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40 | f0fc6f8f | ths | } |
41 | f0fc6f8f | ths | |
42 | f0fc6f8f | ths | /* load initrd */
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43 | f0fc6f8f | ths | initrd_size = 0;
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44 | f0fc6f8f | ths | initrd_offset = 0;
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45 | f0fc6f8f | ths | if (env->initrd_filename) {
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46 | f0fc6f8f | ths | initrd_size = get_image_size (env->initrd_filename); |
47 | f0fc6f8f | ths | if (initrd_size > 0) { |
48 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
49 | f0fc6f8f | ths | if (initrd_offset + initrd_size > env->ram_size) {
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50 | f0fc6f8f | ths | fprintf(stderr, |
51 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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52 | f0fc6f8f | ths | env->initrd_filename); |
53 | f0fc6f8f | ths | exit(1);
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54 | f0fc6f8f | ths | } |
55 | f0fc6f8f | ths | initrd_size = load_image(env->initrd_filename, |
56 | f0fc6f8f | ths | phys_ram_base + initrd_offset); |
57 | f0fc6f8f | ths | } |
58 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
59 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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60 | f0fc6f8f | ths | env->initrd_filename); |
61 | f0fc6f8f | ths | exit(1);
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62 | f0fc6f8f | ths | } |
63 | f0fc6f8f | ths | } |
64 | f0fc6f8f | ths | } |
65 | f0fc6f8f | ths | |
66 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
67 | f0fc6f8f | ths | { |
68 | f0fc6f8f | ths | CPUState *env = opaque; |
69 | f0fc6f8f | ths | cpu_reset(env); |
70 | f0fc6f8f | ths | cpu_mips_register(env, NULL);
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71 | f0fc6f8f | ths | |
72 | f0fc6f8f | ths | if (env->kernel_filename)
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73 | f0fc6f8f | ths | load_kernel (env); |
74 | f0fc6f8f | ths | } |
75 | f0fc6f8f | ths | |
76 | f0fc6f8f | ths | static void |
77 | f0fc6f8f | ths | mips_mipssim_init (int ram_size, int vga_ram_size, int boot_device, |
78 | f0fc6f8f | ths | DisplayState *ds, const char **fd_filename, int snapshot, |
79 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
80 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
81 | f0fc6f8f | ths | { |
82 | f0fc6f8f | ths | char buf[1024]; |
83 | f0fc6f8f | ths | unsigned long bios_offset; |
84 | f0fc6f8f | ths | CPUState *env; |
85 | f0fc6f8f | ths | int ret;
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86 | f0fc6f8f | ths | mips_def_t *def; |
87 | f0fc6f8f | ths | |
88 | f0fc6f8f | ths | /* Init CPUs. */
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89 | f0fc6f8f | ths | if (cpu_model == NULL) { |
90 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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91 | f0fc6f8f | ths | cpu_model = "5Kf";
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92 | f0fc6f8f | ths | #else
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93 | f0fc6f8f | ths | cpu_model = "24Kf";
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94 | f0fc6f8f | ths | #endif
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95 | f0fc6f8f | ths | } |
96 | f0fc6f8f | ths | if (mips_find_by_name(cpu_model, &def) != 0) |
97 | f0fc6f8f | ths | def = NULL;
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98 | f0fc6f8f | ths | env = cpu_init(); |
99 | f0fc6f8f | ths | cpu_mips_register(env, def); |
100 | f0fc6f8f | ths | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
101 | f0fc6f8f | ths | qemu_register_reset(main_cpu_reset, env); |
102 | f0fc6f8f | ths | |
103 | f0fc6f8f | ths | /* Allocate RAM. */
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104 | f0fc6f8f | ths | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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105 | f0fc6f8f | ths | |
106 | f0fc6f8f | ths | /* Map the BIOS / boot exception handler. */
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107 | f0fc6f8f | ths | bios_offset = ram_size + vga_ram_size; |
108 | f0fc6f8f | ths | |
109 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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110 | f0fc6f8f | ths | if (bios_name == NULL) |
111 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
112 | f0fc6f8f | ths | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
113 | f0fc6f8f | ths | ret = load_image(buf, phys_ram_base + bios_offset); |
114 | f0fc6f8f | ths | if ((ret < 0 || ret > BIOS_SIZE) && !kernel_filename) { |
115 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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116 | f0fc6f8f | ths | fprintf(stderr, |
117 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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118 | f0fc6f8f | ths | buf); |
119 | f0fc6f8f | ths | exit(1);
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120 | f0fc6f8f | ths | } else {
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121 | f0fc6f8f | ths | /* We have a boot vector start address. */
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122 | f0fc6f8f | ths | env->PC[env->current_tc] = (target_long)0xbfc00000;
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123 | f0fc6f8f | ths | cpu_register_physical_memory(0x1fc00000LL,
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124 | f0fc6f8f | ths | ret, bios_offset | IO_MEM_ROM); |
125 | f0fc6f8f | ths | } |
126 | f0fc6f8f | ths | |
127 | f0fc6f8f | ths | if (kernel_filename) {
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128 | f0fc6f8f | ths | env->ram_size = ram_size; |
129 | f0fc6f8f | ths | env->kernel_filename = kernel_filename; |
130 | f0fc6f8f | ths | env->kernel_cmdline = kernel_cmdline; |
131 | f0fc6f8f | ths | env->initrd_filename = initrd_filename; |
132 | f0fc6f8f | ths | load_kernel(env); |
133 | f0fc6f8f | ths | } |
134 | f0fc6f8f | ths | |
135 | f0fc6f8f | ths | /* Init CPU internal devices. */
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136 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
137 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
138 | f0fc6f8f | ths | cpu_mips_irqctrl_init(); |
139 | f0fc6f8f | ths | |
140 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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141 | f0fc6f8f | ths | isa_mmio_init(0x1fd00000, 0x00010000); |
142 | f0fc6f8f | ths | |
143 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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144 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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145 | f0fc6f8f | ths | if (serial_hds[0]) |
146 | f0fc6f8f | ths | serial_init(0x3f8, env->irq[4], serial_hds[0]); |
147 | f0fc6f8f | ths | |
148 | f0fc6f8f | ths | if (nd_table[0].vlan) { |
149 | f0fc6f8f | ths | if (nd_table[0].model == NULL |
150 | f0fc6f8f | ths | || strcmp(nd_table[0].model, "mipsnet") == 0) { |
151 | f0fc6f8f | ths | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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152 | f0fc6f8f | ths | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
153 | f0fc6f8f | ths | } else if (strcmp(nd_table[0].model, "?") == 0) { |
154 | f0fc6f8f | ths | fprintf(stderr, "qemu: Supported NICs: mipsnet\n");
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155 | f0fc6f8f | ths | exit (1);
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156 | f0fc6f8f | ths | } else {
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157 | f0fc6f8f | ths | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
158 | f0fc6f8f | ths | exit (1);
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159 | f0fc6f8f | ths | } |
160 | f0fc6f8f | ths | } |
161 | f0fc6f8f | ths | } |
162 | f0fc6f8f | ths | |
163 | f0fc6f8f | ths | QEMUMachine mips_mipssim_machine = { |
164 | f0fc6f8f | ths | "mipssim",
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165 | f0fc6f8f | ths | "MIPS MIPSsim platform",
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166 | f0fc6f8f | ths | mips_mipssim_init, |
167 | f0fc6f8f | ths | }; |