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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "fdc.h" |
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#include "pci.h" |
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#include "block.h" |
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#include "sysemu.h" |
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#include "audio/audio.h" |
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#include "net.h" |
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#include "smbus.h" |
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#include "boards.h" |
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#include "monitor.h" |
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#include "fw_cfg.h" |
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#include "hpet_emul.h" |
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#include "watchdog.h" |
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#include "smbios.h" |
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|
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/* output Bochs bios info messages */
|
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//#define DEBUG_BIOS
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|
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/* Show multiboot debug output */
|
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//#define DEBUG_MULTIBOOT
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|
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#define BIOS_FILENAME "bios.bin" |
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#define VGABIOS_FILENAME "vgabios.bin" |
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
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|
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
| 51 |
|
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
|
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#define ACPI_DATA_SIZE 0x10000 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
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|
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#define MAX_IDE_BUS 2 |
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|
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
|
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static PITState *pit;
|
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static IOAPICState *ioapic;
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static PCIDevice *i440fx_state;
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|
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typedef struct rom_reset_data { |
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uint8_t *data; |
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target_phys_addr_t addr; |
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unsigned size;
|
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} RomResetData; |
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|
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static void option_rom_reset(void *_rrd) |
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{
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RomResetData *rrd = _rrd; |
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|
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cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); |
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} |
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|
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static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) |
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{
|
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RomResetData *rrd = qemu_malloc(sizeof *rrd);
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|
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rrd->data = qemu_malloc(size); |
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cpu_physical_memory_read(addr, rrd->data, size); |
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rrd->addr = addr; |
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rrd->size = size; |
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qemu_register_reset(option_rom_reset, 0, rrd);
|
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} |
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|
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
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{
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} |
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|
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
|
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/* XXX: add IGNNE support */
|
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void cpu_set_ferr(CPUX86State *s)
|
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{
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qemu_irq_raise(ferr_irq); |
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} |
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|
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
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{
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qemu_irq_lower(ferr_irq); |
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} |
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|
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{
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/* Note: when using kqemu, it is more logical to return the host TSC
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because kqemu does not trap the RDTSC instruction for
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performance reasons */
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#ifdef CONFIG_KQEMU
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if (env->kqemu_enabled) {
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return cpu_get_real_ticks();
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} else
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#endif
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{
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return cpu_get_ticks();
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} |
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} |
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|
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/* SMM support */
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void cpu_smm_update(CPUState *env)
|
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{
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if (i440fx_state && env == first_cpu)
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i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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} |
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|
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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int intno;
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|
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intno = apic_get_interrupt(env); |
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if (intno >= 0) { |
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/* set irq request if a PIC irq is still pending */
|
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/* XXX: improve that */
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pic_update_irq(isa_pic); |
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return intno;
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} |
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env))
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return -1; |
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intno = pic_read_irq(isa_pic); |
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return intno;
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} |
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|
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static void pic_irq_request(void *opaque, int irq, int level) |
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{
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CPUState *env = first_cpu; |
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|
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env))
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apic_deliver_pic_intr(env, level); |
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env = env->next_cpu; |
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} |
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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|
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/* PC cmos mappings */
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|
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#define REG_EQUIPMENT_BYTE 0x14 |
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|
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static int cmos_get_fd_drive_type(int fd0) |
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{
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int val;
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switch (fd0) {
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case 0: |
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case 1: |
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case 2: |
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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default:
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val = 0;
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break;
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} |
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return val;
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} |
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|
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
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{
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RTCState *s = rtc_state; |
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders); |
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff); |
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rtc_set_memory(s, info_ofs + 4, 0xff); |
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 8, sectors);
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} |
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|
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device) |
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{
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switch(boot_device) {
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case 'a': |
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case 'b': |
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return 0x01; /* floppy boot */ |
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case 'c': |
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return 0x02; /* hard drive boot */ |
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case 'd': |
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return 0x03; /* CD-ROM boot */ |
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case 'n': |
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return 0x04; /* Network boot */ |
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} |
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return 0; |
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} |
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|
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/* copy/pasted from cmos_init, should be made a general function
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and used there as well */
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static int pc_boot_set(void *opaque, const char *boot_device) |
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{
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Monitor *mon = cur_mon; |
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#define PC_MAX_BOOT_DEVICES 3 |
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RTCState *s = (RTCState *)opaque; |
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int nbds, bds[3] = { 0, }; |
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int i;
|
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|
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nbds = strlen(boot_device); |
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if (nbds > PC_MAX_BOOT_DEVICES) {
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monitor_printf(mon, "Too many boot devices for PC\n");
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return(1); |
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
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if (bds[i] == 0) { |
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monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
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boot_device[i]); |
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return(1); |
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4)); |
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return(0); |
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} |
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|
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/* hd_table must contain 4 block drivers */
|
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
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const char *boot_device, BlockDriverState **hd_table) |
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{
|
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RTCState *s = rtc_state; |
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int nbds, bds[3] = { 0, }; |
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int val;
|
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int fd0, fd1, nb;
|
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int i;
|
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|
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/* various important CMOS locations needed by PC/Bochs bios */
|
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|
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/* memory size */
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val = 640; /* base memory in K */ |
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rtc_set_memory(s, 0x15, val);
|
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rtc_set_memory(s, 0x16, val >> 8); |
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|
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val = (ram_size / 1024) - 1024; |
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if (val > 65535) |
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val = 65535;
|
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rtc_set_memory(s, 0x17, val);
|
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rtc_set_memory(s, 0x18, val >> 8); |
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rtc_set_memory(s, 0x30, val);
|
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rtc_set_memory(s, 0x31, val >> 8); |
| 283 |
|
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if (above_4g_mem_size) {
|
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
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rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
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rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
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} |
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|
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if (ram_size > (16 * 1024 * 1024)) |
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
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else
|
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val = 0;
|
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if (val > 65535) |
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val = 65535;
|
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rtc_set_memory(s, 0x34, val);
|
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rtc_set_memory(s, 0x35, val >> 8); |
| 298 |
|
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/* set the number of CPU */
|
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rtc_set_memory(s, 0x5f, smp_cpus - 1); |
| 301 |
|
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/* set boot devices, and disable floppy signature check if requested */
|
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#define PC_MAX_BOOT_DEVICES 3 |
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nbds = strlen(boot_device); |
| 305 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
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fprintf(stderr, "Too many boot devices for PC\n");
|
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exit(1);
|
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} |
| 309 |
for (i = 0; i < nbds; i++) { |
| 310 |
bds[i] = boot_device2nibble(boot_device[i]); |
| 311 |
if (bds[i] == 0) { |
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fprintf(stderr, "Invalid boot device for PC: '%c'\n",
|
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boot_device[i]); |
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exit(1);
|
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} |
| 316 |
} |
| 317 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
| 318 |
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
| 319 |
|
| 320 |
/* floppy type */
|
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|
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fd0 = fdctrl_get_drive_type(floppy_controller, 0);
|
| 323 |
fd1 = fdctrl_get_drive_type(floppy_controller, 1);
|
| 324 |
|
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val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
|
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rtc_set_memory(s, 0x10, val);
|
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|
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val = 0;
|
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nb = 0;
|
| 330 |
if (fd0 < 3) |
| 331 |
nb++; |
| 332 |
if (fd1 < 3) |
| 333 |
nb++; |
| 334 |
switch (nb) {
|
| 335 |
case 0: |
| 336 |
break;
|
| 337 |
case 1: |
| 338 |
val |= 0x01; /* 1 drive, ready for boot */ |
| 339 |
break;
|
| 340 |
case 2: |
| 341 |
val |= 0x41; /* 2 drives, ready for boot */ |
| 342 |
break;
|
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} |
| 344 |
val |= 0x02; /* FPU is there */ |
| 345 |
val |= 0x04; /* PS/2 mouse installed */ |
| 346 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
| 347 |
|
| 348 |
/* hard drives */
|
| 349 |
|
| 350 |
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
| 351 |
if (hd_table[0]) |
| 352 |
cmos_init_hd(0x19, 0x1b, hd_table[0]); |
| 353 |
if (hd_table[1]) |
| 354 |
cmos_init_hd(0x1a, 0x24, hd_table[1]); |
| 355 |
|
| 356 |
val = 0;
|
| 357 |
for (i = 0; i < 4; i++) { |
| 358 |
if (hd_table[i]) {
|
| 359 |
int cylinders, heads, sectors, translation;
|
| 360 |
/* NOTE: bdrv_get_geometry_hint() returns the physical
|
| 361 |
geometry. It is always such that: 1 <= sects <= 63, 1
|
| 362 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
| 363 |
geometry can be different if a translation is done. */
|
| 364 |
translation = bdrv_get_translation_hint(hd_table[i]); |
| 365 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
| 366 |
bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
| 367 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
| 368 |
/* No translation. */
|
| 369 |
translation = 0;
|
| 370 |
} else {
|
| 371 |
/* LBA translation. */
|
| 372 |
translation = 1;
|
| 373 |
} |
| 374 |
} else {
|
| 375 |
translation--; |
| 376 |
} |
| 377 |
val |= translation << (i * 2);
|
| 378 |
} |
| 379 |
} |
| 380 |
rtc_set_memory(s, 0x39, val);
|
| 381 |
} |
| 382 |
|
| 383 |
void ioport_set_a20(int enable) |
| 384 |
{
|
| 385 |
/* XXX: send to all CPUs ? */
|
| 386 |
cpu_x86_set_a20(first_cpu, enable); |
| 387 |
} |
| 388 |
|
| 389 |
int ioport_get_a20(void) |
| 390 |
{
|
| 391 |
return ((first_cpu->a20_mask >> 20) & 1); |
| 392 |
} |
| 393 |
|
| 394 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
| 395 |
{
|
| 396 |
ioport_set_a20((val >> 1) & 1); |
| 397 |
/* XXX: bit 0 is fast reset */
|
| 398 |
} |
| 399 |
|
| 400 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
| 401 |
{
|
| 402 |
return ioport_get_a20() << 1; |
| 403 |
} |
| 404 |
|
| 405 |
/***********************************************************/
|
| 406 |
/* Bochs BIOS debug ports */
|
| 407 |
|
| 408 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
| 409 |
{
|
| 410 |
static const char shutdown_str[8] = "Shutdown"; |
| 411 |
static int shutdown_index = 0; |
| 412 |
|
| 413 |
switch(addr) {
|
| 414 |
/* Bochs BIOS messages */
|
| 415 |
case 0x400: |
| 416 |
case 0x401: |
| 417 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
| 418 |
exit(1);
|
| 419 |
case 0x402: |
| 420 |
case 0x403: |
| 421 |
#ifdef DEBUG_BIOS
|
| 422 |
fprintf(stderr, "%c", val);
|
| 423 |
#endif
|
| 424 |
break;
|
| 425 |
case 0x8900: |
| 426 |
/* same as Bochs power off */
|
| 427 |
if (val == shutdown_str[shutdown_index]) {
|
| 428 |
shutdown_index++; |
| 429 |
if (shutdown_index == 8) { |
| 430 |
shutdown_index = 0;
|
| 431 |
qemu_system_shutdown_request(); |
| 432 |
} |
| 433 |
} else {
|
| 434 |
shutdown_index = 0;
|
| 435 |
} |
| 436 |
break;
|
| 437 |
|
| 438 |
/* LGPL'ed VGA BIOS messages */
|
| 439 |
case 0x501: |
| 440 |
case 0x502: |
| 441 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
| 442 |
exit(1);
|
| 443 |
case 0x500: |
| 444 |
case 0x503: |
| 445 |
#ifdef DEBUG_BIOS
|
| 446 |
fprintf(stderr, "%c", val);
|
| 447 |
#endif
|
| 448 |
break;
|
| 449 |
} |
| 450 |
} |
| 451 |
|
| 452 |
extern uint64_t node_cpumask[MAX_NODES];
|
| 453 |
|
| 454 |
static void *bochs_bios_init(void) |
| 455 |
{
|
| 456 |
void *fw_cfg;
|
| 457 |
uint8_t *smbios_table; |
| 458 |
size_t smbios_len; |
| 459 |
uint64_t *numa_fw_cfg; |
| 460 |
int i, j;
|
| 461 |
|
| 462 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
| 463 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
| 464 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
| 465 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
| 466 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
| 467 |
|
| 468 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
| 469 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
| 470 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
| 471 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
| 472 |
|
| 473 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
| 474 |
|
| 475 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
| 476 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
| 477 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
| 478 |
acpi_tables_len); |
| 479 |
|
| 480 |
smbios_table = smbios_get_table(&smbios_len); |
| 481 |
if (smbios_table)
|
| 482 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
| 483 |
smbios_table, smbios_len); |
| 484 |
|
| 485 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
| 486 |
* of nodes, one word for each VCPU->node and one word for each node to
|
| 487 |
* hold the amount of memory.
|
| 488 |
*/
|
| 489 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
| 490 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
| 491 |
for (i = 0; i < smp_cpus; i++) { |
| 492 |
for (j = 0; j < nb_numa_nodes; j++) { |
| 493 |
if (node_cpumask[j] & (1 << i)) { |
| 494 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
| 495 |
break;
|
| 496 |
} |
| 497 |
} |
| 498 |
} |
| 499 |
for (i = 0; i < nb_numa_nodes; i++) { |
| 500 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
| 501 |
} |
| 502 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
| 503 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
| 504 |
|
| 505 |
return fw_cfg;
|
| 506 |
} |
| 507 |
|
| 508 |
/* Generate an initial boot sector which sets state and jump to
|
| 509 |
a specified vector */
|
| 510 |
static void generate_bootsect(target_phys_addr_t option_rom, |
| 511 |
uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
| 512 |
{
|
| 513 |
uint8_t rom[512], *p, *reloc;
|
| 514 |
uint8_t sum; |
| 515 |
int i;
|
| 516 |
|
| 517 |
memset(rom, 0, sizeof(rom)); |
| 518 |
|
| 519 |
p = rom; |
| 520 |
/* Make sure we have an option rom signature */
|
| 521 |
*p++ = 0x55;
|
| 522 |
*p++ = 0xaa;
|
| 523 |
|
| 524 |
/* ROM size in sectors*/
|
| 525 |
*p++ = 1;
|
| 526 |
|
| 527 |
/* Hook int19 */
|
| 528 |
|
| 529 |
*p++ = 0x50; /* push ax */ |
| 530 |
*p++ = 0x1e; /* push ds */ |
| 531 |
*p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ |
| 532 |
*p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ |
| 533 |
|
| 534 |
*p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
| 535 |
*p++ = 0x64; *p++ = 0x00; |
| 536 |
reloc = p; |
| 537 |
*p++ = 0x00; *p++ = 0x00; |
| 538 |
|
| 539 |
*p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ |
| 540 |
*p++ = 0x66; *p++ = 0x00; |
| 541 |
|
| 542 |
*p++ = 0x1f; /* pop ds */ |
| 543 |
*p++ = 0x58; /* pop ax */ |
| 544 |
*p++ = 0xcb; /* lret */ |
| 545 |
|
| 546 |
/* Actual code */
|
| 547 |
*reloc = (p - rom); |
| 548 |
|
| 549 |
*p++ = 0xfa; /* CLI */ |
| 550 |
*p++ = 0xfc; /* CLD */ |
| 551 |
|
| 552 |
for (i = 0; i < 6; i++) { |
| 553 |
if (i == 1) /* Skip CS */ |
| 554 |
continue;
|
| 555 |
|
| 556 |
*p++ = 0xb8; /* MOV AX,imm16 */ |
| 557 |
*p++ = segs[i]; |
| 558 |
*p++ = segs[i] >> 8;
|
| 559 |
*p++ = 0x8e; /* MOV <seg>,AX */ |
| 560 |
*p++ = 0xc0 + (i << 3); |
| 561 |
} |
| 562 |
|
| 563 |
for (i = 0; i < 8; i++) { |
| 564 |
*p++ = 0x66; /* 32-bit operand size */ |
| 565 |
*p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
| 566 |
*p++ = gpr[i]; |
| 567 |
*p++ = gpr[i] >> 8;
|
| 568 |
*p++ = gpr[i] >> 16;
|
| 569 |
*p++ = gpr[i] >> 24;
|
| 570 |
} |
| 571 |
|
| 572 |
*p++ = 0xea; /* JMP FAR */ |
| 573 |
*p++ = ip; /* IP */
|
| 574 |
*p++ = ip >> 8;
|
| 575 |
*p++ = segs[1]; /* CS */ |
| 576 |
*p++ = segs[1] >> 8; |
| 577 |
|
| 578 |
/* sign rom */
|
| 579 |
sum = 0;
|
| 580 |
for (i = 0; i < (sizeof(rom) - 1); i++) |
| 581 |
sum += rom[i]; |
| 582 |
rom[sizeof(rom) - 1] = -sum; |
| 583 |
|
| 584 |
cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
|
| 585 |
option_rom_setup_reset(option_rom, sizeof (rom));
|
| 586 |
} |
| 587 |
|
| 588 |
static long get_file_size(FILE *f) |
| 589 |
{
|
| 590 |
long where, size;
|
| 591 |
|
| 592 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
| 593 |
|
| 594 |
where = ftell(f); |
| 595 |
fseek(f, 0, SEEK_END);
|
| 596 |
size = ftell(f); |
| 597 |
fseek(f, where, SEEK_SET); |
| 598 |
|
| 599 |
return size;
|
| 600 |
} |
| 601 |
|
| 602 |
#define MULTIBOOT_STRUCT_ADDR 0x9000 |
| 603 |
|
| 604 |
#if MULTIBOOT_STRUCT_ADDR > 0xf0000 |
| 605 |
#error multiboot struct needs to fit in 16 bit real mode |
| 606 |
#endif
|
| 607 |
|
| 608 |
static int load_multiboot(void *fw_cfg, |
| 609 |
FILE *f, |
| 610 |
const char *kernel_filename, |
| 611 |
const char *initrd_filename, |
| 612 |
const char *kernel_cmdline, |
| 613 |
uint8_t *header) |
| 614 |
{
|
| 615 |
int i, t, is_multiboot = 0; |
| 616 |
uint32_t flags = 0;
|
| 617 |
uint32_t mh_entry_addr; |
| 618 |
uint32_t mh_load_addr; |
| 619 |
uint32_t mb_kernel_size; |
| 620 |
uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR; |
| 621 |
uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
|
| 622 |
uint32_t mb_cmdline = mb_bootinfo + 0x200;
|
| 623 |
uint32_t mb_mod_end; |
| 624 |
|
| 625 |
/* Ok, let's see if it is a multiboot image.
|
| 626 |
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
|
| 627 |
for (i = 0; i < (8192 - 48); i += 4) { |
| 628 |
if (ldl_p(header+i) == 0x1BADB002) { |
| 629 |
uint32_t checksum = ldl_p(header+i+8);
|
| 630 |
flags = ldl_p(header+i+4);
|
| 631 |
checksum += flags; |
| 632 |
checksum += (uint32_t)0x1BADB002;
|
| 633 |
if (!checksum) {
|
| 634 |
is_multiboot = 1;
|
| 635 |
break;
|
| 636 |
} |
| 637 |
} |
| 638 |
} |
| 639 |
|
| 640 |
if (!is_multiboot)
|
| 641 |
return 0; /* no multiboot */ |
| 642 |
|
| 643 |
#ifdef DEBUG_MULTIBOOT
|
| 644 |
fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
|
| 645 |
#endif
|
| 646 |
|
| 647 |
if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */ |
| 648 |
fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
|
| 649 |
} |
| 650 |
if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */ |
| 651 |
uint64_t elf_entry; |
| 652 |
int kernel_size;
|
| 653 |
fclose(f); |
| 654 |
kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
| 655 |
if (kernel_size < 0) { |
| 656 |
fprintf(stderr, "Error while loading elf kernel\n");
|
| 657 |
exit(1);
|
| 658 |
} |
| 659 |
mh_load_addr = mh_entry_addr = elf_entry; |
| 660 |
mb_kernel_size = kernel_size; |
| 661 |
|
| 662 |
#ifdef DEBUG_MULTIBOOT
|
| 663 |
fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
|
| 664 |
mb_kernel_size, (size_t)mh_entry_addr); |
| 665 |
#endif
|
| 666 |
} else {
|
| 667 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
|
| 668 |
uint32_t mh_header_addr = ldl_p(header+i+12);
|
| 669 |
mh_load_addr = ldl_p(header+i+16);
|
| 670 |
#ifdef DEBUG_MULTIBOOT
|
| 671 |
uint32_t mh_load_end_addr = ldl_p(header+i+20);
|
| 672 |
uint32_t mh_bss_end_addr = ldl_p(header+i+24);
|
| 673 |
#endif
|
| 674 |
uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); |
| 675 |
|
| 676 |
mh_entry_addr = ldl_p(header+i+28);
|
| 677 |
mb_kernel_size = get_file_size(f) - mb_kernel_text_offset; |
| 678 |
|
| 679 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
|
| 680 |
uint32_t mh_mode_type = ldl_p(header+i+32);
|
| 681 |
uint32_t mh_width = ldl_p(header+i+36);
|
| 682 |
uint32_t mh_height = ldl_p(header+i+40);
|
| 683 |
uint32_t mh_depth = ldl_p(header+i+44); */
|
| 684 |
|
| 685 |
#ifdef DEBUG_MULTIBOOT
|
| 686 |
fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
|
| 687 |
fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
|
| 688 |
fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
|
| 689 |
fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
|
| 690 |
#endif
|
| 691 |
|
| 692 |
fseek(f, mb_kernel_text_offset, SEEK_SET); |
| 693 |
|
| 694 |
#ifdef DEBUG_MULTIBOOT
|
| 695 |
fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
|
| 696 |
mb_kernel_size, mh_load_addr); |
| 697 |
#endif
|
| 698 |
|
| 699 |
if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
|
| 700 |
fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
|
| 701 |
kernel_filename, mb_kernel_size); |
| 702 |
exit(1);
|
| 703 |
} |
| 704 |
fclose(f); |
| 705 |
} |
| 706 |
|
| 707 |
/* blob size is only the kernel for now */
|
| 708 |
mb_mod_end = mh_load_addr + mb_kernel_size; |
| 709 |
|
| 710 |
/* load modules */
|
| 711 |
stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */ |
| 712 |
if (initrd_filename) {
|
| 713 |
uint32_t mb_mod_info = mb_bootinfo + 0x100;
|
| 714 |
uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
|
| 715 |
uint32_t mb_mod_start = mh_load_addr; |
| 716 |
uint32_t mb_mod_length = mb_kernel_size; |
| 717 |
char *next_initrd;
|
| 718 |
char *next_space;
|
| 719 |
int mb_mod_count = 0; |
| 720 |
|
| 721 |
do {
|
| 722 |
next_initrd = strchr(initrd_filename, ',');
|
| 723 |
if (next_initrd)
|
| 724 |
*next_initrd = '\0';
|
| 725 |
/* if a space comes after the module filename, treat everything
|
| 726 |
after that as parameters */
|
| 727 |
cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename, |
| 728 |
strlen(initrd_filename) + 1);
|
| 729 |
stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */ |
| 730 |
mb_mod_cmdline += strlen(initrd_filename) + 1;
|
| 731 |
if ((next_space = strchr(initrd_filename, ' '))) |
| 732 |
*next_space = '\0';
|
| 733 |
#ifdef DEBUG_MULTIBOOT
|
| 734 |
printf("multiboot loading module: %s\n", initrd_filename);
|
| 735 |
#endif
|
| 736 |
f = fopen(initrd_filename, "rb");
|
| 737 |
if (f) {
|
| 738 |
mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
|
| 739 |
& (TARGET_PAGE_MASK); |
| 740 |
mb_mod_length = get_file_size(f); |
| 741 |
mb_mod_end = mb_mod_start + mb_mod_length; |
| 742 |
|
| 743 |
if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
|
| 744 |
fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
|
| 745 |
initrd_filename, mb_mod_length); |
| 746 |
exit(1);
|
| 747 |
} |
| 748 |
|
| 749 |
mb_mod_count++; |
| 750 |
stl_phys(mb_mod_info + 0, mb_mod_start);
|
| 751 |
stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
|
| 752 |
#ifdef DEBUG_MULTIBOOT
|
| 753 |
printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
|
| 754 |
mb_mod_start + mb_mod_length); |
| 755 |
#endif
|
| 756 |
stl_phys(mb_mod_info + 12, 0x0); /* reserved */ |
| 757 |
} |
| 758 |
initrd_filename = next_initrd+1;
|
| 759 |
mb_mod_info += 16;
|
| 760 |
} while (next_initrd);
|
| 761 |
stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */ |
| 762 |
stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */ |
| 763 |
} |
| 764 |
|
| 765 |
/* Make sure we're getting kernel + modules back after reset */
|
| 766 |
option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr); |
| 767 |
|
| 768 |
/* Commandline support */
|
| 769 |
stl_phys(mb_bootinfo + 16, mb_cmdline);
|
| 770 |
t = strlen(kernel_filename); |
| 771 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t); |
| 772 |
mb_cmdline += t; |
| 773 |
stb_phys(mb_cmdline++, ' ');
|
| 774 |
t = strlen(kernel_cmdline) + 1;
|
| 775 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t); |
| 776 |
|
| 777 |
/* the kernel is where we want it to be now */
|
| 778 |
|
| 779 |
#define MULTIBOOT_FLAGS_MEMORY (1 << 0) |
| 780 |
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1) |
| 781 |
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2) |
| 782 |
#define MULTIBOOT_FLAGS_MODULES (1 << 3) |
| 783 |
#define MULTIBOOT_FLAGS_MMAP (1 << 6) |
| 784 |
stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY |
| 785 |
| MULTIBOOT_FLAGS_BOOT_DEVICE |
| 786 |
| MULTIBOOT_FLAGS_CMDLINE |
| 787 |
| MULTIBOOT_FLAGS_MODULES |
| 788 |
| MULTIBOOT_FLAGS_MMAP); |
| 789 |
stl_phys(mb_bootinfo + 4, 640); /* mem_lower */ |
| 790 |
stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */ |
| 791 |
stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */ |
| 792 |
stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */ |
| 793 |
|
| 794 |
#ifdef DEBUG_MULTIBOOT
|
| 795 |
fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
|
| 796 |
#endif
|
| 797 |
|
| 798 |
/* Pass variables to option rom */
|
| 799 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr); |
| 800 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo); |
| 801 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr); |
| 802 |
|
| 803 |
/* Make sure we're getting the config space back after reset */
|
| 804 |
option_rom_setup_reset(mb_bootinfo, 0x500);
|
| 805 |
|
| 806 |
option_rom[nb_option_roms] = "multiboot.bin";
|
| 807 |
nb_option_roms++; |
| 808 |
|
| 809 |
return 1; /* yes, we are multiboot */ |
| 810 |
} |
| 811 |
|
| 812 |
static void load_linux(void *fw_cfg, |
| 813 |
target_phys_addr_t option_rom, |
| 814 |
const char *kernel_filename, |
| 815 |
const char *initrd_filename, |
| 816 |
const char *kernel_cmdline, |
| 817 |
target_phys_addr_t max_ram_size) |
| 818 |
{
|
| 819 |
uint16_t protocol; |
| 820 |
uint32_t gpr[8];
|
| 821 |
uint16_t seg[6];
|
| 822 |
uint16_t real_seg; |
| 823 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
| 824 |
uint32_t initrd_max; |
| 825 |
uint8_t header[8192];
|
| 826 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
| 827 |
FILE *f, *fi; |
| 828 |
|
| 829 |
/* Align to 16 bytes as a paranoia measure */
|
| 830 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
| 831 |
|
| 832 |
/* load the kernel header */
|
| 833 |
f = fopen(kernel_filename, "rb");
|
| 834 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
| 835 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
| 836 |
MIN(ARRAY_SIZE(header), kernel_size)) {
|
| 837 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
| 838 |
kernel_filename); |
| 839 |
exit(1);
|
| 840 |
} |
| 841 |
|
| 842 |
/* kernel protocol version */
|
| 843 |
#if 0
|
| 844 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
| 845 |
#endif
|
| 846 |
if (ldl_p(header+0x202) == 0x53726448) |
| 847 |
protocol = lduw_p(header+0x206);
|
| 848 |
else {
|
| 849 |
/* This looks like a multiboot kernel. If it is, let's stop
|
| 850 |
treating it like a Linux kernel. */
|
| 851 |
if (load_multiboot(fw_cfg, f, kernel_filename,
|
| 852 |
initrd_filename, kernel_cmdline, header)) |
| 853 |
return;
|
| 854 |
protocol = 0;
|
| 855 |
} |
| 856 |
|
| 857 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
| 858 |
/* Low kernel */
|
| 859 |
real_addr = 0x90000;
|
| 860 |
cmdline_addr = 0x9a000 - cmdline_size;
|
| 861 |
prot_addr = 0x10000;
|
| 862 |
} else if (protocol < 0x202) { |
| 863 |
/* High but ancient kernel */
|
| 864 |
real_addr = 0x90000;
|
| 865 |
cmdline_addr = 0x9a000 - cmdline_size;
|
| 866 |
prot_addr = 0x100000;
|
| 867 |
} else {
|
| 868 |
/* High and recent kernel */
|
| 869 |
real_addr = 0x10000;
|
| 870 |
cmdline_addr = 0x20000;
|
| 871 |
prot_addr = 0x100000;
|
| 872 |
} |
| 873 |
|
| 874 |
#if 0
|
| 875 |
fprintf(stderr,
|
| 876 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
| 877 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
| 878 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
| 879 |
real_addr,
|
| 880 |
cmdline_addr,
|
| 881 |
prot_addr);
|
| 882 |
#endif
|
| 883 |
|
| 884 |
/* highest address for loading the initrd */
|
| 885 |
if (protocol >= 0x203) |
| 886 |
initrd_max = ldl_p(header+0x22c);
|
| 887 |
else
|
| 888 |
initrd_max = 0x37ffffff;
|
| 889 |
|
| 890 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
| 891 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
| 892 |
|
| 893 |
/* kernel command line */
|
| 894 |
pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
|
| 895 |
|
| 896 |
if (protocol >= 0x202) { |
| 897 |
stl_p(header+0x228, cmdline_addr);
|
| 898 |
} else {
|
| 899 |
stw_p(header+0x20, 0xA33F); |
| 900 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
| 901 |
} |
| 902 |
|
| 903 |
/* loader type */
|
| 904 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
| 905 |
If this code is substantially changed, you may want to consider
|
| 906 |
incrementing the revision. */
|
| 907 |
if (protocol >= 0x200) |
| 908 |
header[0x210] = 0xB0; |
| 909 |
|
| 910 |
/* heap */
|
| 911 |
if (protocol >= 0x201) { |
| 912 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
| 913 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
| 914 |
} |
| 915 |
|
| 916 |
/* load initrd */
|
| 917 |
if (initrd_filename) {
|
| 918 |
if (protocol < 0x200) { |
| 919 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
| 920 |
exit(1);
|
| 921 |
} |
| 922 |
|
| 923 |
fi = fopen(initrd_filename, "rb");
|
| 924 |
if (!fi) {
|
| 925 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
| 926 |
initrd_filename); |
| 927 |
exit(1);
|
| 928 |
} |
| 929 |
|
| 930 |
initrd_size = get_file_size(fi); |
| 931 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
| 932 |
|
| 933 |
if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
|
| 934 |
fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
| 935 |
initrd_filename); |
| 936 |
exit(1);
|
| 937 |
} |
| 938 |
fclose(fi); |
| 939 |
|
| 940 |
stl_p(header+0x218, initrd_addr);
|
| 941 |
stl_p(header+0x21c, initrd_size);
|
| 942 |
} |
| 943 |
|
| 944 |
/* store the finalized header and load the rest of the kernel */
|
| 945 |
cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header)); |
| 946 |
|
| 947 |
setup_size = header[0x1f1];
|
| 948 |
if (setup_size == 0) |
| 949 |
setup_size = 4;
|
| 950 |
|
| 951 |
setup_size = (setup_size+1)*512; |
| 952 |
/* Size of protected-mode code */
|
| 953 |
kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header); |
| 954 |
|
| 955 |
/* In case we have read too much already, copy that over */
|
| 956 |
if (setup_size < ARRAY_SIZE(header)) {
|
| 957 |
cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size); |
| 958 |
prot_addr += (ARRAY_SIZE(header) - setup_size); |
| 959 |
setup_size = ARRAY_SIZE(header); |
| 960 |
} |
| 961 |
|
| 962 |
if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
|
| 963 |
setup_size - ARRAY_SIZE(header), f) || |
| 964 |
!fread_targphys_ok(prot_addr, kernel_size, f)) {
|
| 965 |
fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
| 966 |
kernel_filename); |
| 967 |
exit(1);
|
| 968 |
} |
| 969 |
fclose(f); |
| 970 |
|
| 971 |
/* generate bootsector to set up the initial register state */
|
| 972 |
real_seg = real_addr >> 4;
|
| 973 |
seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
| 974 |
seg[1] = real_seg+0x20; /* CS */ |
| 975 |
memset(gpr, 0, sizeof gpr); |
| 976 |
gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
| 977 |
|
| 978 |
option_rom_setup_reset(real_addr, setup_size); |
| 979 |
option_rom_setup_reset(prot_addr, kernel_size); |
| 980 |
option_rom_setup_reset(cmdline_addr, cmdline_size); |
| 981 |
if (initrd_filename)
|
| 982 |
option_rom_setup_reset(initrd_addr, initrd_size); |
| 983 |
|
| 984 |
generate_bootsect(option_rom, gpr, seg, 0);
|
| 985 |
} |
| 986 |
|
| 987 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
| 988 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
| 989 |
static const int ide_irq[2] = { 14, 15 }; |
| 990 |
|
| 991 |
#define NE2000_NB_MAX 6 |
| 992 |
|
| 993 |
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
| 994 |
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
| 995 |
|
| 996 |
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
| 997 |
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
| 998 |
|
| 999 |
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
| 1000 |
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
| 1001 |
|
| 1002 |
#ifdef HAS_AUDIO
|
| 1003 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
| 1004 |
{
|
| 1005 |
struct soundhw *c;
|
| 1006 |
|
| 1007 |
for (c = soundhw; c->name; ++c) {
|
| 1008 |
if (c->enabled) {
|
| 1009 |
if (c->isa) {
|
| 1010 |
c->init.init_isa(pic); |
| 1011 |
} else {
|
| 1012 |
if (pci_bus) {
|
| 1013 |
c->init.init_pci(pci_bus); |
| 1014 |
} |
| 1015 |
} |
| 1016 |
} |
| 1017 |
} |
| 1018 |
} |
| 1019 |
#endif
|
| 1020 |
|
| 1021 |
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
| 1022 |
{
|
| 1023 |
static int nb_ne2k = 0; |
| 1024 |
|
| 1025 |
if (nb_ne2k == NE2000_NB_MAX)
|
| 1026 |
return;
|
| 1027 |
isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
| 1028 |
nb_ne2k++; |
| 1029 |
} |
| 1030 |
|
| 1031 |
static int load_option_rom(const char *oprom, target_phys_addr_t start, |
| 1032 |
target_phys_addr_t end) |
| 1033 |
{
|
| 1034 |
int size;
|
| 1035 |
char *filename;
|
| 1036 |
|
| 1037 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom); |
| 1038 |
if (filename) {
|
| 1039 |
size = get_image_size(filename); |
| 1040 |
if (size > 0 && start + size > end) { |
| 1041 |
fprintf(stderr, "Not enough space to load option rom '%s'\n",
|
| 1042 |
oprom); |
| 1043 |
exit(1);
|
| 1044 |
} |
| 1045 |
size = load_image_targphys(filename, start, end - start); |
| 1046 |
qemu_free(filename); |
| 1047 |
} else {
|
| 1048 |
size = -1;
|
| 1049 |
} |
| 1050 |
if (size < 0) { |
| 1051 |
fprintf(stderr, "Could not load option rom '%s'\n", oprom);
|
| 1052 |
exit(1);
|
| 1053 |
} |
| 1054 |
/* Round up optiom rom size to the next 2k boundary */
|
| 1055 |
size = (size + 2047) & ~2047; |
| 1056 |
option_rom_setup_reset(start, size); |
| 1057 |
return size;
|
| 1058 |
} |
| 1059 |
|
| 1060 |
int cpu_is_bsp(CPUState *env)
|
| 1061 |
{
|
| 1062 |
return env->cpuid_apic_id == 0; |
| 1063 |
} |
| 1064 |
|
| 1065 |
/* PC hardware initialisation */
|
| 1066 |
static void pc_init1(ram_addr_t ram_size, |
| 1067 |
const char *boot_device, |
| 1068 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1069 |
const char *initrd_filename, |
| 1070 |
int pci_enabled, const char *cpu_model) |
| 1071 |
{
|
| 1072 |
char *filename;
|
| 1073 |
int ret, linux_boot, i;
|
| 1074 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
| 1075 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
| 1076 |
int bios_size, isa_bios_size, oprom_area_size;
|
| 1077 |
PCIBus *pci_bus; |
| 1078 |
PCIDevice *pci_dev; |
| 1079 |
int piix3_devfn = -1; |
| 1080 |
CPUState *env; |
| 1081 |
qemu_irq *cpu_irq; |
| 1082 |
qemu_irq *i8259; |
| 1083 |
int index;
|
| 1084 |
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 1085 |
BlockDriverState *fd[MAX_FD]; |
| 1086 |
int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
|
| 1087 |
void *fw_cfg;
|
| 1088 |
|
| 1089 |
if (ram_size >= 0xe0000000 ) { |
| 1090 |
above_4g_mem_size = ram_size - 0xe0000000;
|
| 1091 |
below_4g_mem_size = 0xe0000000;
|
| 1092 |
} else {
|
| 1093 |
below_4g_mem_size = ram_size; |
| 1094 |
} |
| 1095 |
|
| 1096 |
linux_boot = (kernel_filename != NULL);
|
| 1097 |
|
| 1098 |
/* init CPUs */
|
| 1099 |
if (cpu_model == NULL) { |
| 1100 |
#ifdef TARGET_X86_64
|
| 1101 |
cpu_model = "qemu64";
|
| 1102 |
#else
|
| 1103 |
cpu_model = "qemu32";
|
| 1104 |
#endif
|
| 1105 |
} |
| 1106 |
|
| 1107 |
for(i = 0; i < smp_cpus; i++) { |
| 1108 |
env = cpu_init(cpu_model); |
| 1109 |
if (!env) {
|
| 1110 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
| 1111 |
exit(1);
|
| 1112 |
} |
| 1113 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
| 1114 |
env->cpuid_apic_id = env->cpu_index; |
| 1115 |
/* APIC reset callback resets cpu */
|
| 1116 |
apic_init(env); |
| 1117 |
} else {
|
| 1118 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, 0, env);
|
| 1119 |
} |
| 1120 |
} |
| 1121 |
|
| 1122 |
vmport_init(); |
| 1123 |
|
| 1124 |
/* allocate RAM */
|
| 1125 |
ram_addr = qemu_ram_alloc(0xa0000);
|
| 1126 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
| 1127 |
|
| 1128 |
/* Allocate, even though we won't register, so we don't break the
|
| 1129 |
* phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
| 1130 |
* and some bios areas, which will be registered later
|
| 1131 |
*/
|
| 1132 |
ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
| 1133 |
ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
| 1134 |
cpu_register_physical_memory(0x100000,
|
| 1135 |
below_4g_mem_size - 0x100000,
|
| 1136 |
ram_addr); |
| 1137 |
|
| 1138 |
/* above 4giga memory allocation */
|
| 1139 |
if (above_4g_mem_size > 0) { |
| 1140 |
#if TARGET_PHYS_ADDR_BITS == 32 |
| 1141 |
hw_error("To much RAM for 32-bit physical address");
|
| 1142 |
#else
|
| 1143 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
| 1144 |
cpu_register_physical_memory(0x100000000ULL,
|
| 1145 |
above_4g_mem_size, |
| 1146 |
ram_addr); |
| 1147 |
#endif
|
| 1148 |
} |
| 1149 |
|
| 1150 |
|
| 1151 |
/* BIOS load */
|
| 1152 |
if (bios_name == NULL) |
| 1153 |
bios_name = BIOS_FILENAME; |
| 1154 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 1155 |
if (filename) {
|
| 1156 |
bios_size = get_image_size(filename); |
| 1157 |
} else {
|
| 1158 |
bios_size = -1;
|
| 1159 |
} |
| 1160 |
if (bios_size <= 0 || |
| 1161 |
(bios_size % 65536) != 0) { |
| 1162 |
goto bios_error;
|
| 1163 |
} |
| 1164 |
bios_offset = qemu_ram_alloc(bios_size); |
| 1165 |
ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); |
| 1166 |
if (ret != bios_size) {
|
| 1167 |
bios_error:
|
| 1168 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
| 1169 |
exit(1);
|
| 1170 |
} |
| 1171 |
if (filename) {
|
| 1172 |
qemu_free(filename); |
| 1173 |
} |
| 1174 |
/* map the last 128KB of the BIOS in ISA space */
|
| 1175 |
isa_bios_size = bios_size; |
| 1176 |
if (isa_bios_size > (128 * 1024)) |
| 1177 |
isa_bios_size = 128 * 1024; |
| 1178 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
| 1179 |
isa_bios_size, |
| 1180 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
| 1181 |
|
| 1182 |
|
| 1183 |
|
| 1184 |
option_rom_offset = qemu_ram_alloc(0x20000);
|
| 1185 |
oprom_area_size = 0;
|
| 1186 |
cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); |
| 1187 |
|
| 1188 |
if (using_vga) {
|
| 1189 |
const char *vgabios_filename; |
| 1190 |
/* VGA BIOS load */
|
| 1191 |
if (cirrus_vga_enabled) {
|
| 1192 |
vgabios_filename = VGABIOS_CIRRUS_FILENAME; |
| 1193 |
} else {
|
| 1194 |
vgabios_filename = VGABIOS_FILENAME; |
| 1195 |
} |
| 1196 |
oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000); |
| 1197 |
} |
| 1198 |
/* Although video roms can grow larger than 0x8000, the area between
|
| 1199 |
* 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
|
| 1200 |
* for any other kind of option rom inside this area */
|
| 1201 |
if (oprom_area_size < 0x8000) |
| 1202 |
oprom_area_size = 0x8000;
|
| 1203 |
|
| 1204 |
/* map all the bios at the top of memory */
|
| 1205 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
| 1206 |
bios_size, bios_offset | IO_MEM_ROM); |
| 1207 |
|
| 1208 |
fw_cfg = bochs_bios_init(); |
| 1209 |
|
| 1210 |
if (linux_boot) {
|
| 1211 |
load_linux(fw_cfg, 0xc0000 + oprom_area_size,
|
| 1212 |
kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
| 1213 |
oprom_area_size += 2048;
|
| 1214 |
} |
| 1215 |
|
| 1216 |
for (i = 0; i < nb_option_roms; i++) { |
| 1217 |
oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
|
| 1218 |
0xe0000);
|
| 1219 |
} |
| 1220 |
|
| 1221 |
for (i = 0; i < nb_nics; i++) { |
| 1222 |
char nic_oprom[1024]; |
| 1223 |
const char *model = nd_table[i].model; |
| 1224 |
|
| 1225 |
if (!nd_table[i].bootable)
|
| 1226 |
continue;
|
| 1227 |
|
| 1228 |
if (model == NULL) |
| 1229 |
model = "ne2k_pci";
|
| 1230 |
snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model); |
| 1231 |
|
| 1232 |
oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
|
| 1233 |
0xe0000);
|
| 1234 |
} |
| 1235 |
|
| 1236 |
cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
| 1237 |
i8259 = i8259_init(cpu_irq[0]);
|
| 1238 |
ferr_irq = i8259[13];
|
| 1239 |
|
| 1240 |
if (pci_enabled) {
|
| 1241 |
pci_bus = i440fx_init(&i440fx_state, i8259); |
| 1242 |
piix3_devfn = piix3_init(pci_bus, -1);
|
| 1243 |
} else {
|
| 1244 |
pci_bus = NULL;
|
| 1245 |
} |
| 1246 |
|
| 1247 |
/* init basic PC hardware */
|
| 1248 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
| 1249 |
|
| 1250 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
| 1251 |
|
| 1252 |
if (cirrus_vga_enabled) {
|
| 1253 |
if (pci_enabled) {
|
| 1254 |
pci_cirrus_vga_init(pci_bus); |
| 1255 |
} else {
|
| 1256 |
isa_cirrus_vga_init(); |
| 1257 |
} |
| 1258 |
} else if (vmsvga_enabled) { |
| 1259 |
if (pci_enabled)
|
| 1260 |
pci_vmsvga_init(pci_bus); |
| 1261 |
else
|
| 1262 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
| 1263 |
} else if (std_vga_enabled) { |
| 1264 |
if (pci_enabled) {
|
| 1265 |
pci_vga_init(pci_bus, 0, 0); |
| 1266 |
} else {
|
| 1267 |
isa_vga_init(); |
| 1268 |
} |
| 1269 |
} |
| 1270 |
|
| 1271 |
rtc_state = rtc_init(0x70, i8259[8], 2000); |
| 1272 |
|
| 1273 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
| 1274 |
|
| 1275 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
| 1276 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
| 1277 |
|
| 1278 |
if (pci_enabled) {
|
| 1279 |
ioapic = ioapic_init(); |
| 1280 |
} |
| 1281 |
pit = pit_init(0x40, i8259[0]); |
| 1282 |
pcspk_init(pit); |
| 1283 |
if (!no_hpet) {
|
| 1284 |
hpet_init(i8259); |
| 1285 |
} |
| 1286 |
if (pci_enabled) {
|
| 1287 |
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
| 1288 |
} |
| 1289 |
|
| 1290 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
| 1291 |
if (serial_hds[i]) {
|
| 1292 |
serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
|
| 1293 |
serial_hds[i]); |
| 1294 |
} |
| 1295 |
} |
| 1296 |
|
| 1297 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
| 1298 |
if (parallel_hds[i]) {
|
| 1299 |
parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
| 1300 |
parallel_hds[i]); |
| 1301 |
} |
| 1302 |
} |
| 1303 |
|
| 1304 |
watchdog_pc_init(pci_bus); |
| 1305 |
|
| 1306 |
for(i = 0; i < nb_nics; i++) { |
| 1307 |
NICInfo *nd = &nd_table[i]; |
| 1308 |
|
| 1309 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
| 1310 |
pc_init_ne2k_isa(nd, i8259); |
| 1311 |
else
|
| 1312 |
pci_nic_init(nd, "ne2k_pci", NULL); |
| 1313 |
} |
| 1314 |
|
| 1315 |
piix4_acpi_system_hot_add_init(); |
| 1316 |
|
| 1317 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
| 1318 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
| 1319 |
exit(1);
|
| 1320 |
} |
| 1321 |
|
| 1322 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
| 1323 |
index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
| 1324 |
if (index != -1) |
| 1325 |
hd[i] = drives_table[index].bdrv; |
| 1326 |
else
|
| 1327 |
hd[i] = NULL;
|
| 1328 |
} |
| 1329 |
|
| 1330 |
if (pci_enabled) {
|
| 1331 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
|
| 1332 |
} else {
|
| 1333 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
| 1334 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
| 1335 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
| 1336 |
} |
| 1337 |
} |
| 1338 |
|
| 1339 |
i8042_init(i8259[1], i8259[12], 0x60); |
| 1340 |
DMA_init(0);
|
| 1341 |
#ifdef HAS_AUDIO
|
| 1342 |
audio_init(pci_enabled ? pci_bus : NULL, i8259);
|
| 1343 |
#endif
|
| 1344 |
|
| 1345 |
for(i = 0; i < MAX_FD; i++) { |
| 1346 |
index = drive_get_index(IF_FLOPPY, 0, i);
|
| 1347 |
if (index != -1) |
| 1348 |
fd[i] = drives_table[index].bdrv; |
| 1349 |
else
|
| 1350 |
fd[i] = NULL;
|
| 1351 |
} |
| 1352 |
floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
| 1353 |
|
| 1354 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
| 1355 |
|
| 1356 |
if (pci_enabled && usb_enabled) {
|
| 1357 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
| 1358 |
} |
| 1359 |
|
| 1360 |
if (pci_enabled && acpi_enabled) {
|
| 1361 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
| 1362 |
i2c_bus *smbus; |
| 1363 |
|
| 1364 |
/* TODO: Populate SPD eeprom data. */
|
| 1365 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
| 1366 |
for (i = 0; i < 8; i++) { |
| 1367 |
DeviceState *eeprom; |
| 1368 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
| 1369 |
qdev_set_prop_int(eeprom, "address", 0x50 + i); |
| 1370 |
qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
| 1371 |
qdev_init(eeprom); |
| 1372 |
} |
| 1373 |
} |
| 1374 |
|
| 1375 |
if (i440fx_state) {
|
| 1376 |
i440fx_init_memory_mappings(i440fx_state); |
| 1377 |
} |
| 1378 |
|
| 1379 |
if (pci_enabled) {
|
| 1380 |
int max_bus;
|
| 1381 |
int bus;
|
| 1382 |
|
| 1383 |
max_bus = drive_get_max_bus(IF_SCSI); |
| 1384 |
for (bus = 0; bus <= max_bus; bus++) { |
| 1385 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
| 1386 |
} |
| 1387 |
} |
| 1388 |
|
| 1389 |
/* Add virtio block devices */
|
| 1390 |
if (pci_enabled) {
|
| 1391 |
int index;
|
| 1392 |
int unit_id = 0; |
| 1393 |
|
| 1394 |
while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { |
| 1395 |
pci_dev = pci_create("virtio-blk-pci",
|
| 1396 |
drives_table[index].devaddr); |
| 1397 |
qdev_init(&pci_dev->qdev); |
| 1398 |
unit_id++; |
| 1399 |
} |
| 1400 |
} |
| 1401 |
|
| 1402 |
/* Add virtio balloon device */
|
| 1403 |
if (pci_enabled && !no_virtio_balloon) {
|
| 1404 |
pci_create_simple(pci_bus, -1, "virtio-balloon-pci"); |
| 1405 |
} |
| 1406 |
|
| 1407 |
/* Add virtio console devices */
|
| 1408 |
if (pci_enabled) {
|
| 1409 |
for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { |
| 1410 |
if (virtcon_hds[i]) {
|
| 1411 |
pci_create_simple(pci_bus, -1, "virtio-console-pci"); |
| 1412 |
} |
| 1413 |
} |
| 1414 |
} |
| 1415 |
} |
| 1416 |
|
| 1417 |
static void pc_init_pci(ram_addr_t ram_size, |
| 1418 |
const char *boot_device, |
| 1419 |
const char *kernel_filename, |
| 1420 |
const char *kernel_cmdline, |
| 1421 |
const char *initrd_filename, |
| 1422 |
const char *cpu_model) |
| 1423 |
{
|
| 1424 |
pc_init1(ram_size, boot_device, |
| 1425 |
kernel_filename, kernel_cmdline, |
| 1426 |
initrd_filename, 1, cpu_model);
|
| 1427 |
} |
| 1428 |
|
| 1429 |
static void pc_init_isa(ram_addr_t ram_size, |
| 1430 |
const char *boot_device, |
| 1431 |
const char *kernel_filename, |
| 1432 |
const char *kernel_cmdline, |
| 1433 |
const char *initrd_filename, |
| 1434 |
const char *cpu_model) |
| 1435 |
{
|
| 1436 |
pc_init1(ram_size, boot_device, |
| 1437 |
kernel_filename, kernel_cmdline, |
| 1438 |
initrd_filename, 0, cpu_model);
|
| 1439 |
} |
| 1440 |
|
| 1441 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
| 1442 |
BIOS will read it and start S3 resume at POST Entry */
|
| 1443 |
void cmos_set_s3_resume(void) |
| 1444 |
{
|
| 1445 |
if (rtc_state)
|
| 1446 |
rtc_set_memory(rtc_state, 0xF, 0xFE); |
| 1447 |
} |
| 1448 |
|
| 1449 |
static QEMUMachine pc_machine = {
|
| 1450 |
.name = "pc",
|
| 1451 |
.desc = "Standard PC",
|
| 1452 |
.init = pc_init_pci, |
| 1453 |
.max_cpus = 255,
|
| 1454 |
.is_default = 1,
|
| 1455 |
}; |
| 1456 |
|
| 1457 |
static QEMUMachine isapc_machine = {
|
| 1458 |
.name = "isapc",
|
| 1459 |
.desc = "ISA-only PC",
|
| 1460 |
.init = pc_init_isa, |
| 1461 |
.max_cpus = 1,
|
| 1462 |
}; |
| 1463 |
|
| 1464 |
static void pc_machine_init(void) |
| 1465 |
{
|
| 1466 |
qemu_register_machine(&pc_machine); |
| 1467 |
qemu_register_machine(&isapc_machine); |
| 1468 |
} |
| 1469 |
|
| 1470 |
machine_init(pc_machine_init); |