Revision f19410ca

b/Makefile.target
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obj-lm32-y += lm32_juart.o
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obj-lm32-y += lm32_timer.o
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obj-lm32-y += lm32_uart.o
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obj-lm32-y += lm32_sys.o
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obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
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obj-mips-y += mips_addr.o mips_timer.o mips_int.o
b/hw/lm32_sys.c
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/*
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 *  QEMU model of the LatticeMico32 system control block.
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 *
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 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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/*
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 * This model is mainly intended for testing purposes and doesn't fit to any
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 * real hardware. On the one hand it provides a control register (R_CTRL) on
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 * the other hand it supports the lm32 tests.
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 *
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 * A write to the control register causes a system shutdown.
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 * Tests first write the pointer to a test name to the test name register
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 * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
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 * the test is passed or any non-zero value to it if the test is failed.
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 */
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-log.h"
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#include "qemu-error.h"
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#include "sysemu.h"
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#include "qemu-log.h"
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enum {
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    R_CTRL = 0,
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    R_PASSFAIL,
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    R_TESTNAME,
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    R_MAX
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};
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#define MAX_TESTNAME_LEN 16
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struct LM32SysState {
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    SysBusDevice busdev;
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    uint32_t base;
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    uint32_t regs[R_MAX];
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    uint8_t testname[MAX_TESTNAME_LEN];
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};
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typedef struct LM32SysState LM32SysState;
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static void copy_testname(LM32SysState *s)
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{
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    cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname,
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            MAX_TESTNAME_LEN);
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    s->testname[MAX_TESTNAME_LEN - 1] = '\0';
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}
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static void sys_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    LM32SysState *s = opaque;
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    char *testname;
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    trace_lm32_sys_memory_write(addr, value);
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    addr >>= 2;
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    switch (addr) {
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    case R_CTRL:
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        qemu_system_shutdown_request();
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        break;
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    case R_PASSFAIL:
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        s->regs[addr] = value;
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        testname = (char *)s->testname;
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        qemu_log("TC  %-16s %s\n", testname, (value) ? "FAILED" : "OK");
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        break;
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    case R_TESTNAME:
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        s->regs[addr] = value;
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        copy_testname(s);
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        break;
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    default:
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        error_report("lm32_sys: write access to unkown register 0x"
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                TARGET_FMT_plx, addr << 2);
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        break;
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    }
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}
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static CPUReadMemoryFunc * const sys_read_fn[] = {
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    NULL,
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    NULL,
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    NULL,
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};
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static CPUWriteMemoryFunc * const sys_write_fn[] = {
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    NULL,
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    NULL,
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    &sys_write,
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};
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static void sys_reset(DeviceState *d)
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{
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    LM32SysState *s = container_of(d, LM32SysState, busdev.qdev);
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    int i;
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    for (i = 0; i < R_MAX; i++) {
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        s->regs[i] = 0;
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    }
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    memset(s->testname, 0, MAX_TESTNAME_LEN);
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}
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static int lm32_sys_init(SysBusDevice *dev)
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{
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    LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
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    int sys_regs;
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    sys_regs = cpu_register_io_memory(sys_read_fn, sys_write_fn, s,
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            DEVICE_NATIVE_ENDIAN);
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    sysbus_init_mmio(dev, R_MAX * 4, sys_regs);
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    /* Note: This device is not created in the board initialization,
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     * instead it has to be added with the -device parameter. Therefore,
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     * the device maps itself. */
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    sysbus_mmio_map(dev, 0, s->base);
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    return 0;
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}
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static const VMStateDescription vmstate_lm32_sys = {
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    .name = "lm32-sys",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .minimum_version_id_old = 1,
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    .fields      = (VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX),
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        VMSTATE_BUFFER(testname, LM32SysState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static SysBusDeviceInfo lm32_sys_info = {
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    .init = lm32_sys_init,
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    .qdev.name  = "lm32-sys",
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    .qdev.size  = sizeof(LM32SysState),
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    .qdev.vmsd  = &vmstate_lm32_sys,
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    .qdev.reset = sys_reset,
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    .qdev.props = (Property[]) {
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        DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000),
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        DEFINE_PROP_END_OF_LIST(),
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    }
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};
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static void lm32_sys_register(void)
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{
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    sysbus_register_withprop(&lm32_sys_info);
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}
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device_init(lm32_sys_register)
b/trace-events
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disable lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_irq_state(int level) "irq state %d"
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# hw/lm32_sys.c
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disable lm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"

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